1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 250346 2013-05-08 01:11:25Z adrian $
| 29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 250665 2013-05-15 18:33:05Z adrian $
|
30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_rx_keymiss;
165 u_int32_t ast_tx_swfiltered;
| 30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_rx_keymiss;
165 u_int32_t ast_tx_swfiltered;
|
| 166 u_int32_t ast_tx_node_psq_overflow;
|
166 u_int32_t ast_rx_stbc; /* RX STBC frame */
167 u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */
| 167 u_int32_t ast_rx_stbc; /* RX STBC frame */
168 u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */
|
168 u_int32_t ast_pad[13];
| 169 u_int32_t ast_pad[12];
|
169};
170
171#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
172#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
173#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
174
175struct ath_diag {
176 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
177 u_int16_t ad_id;
178#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
179#define ATH_DIAG_IN 0x4000 /* copy in parameters */
180#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
181#define ATH_DIAG_ID 0x0fff
182 u_int16_t ad_in_size; /* pack to fit, yech */
183 caddr_t ad_in_data;
184 caddr_t ad_out_data;
185 u_int ad_out_size;
186
187};
188#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
189#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
190
191
192/*
193 * The rate control ioctl has to support multiple potential rate
194 * control classes. For now, instead of trying to support an
195 * abstraction for this in the API, let's just use a TLV
196 * representation for the payload and let userspace sort it out.
197 */
198struct ath_rateioctl_tlv {
199 uint16_t tlv_id;
200 uint16_t tlv_len; /* length excluding TLV header */
201};
202
203/*
204 * This is purely the six byte MAC address.
205 */
206#define ATH_RATE_TLV_MACADDR 0xaab0
207
208/*
209 * The rate control modules may decide to push a mapping table
210 * of rix -> net80211 ratecode as part of the update.
211 */
212#define ATH_RATE_TLV_RATETABLE_NENTRIES 64
213struct ath_rateioctl_rt {
214 uint16_t nentries;
215 uint16_t pad[1];
216 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
217};
218#define ATH_RATE_TLV_RATETABLE 0xaab1
219
220/*
221 * This is the sample node statistics structure.
222 * More in ath_rate/sample/sample.h.
223 */
224#define ATH_RATE_TLV_SAMPLENODE 0xaab2
225
226struct ath_rateioctl {
227 char if_name[IFNAMSIZ]; /* if name */
228 union {
229 uint8_t macaddr[IEEE80211_ADDR_LEN];
230 uint64_t pad;
231 } is_u;
232 uint32_t len;
233 caddr_t buf;
234};
235#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl)
236#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl)
237
238/*
239 * Radio capture format.
240 */
241#define ATH_RX_RADIOTAP_PRESENT_BASE ( \
242 (1 << IEEE80211_RADIOTAP_TSFT) | \
243 (1 << IEEE80211_RADIOTAP_FLAGS) | \
244 (1 << IEEE80211_RADIOTAP_RATE) | \
245 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
246 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
247 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
248 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
249 0)
250
251#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
252#define ATH_RX_RADIOTAP_PRESENT \
253 (ATH_RX_RADIOTAP_PRESENT_BASE | \
254 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \
255 (1 << IEEE80211_RADIOTAP_EXT) | \
256 0)
257#else
258#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE
259#endif /* ATH_ENABLE_RADIOTAP_PRESENT */
260
261#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
262/*
263 * This is higher than the vendor bitmap used inside
264 * the Atheros reference codebase.
265 */
266
267/* Bit 8 */
268#define ATH_RADIOTAP_VENDOR_HEADER 8
269
270/*
271 * Using four chains makes all the fields in the
272 * per-chain info header be 4-byte aligned.
273 */
274#define ATH_RADIOTAP_MAX_CHAINS 4
275
276/*
277 * AR9380 and later chips are 3x3, which requires
278 * 5 EVM DWORDs in HT40 mode.
279 */
280#define ATH_RADIOTAP_MAX_EVM 5
281
282/*
283 * The vendor radiotap header data needs to be:
284 *
285 * + Aligned to a 4 byte address
286 * + .. so all internal fields are 4 bytes aligned;
287 * + .. and no 64 bit fields are allowed.
288 *
289 * So padding is required to ensure this is the case.
290 *
291 * Note that because of the lack of alignment with the
292 * vendor header (6 bytes), the first field must be
293 * two bytes so it can be accessed by alignment-strict
294 * platform (eg MIPS.)
295 */
296struct ath_radiotap_vendor_hdr { /* 30 bytes */
297 uint8_t vh_version; /* 1 */
298 uint8_t vh_rx_chainmask; /* 1 */
299
300 /* At this point it should be 4 byte aligned */
301 uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */
302
303 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
304 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
305
306 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */
307 uint8_t vh_rs_status; /* RX status */
308 uint8_t vh_rssi; /* Raw RSSI */
309 uint8_t vh_flags; /* General flags */
310#define ATH_VENDOR_PKT_RX 0x01
311#define ATH_VENDOR_PKT_TX 0x02
312#define ATH_VENDOR_PKT_RXPHYERR 0x04
313#define ATH_VENDOR_PKT_ISAGGR 0x08
314#define ATH_VENDOR_PKT_MOREAGGR 0x10
315
316 uint8_t vh_rx_hwrate; /* hardware RX ratecode */
317 uint8_t vh_rs_flags; /* RX HAL flags */
318 uint8_t vh_pad[2]; /* pad to DWORD boundary */
319} __packed;
320#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
321
322struct ath_rx_radiotap_header {
323 struct ieee80211_radiotap_header wr_ihdr;
324
325#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
326 /* Vendor extension header bitmap */
327 uint32_t wr_ext_bitmap; /* 4 */
328
329 /*
330 * This padding is needed because:
331 * + the radiotap header is 8 bytes;
332 * + the extension bitmap is 4 bytes;
333 * + the tsf is 8 bytes, so it must start on an 8 byte
334 * boundary.
335 */
336 uint32_t wr_pad1;
337#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
338
339 /* Normal radiotap fields */
340 u_int64_t wr_tsf;
341 u_int8_t wr_flags;
342 u_int8_t wr_rate;
343 int8_t wr_antsignal;
344 int8_t wr_antnoise;
345 u_int8_t wr_antenna;
346 u_int8_t wr_pad[3];
347 u_int32_t wr_chan_flags;
348 u_int16_t wr_chan_freq;
349 u_int8_t wr_chan_ieee;
350 int8_t wr_chan_maxpow;
351
352#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
353 /*
354 * Vendor header section, as required by the
355 * presence of the vendor extension bit and bitmap
356 * entry.
357 *
358 * XXX This must be aligned to a 4 byte address?
359 * XXX or 8 byte address?
360 */
361 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */
362
363 /*
364 * Because of the lack of alignment enforced by the above
365 * header, this vendor section won't be aligned in any
366 * useful way. So, this will include a two-byte version
367 * value which will force the structure to be 4-byte aligned.
368 */
369 struct ath_radiotap_vendor_hdr wr_v;
370#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
371} __packed;
372
373#define ATH_TX_RADIOTAP_PRESENT ( \
374 (1 << IEEE80211_RADIOTAP_TSFT) | \
375 (1 << IEEE80211_RADIOTAP_FLAGS) | \
376 (1 << IEEE80211_RADIOTAP_RATE) | \
377 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
378 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
379 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
380 0)
381
382struct ath_tx_radiotap_header {
383 struct ieee80211_radiotap_header wt_ihdr;
384 u_int64_t wt_tsf;
385 u_int8_t wt_flags;
386 u_int8_t wt_rate;
387 u_int8_t wt_txpower;
388 u_int8_t wt_antenna;
389 u_int32_t wt_chan_flags;
390 u_int16_t wt_chan_freq;
391 u_int8_t wt_chan_ieee;
392 int8_t wt_chan_maxpow;
393} __packed;
394
395/*
396 * DFS ioctl commands
397 */
398
399#define DFS_SET_THRESH 2
400#define DFS_GET_THRESH 3
401#define DFS_RADARDETECTS 6
402
403/*
404 * DFS ioctl parameter types
405 */
406#define DFS_PARAM_FIRPWR 1
407#define DFS_PARAM_RRSSI 2
408#define DFS_PARAM_HEIGHT 3
409#define DFS_PARAM_PRSSI 4
410#define DFS_PARAM_INBAND 5
411#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
412#define DFS_PARAM_RELSTEP_EN 7
413#define DFS_PARAM_RELSTEP 8
414#define DFS_PARAM_RELPWR_EN 9
415#define DFS_PARAM_RELPWR 10
416#define DFS_PARAM_MAXLEN 11
417#define DFS_PARAM_USEFIR128 12
418#define DFS_PARAM_BLOCKRADAR 13
419#define DFS_PARAM_MAXRSSI_EN 14
420
421/* FreeBSD-specific start at 32 */
422#define DFS_PARAM_ENABLE 32
423#define DFS_PARAM_EN_EXTCH 33
424
425/*
426 * Spectral ioctl parameter types
427 */
428#define SPECTRAL_PARAM_FFT_PERIOD 1
429#define SPECTRAL_PARAM_SS_PERIOD 2
430#define SPECTRAL_PARAM_SS_COUNT 3
431#define SPECTRAL_PARAM_SS_SHORT_RPT 4
432#define SPECTRAL_PARAM_ENABLED 5
433#define SPECTRAL_PARAM_ACTIVE 6
434
435/*
436 * Spectral control parameters
437 */
438#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag)
439
440#define SPECTRAL_CONTROL_ENABLE 2
441#define SPECTRAL_CONTROL_DISABLE 3
442#define SPECTRAL_CONTROL_START 4
443#define SPECTRAL_CONTROL_STOP 5
444#define SPECTRAL_CONTROL_GET_PARAMS 6
445#define SPECTRAL_CONTROL_SET_PARAMS 7
446#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8
447#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9
448
449#endif /* _DEV_ATH_ATHIOCTL_H */
| 170};
171
172#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
173#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
174#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
175
176struct ath_diag {
177 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
178 u_int16_t ad_id;
179#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
180#define ATH_DIAG_IN 0x4000 /* copy in parameters */
181#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
182#define ATH_DIAG_ID 0x0fff
183 u_int16_t ad_in_size; /* pack to fit, yech */
184 caddr_t ad_in_data;
185 caddr_t ad_out_data;
186 u_int ad_out_size;
187
188};
189#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
190#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
191
192
193/*
194 * The rate control ioctl has to support multiple potential rate
195 * control classes. For now, instead of trying to support an
196 * abstraction for this in the API, let's just use a TLV
197 * representation for the payload and let userspace sort it out.
198 */
199struct ath_rateioctl_tlv {
200 uint16_t tlv_id;
201 uint16_t tlv_len; /* length excluding TLV header */
202};
203
204/*
205 * This is purely the six byte MAC address.
206 */
207#define ATH_RATE_TLV_MACADDR 0xaab0
208
209/*
210 * The rate control modules may decide to push a mapping table
211 * of rix -> net80211 ratecode as part of the update.
212 */
213#define ATH_RATE_TLV_RATETABLE_NENTRIES 64
214struct ath_rateioctl_rt {
215 uint16_t nentries;
216 uint16_t pad[1];
217 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
218};
219#define ATH_RATE_TLV_RATETABLE 0xaab1
220
221/*
222 * This is the sample node statistics structure.
223 * More in ath_rate/sample/sample.h.
224 */
225#define ATH_RATE_TLV_SAMPLENODE 0xaab2
226
227struct ath_rateioctl {
228 char if_name[IFNAMSIZ]; /* if name */
229 union {
230 uint8_t macaddr[IEEE80211_ADDR_LEN];
231 uint64_t pad;
232 } is_u;
233 uint32_t len;
234 caddr_t buf;
235};
236#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl)
237#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl)
238
239/*
240 * Radio capture format.
241 */
242#define ATH_RX_RADIOTAP_PRESENT_BASE ( \
243 (1 << IEEE80211_RADIOTAP_TSFT) | \
244 (1 << IEEE80211_RADIOTAP_FLAGS) | \
245 (1 << IEEE80211_RADIOTAP_RATE) | \
246 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
247 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
248 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
249 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
250 0)
251
252#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
253#define ATH_RX_RADIOTAP_PRESENT \
254 (ATH_RX_RADIOTAP_PRESENT_BASE | \
255 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \
256 (1 << IEEE80211_RADIOTAP_EXT) | \
257 0)
258#else
259#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE
260#endif /* ATH_ENABLE_RADIOTAP_PRESENT */
261
262#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
263/*
264 * This is higher than the vendor bitmap used inside
265 * the Atheros reference codebase.
266 */
267
268/* Bit 8 */
269#define ATH_RADIOTAP_VENDOR_HEADER 8
270
271/*
272 * Using four chains makes all the fields in the
273 * per-chain info header be 4-byte aligned.
274 */
275#define ATH_RADIOTAP_MAX_CHAINS 4
276
277/*
278 * AR9380 and later chips are 3x3, which requires
279 * 5 EVM DWORDs in HT40 mode.
280 */
281#define ATH_RADIOTAP_MAX_EVM 5
282
283/*
284 * The vendor radiotap header data needs to be:
285 *
286 * + Aligned to a 4 byte address
287 * + .. so all internal fields are 4 bytes aligned;
288 * + .. and no 64 bit fields are allowed.
289 *
290 * So padding is required to ensure this is the case.
291 *
292 * Note that because of the lack of alignment with the
293 * vendor header (6 bytes), the first field must be
294 * two bytes so it can be accessed by alignment-strict
295 * platform (eg MIPS.)
296 */
297struct ath_radiotap_vendor_hdr { /* 30 bytes */
298 uint8_t vh_version; /* 1 */
299 uint8_t vh_rx_chainmask; /* 1 */
300
301 /* At this point it should be 4 byte aligned */
302 uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */
303
304 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
305 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
306
307 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */
308 uint8_t vh_rs_status; /* RX status */
309 uint8_t vh_rssi; /* Raw RSSI */
310 uint8_t vh_flags; /* General flags */
311#define ATH_VENDOR_PKT_RX 0x01
312#define ATH_VENDOR_PKT_TX 0x02
313#define ATH_VENDOR_PKT_RXPHYERR 0x04
314#define ATH_VENDOR_PKT_ISAGGR 0x08
315#define ATH_VENDOR_PKT_MOREAGGR 0x10
316
317 uint8_t vh_rx_hwrate; /* hardware RX ratecode */
318 uint8_t vh_rs_flags; /* RX HAL flags */
319 uint8_t vh_pad[2]; /* pad to DWORD boundary */
320} __packed;
321#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
322
323struct ath_rx_radiotap_header {
324 struct ieee80211_radiotap_header wr_ihdr;
325
326#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
327 /* Vendor extension header bitmap */
328 uint32_t wr_ext_bitmap; /* 4 */
329
330 /*
331 * This padding is needed because:
332 * + the radiotap header is 8 bytes;
333 * + the extension bitmap is 4 bytes;
334 * + the tsf is 8 bytes, so it must start on an 8 byte
335 * boundary.
336 */
337 uint32_t wr_pad1;
338#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
339
340 /* Normal radiotap fields */
341 u_int64_t wr_tsf;
342 u_int8_t wr_flags;
343 u_int8_t wr_rate;
344 int8_t wr_antsignal;
345 int8_t wr_antnoise;
346 u_int8_t wr_antenna;
347 u_int8_t wr_pad[3];
348 u_int32_t wr_chan_flags;
349 u_int16_t wr_chan_freq;
350 u_int8_t wr_chan_ieee;
351 int8_t wr_chan_maxpow;
352
353#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
354 /*
355 * Vendor header section, as required by the
356 * presence of the vendor extension bit and bitmap
357 * entry.
358 *
359 * XXX This must be aligned to a 4 byte address?
360 * XXX or 8 byte address?
361 */
362 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */
363
364 /*
365 * Because of the lack of alignment enforced by the above
366 * header, this vendor section won't be aligned in any
367 * useful way. So, this will include a two-byte version
368 * value which will force the structure to be 4-byte aligned.
369 */
370 struct ath_radiotap_vendor_hdr wr_v;
371#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
372} __packed;
373
374#define ATH_TX_RADIOTAP_PRESENT ( \
375 (1 << IEEE80211_RADIOTAP_TSFT) | \
376 (1 << IEEE80211_RADIOTAP_FLAGS) | \
377 (1 << IEEE80211_RADIOTAP_RATE) | \
378 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
379 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
380 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
381 0)
382
383struct ath_tx_radiotap_header {
384 struct ieee80211_radiotap_header wt_ihdr;
385 u_int64_t wt_tsf;
386 u_int8_t wt_flags;
387 u_int8_t wt_rate;
388 u_int8_t wt_txpower;
389 u_int8_t wt_antenna;
390 u_int32_t wt_chan_flags;
391 u_int16_t wt_chan_freq;
392 u_int8_t wt_chan_ieee;
393 int8_t wt_chan_maxpow;
394} __packed;
395
396/*
397 * DFS ioctl commands
398 */
399
400#define DFS_SET_THRESH 2
401#define DFS_GET_THRESH 3
402#define DFS_RADARDETECTS 6
403
404/*
405 * DFS ioctl parameter types
406 */
407#define DFS_PARAM_FIRPWR 1
408#define DFS_PARAM_RRSSI 2
409#define DFS_PARAM_HEIGHT 3
410#define DFS_PARAM_PRSSI 4
411#define DFS_PARAM_INBAND 5
412#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
413#define DFS_PARAM_RELSTEP_EN 7
414#define DFS_PARAM_RELSTEP 8
415#define DFS_PARAM_RELPWR_EN 9
416#define DFS_PARAM_RELPWR 10
417#define DFS_PARAM_MAXLEN 11
418#define DFS_PARAM_USEFIR128 12
419#define DFS_PARAM_BLOCKRADAR 13
420#define DFS_PARAM_MAXRSSI_EN 14
421
422/* FreeBSD-specific start at 32 */
423#define DFS_PARAM_ENABLE 32
424#define DFS_PARAM_EN_EXTCH 33
425
426/*
427 * Spectral ioctl parameter types
428 */
429#define SPECTRAL_PARAM_FFT_PERIOD 1
430#define SPECTRAL_PARAM_SS_PERIOD 2
431#define SPECTRAL_PARAM_SS_COUNT 3
432#define SPECTRAL_PARAM_SS_SHORT_RPT 4
433#define SPECTRAL_PARAM_ENABLED 5
434#define SPECTRAL_PARAM_ACTIVE 6
435
436/*
437 * Spectral control parameters
438 */
439#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag)
440
441#define SPECTRAL_CONTROL_ENABLE 2
442#define SPECTRAL_CONTROL_DISABLE 3
443#define SPECTRAL_CONTROL_START 4
444#define SPECTRAL_CONTROL_STOP 5
445#define SPECTRAL_CONTROL_GET_PARAMS 6
446#define SPECTRAL_CONTROL_SET_PARAMS 7
447#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8
448#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9
449
450#endif /* _DEV_ATH_ATHIOCTL_H */
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