1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 248143 2013-03-11 06:01:00Z adrian $
| 29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 248146 2013-03-11 06:54:58Z adrian $
|
30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_rx_keymiss;
165 u_int32_t ast_tx_swfiltered;
166
167 u_int32_t ast_pad[15];
168};
169
170#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
171#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
172#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
173
174struct ath_diag {
175 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
176 u_int16_t ad_id;
177#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
178#define ATH_DIAG_IN 0x4000 /* copy in parameters */
179#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
180#define ATH_DIAG_ID 0x0fff
181 u_int16_t ad_in_size; /* pack to fit, yech */
182 caddr_t ad_in_data;
183 caddr_t ad_out_data;
184 u_int ad_out_size;
185
186};
187#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
188#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
189
190
191/*
192 * The rate control ioctl has to support multiple potential rate
193 * control classes. For now, instead of trying to support an
194 * abstraction for this in the API, let's just use a TLV
195 * representation for the payload and let userspace sort it out.
196 */
197struct ath_rateioctl_tlv {
198 uint16_t tlv_id;
199 uint16_t tlv_len; /* length excluding TLV header */
200};
201
202/*
203 * This is purely the six byte MAC address.
204 */
205#define ATH_RATE_TLV_MACADDR 0xaab0
206
207/*
208 * The rate control modules may decide to push a mapping table
209 * of rix -> net80211 ratecode as part of the update.
210 */
211#define ATH_RATE_TLV_RATETABLE_NENTRIES 64
212struct ath_rateioctl_rt {
213 uint16_t nentries;
214 uint16_t pad[1];
215 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
216};
217#define ATH_RATE_TLV_RATETABLE 0xaab1
218
219/*
220 * This is the sample node statistics structure.
221 * More in ath_rate/sample/sample.h.
222 */
223#define ATH_RATE_TLV_SAMPLENODE 0xaab2
224
225struct ath_rateioctl {
226 char if_name[IFNAMSIZ]; /* if name */
227 union {
228 uint8_t macaddr[IEEE80211_ADDR_LEN];
229 uint64_t pad;
230 } is_u;
231 uint32_t len;
232 caddr_t buf;
233};
234#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl)
235#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl)
236
237/*
238 * Radio capture format.
239 */
240#define ATH_RX_RADIOTAP_PRESENT_BASE ( \
241 (1 << IEEE80211_RADIOTAP_TSFT) | \
242 (1 << IEEE80211_RADIOTAP_FLAGS) | \
243 (1 << IEEE80211_RADIOTAP_RATE) | \
244 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
245 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
246 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
247 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
248 0)
249
250#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
251#define ATH_RX_RADIOTAP_PRESENT \
252 (ATH_RX_RADIOTAP_PRESENT_BASE | \
253 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \
254 (1 << IEEE80211_RADIOTAP_EXT) | \
255 0)
256#else
257#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE
258#endif /* ATH_ENABLE_RADIOTAP_PRESENT */
259
260#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
261/*
262 * This is higher than the vendor bitmap used inside
263 * the Atheros reference codebase.
264 */
265
266/* Bit 8 */
267#define ATH_RADIOTAP_VENDOR_HEADER 8
268
269/*
270 * Using four chains makes all the fields in the
271 * per-chain info header be 4-byte aligned.
272 */
273#define ATH_RADIOTAP_MAX_CHAINS 4
274
275/*
276 * AR9380 and later chips are 3x3, which requires
277 * 5 EVM DWORDs in HT40 mode.
278 */
279#define ATH_RADIOTAP_MAX_EVM 5
280
281/*
282 * The vendor radiotap header data needs to be:
283 *
284 * + Aligned to a 4 byte address
285 * + .. so all internal fields are 4 bytes aligned;
286 * + .. and no 64 bit fields are allowed.
287 *
288 * So padding is required to ensure this is the case.
289 *
290 * Note that because of the lack of alignment with the
291 * vendor header (6 bytes), the first field must be
292 * two bytes so it can be accessed by alignment-strict
293 * platform (eg MIPS.)
294 */
295struct ath_radiotap_vendor_hdr { /* 30 bytes */
296 uint8_t vh_version; /* 1 */
297 uint8_t vh_rx_chainmask; /* 1 */
298
299 /* At this point it should be 4 byte aligned */
300 uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */
301
302 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
303 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
304
305 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */
306 uint8_t vh_rs_status; /* RX status */
307 uint8_t vh_rssi; /* Raw RSSI */
| 30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_rx_keymiss;
165 u_int32_t ast_tx_swfiltered;
166
167 u_int32_t ast_pad[15];
168};
169
170#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
171#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
172#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
173
174struct ath_diag {
175 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
176 u_int16_t ad_id;
177#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
178#define ATH_DIAG_IN 0x4000 /* copy in parameters */
179#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
180#define ATH_DIAG_ID 0x0fff
181 u_int16_t ad_in_size; /* pack to fit, yech */
182 caddr_t ad_in_data;
183 caddr_t ad_out_data;
184 u_int ad_out_size;
185
186};
187#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
188#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
189
190
191/*
192 * The rate control ioctl has to support multiple potential rate
193 * control classes. For now, instead of trying to support an
194 * abstraction for this in the API, let's just use a TLV
195 * representation for the payload and let userspace sort it out.
196 */
197struct ath_rateioctl_tlv {
198 uint16_t tlv_id;
199 uint16_t tlv_len; /* length excluding TLV header */
200};
201
202/*
203 * This is purely the six byte MAC address.
204 */
205#define ATH_RATE_TLV_MACADDR 0xaab0
206
207/*
208 * The rate control modules may decide to push a mapping table
209 * of rix -> net80211 ratecode as part of the update.
210 */
211#define ATH_RATE_TLV_RATETABLE_NENTRIES 64
212struct ath_rateioctl_rt {
213 uint16_t nentries;
214 uint16_t pad[1];
215 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
216};
217#define ATH_RATE_TLV_RATETABLE 0xaab1
218
219/*
220 * This is the sample node statistics structure.
221 * More in ath_rate/sample/sample.h.
222 */
223#define ATH_RATE_TLV_SAMPLENODE 0xaab2
224
225struct ath_rateioctl {
226 char if_name[IFNAMSIZ]; /* if name */
227 union {
228 uint8_t macaddr[IEEE80211_ADDR_LEN];
229 uint64_t pad;
230 } is_u;
231 uint32_t len;
232 caddr_t buf;
233};
234#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl)
235#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl)
236
237/*
238 * Radio capture format.
239 */
240#define ATH_RX_RADIOTAP_PRESENT_BASE ( \
241 (1 << IEEE80211_RADIOTAP_TSFT) | \
242 (1 << IEEE80211_RADIOTAP_FLAGS) | \
243 (1 << IEEE80211_RADIOTAP_RATE) | \
244 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
245 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
246 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
247 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
248 0)
249
250#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
251#define ATH_RX_RADIOTAP_PRESENT \
252 (ATH_RX_RADIOTAP_PRESENT_BASE | \
253 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \
254 (1 << IEEE80211_RADIOTAP_EXT) | \
255 0)
256#else
257#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE
258#endif /* ATH_ENABLE_RADIOTAP_PRESENT */
259
260#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
261/*
262 * This is higher than the vendor bitmap used inside
263 * the Atheros reference codebase.
264 */
265
266/* Bit 8 */
267#define ATH_RADIOTAP_VENDOR_HEADER 8
268
269/*
270 * Using four chains makes all the fields in the
271 * per-chain info header be 4-byte aligned.
272 */
273#define ATH_RADIOTAP_MAX_CHAINS 4
274
275/*
276 * AR9380 and later chips are 3x3, which requires
277 * 5 EVM DWORDs in HT40 mode.
278 */
279#define ATH_RADIOTAP_MAX_EVM 5
280
281/*
282 * The vendor radiotap header data needs to be:
283 *
284 * + Aligned to a 4 byte address
285 * + .. so all internal fields are 4 bytes aligned;
286 * + .. and no 64 bit fields are allowed.
287 *
288 * So padding is required to ensure this is the case.
289 *
290 * Note that because of the lack of alignment with the
291 * vendor header (6 bytes), the first field must be
292 * two bytes so it can be accessed by alignment-strict
293 * platform (eg MIPS.)
294 */
295struct ath_radiotap_vendor_hdr { /* 30 bytes */
296 uint8_t vh_version; /* 1 */
297 uint8_t vh_rx_chainmask; /* 1 */
298
299 /* At this point it should be 4 byte aligned */
300 uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */
301
302 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
303 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
304
305 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */
306 uint8_t vh_rs_status; /* RX status */
307 uint8_t vh_rssi; /* Raw RSSI */
|
308 uint8_t vh_pad1[1]; /* Pad to 4 byte boundary */
| 308 uint8_t vh_flags; /* General flags */
309#define ATH_VENDOR_PKT_RX 0x01
310#define ATH_VENDOR_PKT_TX 0x02
311#define ATH_VENDOR_PKT_RXPHYERR 0x04
312#define ATH_VENDOR_PKT_ISAGGR 0x08
313#define ATH_VENDOR_PKT_MOREAGGR 0x10
314
315 uint8_t vh_rx_hwrate; /* hardware RX ratecode */
316 uint8_t vh_rs_flags; /* RX HAL flags */
317 uint8_t vh_pad[2]; /* pad to DWORD boundary */
|
309} __packed;
310#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
311
312struct ath_rx_radiotap_header {
313 struct ieee80211_radiotap_header wr_ihdr;
314
315#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
316 /* Vendor extension header bitmap */
317 uint32_t wr_ext_bitmap; /* 4 */
318
319 /*
320 * This padding is needed because:
321 * + the radiotap header is 8 bytes;
322 * + the extension bitmap is 4 bytes;
323 * + the tsf is 8 bytes, so it must start on an 8 byte
324 * boundary.
325 */
326 uint32_t wr_pad1;
327#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
328
329 /* Normal radiotap fields */
330 u_int64_t wr_tsf;
331 u_int8_t wr_flags;
332 u_int8_t wr_rate;
333 int8_t wr_antsignal;
334 int8_t wr_antnoise;
335 u_int8_t wr_antenna;
336 u_int8_t wr_pad[3];
337 u_int32_t wr_chan_flags;
338 u_int16_t wr_chan_freq;
339 u_int8_t wr_chan_ieee;
340 int8_t wr_chan_maxpow;
341
342#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
343 /*
344 * Vendor header section, as required by the
345 * presence of the vendor extension bit and bitmap
346 * entry.
347 *
348 * XXX This must be aligned to a 4 byte address?
349 * XXX or 8 byte address?
350 */
351 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */
352
353 /*
354 * Because of the lack of alignment enforced by the above
355 * header, this vendor section won't be aligned in any
356 * useful way. So, this will include a two-byte version
357 * value which will force the structure to be 4-byte aligned.
358 */
359 struct ath_radiotap_vendor_hdr wr_v;
360#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
361} __packed;
362
363#define ATH_TX_RADIOTAP_PRESENT ( \
364 (1 << IEEE80211_RADIOTAP_TSFT) | \
365 (1 << IEEE80211_RADIOTAP_FLAGS) | \
366 (1 << IEEE80211_RADIOTAP_RATE) | \
367 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
368 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
369 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
370 0)
371
372struct ath_tx_radiotap_header {
373 struct ieee80211_radiotap_header wt_ihdr;
374 u_int64_t wt_tsf;
375 u_int8_t wt_flags;
376 u_int8_t wt_rate;
377 u_int8_t wt_txpower;
378 u_int8_t wt_antenna;
379 u_int32_t wt_chan_flags;
380 u_int16_t wt_chan_freq;
381 u_int8_t wt_chan_ieee;
382 int8_t wt_chan_maxpow;
383} __packed;
384
385/*
386 * DFS ioctl commands
387 */
388
389#define DFS_SET_THRESH 2
390#define DFS_GET_THRESH 3
391#define DFS_RADARDETECTS 6
392
393/*
394 * DFS ioctl parameter types
395 */
396#define DFS_PARAM_FIRPWR 1
397#define DFS_PARAM_RRSSI 2
398#define DFS_PARAM_HEIGHT 3
399#define DFS_PARAM_PRSSI 4
400#define DFS_PARAM_INBAND 5
401#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
402#define DFS_PARAM_RELSTEP_EN 7
403#define DFS_PARAM_RELSTEP 8
404#define DFS_PARAM_RELPWR_EN 9
405#define DFS_PARAM_RELPWR 10
406#define DFS_PARAM_MAXLEN 11
407#define DFS_PARAM_USEFIR128 12
408#define DFS_PARAM_BLOCKRADAR 13
409#define DFS_PARAM_MAXRSSI_EN 14
410
411/* FreeBSD-specific start at 32 */
412#define DFS_PARAM_ENABLE 32
413#define DFS_PARAM_EN_EXTCH 33
414
415/*
416 * Spectral ioctl parameter types
417 */
418#define SPECTRAL_PARAM_FFT_PERIOD 1
419#define SPECTRAL_PARAM_SS_PERIOD 2
420#define SPECTRAL_PARAM_SS_COUNT 3
421#define SPECTRAL_PARAM_SS_SHORT_RPT 4
422#define SPECTRAL_PARAM_ENABLED 5
423#define SPECTRAL_PARAM_ACTIVE 6
424
425/*
426 * Spectral control parameters
427 */
428#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag)
429
430#define SPECTRAL_CONTROL_ENABLE 2
431#define SPECTRAL_CONTROL_DISABLE 3
432#define SPECTRAL_CONTROL_START 4
433#define SPECTRAL_CONTROL_STOP 5
434#define SPECTRAL_CONTROL_GET_PARAMS 6
435#define SPECTRAL_CONTROL_SET_PARAMS 7
436#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8
437#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9
438
439#endif /* _DEV_ATH_ATHIOCTL_H */
| 318} __packed;
319#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
320
321struct ath_rx_radiotap_header {
322 struct ieee80211_radiotap_header wr_ihdr;
323
324#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
325 /* Vendor extension header bitmap */
326 uint32_t wr_ext_bitmap; /* 4 */
327
328 /*
329 * This padding is needed because:
330 * + the radiotap header is 8 bytes;
331 * + the extension bitmap is 4 bytes;
332 * + the tsf is 8 bytes, so it must start on an 8 byte
333 * boundary.
334 */
335 uint32_t wr_pad1;
336#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
337
338 /* Normal radiotap fields */
339 u_int64_t wr_tsf;
340 u_int8_t wr_flags;
341 u_int8_t wr_rate;
342 int8_t wr_antsignal;
343 int8_t wr_antnoise;
344 u_int8_t wr_antenna;
345 u_int8_t wr_pad[3];
346 u_int32_t wr_chan_flags;
347 u_int16_t wr_chan_freq;
348 u_int8_t wr_chan_ieee;
349 int8_t wr_chan_maxpow;
350
351#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
352 /*
353 * Vendor header section, as required by the
354 * presence of the vendor extension bit and bitmap
355 * entry.
356 *
357 * XXX This must be aligned to a 4 byte address?
358 * XXX or 8 byte address?
359 */
360 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */
361
362 /*
363 * Because of the lack of alignment enforced by the above
364 * header, this vendor section won't be aligned in any
365 * useful way. So, this will include a two-byte version
366 * value which will force the structure to be 4-byte aligned.
367 */
368 struct ath_radiotap_vendor_hdr wr_v;
369#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
370} __packed;
371
372#define ATH_TX_RADIOTAP_PRESENT ( \
373 (1 << IEEE80211_RADIOTAP_TSFT) | \
374 (1 << IEEE80211_RADIOTAP_FLAGS) | \
375 (1 << IEEE80211_RADIOTAP_RATE) | \
376 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
377 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
378 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
379 0)
380
381struct ath_tx_radiotap_header {
382 struct ieee80211_radiotap_header wt_ihdr;
383 u_int64_t wt_tsf;
384 u_int8_t wt_flags;
385 u_int8_t wt_rate;
386 u_int8_t wt_txpower;
387 u_int8_t wt_antenna;
388 u_int32_t wt_chan_flags;
389 u_int16_t wt_chan_freq;
390 u_int8_t wt_chan_ieee;
391 int8_t wt_chan_maxpow;
392} __packed;
393
394/*
395 * DFS ioctl commands
396 */
397
398#define DFS_SET_THRESH 2
399#define DFS_GET_THRESH 3
400#define DFS_RADARDETECTS 6
401
402/*
403 * DFS ioctl parameter types
404 */
405#define DFS_PARAM_FIRPWR 1
406#define DFS_PARAM_RRSSI 2
407#define DFS_PARAM_HEIGHT 3
408#define DFS_PARAM_PRSSI 4
409#define DFS_PARAM_INBAND 5
410#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
411#define DFS_PARAM_RELSTEP_EN 7
412#define DFS_PARAM_RELSTEP 8
413#define DFS_PARAM_RELPWR_EN 9
414#define DFS_PARAM_RELPWR 10
415#define DFS_PARAM_MAXLEN 11
416#define DFS_PARAM_USEFIR128 12
417#define DFS_PARAM_BLOCKRADAR 13
418#define DFS_PARAM_MAXRSSI_EN 14
419
420/* FreeBSD-specific start at 32 */
421#define DFS_PARAM_ENABLE 32
422#define DFS_PARAM_EN_EXTCH 33
423
424/*
425 * Spectral ioctl parameter types
426 */
427#define SPECTRAL_PARAM_FFT_PERIOD 1
428#define SPECTRAL_PARAM_SS_PERIOD 2
429#define SPECTRAL_PARAM_SS_COUNT 3
430#define SPECTRAL_PARAM_SS_SHORT_RPT 4
431#define SPECTRAL_PARAM_ENABLED 5
432#define SPECTRAL_PARAM_ACTIVE 6
433
434/*
435 * Spectral control parameters
436 */
437#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag)
438
439#define SPECTRAL_CONTROL_ENABLE 2
440#define SPECTRAL_CONTROL_DISABLE 3
441#define SPECTRAL_CONTROL_START 4
442#define SPECTRAL_CONTROL_STOP 5
443#define SPECTRAL_CONTROL_GET_PARAMS 6
444#define SPECTRAL_CONTROL_SET_PARAMS 7
445#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8
446#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9
447
448#endif /* _DEV_ATH_ATHIOCTL_H */
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