1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 238638 2012-07-20 02:17:48Z adrian $
| 29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 238929 2012-07-31 02:18:10Z adrian $
|
30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_rx_keymiss;
165
166 u_int32_t ast_pad[16];
167};
168
169#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
170#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
171#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
172
173struct ath_diag {
174 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
175 u_int16_t ad_id;
176#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
177#define ATH_DIAG_IN 0x4000 /* copy in parameters */
178#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
179#define ATH_DIAG_ID 0x0fff
180 u_int16_t ad_in_size; /* pack to fit, yech */
181 caddr_t ad_in_data;
182 caddr_t ad_out_data;
183 u_int ad_out_size;
184
185};
186#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
187#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
188
189
190/*
191 * The rate control ioctl has to support multiple potential rate
192 * control classes. For now, instead of trying to support an
193 * abstraction for this in the API, let's just use a TLV
194 * representation for the payload and let userspace sort it out.
195 */
196struct ath_rateioctl_tlv {
197 uint16_t tlv_id;
198 uint16_t tlv_len; /* length excluding TLV header */
199};
200
201/*
202 * This is purely the six byte MAC address.
203 */
204#define ATH_RATE_TLV_MACADDR 0xaab0
205
206/*
207 * The rate control modules may decide to push a mapping table
208 * of rix -> net80211 ratecode as part of the update.
209 */
210#define ATH_RATE_TLV_RATETABLE_NENTRIES 64
211struct ath_rateioctl_rt {
212 uint16_t nentries;
213 uint16_t pad[1];
214 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
215};
216#define ATH_RATE_TLV_RATETABLE 0xaab1
217
218/*
219 * This is the sample node statistics structure.
220 * More in ath_rate/sample/sample.h.
221 */
222#define ATH_RATE_TLV_SAMPLENODE 0xaab2
223
224struct ath_rateioctl {
225 char if_name[IFNAMSIZ]; /* if name */
226 union {
227 uint8_t macaddr[IEEE80211_ADDR_LEN];
228 uint64_t pad;
229 } is_u;
230 uint32_t len;
231 caddr_t buf;
232};
233#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl)
| 30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_rx_keymiss;
165
166 u_int32_t ast_pad[16];
167};
168
169#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
170#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
171#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
172
173struct ath_diag {
174 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
175 u_int16_t ad_id;
176#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
177#define ATH_DIAG_IN 0x4000 /* copy in parameters */
178#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
179#define ATH_DIAG_ID 0x0fff
180 u_int16_t ad_in_size; /* pack to fit, yech */
181 caddr_t ad_in_data;
182 caddr_t ad_out_data;
183 u_int ad_out_size;
184
185};
186#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
187#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
188
189
190/*
191 * The rate control ioctl has to support multiple potential rate
192 * control classes. For now, instead of trying to support an
193 * abstraction for this in the API, let's just use a TLV
194 * representation for the payload and let userspace sort it out.
195 */
196struct ath_rateioctl_tlv {
197 uint16_t tlv_id;
198 uint16_t tlv_len; /* length excluding TLV header */
199};
200
201/*
202 * This is purely the six byte MAC address.
203 */
204#define ATH_RATE_TLV_MACADDR 0xaab0
205
206/*
207 * The rate control modules may decide to push a mapping table
208 * of rix -> net80211 ratecode as part of the update.
209 */
210#define ATH_RATE_TLV_RATETABLE_NENTRIES 64
211struct ath_rateioctl_rt {
212 uint16_t nentries;
213 uint16_t pad[1];
214 uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES];
215};
216#define ATH_RATE_TLV_RATETABLE 0xaab1
217
218/*
219 * This is the sample node statistics structure.
220 * More in ath_rate/sample/sample.h.
221 */
222#define ATH_RATE_TLV_SAMPLENODE 0xaab2
223
224struct ath_rateioctl {
225 char if_name[IFNAMSIZ]; /* if name */
226 union {
227 uint8_t macaddr[IEEE80211_ADDR_LEN];
228 uint64_t pad;
229 } is_u;
230 uint32_t len;
231 caddr_t buf;
232};
233#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl)
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| 234#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl)
|
234
235/*
236 * Radio capture format.
237 */
238#define ATH_RX_RADIOTAP_PRESENT_BASE ( \
239 (1 << IEEE80211_RADIOTAP_TSFT) | \
240 (1 << IEEE80211_RADIOTAP_FLAGS) | \
241 (1 << IEEE80211_RADIOTAP_RATE) | \
242 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
243 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
244 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
245 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
246 0)
247
248#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
249#define ATH_RX_RADIOTAP_PRESENT \
250 (ATH_RX_RADIOTAP_PRESENT_BASE | \
251 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \
252 (1 << IEEE80211_RADIOTAP_EXT) | \
253 0)
254#else
255#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE
256#endif /* ATH_ENABLE_RADIOTAP_PRESENT */
257
258#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
259/*
260 * This is higher than the vendor bitmap used inside
261 * the Atheros reference codebase.
262 */
263
264/* Bit 8 */
265#define ATH_RADIOTAP_VENDOR_HEADER 8
266
267/*
268 * Using four chains makes all the fields in the
269 * per-chain info header be 4-byte aligned.
270 */
271#define ATH_RADIOTAP_MAX_CHAINS 4
272
273/*
274 * The vendor radiotap header data needs to be:
275 *
276 * + Aligned to a 4 byte address
277 * + .. so all internal fields are 4 bytes aligned;
278 * + .. and no 64 bit fields are allowed.
279 *
280 * So padding is required to ensure this is the case.
281 *
282 * Note that because of the lack of alignment with the
283 * vendor header (6 bytes), the first field must be
284 * two bytes so it can be accessed by alignment-strict
285 * platform (eg MIPS.)
286 */
287struct ath_radiotap_vendor_hdr { /* 30 bytes */
288 uint8_t vh_version; /* 1 */
289 uint8_t vh_rx_chainmask; /* 1 */
290
291 /* At this point it should be 4 byte aligned */
292 uint32_t evm[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */
293
294 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
295 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
296
297 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */
298 uint8_t vh_rs_status; /* RX status */
299 uint8_t vh_rssi; /* Raw RSSI */
300 uint8_t vh_pad1[1]; /* Pad to 4 byte boundary */
301} __packed;
302#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
303
304struct ath_rx_radiotap_header {
305 struct ieee80211_radiotap_header wr_ihdr;
306
307#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
308 /* Vendor extension header bitmap */
309 uint32_t wr_ext_bitmap; /* 4 */
310
311 /*
312 * This padding is needed because:
313 * + the radiotap header is 8 bytes;
314 * + the extension bitmap is 4 bytes;
315 * + the tsf is 8 bytes, so it must start on an 8 byte
316 * boundary.
317 */
318 uint32_t wr_pad1;
319#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
320
321 /* Normal radiotap fields */
322 u_int64_t wr_tsf;
323 u_int8_t wr_flags;
324 u_int8_t wr_rate;
325 int8_t wr_antsignal;
326 int8_t wr_antnoise;
327 u_int8_t wr_antenna;
328 u_int8_t wr_pad[3];
329 u_int32_t wr_chan_flags;
330 u_int16_t wr_chan_freq;
331 u_int8_t wr_chan_ieee;
332 int8_t wr_chan_maxpow;
333
334#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
335 /*
336 * Vendor header section, as required by the
337 * presence of the vendor extension bit and bitmap
338 * entry.
339 *
340 * XXX This must be aligned to a 4 byte address?
341 * XXX or 8 byte address?
342 */
343 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */
344
345 /*
346 * Because of the lack of alignment enforced by the above
347 * header, this vendor section won't be aligned in any
348 * useful way. So, this will include a two-byte version
349 * value which will force the structure to be 4-byte aligned.
350 */
351 struct ath_radiotap_vendor_hdr wr_v;
352#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
353} __packed;
354
355#define ATH_TX_RADIOTAP_PRESENT ( \
356 (1 << IEEE80211_RADIOTAP_TSFT) | \
357 (1 << IEEE80211_RADIOTAP_FLAGS) | \
358 (1 << IEEE80211_RADIOTAP_RATE) | \
359 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
360 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
361 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
362 0)
363
364struct ath_tx_radiotap_header {
365 struct ieee80211_radiotap_header wt_ihdr;
366 u_int64_t wt_tsf;
367 u_int8_t wt_flags;
368 u_int8_t wt_rate;
369 u_int8_t wt_txpower;
370 u_int8_t wt_antenna;
371 u_int32_t wt_chan_flags;
372 u_int16_t wt_chan_freq;
373 u_int8_t wt_chan_ieee;
374 int8_t wt_chan_maxpow;
375} __packed;
376
377/*
378 * DFS ioctl commands
379 */
380
381#define DFS_SET_THRESH 2
382#define DFS_GET_THRESH 3
383#define DFS_RADARDETECTS 6
384
385/*
386 * DFS ioctl parameter types
387 */
388#define DFS_PARAM_FIRPWR 1
389#define DFS_PARAM_RRSSI 2
390#define DFS_PARAM_HEIGHT 3
391#define DFS_PARAM_PRSSI 4
392#define DFS_PARAM_INBAND 5
393#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
394#define DFS_PARAM_RELSTEP_EN 7
395#define DFS_PARAM_RELSTEP 8
396#define DFS_PARAM_RELPWR_EN 9
397#define DFS_PARAM_RELPWR 10
398#define DFS_PARAM_MAXLEN 11
399#define DFS_PARAM_USEFIR128 12
400#define DFS_PARAM_BLOCKRADAR 13
401#define DFS_PARAM_MAXRSSI_EN 14
402
403/* FreeBSD-specific start at 32 */
404#define DFS_PARAM_ENABLE 32
405#define DFS_PARAM_EN_EXTCH 33
406
407#endif /* _DEV_ATH_ATHIOCTL_H */
| 235
236/*
237 * Radio capture format.
238 */
239#define ATH_RX_RADIOTAP_PRESENT_BASE ( \
240 (1 << IEEE80211_RADIOTAP_TSFT) | \
241 (1 << IEEE80211_RADIOTAP_FLAGS) | \
242 (1 << IEEE80211_RADIOTAP_RATE) | \
243 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
244 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
245 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
246 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
247 0)
248
249#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
250#define ATH_RX_RADIOTAP_PRESENT \
251 (ATH_RX_RADIOTAP_PRESENT_BASE | \
252 (1 << IEEE80211_RADIOTAP_VENDOREXT) | \
253 (1 << IEEE80211_RADIOTAP_EXT) | \
254 0)
255#else
256#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE
257#endif /* ATH_ENABLE_RADIOTAP_PRESENT */
258
259#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
260/*
261 * This is higher than the vendor bitmap used inside
262 * the Atheros reference codebase.
263 */
264
265/* Bit 8 */
266#define ATH_RADIOTAP_VENDOR_HEADER 8
267
268/*
269 * Using four chains makes all the fields in the
270 * per-chain info header be 4-byte aligned.
271 */
272#define ATH_RADIOTAP_MAX_CHAINS 4
273
274/*
275 * The vendor radiotap header data needs to be:
276 *
277 * + Aligned to a 4 byte address
278 * + .. so all internal fields are 4 bytes aligned;
279 * + .. and no 64 bit fields are allowed.
280 *
281 * So padding is required to ensure this is the case.
282 *
283 * Note that because of the lack of alignment with the
284 * vendor header (6 bytes), the first field must be
285 * two bytes so it can be accessed by alignment-strict
286 * platform (eg MIPS.)
287 */
288struct ath_radiotap_vendor_hdr { /* 30 bytes */
289 uint8_t vh_version; /* 1 */
290 uint8_t vh_rx_chainmask; /* 1 */
291
292 /* At this point it should be 4 byte aligned */
293 uint32_t evm[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */
294
295 uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
296 uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */
297
298 uint8_t vh_phyerr_code; /* Phy error code, or 0xff */
299 uint8_t vh_rs_status; /* RX status */
300 uint8_t vh_rssi; /* Raw RSSI */
301 uint8_t vh_pad1[1]; /* Pad to 4 byte boundary */
302} __packed;
303#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
304
305struct ath_rx_radiotap_header {
306 struct ieee80211_radiotap_header wr_ihdr;
307
308#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
309 /* Vendor extension header bitmap */
310 uint32_t wr_ext_bitmap; /* 4 */
311
312 /*
313 * This padding is needed because:
314 * + the radiotap header is 8 bytes;
315 * + the extension bitmap is 4 bytes;
316 * + the tsf is 8 bytes, so it must start on an 8 byte
317 * boundary.
318 */
319 uint32_t wr_pad1;
320#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
321
322 /* Normal radiotap fields */
323 u_int64_t wr_tsf;
324 u_int8_t wr_flags;
325 u_int8_t wr_rate;
326 int8_t wr_antsignal;
327 int8_t wr_antnoise;
328 u_int8_t wr_antenna;
329 u_int8_t wr_pad[3];
330 u_int32_t wr_chan_flags;
331 u_int16_t wr_chan_freq;
332 u_int8_t wr_chan_ieee;
333 int8_t wr_chan_maxpow;
334
335#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
336 /*
337 * Vendor header section, as required by the
338 * presence of the vendor extension bit and bitmap
339 * entry.
340 *
341 * XXX This must be aligned to a 4 byte address?
342 * XXX or 8 byte address?
343 */
344 struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */
345
346 /*
347 * Because of the lack of alignment enforced by the above
348 * header, this vendor section won't be aligned in any
349 * useful way. So, this will include a two-byte version
350 * value which will force the structure to be 4-byte aligned.
351 */
352 struct ath_radiotap_vendor_hdr wr_v;
353#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
354} __packed;
355
356#define ATH_TX_RADIOTAP_PRESENT ( \
357 (1 << IEEE80211_RADIOTAP_TSFT) | \
358 (1 << IEEE80211_RADIOTAP_FLAGS) | \
359 (1 << IEEE80211_RADIOTAP_RATE) | \
360 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
361 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
362 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
363 0)
364
365struct ath_tx_radiotap_header {
366 struct ieee80211_radiotap_header wt_ihdr;
367 u_int64_t wt_tsf;
368 u_int8_t wt_flags;
369 u_int8_t wt_rate;
370 u_int8_t wt_txpower;
371 u_int8_t wt_antenna;
372 u_int32_t wt_chan_flags;
373 u_int16_t wt_chan_freq;
374 u_int8_t wt_chan_ieee;
375 int8_t wt_chan_maxpow;
376} __packed;
377
378/*
379 * DFS ioctl commands
380 */
381
382#define DFS_SET_THRESH 2
383#define DFS_GET_THRESH 3
384#define DFS_RADARDETECTS 6
385
386/*
387 * DFS ioctl parameter types
388 */
389#define DFS_PARAM_FIRPWR 1
390#define DFS_PARAM_RRSSI 2
391#define DFS_PARAM_HEIGHT 3
392#define DFS_PARAM_PRSSI 4
393#define DFS_PARAM_INBAND 5
394#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
395#define DFS_PARAM_RELSTEP_EN 7
396#define DFS_PARAM_RELSTEP 8
397#define DFS_PARAM_RELPWR_EN 9
398#define DFS_PARAM_RELPWR 10
399#define DFS_PARAM_MAXLEN 11
400#define DFS_PARAM_USEFIR128 12
401#define DFS_PARAM_BLOCKRADAR 13
402#define DFS_PARAM_MAXRSSI_EN 14
403
404/* FreeBSD-specific start at 32 */
405#define DFS_PARAM_ENABLE 32
406#define DFS_PARAM_EN_EXTCH 33
407
408#endif /* _DEV_ATH_ATHIOCTL_H */
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