1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 234090 2012-04-10 07:23:37Z adrian $
| 29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 236833 2012-06-10 06:42:18Z adrian $
|
30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_pad[1];
165};
166
167#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
168#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
| 30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_tx_aggr_stats {
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
47};
48
49struct ath_intr_stats {
50 u_int32_t sync_intr[32];
51};
52
53struct ath_stats {
54 u_int32_t ast_watchdog; /* device reset by watchdog */
55 u_int32_t ast_hardware; /* fatal hardware error interrupts */
56 u_int32_t ast_bmiss; /* beacon miss interrupts */
57 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
58 u_int32_t ast_bstuck; /* beacon stuck interrupts */
59 u_int32_t ast_rxorn; /* rx overrun interrupts */
60 u_int32_t ast_rxeol; /* rx eol interrupts */
61 u_int32_t ast_txurn; /* tx underrun interrupts */
62 u_int32_t ast_mib; /* mib interrupts */
63 u_int32_t ast_intrcoal; /* interrupts coalesced */
64 u_int32_t ast_tx_packets; /* packet sent on the interface */
65 u_int32_t ast_tx_mgmt; /* management frames transmitted */
66 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
67 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
68 u_int32_t ast_tx_encap; /* tx encapsulation failed */
69 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
70 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
71 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
72 u_int32_t ast_tx_linear; /* tx linearized to cluster */
73 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
74 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
75 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
76 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
77 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
78 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
79 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
80 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
81 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
82 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
83 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
84 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
85 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
86 u_int32_t ast_tx_protect; /* tx frames with protection */
87 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
88 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
89 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
90 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
91 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
92 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
93 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
94 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
95 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
96 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
97 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
98 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
99 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
100 u_int32_t ast_rx_packets; /* packet recv on the interface */
101 u_int32_t ast_rx_mgt; /* management frames received */
102 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
103 int8_t ast_tx_rssi; /* tx rssi of last ack */
104 int8_t ast_rx_rssi; /* rx rssi from histogram */
105 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
106 u_int32_t ast_be_xmit; /* beacons transmitted */
107 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
108 u_int32_t ast_per_cal; /* periodic calibration calls */
109 u_int32_t ast_per_calfail;/* periodic calibration failed */
110 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
111 u_int32_t ast_rate_calls; /* rate control checks */
112 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
113 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
114 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
115 u_int32_t ast_ant_txswitch;/* tx antenna switches */
116 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
117 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
118 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
119 u_int32_t ast_cabq_busy; /* cabq found busy */
120 u_int32_t ast_tx_raw; /* tx frames through raw api */
121 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
122 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
123 u_int32_t ast_ff_rx; /* fast frames rx'd */
124 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
125 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
126 int8_t ast_rx_noise; /* rx noise floor */
127 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
128 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
129 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
130 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
131 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
132 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
133 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
134 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
135 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
136 u_int32_t ast_be_missed; /* missed beacons */
137 u_int32_t ast_ani_cal; /* ANI calibrations performed */
138 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
139 u_int32_t ast_rx_halfgi; /* RX half-GI */
140 u_int32_t ast_rx_2040; /* RX 40mhz frame */
141 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
142 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
143 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
144 u_int32_t ast_rx_hi_rx_chain;
145 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
146 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
147 u_int32_t ast_tx_timeout; /* Global TX timeout */
148 u_int32_t ast_tx_cst; /* Carrier sense timeout */
149 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
150 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
151 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
152 u_int32_t ast_tx_swretries; /* software TX retries */
153 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
154 u_int32_t ast_tx_data_underrun;
155 u_int32_t ast_tx_delim_underrun;
156 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
157 u_int32_t ast_tx_getnobuf;
158 u_int32_t ast_tx_getbusybuf;
159 u_int32_t ast_tx_intr;
160 u_int32_t ast_rx_intr;
161 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
162 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
163 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
164 u_int32_t ast_pad[1];
165};
166
167#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
168#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
|
| 169#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq)
|
169
170struct ath_diag {
171 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
172 u_int16_t ad_id;
173#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
174#define ATH_DIAG_IN 0x4000 /* copy in parameters */
175#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
176#define ATH_DIAG_ID 0x0fff
177 u_int16_t ad_in_size; /* pack to fit, yech */
178 caddr_t ad_in_data;
179 caddr_t ad_out_data;
180 u_int ad_out_size;
181
182};
183#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
184#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
185
186/*
187 * Radio capture format.
188 */
189#define ATH_RX_RADIOTAP_PRESENT ( \
190 (1 << IEEE80211_RADIOTAP_TSFT) | \
191 (1 << IEEE80211_RADIOTAP_FLAGS) | \
192 (1 << IEEE80211_RADIOTAP_RATE) | \
193 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
194 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
195 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
196 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
197 0)
198
199struct ath_rx_radiotap_header {
200 struct ieee80211_radiotap_header wr_ihdr;
201 u_int64_t wr_tsf;
202 u_int8_t wr_flags;
203 u_int8_t wr_rate;
204 int8_t wr_antsignal;
205 int8_t wr_antnoise;
206 u_int8_t wr_antenna;
207 u_int8_t wr_pad[3];
208 u_int32_t wr_chan_flags;
209 u_int16_t wr_chan_freq;
210 u_int8_t wr_chan_ieee;
211 int8_t wr_chan_maxpow;
212} __packed;
213
214#define ATH_TX_RADIOTAP_PRESENT ( \
215 (1 << IEEE80211_RADIOTAP_TSFT) | \
216 (1 << IEEE80211_RADIOTAP_FLAGS) | \
217 (1 << IEEE80211_RADIOTAP_RATE) | \
218 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
219 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
220 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
221 0)
222
223struct ath_tx_radiotap_header {
224 struct ieee80211_radiotap_header wt_ihdr;
225 u_int64_t wt_tsf;
226 u_int8_t wt_flags;
227 u_int8_t wt_rate;
228 u_int8_t wt_txpower;
229 u_int8_t wt_antenna;
230 u_int32_t wt_chan_flags;
231 u_int16_t wt_chan_freq;
232 u_int8_t wt_chan_ieee;
233 int8_t wt_chan_maxpow;
234} __packed;
235
236/*
237 * DFS ioctl commands
238 */
239
240#define DFS_SET_THRESH 2
241#define DFS_GET_THRESH 3
242#define DFS_RADARDETECTS 6
243
244/*
245 * DFS ioctl parameter types
246 */
247#define DFS_PARAM_FIRPWR 1
248#define DFS_PARAM_RRSSI 2
249#define DFS_PARAM_HEIGHT 3
250#define DFS_PARAM_PRSSI 4
251#define DFS_PARAM_INBAND 5
252#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
253#define DFS_PARAM_RELSTEP_EN 7
254#define DFS_PARAM_RELSTEP 8
255#define DFS_PARAM_RELPWR_EN 9
256#define DFS_PARAM_RELPWR 10
257#define DFS_PARAM_MAXLEN 11
258#define DFS_PARAM_USEFIR128 12
259#define DFS_PARAM_BLOCKRADAR 13
260#define DFS_PARAM_MAXRSSI_EN 14
261
262/* FreeBSD-specific start at 32 */
263#define DFS_PARAM_ENABLE 32
264#define DFS_PARAM_EN_EXTCH 33
265
266#endif /* _DEV_ATH_ATHIOCTL_H */
| 170
171struct ath_diag {
172 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
173 u_int16_t ad_id;
174#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
175#define ATH_DIAG_IN 0x4000 /* copy in parameters */
176#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
177#define ATH_DIAG_ID 0x0fff
178 u_int16_t ad_in_size; /* pack to fit, yech */
179 caddr_t ad_in_data;
180 caddr_t ad_out_data;
181 u_int ad_out_size;
182
183};
184#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
185#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
186
187/*
188 * Radio capture format.
189 */
190#define ATH_RX_RADIOTAP_PRESENT ( \
191 (1 << IEEE80211_RADIOTAP_TSFT) | \
192 (1 << IEEE80211_RADIOTAP_FLAGS) | \
193 (1 << IEEE80211_RADIOTAP_RATE) | \
194 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
195 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
196 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
197 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
198 0)
199
200struct ath_rx_radiotap_header {
201 struct ieee80211_radiotap_header wr_ihdr;
202 u_int64_t wr_tsf;
203 u_int8_t wr_flags;
204 u_int8_t wr_rate;
205 int8_t wr_antsignal;
206 int8_t wr_antnoise;
207 u_int8_t wr_antenna;
208 u_int8_t wr_pad[3];
209 u_int32_t wr_chan_flags;
210 u_int16_t wr_chan_freq;
211 u_int8_t wr_chan_ieee;
212 int8_t wr_chan_maxpow;
213} __packed;
214
215#define ATH_TX_RADIOTAP_PRESENT ( \
216 (1 << IEEE80211_RADIOTAP_TSFT) | \
217 (1 << IEEE80211_RADIOTAP_FLAGS) | \
218 (1 << IEEE80211_RADIOTAP_RATE) | \
219 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
220 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
221 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
222 0)
223
224struct ath_tx_radiotap_header {
225 struct ieee80211_radiotap_header wt_ihdr;
226 u_int64_t wt_tsf;
227 u_int8_t wt_flags;
228 u_int8_t wt_rate;
229 u_int8_t wt_txpower;
230 u_int8_t wt_antenna;
231 u_int32_t wt_chan_flags;
232 u_int16_t wt_chan_freq;
233 u_int8_t wt_chan_ieee;
234 int8_t wt_chan_maxpow;
235} __packed;
236
237/*
238 * DFS ioctl commands
239 */
240
241#define DFS_SET_THRESH 2
242#define DFS_GET_THRESH 3
243#define DFS_RADARDETECTS 6
244
245/*
246 * DFS ioctl parameter types
247 */
248#define DFS_PARAM_FIRPWR 1
249#define DFS_PARAM_RRSSI 2
250#define DFS_PARAM_HEIGHT 3
251#define DFS_PARAM_PRSSI 4
252#define DFS_PARAM_INBAND 5
253#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
254#define DFS_PARAM_RELSTEP_EN 7
255#define DFS_PARAM_RELSTEP 8
256#define DFS_PARAM_RELPWR_EN 9
257#define DFS_PARAM_RELPWR 10
258#define DFS_PARAM_MAXLEN 11
259#define DFS_PARAM_USEFIR128 12
260#define DFS_PARAM_BLOCKRADAR 13
261#define DFS_PARAM_MAXRSSI_EN 14
262
263/* FreeBSD-specific start at 32 */
264#define DFS_PARAM_ENABLE 32
265#define DFS_PARAM_EN_EXTCH 33
266
267#endif /* _DEV_ATH_ATHIOCTL_H */
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