1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 218689 2011-02-14 21:24:54Z adrian $
| 29 * $FreeBSD: head/sys/dev/ath/if_athioctl.h 218924 2011-02-21 19:19:05Z adrian $
|
30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_stats {
39 u_int32_t ast_watchdog; /* device reset by watchdog */
40 u_int32_t ast_hardware; /* fatal hardware error interrupts */
41 u_int32_t ast_bmiss; /* beacon miss interrupts */
42 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
43 u_int32_t ast_bstuck; /* beacon stuck interrupts */
44 u_int32_t ast_rxorn; /* rx overrun interrupts */
45 u_int32_t ast_rxeol; /* rx eol interrupts */
46 u_int32_t ast_txurn; /* tx underrun interrupts */
47 u_int32_t ast_mib; /* mib interrupts */
48 u_int32_t ast_intrcoal; /* interrupts coalesced */
49 u_int32_t ast_tx_packets; /* packet sent on the interface */
50 u_int32_t ast_tx_mgmt; /* management frames transmitted */
51 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
52 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
53 u_int32_t ast_tx_encap; /* tx encapsulation failed */
54 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
55 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
56 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
57 u_int32_t ast_tx_linear; /* tx linearized to cluster */
58 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
59 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
60 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
61 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
62 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
63 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
64 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
65 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
66 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
67 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
68 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
69 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
70 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
71 u_int32_t ast_tx_protect; /* tx frames with protection */
72 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
73 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
74 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
75 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
76 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
77 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
78 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
79 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
80 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
81 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
82 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
83 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
84 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
85 u_int32_t ast_rx_packets; /* packet recv on the interface */
86 u_int32_t ast_rx_mgt; /* management frames received */
87 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
88 int8_t ast_tx_rssi; /* tx rssi of last ack */
89 int8_t ast_rx_rssi; /* rx rssi from histogram */
90 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
91 u_int32_t ast_be_xmit; /* beacons transmitted */
92 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
93 u_int32_t ast_per_cal; /* periodic calibration calls */
94 u_int32_t ast_per_calfail;/* periodic calibration failed */
95 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
96 u_int32_t ast_rate_calls; /* rate control checks */
97 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
98 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
99 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
100 u_int32_t ast_ant_txswitch;/* tx antenna switches */
101 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
102 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
103 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
104 u_int32_t ast_cabq_busy; /* cabq found busy */
105 u_int32_t ast_tx_raw; /* tx frames through raw api */
106 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
107 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
108 u_int32_t ast_ff_rx; /* fast frames rx'd */
109 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
110 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
111 int8_t ast_rx_noise; /* rx noise floor */
112 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
113 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
114 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
115 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
116 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
117 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
118 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
119 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
120 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
121 u_int32_t ast_be_missed; /* missed beacons */
122 u_int32_t ast_ani_cal; /* ANI calibrations performed */
123 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
124 u_int32_t ast_rx_halfgi;
125 u_int32_t ast_rx_2040;
126 u_int32_t ast_rx_pre_crc_err;
127 u_int32_t ast_rx_post_crc_err;
128 u_int32_t ast_rx_decrypt_busy_err;
129 u_int32_t ast_rx_hi_rx_chain;
| 30 */
31
32/*
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHIOCTL_H
36#define _DEV_ATH_ATHIOCTL_H
37
38struct ath_stats {
39 u_int32_t ast_watchdog; /* device reset by watchdog */
40 u_int32_t ast_hardware; /* fatal hardware error interrupts */
41 u_int32_t ast_bmiss; /* beacon miss interrupts */
42 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
43 u_int32_t ast_bstuck; /* beacon stuck interrupts */
44 u_int32_t ast_rxorn; /* rx overrun interrupts */
45 u_int32_t ast_rxeol; /* rx eol interrupts */
46 u_int32_t ast_txurn; /* tx underrun interrupts */
47 u_int32_t ast_mib; /* mib interrupts */
48 u_int32_t ast_intrcoal; /* interrupts coalesced */
49 u_int32_t ast_tx_packets; /* packet sent on the interface */
50 u_int32_t ast_tx_mgmt; /* management frames transmitted */
51 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
52 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
53 u_int32_t ast_tx_encap; /* tx encapsulation failed */
54 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
55 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
56 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
57 u_int32_t ast_tx_linear; /* tx linearized to cluster */
58 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
59 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
60 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
61 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
62 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
63 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
64 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
65 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
66 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
67 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
68 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
69 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
70 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
71 u_int32_t ast_tx_protect; /* tx frames with protection */
72 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
73 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
74 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
75 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
76 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
77 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
78 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
79 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
80 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
81 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
82 u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
83 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
84 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
85 u_int32_t ast_rx_packets; /* packet recv on the interface */
86 u_int32_t ast_rx_mgt; /* management frames received */
87 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
88 int8_t ast_tx_rssi; /* tx rssi of last ack */
89 int8_t ast_rx_rssi; /* rx rssi from histogram */
90 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
91 u_int32_t ast_be_xmit; /* beacons transmitted */
92 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
93 u_int32_t ast_per_cal; /* periodic calibration calls */
94 u_int32_t ast_per_calfail;/* periodic calibration failed */
95 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
96 u_int32_t ast_rate_calls; /* rate control checks */
97 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
98 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
99 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
100 u_int32_t ast_ant_txswitch;/* tx antenna switches */
101 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
102 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
103 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
104 u_int32_t ast_cabq_busy; /* cabq found busy */
105 u_int32_t ast_tx_raw; /* tx frames through raw api */
106 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
107 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
108 u_int32_t ast_ff_rx; /* fast frames rx'd */
109 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
110 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
111 int8_t ast_rx_noise; /* rx noise floor */
112 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
113 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
114 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
115 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
116 u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
117 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
118 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
119 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
120 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
121 u_int32_t ast_be_missed; /* missed beacons */
122 u_int32_t ast_ani_cal; /* ANI calibrations performed */
123 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
124 u_int32_t ast_rx_halfgi;
125 u_int32_t ast_rx_2040;
126 u_int32_t ast_rx_pre_crc_err;
127 u_int32_t ast_rx_post_crc_err;
128 u_int32_t ast_rx_decrypt_busy_err;
129 u_int32_t ast_rx_hi_rx_chain;
|
130 u_int32_t ast_pad[4];
| 130 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
131 u_int32_t ast_pad[3];
|
131};
132
133#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
134#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
135
136struct ath_diag {
137 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
138 u_int16_t ad_id;
139#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
140#define ATH_DIAG_IN 0x4000 /* copy in parameters */
141#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
142#define ATH_DIAG_ID 0x0fff
143 u_int16_t ad_in_size; /* pack to fit, yech */
144 caddr_t ad_in_data;
145 caddr_t ad_out_data;
146 u_int ad_out_size;
147
148};
149#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
150
151/*
152 * Radio capture format.
153 */
154#define ATH_RX_RADIOTAP_PRESENT ( \
155 (1 << IEEE80211_RADIOTAP_TSFT) | \
156 (1 << IEEE80211_RADIOTAP_FLAGS) | \
157 (1 << IEEE80211_RADIOTAP_RATE) | \
158 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
159 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
160 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
161 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
162 0)
163
164struct ath_rx_radiotap_header {
165 struct ieee80211_radiotap_header wr_ihdr;
166 u_int64_t wr_tsf;
167 u_int8_t wr_flags;
168 u_int8_t wr_rate;
169 int8_t wr_antsignal;
170 int8_t wr_antnoise;
171 u_int8_t wr_antenna;
172 u_int8_t wr_pad[3];
173 u_int32_t wr_chan_flags;
174 u_int16_t wr_chan_freq;
175 u_int8_t wr_chan_ieee;
176 int8_t wr_chan_maxpow;
177} __packed;
178
179#define ATH_TX_RADIOTAP_PRESENT ( \
180 (1 << IEEE80211_RADIOTAP_TSFT) | \
181 (1 << IEEE80211_RADIOTAP_FLAGS) | \
182 (1 << IEEE80211_RADIOTAP_RATE) | \
183 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
184 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
185 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
186 0)
187
188struct ath_tx_radiotap_header {
189 struct ieee80211_radiotap_header wt_ihdr;
190 u_int64_t wt_tsf;
191 u_int8_t wt_flags;
192 u_int8_t wt_rate;
193 u_int8_t wt_txpower;
194 u_int8_t wt_antenna;
195 u_int32_t wt_chan_flags;
196 u_int16_t wt_chan_freq;
197 u_int8_t wt_chan_ieee;
198 int8_t wt_chan_maxpow;
199} __packed;
200
201#endif /* _DEV_ATH_ATHIOCTL_H */
| 132};
133
134#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
135#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
136
137struct ath_diag {
138 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
139 u_int16_t ad_id;
140#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
141#define ATH_DIAG_IN 0x4000 /* copy in parameters */
142#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
143#define ATH_DIAG_ID 0x0fff
144 u_int16_t ad_in_size; /* pack to fit, yech */
145 caddr_t ad_in_data;
146 caddr_t ad_out_data;
147 u_int ad_out_size;
148
149};
150#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
151
152/*
153 * Radio capture format.
154 */
155#define ATH_RX_RADIOTAP_PRESENT ( \
156 (1 << IEEE80211_RADIOTAP_TSFT) | \
157 (1 << IEEE80211_RADIOTAP_FLAGS) | \
158 (1 << IEEE80211_RADIOTAP_RATE) | \
159 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
160 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
161 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
162 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
163 0)
164
165struct ath_rx_radiotap_header {
166 struct ieee80211_radiotap_header wr_ihdr;
167 u_int64_t wr_tsf;
168 u_int8_t wr_flags;
169 u_int8_t wr_rate;
170 int8_t wr_antsignal;
171 int8_t wr_antnoise;
172 u_int8_t wr_antenna;
173 u_int8_t wr_pad[3];
174 u_int32_t wr_chan_flags;
175 u_int16_t wr_chan_freq;
176 u_int8_t wr_chan_ieee;
177 int8_t wr_chan_maxpow;
178} __packed;
179
180#define ATH_TX_RADIOTAP_PRESENT ( \
181 (1 << IEEE80211_RADIOTAP_TSFT) | \
182 (1 << IEEE80211_RADIOTAP_FLAGS) | \
183 (1 << IEEE80211_RADIOTAP_RATE) | \
184 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
185 (1 << IEEE80211_RADIOTAP_ANTENNA) | \
186 (1 << IEEE80211_RADIOTAP_XCHANNEL) | \
187 0)
188
189struct ath_tx_radiotap_header {
190 struct ieee80211_radiotap_header wt_ihdr;
191 u_int64_t wt_tsf;
192 u_int8_t wt_flags;
193 u_int8_t wt_rate;
194 u_int8_t wt_txpower;
195 u_int8_t wt_antenna;
196 u_int32_t wt_chan_flags;
197 u_int16_t wt_chan_freq;
198 u_int8_t wt_chan_ieee;
199 int8_t wt_chan_maxpow;
200} __packed;
201
202#endif /* _DEV_ATH_ATHIOCTL_H */
|