1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
|
31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 232794 2012-03-10 19:58:23Z adrian $");
| 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 233227 2012-03-20 04:50:25Z adrian $");
|
32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42#include "opt_wlan.h"
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/sysctl.h>
47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/lock.h>
50#include <sys/mutex.h>
51#include <sys/kernel.h>
52#include <sys/socket.h>
53#include <sys/sockio.h>
54#include <sys/errno.h>
55#include <sys/callout.h>
56#include <sys/bus.h>
57#include <sys/endian.h>
58#include <sys/kthread.h>
59#include <sys/taskqueue.h>
60#include <sys/priv.h>
61
62#include <machine/bus.h>
63
64#include <net/if.h>
65#include <net/if_dl.h>
66#include <net/if_media.h>
67#include <net/if_types.h>
68#include <net/if_arp.h>
69#include <net/ethernet.h>
70#include <net/if_llc.h>
71
72#include <net80211/ieee80211_var.h>
73#include <net80211/ieee80211_regdomain.h>
74#ifdef IEEE80211_SUPPORT_SUPERG
75#include <net80211/ieee80211_superg.h>
76#endif
77#ifdef IEEE80211_SUPPORT_TDMA
78#include <net80211/ieee80211_tdma.h>
79#endif
80#include <net80211/ieee80211_ht.h>
81
82#include <net/bpf.h>
83
84#ifdef INET
85#include <netinet/in.h>
86#include <netinet/if_ether.h>
87#endif
88
89#include <dev/ath/if_athvar.h>
90#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
91#include <dev/ath/ath_hal/ah_diagcodes.h>
92
93#include <dev/ath/if_ath_debug.h>
94
95#ifdef ATH_TX99_DIAG
96#include <dev/ath/ath_tx99/ath_tx99.h>
97#endif
98
99#include <dev/ath/if_ath_misc.h>
100#include <dev/ath/if_ath_tx.h>
101#include <dev/ath/if_ath_tx_ht.h>
102
103/*
104 * How many retries to perform in software
105 */
106#define SWMAX_RETRIES 10
107
108static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an,
109 int tid);
110static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an,
111 int tid);
| 32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42#include "opt_wlan.h"
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/sysctl.h>
47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/lock.h>
50#include <sys/mutex.h>
51#include <sys/kernel.h>
52#include <sys/socket.h>
53#include <sys/sockio.h>
54#include <sys/errno.h>
55#include <sys/callout.h>
56#include <sys/bus.h>
57#include <sys/endian.h>
58#include <sys/kthread.h>
59#include <sys/taskqueue.h>
60#include <sys/priv.h>
61
62#include <machine/bus.h>
63
64#include <net/if.h>
65#include <net/if_dl.h>
66#include <net/if_media.h>
67#include <net/if_types.h>
68#include <net/if_arp.h>
69#include <net/ethernet.h>
70#include <net/if_llc.h>
71
72#include <net80211/ieee80211_var.h>
73#include <net80211/ieee80211_regdomain.h>
74#ifdef IEEE80211_SUPPORT_SUPERG
75#include <net80211/ieee80211_superg.h>
76#endif
77#ifdef IEEE80211_SUPPORT_TDMA
78#include <net80211/ieee80211_tdma.h>
79#endif
80#include <net80211/ieee80211_ht.h>
81
82#include <net/bpf.h>
83
84#ifdef INET
85#include <netinet/in.h>
86#include <netinet/if_ether.h>
87#endif
88
89#include <dev/ath/if_athvar.h>
90#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
91#include <dev/ath/ath_hal/ah_diagcodes.h>
92
93#include <dev/ath/if_ath_debug.h>
94
95#ifdef ATH_TX99_DIAG
96#include <dev/ath/ath_tx99/ath_tx99.h>
97#endif
98
99#include <dev/ath/if_ath_misc.h>
100#include <dev/ath/if_ath_tx.h>
101#include <dev/ath/if_ath_tx_ht.h>
102
103/*
104 * How many retries to perform in software
105 */
106#define SWMAX_RETRIES 10
107
108static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an,
109 int tid);
110static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an,
111 int tid);
|
112static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc,
113 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0);
| |
114static int ath_tx_action_frame_override_queue(struct ath_softc *sc,
115 struct ieee80211_node *ni, struct mbuf *m0, int *tid);
| 112static int ath_tx_action_frame_override_queue(struct ath_softc *sc,
113 struct ieee80211_node *ni, struct mbuf *m0, int *tid);
|
| 114static int ath_tx_seqno_required(struct ath_softc *sc,
115 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0);
|
116
117/*
118 * Whether to use the 11n rate scenario functions or not
119 */
120static inline int
121ath_tx_is_11n(struct ath_softc *sc)
122{
123 return (sc->sc_ah->ah_magic == 0x20065416);
124}
125
126/*
127 * Obtain the current TID from the given frame.
128 *
129 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.)
130 * This has implications for which AC/priority the packet is placed
131 * in.
132 */
133static int
134ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0)
135{
136 const struct ieee80211_frame *wh;
137 int pri = M_WME_GETAC(m0);
138
139 wh = mtod(m0, const struct ieee80211_frame *);
140 if (! IEEE80211_QOS_HAS_SEQ(wh))
141 return IEEE80211_NONQOS_TID;
142 else
143 return WME_AC_TO_TID(pri);
144}
145
146/*
147 * Determine what the correct AC queue for the given frame
148 * should be.
149 *
150 * This code assumes that the TIDs map consistently to
151 * the underlying hardware (or software) ath_txq.
152 * Since the sender may try to set an AC which is
153 * arbitrary, non-QoS TIDs may end up being put on
154 * completely different ACs. There's no way to put a
155 * TID into multiple ath_txq's for scheduling, so
156 * for now we override the AC/TXQ selection and set
157 * non-QOS TID frames into the BE queue.
158 *
159 * This may be completely incorrect - specifically,
160 * some management frames may end up out of order
161 * compared to the QoS traffic they're controlling.
162 * I'll look into this later.
163 */
164static int
165ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0)
166{
167 const struct ieee80211_frame *wh;
168 int pri = M_WME_GETAC(m0);
169 wh = mtod(m0, const struct ieee80211_frame *);
170 if (IEEE80211_QOS_HAS_SEQ(wh))
171 return pri;
172
173 return WME_AC_BE;
174}
175
176void
177ath_txfrag_cleanup(struct ath_softc *sc,
178 ath_bufhead *frags, struct ieee80211_node *ni)
179{
180 struct ath_buf *bf, *next;
181
182 ATH_TXBUF_LOCK_ASSERT(sc);
183
184 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
185 /* NB: bf assumed clean */
186 TAILQ_REMOVE(frags, bf, bf_list);
187 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
188 ieee80211_node_decref(ni);
189 }
190}
191
192/*
193 * Setup xmit of a fragmented frame. Allocate a buffer
194 * for each frag and bump the node reference count to
195 * reflect the held reference to be setup by ath_tx_start.
196 */
197int
198ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
199 struct mbuf *m0, struct ieee80211_node *ni)
200{
201 struct mbuf *m;
202 struct ath_buf *bf;
203
204 ATH_TXBUF_LOCK(sc);
205 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
206 bf = _ath_getbuf_locked(sc);
207 if (bf == NULL) { /* out of buffers, cleanup */
208 ath_txfrag_cleanup(sc, frags, ni);
209 break;
210 }
211 ieee80211_node_incref(ni);
212 TAILQ_INSERT_TAIL(frags, bf, bf_list);
213 }
214 ATH_TXBUF_UNLOCK(sc);
215
216 return !TAILQ_EMPTY(frags);
217}
218
219/*
220 * Reclaim mbuf resources. For fragmented frames we
221 * need to claim each frag chained with m_nextpkt.
222 */
223void
224ath_freetx(struct mbuf *m)
225{
226 struct mbuf *next;
227
228 do {
229 next = m->m_nextpkt;
230 m->m_nextpkt = NULL;
231 m_freem(m);
232 } while ((m = next) != NULL);
233}
234
235static int
236ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
237{
238 struct mbuf *m;
239 int error;
240
241 /*
242 * Load the DMA map so any coalescing is done. This
243 * also calculates the number of descriptors we need.
244 */
245 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
246 bf->bf_segs, &bf->bf_nseg,
247 BUS_DMA_NOWAIT);
248 if (error == EFBIG) {
249 /* XXX packet requires too many descriptors */
250 bf->bf_nseg = ATH_TXDESC+1;
251 } else if (error != 0) {
252 sc->sc_stats.ast_tx_busdma++;
253 ath_freetx(m0);
254 return error;
255 }
256 /*
257 * Discard null packets and check for packets that
258 * require too many TX descriptors. We try to convert
259 * the latter to a cluster.
260 */
261 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
262 sc->sc_stats.ast_tx_linear++;
263 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
264 if (m == NULL) {
265 ath_freetx(m0);
266 sc->sc_stats.ast_tx_nombuf++;
267 return ENOMEM;
268 }
269 m0 = m;
270 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
271 bf->bf_segs, &bf->bf_nseg,
272 BUS_DMA_NOWAIT);
273 if (error != 0) {
274 sc->sc_stats.ast_tx_busdma++;
275 ath_freetx(m0);
276 return error;
277 }
278 KASSERT(bf->bf_nseg <= ATH_TXDESC,
279 ("too many segments after defrag; nseg %u", bf->bf_nseg));
280 } else if (bf->bf_nseg == 0) { /* null packet, discard */
281 sc->sc_stats.ast_tx_nodata++;
282 ath_freetx(m0);
283 return EIO;
284 }
285 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
286 __func__, m0, m0->m_pkthdr.len);
287 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
288 bf->bf_m = m0;
289
290 return 0;
291}
292
293/*
294 * Chain together segments+descriptors for a non-11n frame.
295 */
296static void
297ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf)
298{
299 struct ath_hal *ah = sc->sc_ah;
300 struct ath_desc *ds, *ds0;
301 int i;
302
303 /*
304 * Fillin the remainder of the descriptor info.
305 */
306 ds0 = ds = bf->bf_desc;
307 for (i = 0; i < bf->bf_nseg; i++, ds++) {
308 ds->ds_data = bf->bf_segs[i].ds_addr;
309 if (i == bf->bf_nseg - 1)
310 ds->ds_link = 0;
311 else
312 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
313 ath_hal_filltxdesc(ah, ds
314 , bf->bf_segs[i].ds_len /* segment length */
315 , i == 0 /* first segment */
316 , i == bf->bf_nseg - 1 /* last segment */
317 , ds0 /* first descriptor */
318 );
319 DPRINTF(sc, ATH_DEBUG_XMIT,
320 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
321 __func__, i, ds->ds_link, ds->ds_data,
322 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
323 bf->bf_lastds = ds;
324 }
325}
326
327/*
328 * Fill in the descriptor list for a aggregate subframe.
329 *
330 * The subframe is returned with the ds_link field in the last subframe
331 * pointing to 0.
332 */
333static void
334ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf)
335{
336 struct ath_hal *ah = sc->sc_ah;
337 struct ath_desc *ds, *ds0;
338 int i;
339
340 ds0 = ds = bf->bf_desc;
341
342 /*
343 * There's no need to call ath_hal_setupfirsttxdesc here;
344 * That's only going to occur for the first frame in an aggregate.
345 */
346 for (i = 0; i < bf->bf_nseg; i++, ds++) {
347 ds->ds_data = bf->bf_segs[i].ds_addr;
348 if (i == bf->bf_nseg - 1)
349 ds->ds_link = 0;
350 else
351 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
352
353 /*
354 * This performs the setup for an aggregate frame.
355 * This includes enabling the aggregate flags if needed.
356 */
357 ath_hal_chaintxdesc(ah, ds,
358 bf->bf_state.bfs_pktlen,
359 bf->bf_state.bfs_hdrlen,
360 HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */
361 bf->bf_state.bfs_keyix,
362 0, /* cipher, calculated from keyix */
363 bf->bf_state.bfs_ndelim,
364 bf->bf_segs[i].ds_len, /* segment length */
365 i == 0, /* first segment */
366 i == bf->bf_nseg - 1 /* last segment */
367 );
368
369 DPRINTF(sc, ATH_DEBUG_XMIT,
370 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
371 __func__, i, ds->ds_link, ds->ds_data,
372 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
373 bf->bf_lastds = ds;
374 }
375}
376
377/*
378 * Setup segments+descriptors for an 11n aggregate.
379 * bf_first is the first buffer in the aggregate.
380 * The descriptor list must already been linked together using
381 * bf->bf_next.
382 */
383static void
384ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first)
385{
386 struct ath_buf *bf, *bf_prev = NULL;
387
388 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n",
389 __func__, bf_first->bf_state.bfs_nframes,
390 bf_first->bf_state.bfs_al);
391
392 /*
393 * Setup all descriptors of all subframes.
394 */
395 bf = bf_first;
396 while (bf != NULL) {
397 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
398 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n",
399 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen,
400 SEQNO(bf->bf_state.bfs_seqno));
401
402 /* Sub-frame setup */
403 ath_tx_chaindesclist_subframe(sc, bf);
404
405 /*
406 * Link the last descriptor of the previous frame
407 * to the beginning descriptor of this frame.
408 */
409 if (bf_prev != NULL)
410 bf_prev->bf_lastds->ds_link = bf->bf_daddr;
411
412 /* Save a copy so we can link the next descriptor in */
413 bf_prev = bf;
414 bf = bf->bf_next;
415 }
416
417 /*
418 * Setup first descriptor of first frame.
419 * chaintxdesc() overwrites the descriptor entries;
420 * setupfirsttxdesc() merges in things.
421 * Otherwise various fields aren't set correctly (eg flags).
422 */
423 ath_hal_setupfirsttxdesc(sc->sc_ah,
424 bf_first->bf_desc,
425 bf_first->bf_state.bfs_al,
426 bf_first->bf_state.bfs_flags | HAL_TXDESC_INTREQ,
427 bf_first->bf_state.bfs_txpower,
428 bf_first->bf_state.bfs_txrate0,
429 bf_first->bf_state.bfs_try0,
430 bf_first->bf_state.bfs_txantenna,
431 bf_first->bf_state.bfs_ctsrate,
432 bf_first->bf_state.bfs_ctsduration);
433
434 /*
435 * Setup the last descriptor in the list.
436 * bf_prev points to the last; bf is NULL here.
437 */
438 ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_desc,
439 bf_first->bf_desc);
440
441 /*
442 * Set the first descriptor bf_lastds field to point to
443 * the last descriptor in the last subframe, that's where
444 * the status update will occur.
445 */
446 bf_first->bf_lastds = bf_prev->bf_lastds;
447
448 /*
449 * And bf_last in the first descriptor points to the end of
450 * the aggregate list.
451 */
452 bf_first->bf_last = bf_prev;
453
454 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__);
455}
456
457static void
458ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
459 struct ath_buf *bf)
460{
461 ATH_TXQ_LOCK_ASSERT(txq);
462 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
463 ("%s: busy status 0x%x", __func__, bf->bf_flags));
464 if (txq->axq_link != NULL) {
465 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s);
466 struct ieee80211_frame *wh;
467
468 /* mark previous frame */
469 wh = mtod(last->bf_m, struct ieee80211_frame *);
470 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
471 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
472 BUS_DMASYNC_PREWRITE);
473
474 /* link descriptor */
475 *txq->axq_link = bf->bf_daddr;
476 }
477 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
478 txq->axq_link = &bf->bf_lastds->ds_link;
479}
480
481/*
482 * Hand-off packet to a hardware queue.
483 */
484static void
485ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
486 struct ath_buf *bf)
487{
488 struct ath_hal *ah = sc->sc_ah;
489
490 /*
491 * Insert the frame on the outbound list and pass it on
492 * to the hardware. Multicast frames buffered for power
493 * save stations and transmit from the CAB queue are stored
494 * on a s/w only queue and loaded on to the CAB queue in
495 * the SWBA handler since frames only go out on DTIM and
496 * to avoid possible races.
497 */
498 ATH_TXQ_LOCK_ASSERT(txq);
499 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
500 ("%s: busy status 0x%x", __func__, bf->bf_flags));
501 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ,
502 ("ath_tx_handoff_hw called for mcast queue"));
503
504#if 0
505 /*
506 * This causes a LOR. Find out where the PCU lock is being
507 * held whilst the TXQ lock is grabbed - that shouldn't
508 * be occuring.
509 */
510 ATH_PCU_LOCK(sc);
511 if (sc->sc_inreset_cnt) {
512 ATH_PCU_UNLOCK(sc);
513 DPRINTF(sc, ATH_DEBUG_RESET,
514 "%s: called with sc_in_reset != 0\n",
515 __func__);
516 DPRINTF(sc, ATH_DEBUG_XMIT,
517 "%s: queued: TXDP[%u] = %p (%p) depth %d\n",
518 __func__, txq->axq_qnum,
519 (caddr_t)bf->bf_daddr, bf->bf_desc,
520 txq->axq_depth);
521 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
522 if (bf->bf_state.bfs_aggr)
523 txq->axq_aggr_depth++;
524 /*
525 * There's no need to update axq_link; the hardware
526 * is in reset and once the reset is complete, any
527 * non-empty queues will simply have DMA restarted.
528 */
529 return;
530 }
531 ATH_PCU_UNLOCK(sc);
532#endif
533
534 /* For now, so not to generate whitespace diffs */
535 if (1) {
536#ifdef IEEE80211_SUPPORT_TDMA
537 int qbusy;
538
539 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
540 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
541 if (txq->axq_link == NULL) {
542 /*
543 * Be careful writing the address to TXDP. If
544 * the tx q is enabled then this write will be
545 * ignored. Normally this is not an issue but
546 * when tdma is in use and the q is beacon gated
547 * this race can occur. If the q is busy then
548 * defer the work to later--either when another
549 * packet comes along or when we prepare a beacon
550 * frame at SWBA.
551 */
552 if (!qbusy) {
553 ath_hal_puttxbuf(ah, txq->axq_qnum,
554 bf->bf_daddr);
555 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
556 DPRINTF(sc, ATH_DEBUG_XMIT,
557 "%s: TXDP[%u] = %p (%p) depth %d\n",
558 __func__, txq->axq_qnum,
559 (caddr_t)bf->bf_daddr, bf->bf_desc,
560 txq->axq_depth);
561 } else {
562 txq->axq_flags |= ATH_TXQ_PUTPENDING;
563 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
564 "%s: Q%u busy, defer enable\n", __func__,
565 txq->axq_qnum);
566 }
567 } else {
568 *txq->axq_link = bf->bf_daddr;
569 DPRINTF(sc, ATH_DEBUG_XMIT,
570 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
571 txq->axq_qnum, txq->axq_link,
572 (caddr_t)bf->bf_daddr, bf->bf_desc,
573 txq->axq_depth);
574 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
575 /*
576 * The q was busy when we previously tried
577 * to write the address of the first buffer
578 * in the chain. Since it's not busy now
579 * handle this chore. We are certain the
580 * buffer at the front is the right one since
581 * axq_link is NULL only when the buffer list
582 * is/was empty.
583 */
584 ath_hal_puttxbuf(ah, txq->axq_qnum,
585 TAILQ_FIRST(&txq->axq_q)->bf_daddr);
586 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
587 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
588 "%s: Q%u restarted\n", __func__,
589 txq->axq_qnum);
590 }
591 }
592#else
593 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
594 if (txq->axq_link == NULL) {
595 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
596 DPRINTF(sc, ATH_DEBUG_XMIT,
597 "%s: TXDP[%u] = %p (%p) depth %d\n",
598 __func__, txq->axq_qnum,
599 (caddr_t)bf->bf_daddr, bf->bf_desc,
600 txq->axq_depth);
601 } else {
602 *txq->axq_link = bf->bf_daddr;
603 DPRINTF(sc, ATH_DEBUG_XMIT,
604 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
605 txq->axq_qnum, txq->axq_link,
606 (caddr_t)bf->bf_daddr, bf->bf_desc,
607 txq->axq_depth);
608 }
609#endif /* IEEE80211_SUPPORT_TDMA */
610 if (bf->bf_state.bfs_aggr)
611 txq->axq_aggr_depth++;
612 txq->axq_link = &bf->bf_lastds->ds_link;
613 ath_hal_txstart(ah, txq->axq_qnum);
614 }
615}
616
617/*
618 * Restart TX DMA for the given TXQ.
619 *
620 * This must be called whether the queue is empty or not.
621 */
622void
623ath_txq_restart_dma(struct ath_softc *sc, struct ath_txq *txq)
624{
625 struct ath_hal *ah = sc->sc_ah;
626 struct ath_buf *bf, *bf_last;
627
628 ATH_TXQ_LOCK_ASSERT(txq);
629
630 /* This is always going to be cleared, empty or not */
631 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
632
633 /* XXX make this ATH_TXQ_FIRST */
634 bf = TAILQ_FIRST(&txq->axq_q);
635 bf_last = ATH_TXQ_LAST(txq, axq_q_s);
636
637 if (bf == NULL)
638 return;
639
640 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
641 txq->axq_link = &bf_last->bf_lastds->ds_link;
642 ath_hal_txstart(ah, txq->axq_qnum);
643}
644
645/*
646 * Hand off a packet to the hardware (or mcast queue.)
647 *
648 * The relevant hardware txq should be locked.
649 */
650static void
651ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
652{
653 ATH_TXQ_LOCK_ASSERT(txq);
654
655 if (txq->axq_qnum == ATH_TXQ_SWQ)
656 ath_tx_handoff_mcast(sc, txq, bf);
657 else
658 ath_tx_handoff_hw(sc, txq, bf);
659}
660
661static int
662ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni,
663 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen,
664 int *keyix)
665{
666 if (iswep) {
667 const struct ieee80211_cipher *cip;
668 struct ieee80211_key *k;
669
670 /*
671 * Construct the 802.11 header+trailer for an encrypted
672 * frame. The only reason this can fail is because of an
673 * unknown or unsupported cipher/key type.
674 */
675 k = ieee80211_crypto_encap(ni, m0);
676 if (k == NULL) {
677 /*
678 * This can happen when the key is yanked after the
679 * frame was queued. Just discard the frame; the
680 * 802.11 layer counts failures and provides
681 * debugging/diagnostics.
682 */
683 return (0);
684 }
685 /*
686 * Adjust the packet + header lengths for the crypto
687 * additions and calculate the h/w key index. When
688 * a s/w mic is done the frame will have had any mic
689 * added to it prior to entry so m0->m_pkthdr.len will
690 * account for it. Otherwise we need to add it to the
691 * packet length.
692 */
693 cip = k->wk_cipher;
694 (*hdrlen) += cip->ic_header;
695 (*pktlen) += cip->ic_header + cip->ic_trailer;
696 /* NB: frags always have any TKIP MIC done in s/w */
697 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
698 (*pktlen) += cip->ic_miclen;
699 (*keyix) = k->wk_keyix;
700 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
701 /*
702 * Use station key cache slot, if assigned.
703 */
704 (*keyix) = ni->ni_ucastkey.wk_keyix;
705 if ((*keyix) == IEEE80211_KEYIX_NONE)
706 (*keyix) = HAL_TXKEYIX_INVALID;
707 } else
708 (*keyix) = HAL_TXKEYIX_INVALID;
709
710 return (1);
711}
712
713static uint8_t
714ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
715 int cix, int shortPreamble)
716{
717 uint8_t ctsrate;
718
719 /*
720 * CTS transmit rate is derived from the transmit rate
721 * by looking in the h/w rate table. We must also factor
722 * in whether or not a short preamble is to be used.
723 */
724 /* NB: cix is set above where RTS/CTS is enabled */
725 KASSERT(cix != 0xff, ("cix not setup"));
726 ctsrate = rt->info[cix].rateCode;
727
728 /* XXX this should only matter for legacy rates */
729 if (shortPreamble)
730 ctsrate |= rt->info[cix].shortPreamble;
731
732 return (ctsrate);
733}
734
735/*
736 * Calculate the RTS/CTS duration for legacy frames.
737 */
738static int
739ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix,
740 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt,
741 int flags)
742{
743 int ctsduration = 0;
744
745 /* This mustn't be called for HT modes */
746 if (rt->info[cix].phy == IEEE80211_T_HT) {
747 printf("%s: HT rate where it shouldn't be (0x%x)\n",
748 __func__, rt->info[cix].rateCode);
749 return (-1);
750 }
751
752 /*
753 * Compute the transmit duration based on the frame
754 * size and the size of an ACK frame. We call into the
755 * HAL to do the computation since it depends on the
756 * characteristics of the actual PHY being used.
757 *
758 * NB: CTS is assumed the same size as an ACK so we can
759 * use the precalculated ACK durations.
760 */
761 if (shortPreamble) {
762 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
763 ctsduration += rt->info[cix].spAckDuration;
764 ctsduration += ath_hal_computetxtime(ah,
765 rt, pktlen, rix, AH_TRUE);
766 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
767 ctsduration += rt->info[rix].spAckDuration;
768 } else {
769 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
770 ctsduration += rt->info[cix].lpAckDuration;
771 ctsduration += ath_hal_computetxtime(ah,
772 rt, pktlen, rix, AH_FALSE);
773 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
774 ctsduration += rt->info[rix].lpAckDuration;
775 }
776
777 return (ctsduration);
778}
779
780/*
781 * Update the given ath_buf with updated rts/cts setup and duration
782 * values.
783 *
784 * To support rate lookups for each software retry, the rts/cts rate
785 * and cts duration must be re-calculated.
786 *
787 * This function assumes the RTS/CTS flags have been set as needed;
788 * mrr has been disabled; and the rate control lookup has been done.
789 *
790 * XXX TODO: MRR need only be disabled for the pre-11n NICs.
791 * XXX The 11n NICs support per-rate RTS/CTS configuration.
792 */
793static void
794ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf)
795{
796 uint16_t ctsduration = 0;
797 uint8_t ctsrate = 0;
798 uint8_t rix = bf->bf_state.bfs_rc[0].rix;
799 uint8_t cix = 0;
800 const HAL_RATE_TABLE *rt = sc->sc_currates;
801
802 /*
803 * No RTS/CTS enabled? Don't bother.
804 */
805 if ((bf->bf_state.bfs_flags &
806 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) {
807 /* XXX is this really needed? */
808 bf->bf_state.bfs_ctsrate = 0;
809 bf->bf_state.bfs_ctsduration = 0;
810 return;
811 }
812
813 /*
814 * If protection is enabled, use the protection rix control
815 * rate. Otherwise use the rate0 control rate.
816 */
817 if (bf->bf_state.bfs_doprot)
818 rix = sc->sc_protrix;
819 else
820 rix = bf->bf_state.bfs_rc[0].rix;
821
822 /*
823 * If the raw path has hard-coded ctsrate0 to something,
824 * use it.
825 */
826 if (bf->bf_state.bfs_ctsrate0 != 0)
827 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0);
828 else
829 /* Control rate from above */
830 cix = rt->info[rix].controlRate;
831
832 /* Calculate the rtscts rate for the given cix */
833 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix,
834 bf->bf_state.bfs_shpream);
835
836 /* The 11n chipsets do ctsduration calculations for you */
837 if (! ath_tx_is_11n(sc))
838 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix,
839 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen,
840 rt, bf->bf_state.bfs_flags);
841
842 /* Squirrel away in ath_buf */
843 bf->bf_state.bfs_ctsrate = ctsrate;
844 bf->bf_state.bfs_ctsduration = ctsduration;
845
846 /*
847 * Must disable multi-rate retry when using RTS/CTS.
848 * XXX TODO: only for pre-11n NICs.
849 */
850 bf->bf_state.bfs_ismrr = 0;
851 bf->bf_state.bfs_try0 =
852 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */
853}
854
855/*
856 * Setup the descriptor chain for a normal or fast-frame
857 * frame.
858 */
859static void
860ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf)
861{
862 struct ath_desc *ds = bf->bf_desc;
863 struct ath_hal *ah = sc->sc_ah;
864
865 ath_hal_setuptxdesc(ah, ds
866 , bf->bf_state.bfs_pktlen /* packet length */
867 , bf->bf_state.bfs_hdrlen /* header length */
868 , bf->bf_state.bfs_atype /* Atheros packet type */
869 , bf->bf_state.bfs_txpower /* txpower */
870 , bf->bf_state.bfs_txrate0
871 , bf->bf_state.bfs_try0 /* series 0 rate/tries */
872 , bf->bf_state.bfs_keyix /* key cache index */
873 , bf->bf_state.bfs_txantenna /* antenna mode */
874 , bf->bf_state.bfs_flags /* flags */
875 , bf->bf_state.bfs_ctsrate /* rts/cts rate */
876 , bf->bf_state.bfs_ctsduration /* rts/cts duration */
877 );
878
879 /*
880 * This will be overriden when the descriptor chain is written.
881 */
882 bf->bf_lastds = ds;
883 bf->bf_last = bf;
884
885 /* XXX TODO: Setup descriptor chain */
886}
887
888/*
889 * Do a rate lookup.
890 *
891 * This performs a rate lookup for the given ath_buf only if it's required.
892 * Non-data frames and raw frames don't require it.
893 *
894 * This populates the primary and MRR entries; MRR values are
895 * then disabled later on if something requires it (eg RTS/CTS on
896 * pre-11n chipsets.
897 *
898 * This needs to be done before the RTS/CTS fields are calculated
899 * as they may depend upon the rate chosen.
900 */
901static void
902ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf)
903{
904 uint8_t rate, rix;
905 int try0;
906
907 if (! bf->bf_state.bfs_doratelookup)
908 return;
909
910 /* Get rid of any previous state */
911 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
912
913 ATH_NODE_LOCK(ATH_NODE(bf->bf_node));
914 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream,
915 bf->bf_state.bfs_pktlen, &rix, &try0, &rate);
916
917 /* In case MRR is disabled, make sure rc[0] is setup correctly */
918 bf->bf_state.bfs_rc[0].rix = rix;
919 bf->bf_state.bfs_rc[0].ratecode = rate;
920 bf->bf_state.bfs_rc[0].tries = try0;
921
922 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY)
923 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix,
924 bf->bf_state.bfs_rc);
925 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node));
926
927 sc->sc_txrix = rix; /* for LED blinking */
928 sc->sc_lastdatarix = rix; /* for fast frames */
929 bf->bf_state.bfs_try0 = try0;
930 bf->bf_state.bfs_txrate0 = rate;
931}
932
933/*
934 * Set the rate control fields in the given descriptor based on
935 * the bf_state fields and node state.
936 *
937 * The bfs fields should already be set with the relevant rate
938 * control information, including whether MRR is to be enabled.
939 *
940 * Since the FreeBSD HAL currently sets up the first TX rate
941 * in ath_hal_setuptxdesc(), this will setup the MRR
942 * conditionally for the pre-11n chips, and call ath_buf_set_rate
943 * unconditionally for 11n chips. These require the 11n rate
944 * scenario to be set if MCS rates are enabled, so it's easier
945 * to just always call it. The caller can then only set rates 2, 3
946 * and 4 if multi-rate retry is needed.
947 */
948static void
949ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
950 struct ath_buf *bf)
951{
952 struct ath_rc_series *rc = bf->bf_state.bfs_rc;
953
954 /* If mrr is disabled, blank tries 1, 2, 3 */
955 if (! bf->bf_state.bfs_ismrr)
956 rc[1].tries = rc[2].tries = rc[3].tries = 0;
957
958 /*
959 * Always call - that way a retried descriptor will
960 * have the MRR fields overwritten.
961 *
962 * XXX TODO: see if this is really needed - setting up
963 * the first descriptor should set the MRR fields to 0
964 * for us anyway.
965 */
966 if (ath_tx_is_11n(sc)) {
967 ath_buf_set_rate(sc, ni, bf);
968 } else {
969 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc
970 , rc[1].ratecode, rc[1].tries
971 , rc[2].ratecode, rc[2].tries
972 , rc[3].ratecode, rc[3].tries
973 );
974 }
975}
976
977/*
978 * Transmit the given frame to the hardware.
979 *
980 * The frame must already be setup; rate control must already have
981 * been done.
982 *
983 * XXX since the TXQ lock is being held here (and I dislike holding
984 * it for this long when not doing software aggregation), later on
985 * break this function into "setup_normal" and "xmit_normal". The
986 * lock only needs to be held for the ath_tx_handoff call.
987 */
988static void
989ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq,
990 struct ath_buf *bf)
991{
992
993 ATH_TXQ_LOCK_ASSERT(txq);
994
995 /* Setup the descriptor before handoff */
996 ath_tx_do_ratelookup(sc, bf);
997 ath_tx_rate_fill_rcflags(sc, bf);
998 ath_tx_set_rtscts(sc, bf);
999 ath_tx_setds(sc, bf);
1000 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
1001 ath_tx_chaindesclist(sc, bf);
1002
1003 /* Hand off to hardware */
1004 ath_tx_handoff(sc, txq, bf);
1005}
1006
1007
1008
1009static int
1010ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
1011 struct ath_buf *bf, struct mbuf *m0)
1012{
1013 struct ieee80211vap *vap = ni->ni_vap;
1014 struct ath_vap *avp = ATH_VAP(vap);
1015 struct ath_hal *ah = sc->sc_ah;
1016 struct ifnet *ifp = sc->sc_ifp;
1017 struct ieee80211com *ic = ifp->if_l2com;
1018 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
1019 int error, iswep, ismcast, isfrag, ismrr;
1020 int keyix, hdrlen, pktlen, try0 = 0;
1021 u_int8_t rix = 0, txrate = 0;
1022 struct ath_desc *ds;
1023 struct ath_txq *txq;
1024 struct ieee80211_frame *wh;
1025 u_int subtype, flags;
1026 HAL_PKT_TYPE atype;
1027 const HAL_RATE_TABLE *rt;
1028 HAL_BOOL shortPreamble;
1029 struct ath_node *an;
1030 u_int pri;
1031
1032 wh = mtod(m0, struct ieee80211_frame *);
1033 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1034 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1035 isfrag = m0->m_flags & M_FRAG;
1036 hdrlen = ieee80211_anyhdrsize(wh);
1037 /*
1038 * Packet length must not include any
1039 * pad bytes; deduct them here.
1040 */
1041 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
1042
1043 /* Handle encryption twiddling if needed */
1044 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen,
1045 &pktlen, &keyix)) {
1046 ath_freetx(m0);
1047 return EIO;
1048 }
1049
1050 /* packet header may have moved, reset our local pointer */
1051 wh = mtod(m0, struct ieee80211_frame *);
1052
1053 pktlen += IEEE80211_CRC_LEN;
1054
1055 /*
1056 * Load the DMA map so any coalescing is done. This
1057 * also calculates the number of descriptors we need.
1058 */
1059 error = ath_tx_dmasetup(sc, bf, m0);
1060 if (error != 0)
1061 return error;
1062 bf->bf_node = ni; /* NB: held reference */
1063 m0 = bf->bf_m; /* NB: may have changed */
1064 wh = mtod(m0, struct ieee80211_frame *);
1065
1066 /* setup descriptors */
1067 ds = bf->bf_desc;
1068 rt = sc->sc_currates;
1069 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1070
1071 /*
1072 * NB: the 802.11 layer marks whether or not we should
1073 * use short preamble based on the current mode and
1074 * negotiated parameters.
1075 */
1076 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1077 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
1078 shortPreamble = AH_TRUE;
1079 sc->sc_stats.ast_tx_shortpre++;
1080 } else {
1081 shortPreamble = AH_FALSE;
1082 }
1083
1084 an = ATH_NODE(ni);
1085 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1086 ismrr = 0; /* default no multi-rate retry*/
1087 pri = M_WME_GETAC(m0); /* honor classification */
1088 /* XXX use txparams instead of fixed values */
1089 /*
1090 * Calculate Atheros packet type from IEEE80211 packet header,
1091 * setup for rate calculations, and select h/w transmit queue.
1092 */
1093 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1094 case IEEE80211_FC0_TYPE_MGT:
1095 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1096 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
1097 atype = HAL_PKT_TYPE_BEACON;
1098 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1099 atype = HAL_PKT_TYPE_PROBE_RESP;
1100 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1101 atype = HAL_PKT_TYPE_ATIM;
1102 else
1103 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
1104 rix = an->an_mgmtrix;
1105 txrate = rt->info[rix].rateCode;
1106 if (shortPreamble)
1107 txrate |= rt->info[rix].shortPreamble;
1108 try0 = ATH_TXMGTTRY;
1109 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1110 break;
1111 case IEEE80211_FC0_TYPE_CTL:
1112 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
1113 rix = an->an_mgmtrix;
1114 txrate = rt->info[rix].rateCode;
1115 if (shortPreamble)
1116 txrate |= rt->info[rix].shortPreamble;
1117 try0 = ATH_TXMGTTRY;
1118 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1119 break;
1120 case IEEE80211_FC0_TYPE_DATA:
1121 atype = HAL_PKT_TYPE_NORMAL; /* default */
1122 /*
1123 * Data frames: multicast frames go out at a fixed rate,
1124 * EAPOL frames use the mgmt frame rate; otherwise consult
1125 * the rate control module for the rate to use.
1126 */
1127 if (ismcast) {
1128 rix = an->an_mcastrix;
1129 txrate = rt->info[rix].rateCode;
1130 if (shortPreamble)
1131 txrate |= rt->info[rix].shortPreamble;
1132 try0 = 1;
1133 } else if (m0->m_flags & M_EAPOL) {
1134 /* XXX? maybe always use long preamble? */
1135 rix = an->an_mgmtrix;
1136 txrate = rt->info[rix].rateCode;
1137 if (shortPreamble)
1138 txrate |= rt->info[rix].shortPreamble;
1139 try0 = ATH_TXMAXTRY; /* XXX?too many? */
1140 } else {
1141 /*
1142 * Do rate lookup on each TX, rather than using
1143 * the hard-coded TX information decided here.
1144 */
1145 ismrr = 1;
1146 bf->bf_state.bfs_doratelookup = 1;
1147 }
1148 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
1149 flags |= HAL_TXDESC_NOACK;
1150 break;
1151 default:
1152 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
1153 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
1154 /* XXX statistic */
1155 ath_freetx(m0);
1156 return EIO;
1157 }
1158 txq = sc->sc_ac2q[pri];
1159
1160 /*
1161 * When servicing one or more stations in power-save mode
1162 * (or) if there is some mcast data waiting on the mcast
1163 * queue (to prevent out of order delivery) multicast
1164 * frames must be buffered until after the beacon.
1165 *
1166 * XXX This likely means that if there's a station in power
1167 * save mode, we won't be doing any kind of aggregation towards
1168 * anyone. This is likely a very suboptimal way of dealing
1169 * with things.
1170 */
1171 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
1172 txq = &avp->av_mcastq;
1173
1174 /*
1175 * Calculate miscellaneous flags.
1176 */
1177 if (ismcast) {
1178 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
1179 } else if (pktlen > vap->iv_rtsthreshold &&
1180 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
1181 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
1182 sc->sc_stats.ast_tx_rts++;
1183 }
1184 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
1185 sc->sc_stats.ast_tx_noack++;
1186#ifdef IEEE80211_SUPPORT_TDMA
1187 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
1188 DPRINTF(sc, ATH_DEBUG_TDMA,
1189 "%s: discard frame, ACK required w/ TDMA\n", __func__);
1190 sc->sc_stats.ast_tdma_ack++;
1191 ath_freetx(m0);
1192 return EIO;
1193 }
1194#endif
1195
1196 /*
1197 * If 802.11g protection is enabled, determine whether
1198 * to use RTS/CTS or just CTS. Note that this is only
1199 * done for OFDM unicast frames.
1200 */
1201 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1202 rt->info[rix].phy == IEEE80211_T_OFDM &&
1203 (flags & HAL_TXDESC_NOACK) == 0) {
1204 bf->bf_state.bfs_doprot = 1;
1205 /* XXX fragments must use CCK rates w/ protection */
1206 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1207 flags |= HAL_TXDESC_RTSENA;
1208 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1209 flags |= HAL_TXDESC_CTSENA;
1210 }
1211 /*
1212 * For frags it would be desirable to use the
1213 * highest CCK rate for RTS/CTS. But stations
1214 * farther away may detect it at a lower CCK rate
1215 * so use the configured protection rate instead
1216 * (for now).
1217 */
1218 sc->sc_stats.ast_tx_protect++;
1219 }
1220
1221#if 0
1222 /*
1223 * If 11n protection is enabled and it's a HT frame,
1224 * enable RTS.
1225 *
1226 * XXX ic_htprotmode or ic_curhtprotmode?
1227 * XXX should it_htprotmode only matter if ic_curhtprotmode
1228 * XXX indicates it's not a HT pure environment?
1229 */
1230 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) &&
1231 rt->info[rix].phy == IEEE80211_T_HT &&
1232 (flags & HAL_TXDESC_NOACK) == 0) {
1233 cix = rt->info[sc->sc_protrix].controlRate;
1234 flags |= HAL_TXDESC_RTSENA;
1235 sc->sc_stats.ast_tx_htprotect++;
1236 }
1237#endif
1238
1239 /*
1240 * Calculate duration. This logically belongs in the 802.11
1241 * layer but it lacks sufficient information to calculate it.
1242 */
1243 if ((flags & HAL_TXDESC_NOACK) == 0 &&
1244 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
1245 u_int16_t dur;
1246 if (shortPreamble)
1247 dur = rt->info[rix].spAckDuration;
1248 else
1249 dur = rt->info[rix].lpAckDuration;
1250 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
1251 dur += dur; /* additional SIFS+ACK */
1252 KASSERT(m0->m_nextpkt != NULL, ("no fragment"));
1253 /*
1254 * Include the size of next fragment so NAV is
1255 * updated properly. The last fragment uses only
1256 * the ACK duration
1257 */
1258 dur += ath_hal_computetxtime(ah, rt,
1259 m0->m_nextpkt->m_pkthdr.len,
1260 rix, shortPreamble);
1261 }
1262 if (isfrag) {
1263 /*
1264 * Force hardware to use computed duration for next
1265 * fragment by disabling multi-rate retry which updates
1266 * duration based on the multi-rate duration table.
1267 */
1268 ismrr = 0;
1269 try0 = ATH_TXMGTTRY; /* XXX? */
1270 }
1271 *(u_int16_t *)wh->i_dur = htole16(dur);
1272 }
1273
1274 /*
1275 * Determine if a tx interrupt should be generated for
1276 * this descriptor. We take a tx interrupt to reap
1277 * descriptors when the h/w hits an EOL condition or
1278 * when the descriptor is specifically marked to generate
1279 * an interrupt. We periodically mark descriptors in this
1280 * way to insure timely replenishing of the supply needed
1281 * for sending frames. Defering interrupts reduces system
1282 * load and potentially allows more concurrent work to be
1283 * done but if done to aggressively can cause senders to
1284 * backup.
1285 *
1286 * NB: use >= to deal with sc_txintrperiod changing
1287 * dynamically through sysctl.
1288 */
1289 if (flags & HAL_TXDESC_INTREQ) {
1290 txq->axq_intrcnt = 0;
1291 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
1292 flags |= HAL_TXDESC_INTREQ;
1293 txq->axq_intrcnt = 0;
1294 }
1295
1296 /* This point forward is actual TX bits */
1297
1298 /*
1299 * At this point we are committed to sending the frame
1300 * and we don't need to look at m_nextpkt; clear it in
1301 * case this frame is part of frag chain.
1302 */
1303 m0->m_nextpkt = NULL;
1304
1305 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1306 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
1307 sc->sc_hwmap[rix].ieeerate, -1);
1308
1309 if (ieee80211_radiotap_active_vap(vap)) {
1310 u_int64_t tsf = ath_hal_gettsf64(ah);
1311
1312 sc->sc_tx_th.wt_tsf = htole64(tsf);
1313 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1314 if (iswep)
1315 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1316 if (isfrag)
1317 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1318 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1319 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1320 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1321
1322 ieee80211_radiotap_tx(vap, m0);
1323 }
1324
1325 /* Blank the legacy rate array */
1326 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1327
1328 /*
1329 * ath_buf_set_rate needs at least one rate/try to setup
1330 * the rate scenario.
1331 */
1332 bf->bf_state.bfs_rc[0].rix = rix;
1333 bf->bf_state.bfs_rc[0].tries = try0;
1334 bf->bf_state.bfs_rc[0].ratecode = txrate;
1335
1336 /* Store the decided rate index values away */
1337 bf->bf_state.bfs_pktlen = pktlen;
1338 bf->bf_state.bfs_hdrlen = hdrlen;
1339 bf->bf_state.bfs_atype = atype;
1340 bf->bf_state.bfs_txpower = ni->ni_txpower;
1341 bf->bf_state.bfs_txrate0 = txrate;
1342 bf->bf_state.bfs_try0 = try0;
1343 bf->bf_state.bfs_keyix = keyix;
1344 bf->bf_state.bfs_txantenna = sc->sc_txantenna;
1345 bf->bf_state.bfs_flags = flags;
1346 bf->bf_txflags = flags;
1347 bf->bf_state.bfs_shpream = shortPreamble;
1348
1349 /* XXX this should be done in ath_tx_setrate() */
1350 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */
1351 bf->bf_state.bfs_ctsrate = 0; /* calculated later */
1352 bf->bf_state.bfs_ctsduration = 0;
1353 bf->bf_state.bfs_ismrr = ismrr;
1354
1355 return 0;
1356}
1357
1358/*
1359 * Direct-dispatch the current frame to the hardware.
1360 *
1361 * This can be called by the net80211 code.
1362 *
1363 * XXX what about locking? Or, push the seqno assign into the
1364 * XXX aggregate scheduler so its serialised?
1365 */
1366int
1367ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
1368 struct ath_buf *bf, struct mbuf *m0)
1369{
1370 struct ieee80211vap *vap = ni->ni_vap;
1371 struct ath_vap *avp = ATH_VAP(vap);
1372 int r = 0;
1373 u_int pri;
1374 int tid;
1375 struct ath_txq *txq;
1376 int ismcast;
1377 const struct ieee80211_frame *wh;
1378 int is_ampdu, is_ampdu_tx, is_ampdu_pending;
| 116
117/*
118 * Whether to use the 11n rate scenario functions or not
119 */
120static inline int
121ath_tx_is_11n(struct ath_softc *sc)
122{
123 return (sc->sc_ah->ah_magic == 0x20065416);
124}
125
126/*
127 * Obtain the current TID from the given frame.
128 *
129 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.)
130 * This has implications for which AC/priority the packet is placed
131 * in.
132 */
133static int
134ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0)
135{
136 const struct ieee80211_frame *wh;
137 int pri = M_WME_GETAC(m0);
138
139 wh = mtod(m0, const struct ieee80211_frame *);
140 if (! IEEE80211_QOS_HAS_SEQ(wh))
141 return IEEE80211_NONQOS_TID;
142 else
143 return WME_AC_TO_TID(pri);
144}
145
146/*
147 * Determine what the correct AC queue for the given frame
148 * should be.
149 *
150 * This code assumes that the TIDs map consistently to
151 * the underlying hardware (or software) ath_txq.
152 * Since the sender may try to set an AC which is
153 * arbitrary, non-QoS TIDs may end up being put on
154 * completely different ACs. There's no way to put a
155 * TID into multiple ath_txq's for scheduling, so
156 * for now we override the AC/TXQ selection and set
157 * non-QOS TID frames into the BE queue.
158 *
159 * This may be completely incorrect - specifically,
160 * some management frames may end up out of order
161 * compared to the QoS traffic they're controlling.
162 * I'll look into this later.
163 */
164static int
165ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0)
166{
167 const struct ieee80211_frame *wh;
168 int pri = M_WME_GETAC(m0);
169 wh = mtod(m0, const struct ieee80211_frame *);
170 if (IEEE80211_QOS_HAS_SEQ(wh))
171 return pri;
172
173 return WME_AC_BE;
174}
175
176void
177ath_txfrag_cleanup(struct ath_softc *sc,
178 ath_bufhead *frags, struct ieee80211_node *ni)
179{
180 struct ath_buf *bf, *next;
181
182 ATH_TXBUF_LOCK_ASSERT(sc);
183
184 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
185 /* NB: bf assumed clean */
186 TAILQ_REMOVE(frags, bf, bf_list);
187 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
188 ieee80211_node_decref(ni);
189 }
190}
191
192/*
193 * Setup xmit of a fragmented frame. Allocate a buffer
194 * for each frag and bump the node reference count to
195 * reflect the held reference to be setup by ath_tx_start.
196 */
197int
198ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
199 struct mbuf *m0, struct ieee80211_node *ni)
200{
201 struct mbuf *m;
202 struct ath_buf *bf;
203
204 ATH_TXBUF_LOCK(sc);
205 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
206 bf = _ath_getbuf_locked(sc);
207 if (bf == NULL) { /* out of buffers, cleanup */
208 ath_txfrag_cleanup(sc, frags, ni);
209 break;
210 }
211 ieee80211_node_incref(ni);
212 TAILQ_INSERT_TAIL(frags, bf, bf_list);
213 }
214 ATH_TXBUF_UNLOCK(sc);
215
216 return !TAILQ_EMPTY(frags);
217}
218
219/*
220 * Reclaim mbuf resources. For fragmented frames we
221 * need to claim each frag chained with m_nextpkt.
222 */
223void
224ath_freetx(struct mbuf *m)
225{
226 struct mbuf *next;
227
228 do {
229 next = m->m_nextpkt;
230 m->m_nextpkt = NULL;
231 m_freem(m);
232 } while ((m = next) != NULL);
233}
234
235static int
236ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
237{
238 struct mbuf *m;
239 int error;
240
241 /*
242 * Load the DMA map so any coalescing is done. This
243 * also calculates the number of descriptors we need.
244 */
245 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
246 bf->bf_segs, &bf->bf_nseg,
247 BUS_DMA_NOWAIT);
248 if (error == EFBIG) {
249 /* XXX packet requires too many descriptors */
250 bf->bf_nseg = ATH_TXDESC+1;
251 } else if (error != 0) {
252 sc->sc_stats.ast_tx_busdma++;
253 ath_freetx(m0);
254 return error;
255 }
256 /*
257 * Discard null packets and check for packets that
258 * require too many TX descriptors. We try to convert
259 * the latter to a cluster.
260 */
261 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
262 sc->sc_stats.ast_tx_linear++;
263 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
264 if (m == NULL) {
265 ath_freetx(m0);
266 sc->sc_stats.ast_tx_nombuf++;
267 return ENOMEM;
268 }
269 m0 = m;
270 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
271 bf->bf_segs, &bf->bf_nseg,
272 BUS_DMA_NOWAIT);
273 if (error != 0) {
274 sc->sc_stats.ast_tx_busdma++;
275 ath_freetx(m0);
276 return error;
277 }
278 KASSERT(bf->bf_nseg <= ATH_TXDESC,
279 ("too many segments after defrag; nseg %u", bf->bf_nseg));
280 } else if (bf->bf_nseg == 0) { /* null packet, discard */
281 sc->sc_stats.ast_tx_nodata++;
282 ath_freetx(m0);
283 return EIO;
284 }
285 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
286 __func__, m0, m0->m_pkthdr.len);
287 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
288 bf->bf_m = m0;
289
290 return 0;
291}
292
293/*
294 * Chain together segments+descriptors for a non-11n frame.
295 */
296static void
297ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf)
298{
299 struct ath_hal *ah = sc->sc_ah;
300 struct ath_desc *ds, *ds0;
301 int i;
302
303 /*
304 * Fillin the remainder of the descriptor info.
305 */
306 ds0 = ds = bf->bf_desc;
307 for (i = 0; i < bf->bf_nseg; i++, ds++) {
308 ds->ds_data = bf->bf_segs[i].ds_addr;
309 if (i == bf->bf_nseg - 1)
310 ds->ds_link = 0;
311 else
312 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
313 ath_hal_filltxdesc(ah, ds
314 , bf->bf_segs[i].ds_len /* segment length */
315 , i == 0 /* first segment */
316 , i == bf->bf_nseg - 1 /* last segment */
317 , ds0 /* first descriptor */
318 );
319 DPRINTF(sc, ATH_DEBUG_XMIT,
320 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
321 __func__, i, ds->ds_link, ds->ds_data,
322 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
323 bf->bf_lastds = ds;
324 }
325}
326
327/*
328 * Fill in the descriptor list for a aggregate subframe.
329 *
330 * The subframe is returned with the ds_link field in the last subframe
331 * pointing to 0.
332 */
333static void
334ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf)
335{
336 struct ath_hal *ah = sc->sc_ah;
337 struct ath_desc *ds, *ds0;
338 int i;
339
340 ds0 = ds = bf->bf_desc;
341
342 /*
343 * There's no need to call ath_hal_setupfirsttxdesc here;
344 * That's only going to occur for the first frame in an aggregate.
345 */
346 for (i = 0; i < bf->bf_nseg; i++, ds++) {
347 ds->ds_data = bf->bf_segs[i].ds_addr;
348 if (i == bf->bf_nseg - 1)
349 ds->ds_link = 0;
350 else
351 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
352
353 /*
354 * This performs the setup for an aggregate frame.
355 * This includes enabling the aggregate flags if needed.
356 */
357 ath_hal_chaintxdesc(ah, ds,
358 bf->bf_state.bfs_pktlen,
359 bf->bf_state.bfs_hdrlen,
360 HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */
361 bf->bf_state.bfs_keyix,
362 0, /* cipher, calculated from keyix */
363 bf->bf_state.bfs_ndelim,
364 bf->bf_segs[i].ds_len, /* segment length */
365 i == 0, /* first segment */
366 i == bf->bf_nseg - 1 /* last segment */
367 );
368
369 DPRINTF(sc, ATH_DEBUG_XMIT,
370 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
371 __func__, i, ds->ds_link, ds->ds_data,
372 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
373 bf->bf_lastds = ds;
374 }
375}
376
377/*
378 * Setup segments+descriptors for an 11n aggregate.
379 * bf_first is the first buffer in the aggregate.
380 * The descriptor list must already been linked together using
381 * bf->bf_next.
382 */
383static void
384ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first)
385{
386 struct ath_buf *bf, *bf_prev = NULL;
387
388 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n",
389 __func__, bf_first->bf_state.bfs_nframes,
390 bf_first->bf_state.bfs_al);
391
392 /*
393 * Setup all descriptors of all subframes.
394 */
395 bf = bf_first;
396 while (bf != NULL) {
397 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
398 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n",
399 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen,
400 SEQNO(bf->bf_state.bfs_seqno));
401
402 /* Sub-frame setup */
403 ath_tx_chaindesclist_subframe(sc, bf);
404
405 /*
406 * Link the last descriptor of the previous frame
407 * to the beginning descriptor of this frame.
408 */
409 if (bf_prev != NULL)
410 bf_prev->bf_lastds->ds_link = bf->bf_daddr;
411
412 /* Save a copy so we can link the next descriptor in */
413 bf_prev = bf;
414 bf = bf->bf_next;
415 }
416
417 /*
418 * Setup first descriptor of first frame.
419 * chaintxdesc() overwrites the descriptor entries;
420 * setupfirsttxdesc() merges in things.
421 * Otherwise various fields aren't set correctly (eg flags).
422 */
423 ath_hal_setupfirsttxdesc(sc->sc_ah,
424 bf_first->bf_desc,
425 bf_first->bf_state.bfs_al,
426 bf_first->bf_state.bfs_flags | HAL_TXDESC_INTREQ,
427 bf_first->bf_state.bfs_txpower,
428 bf_first->bf_state.bfs_txrate0,
429 bf_first->bf_state.bfs_try0,
430 bf_first->bf_state.bfs_txantenna,
431 bf_first->bf_state.bfs_ctsrate,
432 bf_first->bf_state.bfs_ctsduration);
433
434 /*
435 * Setup the last descriptor in the list.
436 * bf_prev points to the last; bf is NULL here.
437 */
438 ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_desc,
439 bf_first->bf_desc);
440
441 /*
442 * Set the first descriptor bf_lastds field to point to
443 * the last descriptor in the last subframe, that's where
444 * the status update will occur.
445 */
446 bf_first->bf_lastds = bf_prev->bf_lastds;
447
448 /*
449 * And bf_last in the first descriptor points to the end of
450 * the aggregate list.
451 */
452 bf_first->bf_last = bf_prev;
453
454 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__);
455}
456
457static void
458ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
459 struct ath_buf *bf)
460{
461 ATH_TXQ_LOCK_ASSERT(txq);
462 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
463 ("%s: busy status 0x%x", __func__, bf->bf_flags));
464 if (txq->axq_link != NULL) {
465 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s);
466 struct ieee80211_frame *wh;
467
468 /* mark previous frame */
469 wh = mtod(last->bf_m, struct ieee80211_frame *);
470 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
471 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
472 BUS_DMASYNC_PREWRITE);
473
474 /* link descriptor */
475 *txq->axq_link = bf->bf_daddr;
476 }
477 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
478 txq->axq_link = &bf->bf_lastds->ds_link;
479}
480
481/*
482 * Hand-off packet to a hardware queue.
483 */
484static void
485ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
486 struct ath_buf *bf)
487{
488 struct ath_hal *ah = sc->sc_ah;
489
490 /*
491 * Insert the frame on the outbound list and pass it on
492 * to the hardware. Multicast frames buffered for power
493 * save stations and transmit from the CAB queue are stored
494 * on a s/w only queue and loaded on to the CAB queue in
495 * the SWBA handler since frames only go out on DTIM and
496 * to avoid possible races.
497 */
498 ATH_TXQ_LOCK_ASSERT(txq);
499 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
500 ("%s: busy status 0x%x", __func__, bf->bf_flags));
501 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ,
502 ("ath_tx_handoff_hw called for mcast queue"));
503
504#if 0
505 /*
506 * This causes a LOR. Find out where the PCU lock is being
507 * held whilst the TXQ lock is grabbed - that shouldn't
508 * be occuring.
509 */
510 ATH_PCU_LOCK(sc);
511 if (sc->sc_inreset_cnt) {
512 ATH_PCU_UNLOCK(sc);
513 DPRINTF(sc, ATH_DEBUG_RESET,
514 "%s: called with sc_in_reset != 0\n",
515 __func__);
516 DPRINTF(sc, ATH_DEBUG_XMIT,
517 "%s: queued: TXDP[%u] = %p (%p) depth %d\n",
518 __func__, txq->axq_qnum,
519 (caddr_t)bf->bf_daddr, bf->bf_desc,
520 txq->axq_depth);
521 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
522 if (bf->bf_state.bfs_aggr)
523 txq->axq_aggr_depth++;
524 /*
525 * There's no need to update axq_link; the hardware
526 * is in reset and once the reset is complete, any
527 * non-empty queues will simply have DMA restarted.
528 */
529 return;
530 }
531 ATH_PCU_UNLOCK(sc);
532#endif
533
534 /* For now, so not to generate whitespace diffs */
535 if (1) {
536#ifdef IEEE80211_SUPPORT_TDMA
537 int qbusy;
538
539 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
540 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
541 if (txq->axq_link == NULL) {
542 /*
543 * Be careful writing the address to TXDP. If
544 * the tx q is enabled then this write will be
545 * ignored. Normally this is not an issue but
546 * when tdma is in use and the q is beacon gated
547 * this race can occur. If the q is busy then
548 * defer the work to later--either when another
549 * packet comes along or when we prepare a beacon
550 * frame at SWBA.
551 */
552 if (!qbusy) {
553 ath_hal_puttxbuf(ah, txq->axq_qnum,
554 bf->bf_daddr);
555 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
556 DPRINTF(sc, ATH_DEBUG_XMIT,
557 "%s: TXDP[%u] = %p (%p) depth %d\n",
558 __func__, txq->axq_qnum,
559 (caddr_t)bf->bf_daddr, bf->bf_desc,
560 txq->axq_depth);
561 } else {
562 txq->axq_flags |= ATH_TXQ_PUTPENDING;
563 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
564 "%s: Q%u busy, defer enable\n", __func__,
565 txq->axq_qnum);
566 }
567 } else {
568 *txq->axq_link = bf->bf_daddr;
569 DPRINTF(sc, ATH_DEBUG_XMIT,
570 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
571 txq->axq_qnum, txq->axq_link,
572 (caddr_t)bf->bf_daddr, bf->bf_desc,
573 txq->axq_depth);
574 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
575 /*
576 * The q was busy when we previously tried
577 * to write the address of the first buffer
578 * in the chain. Since it's not busy now
579 * handle this chore. We are certain the
580 * buffer at the front is the right one since
581 * axq_link is NULL only when the buffer list
582 * is/was empty.
583 */
584 ath_hal_puttxbuf(ah, txq->axq_qnum,
585 TAILQ_FIRST(&txq->axq_q)->bf_daddr);
586 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
587 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
588 "%s: Q%u restarted\n", __func__,
589 txq->axq_qnum);
590 }
591 }
592#else
593 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
594 if (txq->axq_link == NULL) {
595 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
596 DPRINTF(sc, ATH_DEBUG_XMIT,
597 "%s: TXDP[%u] = %p (%p) depth %d\n",
598 __func__, txq->axq_qnum,
599 (caddr_t)bf->bf_daddr, bf->bf_desc,
600 txq->axq_depth);
601 } else {
602 *txq->axq_link = bf->bf_daddr;
603 DPRINTF(sc, ATH_DEBUG_XMIT,
604 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
605 txq->axq_qnum, txq->axq_link,
606 (caddr_t)bf->bf_daddr, bf->bf_desc,
607 txq->axq_depth);
608 }
609#endif /* IEEE80211_SUPPORT_TDMA */
610 if (bf->bf_state.bfs_aggr)
611 txq->axq_aggr_depth++;
612 txq->axq_link = &bf->bf_lastds->ds_link;
613 ath_hal_txstart(ah, txq->axq_qnum);
614 }
615}
616
617/*
618 * Restart TX DMA for the given TXQ.
619 *
620 * This must be called whether the queue is empty or not.
621 */
622void
623ath_txq_restart_dma(struct ath_softc *sc, struct ath_txq *txq)
624{
625 struct ath_hal *ah = sc->sc_ah;
626 struct ath_buf *bf, *bf_last;
627
628 ATH_TXQ_LOCK_ASSERT(txq);
629
630 /* This is always going to be cleared, empty or not */
631 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
632
633 /* XXX make this ATH_TXQ_FIRST */
634 bf = TAILQ_FIRST(&txq->axq_q);
635 bf_last = ATH_TXQ_LAST(txq, axq_q_s);
636
637 if (bf == NULL)
638 return;
639
640 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
641 txq->axq_link = &bf_last->bf_lastds->ds_link;
642 ath_hal_txstart(ah, txq->axq_qnum);
643}
644
645/*
646 * Hand off a packet to the hardware (or mcast queue.)
647 *
648 * The relevant hardware txq should be locked.
649 */
650static void
651ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
652{
653 ATH_TXQ_LOCK_ASSERT(txq);
654
655 if (txq->axq_qnum == ATH_TXQ_SWQ)
656 ath_tx_handoff_mcast(sc, txq, bf);
657 else
658 ath_tx_handoff_hw(sc, txq, bf);
659}
660
661static int
662ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni,
663 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen,
664 int *keyix)
665{
666 if (iswep) {
667 const struct ieee80211_cipher *cip;
668 struct ieee80211_key *k;
669
670 /*
671 * Construct the 802.11 header+trailer for an encrypted
672 * frame. The only reason this can fail is because of an
673 * unknown or unsupported cipher/key type.
674 */
675 k = ieee80211_crypto_encap(ni, m0);
676 if (k == NULL) {
677 /*
678 * This can happen when the key is yanked after the
679 * frame was queued. Just discard the frame; the
680 * 802.11 layer counts failures and provides
681 * debugging/diagnostics.
682 */
683 return (0);
684 }
685 /*
686 * Adjust the packet + header lengths for the crypto
687 * additions and calculate the h/w key index. When
688 * a s/w mic is done the frame will have had any mic
689 * added to it prior to entry so m0->m_pkthdr.len will
690 * account for it. Otherwise we need to add it to the
691 * packet length.
692 */
693 cip = k->wk_cipher;
694 (*hdrlen) += cip->ic_header;
695 (*pktlen) += cip->ic_header + cip->ic_trailer;
696 /* NB: frags always have any TKIP MIC done in s/w */
697 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
698 (*pktlen) += cip->ic_miclen;
699 (*keyix) = k->wk_keyix;
700 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
701 /*
702 * Use station key cache slot, if assigned.
703 */
704 (*keyix) = ni->ni_ucastkey.wk_keyix;
705 if ((*keyix) == IEEE80211_KEYIX_NONE)
706 (*keyix) = HAL_TXKEYIX_INVALID;
707 } else
708 (*keyix) = HAL_TXKEYIX_INVALID;
709
710 return (1);
711}
712
713static uint8_t
714ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
715 int cix, int shortPreamble)
716{
717 uint8_t ctsrate;
718
719 /*
720 * CTS transmit rate is derived from the transmit rate
721 * by looking in the h/w rate table. We must also factor
722 * in whether or not a short preamble is to be used.
723 */
724 /* NB: cix is set above where RTS/CTS is enabled */
725 KASSERT(cix != 0xff, ("cix not setup"));
726 ctsrate = rt->info[cix].rateCode;
727
728 /* XXX this should only matter for legacy rates */
729 if (shortPreamble)
730 ctsrate |= rt->info[cix].shortPreamble;
731
732 return (ctsrate);
733}
734
735/*
736 * Calculate the RTS/CTS duration for legacy frames.
737 */
738static int
739ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix,
740 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt,
741 int flags)
742{
743 int ctsduration = 0;
744
745 /* This mustn't be called for HT modes */
746 if (rt->info[cix].phy == IEEE80211_T_HT) {
747 printf("%s: HT rate where it shouldn't be (0x%x)\n",
748 __func__, rt->info[cix].rateCode);
749 return (-1);
750 }
751
752 /*
753 * Compute the transmit duration based on the frame
754 * size and the size of an ACK frame. We call into the
755 * HAL to do the computation since it depends on the
756 * characteristics of the actual PHY being used.
757 *
758 * NB: CTS is assumed the same size as an ACK so we can
759 * use the precalculated ACK durations.
760 */
761 if (shortPreamble) {
762 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
763 ctsduration += rt->info[cix].spAckDuration;
764 ctsduration += ath_hal_computetxtime(ah,
765 rt, pktlen, rix, AH_TRUE);
766 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
767 ctsduration += rt->info[rix].spAckDuration;
768 } else {
769 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
770 ctsduration += rt->info[cix].lpAckDuration;
771 ctsduration += ath_hal_computetxtime(ah,
772 rt, pktlen, rix, AH_FALSE);
773 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
774 ctsduration += rt->info[rix].lpAckDuration;
775 }
776
777 return (ctsduration);
778}
779
780/*
781 * Update the given ath_buf with updated rts/cts setup and duration
782 * values.
783 *
784 * To support rate lookups for each software retry, the rts/cts rate
785 * and cts duration must be re-calculated.
786 *
787 * This function assumes the RTS/CTS flags have been set as needed;
788 * mrr has been disabled; and the rate control lookup has been done.
789 *
790 * XXX TODO: MRR need only be disabled for the pre-11n NICs.
791 * XXX The 11n NICs support per-rate RTS/CTS configuration.
792 */
793static void
794ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf)
795{
796 uint16_t ctsduration = 0;
797 uint8_t ctsrate = 0;
798 uint8_t rix = bf->bf_state.bfs_rc[0].rix;
799 uint8_t cix = 0;
800 const HAL_RATE_TABLE *rt = sc->sc_currates;
801
802 /*
803 * No RTS/CTS enabled? Don't bother.
804 */
805 if ((bf->bf_state.bfs_flags &
806 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) {
807 /* XXX is this really needed? */
808 bf->bf_state.bfs_ctsrate = 0;
809 bf->bf_state.bfs_ctsduration = 0;
810 return;
811 }
812
813 /*
814 * If protection is enabled, use the protection rix control
815 * rate. Otherwise use the rate0 control rate.
816 */
817 if (bf->bf_state.bfs_doprot)
818 rix = sc->sc_protrix;
819 else
820 rix = bf->bf_state.bfs_rc[0].rix;
821
822 /*
823 * If the raw path has hard-coded ctsrate0 to something,
824 * use it.
825 */
826 if (bf->bf_state.bfs_ctsrate0 != 0)
827 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0);
828 else
829 /* Control rate from above */
830 cix = rt->info[rix].controlRate;
831
832 /* Calculate the rtscts rate for the given cix */
833 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix,
834 bf->bf_state.bfs_shpream);
835
836 /* The 11n chipsets do ctsduration calculations for you */
837 if (! ath_tx_is_11n(sc))
838 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix,
839 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen,
840 rt, bf->bf_state.bfs_flags);
841
842 /* Squirrel away in ath_buf */
843 bf->bf_state.bfs_ctsrate = ctsrate;
844 bf->bf_state.bfs_ctsduration = ctsduration;
845
846 /*
847 * Must disable multi-rate retry when using RTS/CTS.
848 * XXX TODO: only for pre-11n NICs.
849 */
850 bf->bf_state.bfs_ismrr = 0;
851 bf->bf_state.bfs_try0 =
852 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */
853}
854
855/*
856 * Setup the descriptor chain for a normal or fast-frame
857 * frame.
858 */
859static void
860ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf)
861{
862 struct ath_desc *ds = bf->bf_desc;
863 struct ath_hal *ah = sc->sc_ah;
864
865 ath_hal_setuptxdesc(ah, ds
866 , bf->bf_state.bfs_pktlen /* packet length */
867 , bf->bf_state.bfs_hdrlen /* header length */
868 , bf->bf_state.bfs_atype /* Atheros packet type */
869 , bf->bf_state.bfs_txpower /* txpower */
870 , bf->bf_state.bfs_txrate0
871 , bf->bf_state.bfs_try0 /* series 0 rate/tries */
872 , bf->bf_state.bfs_keyix /* key cache index */
873 , bf->bf_state.bfs_txantenna /* antenna mode */
874 , bf->bf_state.bfs_flags /* flags */
875 , bf->bf_state.bfs_ctsrate /* rts/cts rate */
876 , bf->bf_state.bfs_ctsduration /* rts/cts duration */
877 );
878
879 /*
880 * This will be overriden when the descriptor chain is written.
881 */
882 bf->bf_lastds = ds;
883 bf->bf_last = bf;
884
885 /* XXX TODO: Setup descriptor chain */
886}
887
888/*
889 * Do a rate lookup.
890 *
891 * This performs a rate lookup for the given ath_buf only if it's required.
892 * Non-data frames and raw frames don't require it.
893 *
894 * This populates the primary and MRR entries; MRR values are
895 * then disabled later on if something requires it (eg RTS/CTS on
896 * pre-11n chipsets.
897 *
898 * This needs to be done before the RTS/CTS fields are calculated
899 * as they may depend upon the rate chosen.
900 */
901static void
902ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf)
903{
904 uint8_t rate, rix;
905 int try0;
906
907 if (! bf->bf_state.bfs_doratelookup)
908 return;
909
910 /* Get rid of any previous state */
911 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
912
913 ATH_NODE_LOCK(ATH_NODE(bf->bf_node));
914 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream,
915 bf->bf_state.bfs_pktlen, &rix, &try0, &rate);
916
917 /* In case MRR is disabled, make sure rc[0] is setup correctly */
918 bf->bf_state.bfs_rc[0].rix = rix;
919 bf->bf_state.bfs_rc[0].ratecode = rate;
920 bf->bf_state.bfs_rc[0].tries = try0;
921
922 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY)
923 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix,
924 bf->bf_state.bfs_rc);
925 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node));
926
927 sc->sc_txrix = rix; /* for LED blinking */
928 sc->sc_lastdatarix = rix; /* for fast frames */
929 bf->bf_state.bfs_try0 = try0;
930 bf->bf_state.bfs_txrate0 = rate;
931}
932
933/*
934 * Set the rate control fields in the given descriptor based on
935 * the bf_state fields and node state.
936 *
937 * The bfs fields should already be set with the relevant rate
938 * control information, including whether MRR is to be enabled.
939 *
940 * Since the FreeBSD HAL currently sets up the first TX rate
941 * in ath_hal_setuptxdesc(), this will setup the MRR
942 * conditionally for the pre-11n chips, and call ath_buf_set_rate
943 * unconditionally for 11n chips. These require the 11n rate
944 * scenario to be set if MCS rates are enabled, so it's easier
945 * to just always call it. The caller can then only set rates 2, 3
946 * and 4 if multi-rate retry is needed.
947 */
948static void
949ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
950 struct ath_buf *bf)
951{
952 struct ath_rc_series *rc = bf->bf_state.bfs_rc;
953
954 /* If mrr is disabled, blank tries 1, 2, 3 */
955 if (! bf->bf_state.bfs_ismrr)
956 rc[1].tries = rc[2].tries = rc[3].tries = 0;
957
958 /*
959 * Always call - that way a retried descriptor will
960 * have the MRR fields overwritten.
961 *
962 * XXX TODO: see if this is really needed - setting up
963 * the first descriptor should set the MRR fields to 0
964 * for us anyway.
965 */
966 if (ath_tx_is_11n(sc)) {
967 ath_buf_set_rate(sc, ni, bf);
968 } else {
969 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc
970 , rc[1].ratecode, rc[1].tries
971 , rc[2].ratecode, rc[2].tries
972 , rc[3].ratecode, rc[3].tries
973 );
974 }
975}
976
977/*
978 * Transmit the given frame to the hardware.
979 *
980 * The frame must already be setup; rate control must already have
981 * been done.
982 *
983 * XXX since the TXQ lock is being held here (and I dislike holding
984 * it for this long when not doing software aggregation), later on
985 * break this function into "setup_normal" and "xmit_normal". The
986 * lock only needs to be held for the ath_tx_handoff call.
987 */
988static void
989ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq,
990 struct ath_buf *bf)
991{
992
993 ATH_TXQ_LOCK_ASSERT(txq);
994
995 /* Setup the descriptor before handoff */
996 ath_tx_do_ratelookup(sc, bf);
997 ath_tx_rate_fill_rcflags(sc, bf);
998 ath_tx_set_rtscts(sc, bf);
999 ath_tx_setds(sc, bf);
1000 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
1001 ath_tx_chaindesclist(sc, bf);
1002
1003 /* Hand off to hardware */
1004 ath_tx_handoff(sc, txq, bf);
1005}
1006
1007
1008
1009static int
1010ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
1011 struct ath_buf *bf, struct mbuf *m0)
1012{
1013 struct ieee80211vap *vap = ni->ni_vap;
1014 struct ath_vap *avp = ATH_VAP(vap);
1015 struct ath_hal *ah = sc->sc_ah;
1016 struct ifnet *ifp = sc->sc_ifp;
1017 struct ieee80211com *ic = ifp->if_l2com;
1018 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
1019 int error, iswep, ismcast, isfrag, ismrr;
1020 int keyix, hdrlen, pktlen, try0 = 0;
1021 u_int8_t rix = 0, txrate = 0;
1022 struct ath_desc *ds;
1023 struct ath_txq *txq;
1024 struct ieee80211_frame *wh;
1025 u_int subtype, flags;
1026 HAL_PKT_TYPE atype;
1027 const HAL_RATE_TABLE *rt;
1028 HAL_BOOL shortPreamble;
1029 struct ath_node *an;
1030 u_int pri;
1031
1032 wh = mtod(m0, struct ieee80211_frame *);
1033 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1034 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1035 isfrag = m0->m_flags & M_FRAG;
1036 hdrlen = ieee80211_anyhdrsize(wh);
1037 /*
1038 * Packet length must not include any
1039 * pad bytes; deduct them here.
1040 */
1041 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
1042
1043 /* Handle encryption twiddling if needed */
1044 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen,
1045 &pktlen, &keyix)) {
1046 ath_freetx(m0);
1047 return EIO;
1048 }
1049
1050 /* packet header may have moved, reset our local pointer */
1051 wh = mtod(m0, struct ieee80211_frame *);
1052
1053 pktlen += IEEE80211_CRC_LEN;
1054
1055 /*
1056 * Load the DMA map so any coalescing is done. This
1057 * also calculates the number of descriptors we need.
1058 */
1059 error = ath_tx_dmasetup(sc, bf, m0);
1060 if (error != 0)
1061 return error;
1062 bf->bf_node = ni; /* NB: held reference */
1063 m0 = bf->bf_m; /* NB: may have changed */
1064 wh = mtod(m0, struct ieee80211_frame *);
1065
1066 /* setup descriptors */
1067 ds = bf->bf_desc;
1068 rt = sc->sc_currates;
1069 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1070
1071 /*
1072 * NB: the 802.11 layer marks whether or not we should
1073 * use short preamble based on the current mode and
1074 * negotiated parameters.
1075 */
1076 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1077 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
1078 shortPreamble = AH_TRUE;
1079 sc->sc_stats.ast_tx_shortpre++;
1080 } else {
1081 shortPreamble = AH_FALSE;
1082 }
1083
1084 an = ATH_NODE(ni);
1085 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1086 ismrr = 0; /* default no multi-rate retry*/
1087 pri = M_WME_GETAC(m0); /* honor classification */
1088 /* XXX use txparams instead of fixed values */
1089 /*
1090 * Calculate Atheros packet type from IEEE80211 packet header,
1091 * setup for rate calculations, and select h/w transmit queue.
1092 */
1093 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1094 case IEEE80211_FC0_TYPE_MGT:
1095 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1096 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
1097 atype = HAL_PKT_TYPE_BEACON;
1098 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1099 atype = HAL_PKT_TYPE_PROBE_RESP;
1100 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1101 atype = HAL_PKT_TYPE_ATIM;
1102 else
1103 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
1104 rix = an->an_mgmtrix;
1105 txrate = rt->info[rix].rateCode;
1106 if (shortPreamble)
1107 txrate |= rt->info[rix].shortPreamble;
1108 try0 = ATH_TXMGTTRY;
1109 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1110 break;
1111 case IEEE80211_FC0_TYPE_CTL:
1112 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
1113 rix = an->an_mgmtrix;
1114 txrate = rt->info[rix].rateCode;
1115 if (shortPreamble)
1116 txrate |= rt->info[rix].shortPreamble;
1117 try0 = ATH_TXMGTTRY;
1118 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1119 break;
1120 case IEEE80211_FC0_TYPE_DATA:
1121 atype = HAL_PKT_TYPE_NORMAL; /* default */
1122 /*
1123 * Data frames: multicast frames go out at a fixed rate,
1124 * EAPOL frames use the mgmt frame rate; otherwise consult
1125 * the rate control module for the rate to use.
1126 */
1127 if (ismcast) {
1128 rix = an->an_mcastrix;
1129 txrate = rt->info[rix].rateCode;
1130 if (shortPreamble)
1131 txrate |= rt->info[rix].shortPreamble;
1132 try0 = 1;
1133 } else if (m0->m_flags & M_EAPOL) {
1134 /* XXX? maybe always use long preamble? */
1135 rix = an->an_mgmtrix;
1136 txrate = rt->info[rix].rateCode;
1137 if (shortPreamble)
1138 txrate |= rt->info[rix].shortPreamble;
1139 try0 = ATH_TXMAXTRY; /* XXX?too many? */
1140 } else {
1141 /*
1142 * Do rate lookup on each TX, rather than using
1143 * the hard-coded TX information decided here.
1144 */
1145 ismrr = 1;
1146 bf->bf_state.bfs_doratelookup = 1;
1147 }
1148 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
1149 flags |= HAL_TXDESC_NOACK;
1150 break;
1151 default:
1152 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
1153 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
1154 /* XXX statistic */
1155 ath_freetx(m0);
1156 return EIO;
1157 }
1158 txq = sc->sc_ac2q[pri];
1159
1160 /*
1161 * When servicing one or more stations in power-save mode
1162 * (or) if there is some mcast data waiting on the mcast
1163 * queue (to prevent out of order delivery) multicast
1164 * frames must be buffered until after the beacon.
1165 *
1166 * XXX This likely means that if there's a station in power
1167 * save mode, we won't be doing any kind of aggregation towards
1168 * anyone. This is likely a very suboptimal way of dealing
1169 * with things.
1170 */
1171 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
1172 txq = &avp->av_mcastq;
1173
1174 /*
1175 * Calculate miscellaneous flags.
1176 */
1177 if (ismcast) {
1178 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
1179 } else if (pktlen > vap->iv_rtsthreshold &&
1180 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
1181 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
1182 sc->sc_stats.ast_tx_rts++;
1183 }
1184 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
1185 sc->sc_stats.ast_tx_noack++;
1186#ifdef IEEE80211_SUPPORT_TDMA
1187 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
1188 DPRINTF(sc, ATH_DEBUG_TDMA,
1189 "%s: discard frame, ACK required w/ TDMA\n", __func__);
1190 sc->sc_stats.ast_tdma_ack++;
1191 ath_freetx(m0);
1192 return EIO;
1193 }
1194#endif
1195
1196 /*
1197 * If 802.11g protection is enabled, determine whether
1198 * to use RTS/CTS or just CTS. Note that this is only
1199 * done for OFDM unicast frames.
1200 */
1201 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1202 rt->info[rix].phy == IEEE80211_T_OFDM &&
1203 (flags & HAL_TXDESC_NOACK) == 0) {
1204 bf->bf_state.bfs_doprot = 1;
1205 /* XXX fragments must use CCK rates w/ protection */
1206 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1207 flags |= HAL_TXDESC_RTSENA;
1208 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1209 flags |= HAL_TXDESC_CTSENA;
1210 }
1211 /*
1212 * For frags it would be desirable to use the
1213 * highest CCK rate for RTS/CTS. But stations
1214 * farther away may detect it at a lower CCK rate
1215 * so use the configured protection rate instead
1216 * (for now).
1217 */
1218 sc->sc_stats.ast_tx_protect++;
1219 }
1220
1221#if 0
1222 /*
1223 * If 11n protection is enabled and it's a HT frame,
1224 * enable RTS.
1225 *
1226 * XXX ic_htprotmode or ic_curhtprotmode?
1227 * XXX should it_htprotmode only matter if ic_curhtprotmode
1228 * XXX indicates it's not a HT pure environment?
1229 */
1230 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) &&
1231 rt->info[rix].phy == IEEE80211_T_HT &&
1232 (flags & HAL_TXDESC_NOACK) == 0) {
1233 cix = rt->info[sc->sc_protrix].controlRate;
1234 flags |= HAL_TXDESC_RTSENA;
1235 sc->sc_stats.ast_tx_htprotect++;
1236 }
1237#endif
1238
1239 /*
1240 * Calculate duration. This logically belongs in the 802.11
1241 * layer but it lacks sufficient information to calculate it.
1242 */
1243 if ((flags & HAL_TXDESC_NOACK) == 0 &&
1244 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
1245 u_int16_t dur;
1246 if (shortPreamble)
1247 dur = rt->info[rix].spAckDuration;
1248 else
1249 dur = rt->info[rix].lpAckDuration;
1250 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
1251 dur += dur; /* additional SIFS+ACK */
1252 KASSERT(m0->m_nextpkt != NULL, ("no fragment"));
1253 /*
1254 * Include the size of next fragment so NAV is
1255 * updated properly. The last fragment uses only
1256 * the ACK duration
1257 */
1258 dur += ath_hal_computetxtime(ah, rt,
1259 m0->m_nextpkt->m_pkthdr.len,
1260 rix, shortPreamble);
1261 }
1262 if (isfrag) {
1263 /*
1264 * Force hardware to use computed duration for next
1265 * fragment by disabling multi-rate retry which updates
1266 * duration based on the multi-rate duration table.
1267 */
1268 ismrr = 0;
1269 try0 = ATH_TXMGTTRY; /* XXX? */
1270 }
1271 *(u_int16_t *)wh->i_dur = htole16(dur);
1272 }
1273
1274 /*
1275 * Determine if a tx interrupt should be generated for
1276 * this descriptor. We take a tx interrupt to reap
1277 * descriptors when the h/w hits an EOL condition or
1278 * when the descriptor is specifically marked to generate
1279 * an interrupt. We periodically mark descriptors in this
1280 * way to insure timely replenishing of the supply needed
1281 * for sending frames. Defering interrupts reduces system
1282 * load and potentially allows more concurrent work to be
1283 * done but if done to aggressively can cause senders to
1284 * backup.
1285 *
1286 * NB: use >= to deal with sc_txintrperiod changing
1287 * dynamically through sysctl.
1288 */
1289 if (flags & HAL_TXDESC_INTREQ) {
1290 txq->axq_intrcnt = 0;
1291 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
1292 flags |= HAL_TXDESC_INTREQ;
1293 txq->axq_intrcnt = 0;
1294 }
1295
1296 /* This point forward is actual TX bits */
1297
1298 /*
1299 * At this point we are committed to sending the frame
1300 * and we don't need to look at m_nextpkt; clear it in
1301 * case this frame is part of frag chain.
1302 */
1303 m0->m_nextpkt = NULL;
1304
1305 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1306 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
1307 sc->sc_hwmap[rix].ieeerate, -1);
1308
1309 if (ieee80211_radiotap_active_vap(vap)) {
1310 u_int64_t tsf = ath_hal_gettsf64(ah);
1311
1312 sc->sc_tx_th.wt_tsf = htole64(tsf);
1313 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1314 if (iswep)
1315 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1316 if (isfrag)
1317 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1318 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1319 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1320 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1321
1322 ieee80211_radiotap_tx(vap, m0);
1323 }
1324
1325 /* Blank the legacy rate array */
1326 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1327
1328 /*
1329 * ath_buf_set_rate needs at least one rate/try to setup
1330 * the rate scenario.
1331 */
1332 bf->bf_state.bfs_rc[0].rix = rix;
1333 bf->bf_state.bfs_rc[0].tries = try0;
1334 bf->bf_state.bfs_rc[0].ratecode = txrate;
1335
1336 /* Store the decided rate index values away */
1337 bf->bf_state.bfs_pktlen = pktlen;
1338 bf->bf_state.bfs_hdrlen = hdrlen;
1339 bf->bf_state.bfs_atype = atype;
1340 bf->bf_state.bfs_txpower = ni->ni_txpower;
1341 bf->bf_state.bfs_txrate0 = txrate;
1342 bf->bf_state.bfs_try0 = try0;
1343 bf->bf_state.bfs_keyix = keyix;
1344 bf->bf_state.bfs_txantenna = sc->sc_txantenna;
1345 bf->bf_state.bfs_flags = flags;
1346 bf->bf_txflags = flags;
1347 bf->bf_state.bfs_shpream = shortPreamble;
1348
1349 /* XXX this should be done in ath_tx_setrate() */
1350 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */
1351 bf->bf_state.bfs_ctsrate = 0; /* calculated later */
1352 bf->bf_state.bfs_ctsduration = 0;
1353 bf->bf_state.bfs_ismrr = ismrr;
1354
1355 return 0;
1356}
1357
1358/*
1359 * Direct-dispatch the current frame to the hardware.
1360 *
1361 * This can be called by the net80211 code.
1362 *
1363 * XXX what about locking? Or, push the seqno assign into the
1364 * XXX aggregate scheduler so its serialised?
1365 */
1366int
1367ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
1368 struct ath_buf *bf, struct mbuf *m0)
1369{
1370 struct ieee80211vap *vap = ni->ni_vap;
1371 struct ath_vap *avp = ATH_VAP(vap);
1372 int r = 0;
1373 u_int pri;
1374 int tid;
1375 struct ath_txq *txq;
1376 int ismcast;
1377 const struct ieee80211_frame *wh;
1378 int is_ampdu, is_ampdu_tx, is_ampdu_pending;
|
1379 ieee80211_seq seqno;
| 1379 //ieee80211_seq seqno;
|
1380 uint8_t type, subtype;
1381
1382 /*
1383 * Determine the target hardware queue.
1384 *
1385 * For multicast frames, the txq gets overridden to be the
1386 * software TXQ and it's done via direct-dispatch.
1387 *
1388 * For any other frame, we do a TID/QoS lookup inside the frame
1389 * to see what the TID should be. If it's a non-QoS frame, the
1390 * AC and TID are overridden. The TID/TXQ code assumes the
1391 * TID is on a predictable hardware TXQ, so we don't support
1392 * having a node TID queued to multiple hardware TXQs.
1393 * This may change in the future but would require some locking
1394 * fudgery.
1395 */
1396 pri = ath_tx_getac(sc, m0);
1397 tid = ath_tx_gettid(sc, m0);
1398
1399 txq = sc->sc_ac2q[pri];
1400 wh = mtod(m0, struct ieee80211_frame *);
1401 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1402 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1403 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1404
1405 /*
1406 * Enforce how deep the multicast queue can grow.
1407 *
1408 * XXX duplicated in ath_raw_xmit().
1409 */
1410 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1411 ATH_TXQ_LOCK(sc->sc_cabq);
1412
1413 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
1414 sc->sc_stats.ast_tx_mcastq_overflow++;
1415 r = ENOBUFS;
1416 }
1417
1418 ATH_TXQ_UNLOCK(sc->sc_cabq);
1419
1420 if (r != 0) {
1421 m_freem(m0);
1422 return r;
1423 }
1424 }
1425
1426 /* A-MPDU TX */
1427 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid);
1428 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid);
1429 is_ampdu = is_ampdu_tx | is_ampdu_pending;
1430
| 1380 uint8_t type, subtype;
1381
1382 /*
1383 * Determine the target hardware queue.
1384 *
1385 * For multicast frames, the txq gets overridden to be the
1386 * software TXQ and it's done via direct-dispatch.
1387 *
1388 * For any other frame, we do a TID/QoS lookup inside the frame
1389 * to see what the TID should be. If it's a non-QoS frame, the
1390 * AC and TID are overridden. The TID/TXQ code assumes the
1391 * TID is on a predictable hardware TXQ, so we don't support
1392 * having a node TID queued to multiple hardware TXQs.
1393 * This may change in the future but would require some locking
1394 * fudgery.
1395 */
1396 pri = ath_tx_getac(sc, m0);
1397 tid = ath_tx_gettid(sc, m0);
1398
1399 txq = sc->sc_ac2q[pri];
1400 wh = mtod(m0, struct ieee80211_frame *);
1401 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1402 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1403 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1404
1405 /*
1406 * Enforce how deep the multicast queue can grow.
1407 *
1408 * XXX duplicated in ath_raw_xmit().
1409 */
1410 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1411 ATH_TXQ_LOCK(sc->sc_cabq);
1412
1413 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
1414 sc->sc_stats.ast_tx_mcastq_overflow++;
1415 r = ENOBUFS;
1416 }
1417
1418 ATH_TXQ_UNLOCK(sc->sc_cabq);
1419
1420 if (r != 0) {
1421 m_freem(m0);
1422 return r;
1423 }
1424 }
1425
1426 /* A-MPDU TX */
1427 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid);
1428 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid);
1429 is_ampdu = is_ampdu_tx | is_ampdu_pending;
1430
|
1431 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n",
1432 __func__, tid, pri, is_ampdu);
| 1431 DPRINTF(sc, ATH_DEBUG_SW_TX,
1432 "%s: bf=%p, tid=%d, ac=%d, is_ampdu=%d\n",
1433 __func__, bf, tid, pri, is_ampdu);
|
1433
1434 /* Multicast frames go onto the software multicast queue */
1435 if (ismcast)
1436 txq = &avp->av_mcastq;
1437
1438 /*
1439 * XXX This likely means that if there's a station in power
1440 * save mode, we won't be doing any kind of aggregation towards
1441 * anyone. This is likely a very suboptimal way of dealing
1442 * with things.
1443 */
1444 if ((! is_ampdu) && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
1445 txq = &avp->av_mcastq;
1446
1447 /* Do the generic frame setup */
1448 /* XXX should just bzero the bf_state? */
1449 bf->bf_state.bfs_dobaw = 0;
| 1434
1435 /* Multicast frames go onto the software multicast queue */
1436 if (ismcast)
1437 txq = &avp->av_mcastq;
1438
1439 /*
1440 * XXX This likely means that if there's a station in power
1441 * save mode, we won't be doing any kind of aggregation towards
1442 * anyone. This is likely a very suboptimal way of dealing
1443 * with things.
1444 */
1445 if ((! is_ampdu) && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
1446 txq = &avp->av_mcastq;
1447
1448 /* Do the generic frame setup */
1449 /* XXX should just bzero the bf_state? */
1450 bf->bf_state.bfs_dobaw = 0;
|
| 1451 bf->bf_state.bfs_seqno_assigned = 0;
1452 bf->bf_state.bfs_need_seqno = 0;
1453 bf->bf_state.bfs_seqno = -1; /* XXX debugging */
|
1450
1451 /* A-MPDU TX? Manually set sequence number */
1452 /* Don't do it whilst pending; the net80211 layer still assigns them */
1453 /* XXX do we need locking here? */
1454 if (is_ampdu_tx) {
1455 ATH_TXQ_LOCK(txq);
1456 /*
1457 * Always call; this function will
1458 * handle making sure that null data frames
1459 * don't get a sequence number from the current
1460 * TID and thus mess with the BAW.
1461 */
| 1454
1455 /* A-MPDU TX? Manually set sequence number */
1456 /* Don't do it whilst pending; the net80211 layer still assigns them */
1457 /* XXX do we need locking here? */
1458 if (is_ampdu_tx) {
1459 ATH_TXQ_LOCK(txq);
1460 /*
1461 * Always call; this function will
1462 * handle making sure that null data frames
1463 * don't get a sequence number from the current
1464 * TID and thus mess with the BAW.
1465 */
|
1462 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0);
1463 if (IEEE80211_QOS_HAS_SEQ(wh) &&
1464 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) {
| 1466 //seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0);
1467 if (ath_tx_seqno_required(sc, ni, bf, m0)) {
|
1465 bf->bf_state.bfs_dobaw = 1;
| 1468 bf->bf_state.bfs_dobaw = 1;
|
| 1469 bf->bf_state.bfs_need_seqno = 1;
|
1466 }
1467 ATH_TXQ_UNLOCK(txq);
| 1470 }
1471 ATH_TXQ_UNLOCK(txq);
|
| 1472 } else {
1473 /* No AMPDU TX, we've been assigned a sequence number. */
1474 if (IEEE80211_QOS_HAS_SEQ(wh)) {
1475 bf->bf_state.bfs_seqno_assigned = 1;
1476 bf->bf_state.bfs_seqno =
1477 M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT;
1478 }
|
1468 }
1469
1470 /*
1471 * If needed, the sequence number has been assigned.
1472 * Squirrel it away somewhere easy to get to.
1473 */
| 1479 }
1480
1481 /*
1482 * If needed, the sequence number has been assigned.
1483 * Squirrel it away somewhere easy to get to.
1484 */
|
1474 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT;
| 1485 //bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT;
|
1475
1476 /* Is ampdu pending? fetch the seqno and print it out */
1477 if (is_ampdu_pending)
1478 DPRINTF(sc, ATH_DEBUG_SW_TX,
1479 "%s: tid %d: ampdu pending, seqno %d\n",
1480 __func__, tid, M_SEQNO_GET(m0));
1481
1482 /* This also sets up the DMA map */
1483 r = ath_tx_normal_setup(sc, ni, bf, m0);
1484
1485 if (r != 0)
1486 return r;
1487
1488 /* At this point m0 could have changed! */
1489 m0 = bf->bf_m;
1490
| 1486
1487 /* Is ampdu pending? fetch the seqno and print it out */
1488 if (is_ampdu_pending)
1489 DPRINTF(sc, ATH_DEBUG_SW_TX,
1490 "%s: tid %d: ampdu pending, seqno %d\n",
1491 __func__, tid, M_SEQNO_GET(m0));
1492
1493 /* This also sets up the DMA map */
1494 r = ath_tx_normal_setup(sc, ni, bf, m0);
1495
1496 if (r != 0)
1497 return r;
1498
1499 /* At this point m0 could have changed! */
1500 m0 = bf->bf_m;
1501
|
| 1502 DPRINTF(sc, ATH_DEBUG_SW_TX,
1503 "%s: DONE: bf=%p, tid=%d, ac=%d, is_ampdu=%d, dobaw=%d, seqno=%d\n",
1504 __func__, bf, tid, pri, is_ampdu, bf->bf_state.bfs_dobaw, M_SEQNO_GET(m0));
1505
|
1491#if 1
1492 /*
1493 * If it's a multicast frame, do a direct-dispatch to the
1494 * destination hardware queue. Don't bother software
1495 * queuing it.
1496 */
1497 /*
1498 * If it's a BAR frame, do a direct dispatch to the
1499 * destination hardware queue. Don't bother software
1500 * queuing it, as the TID will now be paused.
1501 * Sending a BAR frame can occur from the net80211 txa timer
1502 * (ie, retries) or from the ath txtask (completion call.)
1503 * It queues directly to hardware because the TID is paused
1504 * at this point (and won't be unpaused until the BAR has
1505 * either been TXed successfully or max retries has been
1506 * reached.)
1507 */
1508 if (txq == &avp->av_mcastq) {
| 1506#if 1
1507 /*
1508 * If it's a multicast frame, do a direct-dispatch to the
1509 * destination hardware queue. Don't bother software
1510 * queuing it.
1511 */
1512 /*
1513 * If it's a BAR frame, do a direct dispatch to the
1514 * destination hardware queue. Don't bother software
1515 * queuing it, as the TID will now be paused.
1516 * Sending a BAR frame can occur from the net80211 txa timer
1517 * (ie, retries) or from the ath txtask (completion call.)
1518 * It queues directly to hardware because the TID is paused
1519 * at this point (and won't be unpaused until the BAR has
1520 * either been TXed successfully or max retries has been
1521 * reached.)
1522 */
1523 if (txq == &avp->av_mcastq) {
|
| 1524 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
1525 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf);
|
1509 ATH_TXQ_LOCK(txq);
1510 ath_tx_xmit_normal(sc, txq, bf);
1511 ATH_TXQ_UNLOCK(txq);
1512 } else if (type == IEEE80211_FC0_TYPE_CTL &&
1513 subtype == IEEE80211_FC0_SUBTYPE_BAR) {
1514 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
1515 "%s: BAR: TX'ing direct\n", __func__);
1516 ATH_TXQ_LOCK(txq);
1517 ath_tx_xmit_normal(sc, txq, bf);
1518 ATH_TXQ_UNLOCK(txq);
1519 } else {
1520 /* add to software queue */
| 1526 ATH_TXQ_LOCK(txq);
1527 ath_tx_xmit_normal(sc, txq, bf);
1528 ATH_TXQ_UNLOCK(txq);
1529 } else if (type == IEEE80211_FC0_TYPE_CTL &&
1530 subtype == IEEE80211_FC0_SUBTYPE_BAR) {
1531 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
1532 "%s: BAR: TX'ing direct\n", __func__);
1533 ATH_TXQ_LOCK(txq);
1534 ath_tx_xmit_normal(sc, txq, bf);
1535 ATH_TXQ_UNLOCK(txq);
1536 } else {
1537 /* add to software queue */
|
| 1538 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
1539 "%s: bf=%p: swq: TX'ing\n", __func__, bf);
|
1521 ath_tx_swq(sc, ni, txq, bf);
1522 }
1523#else
1524 /*
1525 * For now, since there's no software queue,
1526 * direct-dispatch to the hardware.
1527 */
1528 ATH_TXQ_LOCK(txq);
1529 ath_tx_xmit_normal(sc, txq, bf);
1530 ATH_TXQ_UNLOCK(txq);
1531#endif
1532
1533 return 0;
1534}
1535
1536static int
1537ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
1538 struct ath_buf *bf, struct mbuf *m0,
1539 const struct ieee80211_bpf_params *params)
1540{
1541 struct ifnet *ifp = sc->sc_ifp;
1542 struct ieee80211com *ic = ifp->if_l2com;
1543 struct ath_hal *ah = sc->sc_ah;
1544 struct ieee80211vap *vap = ni->ni_vap;
1545 int error, ismcast, ismrr;
1546 int keyix, hdrlen, pktlen, try0, txantenna;
1547 u_int8_t rix, txrate;
1548 struct ieee80211_frame *wh;
1549 u_int flags;
1550 HAL_PKT_TYPE atype;
1551 const HAL_RATE_TABLE *rt;
1552 struct ath_desc *ds;
1553 u_int pri;
1554 int o_tid = -1;
1555 int do_override;
1556
1557 wh = mtod(m0, struct ieee80211_frame *);
1558 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1559 hdrlen = ieee80211_anyhdrsize(wh);
1560 /*
1561 * Packet length must not include any
1562 * pad bytes; deduct them here.
1563 */
1564 /* XXX honor IEEE80211_BPF_DATAPAD */
1565 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
1566
1567
1568 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n",
1569 __func__, ismcast);
1570
1571 /* Handle encryption twiddling if needed */
1572 if (! ath_tx_tag_crypto(sc, ni,
1573 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0,
1574 &hdrlen, &pktlen, &keyix)) {
1575 ath_freetx(m0);
1576 return EIO;
1577 }
1578 /* packet header may have moved, reset our local pointer */
1579 wh = mtod(m0, struct ieee80211_frame *);
1580
1581 /* Do the generic frame setup */
1582 /* XXX should just bzero the bf_state? */
1583 bf->bf_state.bfs_dobaw = 0;
1584
1585 error = ath_tx_dmasetup(sc, bf, m0);
1586 if (error != 0)
1587 return error;
1588 m0 = bf->bf_m; /* NB: may have changed */
1589 wh = mtod(m0, struct ieee80211_frame *);
1590 bf->bf_node = ni; /* NB: held reference */
1591
1592 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1593 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1594 if (params->ibp_flags & IEEE80211_BPF_RTS)
1595 flags |= HAL_TXDESC_RTSENA;
1596 else if (params->ibp_flags & IEEE80211_BPF_CTS) {
1597 /* XXX assume 11g/11n protection? */
1598 bf->bf_state.bfs_doprot = 1;
1599 flags |= HAL_TXDESC_CTSENA;
1600 }
1601 /* XXX leave ismcast to injector? */
1602 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
1603 flags |= HAL_TXDESC_NOACK;
1604
1605 rt = sc->sc_currates;
1606 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1607 rix = ath_tx_findrix(sc, params->ibp_rate0);
1608 txrate = rt->info[rix].rateCode;
1609 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
1610 txrate |= rt->info[rix].shortPreamble;
1611 sc->sc_txrix = rix;
1612 try0 = params->ibp_try0;
1613 ismrr = (params->ibp_try1 != 0);
1614 txantenna = params->ibp_pri >> 2;
1615 if (txantenna == 0) /* XXX? */
1616 txantenna = sc->sc_txantenna;
1617
1618 /*
1619 * Since ctsrate is fixed, store it away for later
1620 * use when the descriptor fields are being set.
1621 */
1622 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA))
1623 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate;
1624
1625 pri = params->ibp_pri & 3;
1626 /* Override pri if the frame isn't a QoS one */
1627 if (! IEEE80211_QOS_HAS_SEQ(wh))
1628 pri = ath_tx_getac(sc, m0);
1629
1630 /*
1631 * NB: we mark all packets as type PSPOLL so the h/w won't
1632 * set the sequence number, duration, etc.
1633 */
1634 atype = HAL_PKT_TYPE_PSPOLL;
1635
1636 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1637 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
1638 sc->sc_hwmap[rix].ieeerate, -1);
1639
1640 if (ieee80211_radiotap_active_vap(vap)) {
1641 u_int64_t tsf = ath_hal_gettsf64(ah);
1642
1643 sc->sc_tx_th.wt_tsf = htole64(tsf);
1644 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1645 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
1646 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1647 if (m0->m_flags & M_FRAG)
1648 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1649 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1650 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1651 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1652
1653 ieee80211_radiotap_tx(vap, m0);
1654 }
1655
1656 /*
1657 * Formulate first tx descriptor with tx controls.
1658 */
1659 ds = bf->bf_desc;
1660 /* XXX check return value? */
1661
1662 /* Store the decided rate index values away */
1663 bf->bf_state.bfs_pktlen = pktlen;
1664 bf->bf_state.bfs_hdrlen = hdrlen;
1665 bf->bf_state.bfs_atype = atype;
1666 bf->bf_state.bfs_txpower = params->ibp_power;
1667 bf->bf_state.bfs_txrate0 = txrate;
1668 bf->bf_state.bfs_try0 = try0;
1669 bf->bf_state.bfs_keyix = keyix;
1670 bf->bf_state.bfs_txantenna = txantenna;
1671 bf->bf_state.bfs_flags = flags;
1672 bf->bf_txflags = flags;
1673 bf->bf_state.bfs_shpream =
1674 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE);
1675
1676 /* XXX this should be done in ath_tx_setrate() */
1677 bf->bf_state.bfs_ctsrate = 0;
1678 bf->bf_state.bfs_ctsduration = 0;
1679 bf->bf_state.bfs_ismrr = ismrr;
1680
1681 /* Blank the legacy rate array */
1682 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1683
1684 bf->bf_state.bfs_rc[0].rix =
1685 ath_tx_findrix(sc, params->ibp_rate0);
1686 bf->bf_state.bfs_rc[0].tries = try0;
1687 bf->bf_state.bfs_rc[0].ratecode = txrate;
1688
1689 if (ismrr) {
1690 int rix;
1691
1692 rix = ath_tx_findrix(sc, params->ibp_rate1);
1693 bf->bf_state.bfs_rc[1].rix = rix;
1694 bf->bf_state.bfs_rc[1].tries = params->ibp_try1;
1695
1696 rix = ath_tx_findrix(sc, params->ibp_rate2);
1697 bf->bf_state.bfs_rc[2].rix = rix;
1698 bf->bf_state.bfs_rc[2].tries = params->ibp_try2;
1699
1700 rix = ath_tx_findrix(sc, params->ibp_rate3);
1701 bf->bf_state.bfs_rc[3].rix = rix;
1702 bf->bf_state.bfs_rc[3].tries = params->ibp_try3;
1703 }
1704 /*
1705 * All the required rate control decisions have been made;
1706 * fill in the rc flags.
1707 */
1708 ath_tx_rate_fill_rcflags(sc, bf);
1709
1710 /* NB: no buffered multicast in power save support */
1711
1712 /* XXX If it's an ADDBA, override the correct queue */
1713 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid);
1714
1715 /* Map ADDBA to the correct priority */
1716 if (do_override) {
1717#if 0
1718 device_printf(sc->sc_dev,
1719 "%s: overriding tid %d pri %d -> %d\n",
1720 __func__, o_tid, pri, TID_TO_WME_AC(o_tid));
1721#endif
1722 pri = TID_TO_WME_AC(o_tid);
1723 }
1724
1725 /*
1726 * If we're overiding the ADDBA destination, dump directly
1727 * into the hardware queue, right after any pending
1728 * frames to that node are.
1729 */
1730 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n",
1731 __func__, do_override);
1732
1733 if (do_override) {
1734 ATH_TXQ_LOCK(sc->sc_ac2q[pri]);
1735 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
1736 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]);
1737 } else {
1738 /* Queue to software queue */
1739 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf);
1740 }
1741
1742 return 0;
1743}
1744
1745/*
1746 * Send a raw frame.
1747 *
1748 * This can be called by net80211.
1749 */
1750int
1751ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1752 const struct ieee80211_bpf_params *params)
1753{
1754 struct ieee80211com *ic = ni->ni_ic;
1755 struct ifnet *ifp = ic->ic_ifp;
1756 struct ath_softc *sc = ifp->if_softc;
1757 struct ath_buf *bf;
1758 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *);
1759 int error = 0;
1760
1761 ATH_PCU_LOCK(sc);
1762 if (sc->sc_inreset_cnt > 0) {
1763 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n",
1764 __func__);
1765 error = EIO;
1766 ATH_PCU_UNLOCK(sc);
1767 goto bad0;
1768 }
1769 sc->sc_txstart_cnt++;
1770 ATH_PCU_UNLOCK(sc);
1771
1772 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
1773 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
1774 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
1775 "!running" : "invalid");
1776 m_freem(m);
1777 error = ENETDOWN;
1778 goto bad;
1779 }
1780
1781 /*
1782 * Enforce how deep the multicast queue can grow.
1783 *
1784 * XXX duplicated in ath_tx_start().
1785 */
1786 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1787 ATH_TXQ_LOCK(sc->sc_cabq);
1788
1789 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
1790 sc->sc_stats.ast_tx_mcastq_overflow++;
1791 error = ENOBUFS;
1792 }
1793
1794 ATH_TXQ_UNLOCK(sc->sc_cabq);
1795
1796 if (error != 0) {
1797 m_freem(m);
1798 goto bad;
1799 }
1800 }
1801
1802 /*
1803 * Grab a TX buffer and associated resources.
1804 */
1805 bf = ath_getbuf(sc);
1806 if (bf == NULL) {
1807 sc->sc_stats.ast_tx_nobuf++;
1808 m_freem(m);
1809 error = ENOBUFS;
1810 goto bad;
1811 }
1812
1813 if (params == NULL) {
1814 /*
1815 * Legacy path; interpret frame contents to decide
1816 * precisely how to send the frame.
1817 */
1818 if (ath_tx_start(sc, ni, bf, m)) {
1819 error = EIO; /* XXX */
1820 goto bad2;
1821 }
1822 } else {
1823 /*
1824 * Caller supplied explicit parameters to use in
1825 * sending the frame.
1826 */
1827 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
1828 error = EIO; /* XXX */
1829 goto bad2;
1830 }
1831 }
1832 sc->sc_wd_timer = 5;
1833 ifp->if_opackets++;
1834 sc->sc_stats.ast_tx_raw++;
1835
1836 ATH_PCU_LOCK(sc);
1837 sc->sc_txstart_cnt--;
1838 ATH_PCU_UNLOCK(sc);
1839
1840 return 0;
1841bad2:
1842 ATH_TXBUF_LOCK(sc);
1843 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1844 ATH_TXBUF_UNLOCK(sc);
1845bad:
1846 ATH_PCU_LOCK(sc);
1847 sc->sc_txstart_cnt--;
1848 ATH_PCU_UNLOCK(sc);
1849bad0:
1850 ifp->if_oerrors++;
1851 sc->sc_stats.ast_tx_raw_fail++;
1852 ieee80211_free_node(ni);
1853
1854 return error;
1855}
1856
1857/* Some helper functions */
1858
1859/*
1860 * ADDBA (and potentially others) need to be placed in the same
1861 * hardware queue as the TID/node it's relating to. This is so
1862 * it goes out after any pending non-aggregate frames to the
1863 * same node/TID.
1864 *
1865 * If this isn't done, the ADDBA can go out before the frames
1866 * queued in hardware. Even though these frames have a sequence
1867 * number -earlier- than the ADDBA can be transmitted (but
1868 * no frames whose sequence numbers are after the ADDBA should
1869 * be!) they'll arrive after the ADDBA - and the receiving end
1870 * will simply drop them as being out of the BAW.
1871 *
1872 * The frames can't be appended to the TID software queue - it'll
1873 * never be sent out. So these frames have to be directly
1874 * dispatched to the hardware, rather than queued in software.
1875 * So if this function returns true, the TXQ has to be
1876 * overridden and it has to be directly dispatched.
1877 *
1878 * It's a dirty hack, but someone's gotta do it.
1879 */
1880
1881/*
1882 * XXX doesn't belong here!
1883 */
1884static int
1885ieee80211_is_action(struct ieee80211_frame *wh)
1886{
1887 /* Type: Management frame? */
1888 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
1889 IEEE80211_FC0_TYPE_MGT)
1890 return 0;
1891
1892 /* Subtype: Action frame? */
1893 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) !=
1894 IEEE80211_FC0_SUBTYPE_ACTION)
1895 return 0;
1896
1897 return 1;
1898}
1899
1900#define MS(_v, _f) (((_v) & _f) >> _f##_S)
1901/*
1902 * Return an alternate TID for ADDBA request frames.
1903 *
1904 * Yes, this likely should be done in the net80211 layer.
1905 */
1906static int
1907ath_tx_action_frame_override_queue(struct ath_softc *sc,
1908 struct ieee80211_node *ni,
1909 struct mbuf *m0, int *tid)
1910{
1911 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1912 struct ieee80211_action_ba_addbarequest *ia;
1913 uint8_t *frm;
1914 uint16_t baparamset;
1915
1916 /* Not action frame? Bail */
1917 if (! ieee80211_is_action(wh))
1918 return 0;
1919
1920 /* XXX Not needed for frames we send? */
1921#if 0
1922 /* Correct length? */
1923 if (! ieee80211_parse_action(ni, m))
1924 return 0;
1925#endif
1926
1927 /* Extract out action frame */
1928 frm = (u_int8_t *)&wh[1];
1929 ia = (struct ieee80211_action_ba_addbarequest *) frm;
1930
1931 /* Not ADDBA? Bail */
1932 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA)
1933 return 0;
1934 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST)
1935 return 0;
1936
1937 /* Extract TID, return it */
1938 baparamset = le16toh(ia->rq_baparamset);
1939 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID);
1940
1941 return 1;
1942}
1943#undef MS
1944
1945/* Per-node software queue operations */
1946
1947/*
1948 * Add the current packet to the given BAW.
1949 * It is assumed that the current packet
1950 *
1951 * + fits inside the BAW;
1952 * + already has had a sequence number allocated.
1953 *
1954 * Since the BAW status may be modified by both the ath task and
1955 * the net80211/ifnet contexts, the TID must be locked.
1956 */
1957void
1958ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an,
1959 struct ath_tid *tid, struct ath_buf *bf)
1960{
1961 int index, cindex;
1962 struct ieee80211_tx_ampdu *tap;
1963
1964 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
1965
1966 if (bf->bf_state.bfs_isretried)
1967 return;
1968
| 1540 ath_tx_swq(sc, ni, txq, bf);
1541 }
1542#else
1543 /*
1544 * For now, since there's no software queue,
1545 * direct-dispatch to the hardware.
1546 */
1547 ATH_TXQ_LOCK(txq);
1548 ath_tx_xmit_normal(sc, txq, bf);
1549 ATH_TXQ_UNLOCK(txq);
1550#endif
1551
1552 return 0;
1553}
1554
1555static int
1556ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
1557 struct ath_buf *bf, struct mbuf *m0,
1558 const struct ieee80211_bpf_params *params)
1559{
1560 struct ifnet *ifp = sc->sc_ifp;
1561 struct ieee80211com *ic = ifp->if_l2com;
1562 struct ath_hal *ah = sc->sc_ah;
1563 struct ieee80211vap *vap = ni->ni_vap;
1564 int error, ismcast, ismrr;
1565 int keyix, hdrlen, pktlen, try0, txantenna;
1566 u_int8_t rix, txrate;
1567 struct ieee80211_frame *wh;
1568 u_int flags;
1569 HAL_PKT_TYPE atype;
1570 const HAL_RATE_TABLE *rt;
1571 struct ath_desc *ds;
1572 u_int pri;
1573 int o_tid = -1;
1574 int do_override;
1575
1576 wh = mtod(m0, struct ieee80211_frame *);
1577 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1578 hdrlen = ieee80211_anyhdrsize(wh);
1579 /*
1580 * Packet length must not include any
1581 * pad bytes; deduct them here.
1582 */
1583 /* XXX honor IEEE80211_BPF_DATAPAD */
1584 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
1585
1586
1587 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n",
1588 __func__, ismcast);
1589
1590 /* Handle encryption twiddling if needed */
1591 if (! ath_tx_tag_crypto(sc, ni,
1592 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0,
1593 &hdrlen, &pktlen, &keyix)) {
1594 ath_freetx(m0);
1595 return EIO;
1596 }
1597 /* packet header may have moved, reset our local pointer */
1598 wh = mtod(m0, struct ieee80211_frame *);
1599
1600 /* Do the generic frame setup */
1601 /* XXX should just bzero the bf_state? */
1602 bf->bf_state.bfs_dobaw = 0;
1603
1604 error = ath_tx_dmasetup(sc, bf, m0);
1605 if (error != 0)
1606 return error;
1607 m0 = bf->bf_m; /* NB: may have changed */
1608 wh = mtod(m0, struct ieee80211_frame *);
1609 bf->bf_node = ni; /* NB: held reference */
1610
1611 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1612 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1613 if (params->ibp_flags & IEEE80211_BPF_RTS)
1614 flags |= HAL_TXDESC_RTSENA;
1615 else if (params->ibp_flags & IEEE80211_BPF_CTS) {
1616 /* XXX assume 11g/11n protection? */
1617 bf->bf_state.bfs_doprot = 1;
1618 flags |= HAL_TXDESC_CTSENA;
1619 }
1620 /* XXX leave ismcast to injector? */
1621 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
1622 flags |= HAL_TXDESC_NOACK;
1623
1624 rt = sc->sc_currates;
1625 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1626 rix = ath_tx_findrix(sc, params->ibp_rate0);
1627 txrate = rt->info[rix].rateCode;
1628 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
1629 txrate |= rt->info[rix].shortPreamble;
1630 sc->sc_txrix = rix;
1631 try0 = params->ibp_try0;
1632 ismrr = (params->ibp_try1 != 0);
1633 txantenna = params->ibp_pri >> 2;
1634 if (txantenna == 0) /* XXX? */
1635 txantenna = sc->sc_txantenna;
1636
1637 /*
1638 * Since ctsrate is fixed, store it away for later
1639 * use when the descriptor fields are being set.
1640 */
1641 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA))
1642 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate;
1643
1644 pri = params->ibp_pri & 3;
1645 /* Override pri if the frame isn't a QoS one */
1646 if (! IEEE80211_QOS_HAS_SEQ(wh))
1647 pri = ath_tx_getac(sc, m0);
1648
1649 /*
1650 * NB: we mark all packets as type PSPOLL so the h/w won't
1651 * set the sequence number, duration, etc.
1652 */
1653 atype = HAL_PKT_TYPE_PSPOLL;
1654
1655 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1656 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
1657 sc->sc_hwmap[rix].ieeerate, -1);
1658
1659 if (ieee80211_radiotap_active_vap(vap)) {
1660 u_int64_t tsf = ath_hal_gettsf64(ah);
1661
1662 sc->sc_tx_th.wt_tsf = htole64(tsf);
1663 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1664 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
1665 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1666 if (m0->m_flags & M_FRAG)
1667 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1668 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1669 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1670 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1671
1672 ieee80211_radiotap_tx(vap, m0);
1673 }
1674
1675 /*
1676 * Formulate first tx descriptor with tx controls.
1677 */
1678 ds = bf->bf_desc;
1679 /* XXX check return value? */
1680
1681 /* Store the decided rate index values away */
1682 bf->bf_state.bfs_pktlen = pktlen;
1683 bf->bf_state.bfs_hdrlen = hdrlen;
1684 bf->bf_state.bfs_atype = atype;
1685 bf->bf_state.bfs_txpower = params->ibp_power;
1686 bf->bf_state.bfs_txrate0 = txrate;
1687 bf->bf_state.bfs_try0 = try0;
1688 bf->bf_state.bfs_keyix = keyix;
1689 bf->bf_state.bfs_txantenna = txantenna;
1690 bf->bf_state.bfs_flags = flags;
1691 bf->bf_txflags = flags;
1692 bf->bf_state.bfs_shpream =
1693 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE);
1694
1695 /* XXX this should be done in ath_tx_setrate() */
1696 bf->bf_state.bfs_ctsrate = 0;
1697 bf->bf_state.bfs_ctsduration = 0;
1698 bf->bf_state.bfs_ismrr = ismrr;
1699
1700 /* Blank the legacy rate array */
1701 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1702
1703 bf->bf_state.bfs_rc[0].rix =
1704 ath_tx_findrix(sc, params->ibp_rate0);
1705 bf->bf_state.bfs_rc[0].tries = try0;
1706 bf->bf_state.bfs_rc[0].ratecode = txrate;
1707
1708 if (ismrr) {
1709 int rix;
1710
1711 rix = ath_tx_findrix(sc, params->ibp_rate1);
1712 bf->bf_state.bfs_rc[1].rix = rix;
1713 bf->bf_state.bfs_rc[1].tries = params->ibp_try1;
1714
1715 rix = ath_tx_findrix(sc, params->ibp_rate2);
1716 bf->bf_state.bfs_rc[2].rix = rix;
1717 bf->bf_state.bfs_rc[2].tries = params->ibp_try2;
1718
1719 rix = ath_tx_findrix(sc, params->ibp_rate3);
1720 bf->bf_state.bfs_rc[3].rix = rix;
1721 bf->bf_state.bfs_rc[3].tries = params->ibp_try3;
1722 }
1723 /*
1724 * All the required rate control decisions have been made;
1725 * fill in the rc flags.
1726 */
1727 ath_tx_rate_fill_rcflags(sc, bf);
1728
1729 /* NB: no buffered multicast in power save support */
1730
1731 /* XXX If it's an ADDBA, override the correct queue */
1732 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid);
1733
1734 /* Map ADDBA to the correct priority */
1735 if (do_override) {
1736#if 0
1737 device_printf(sc->sc_dev,
1738 "%s: overriding tid %d pri %d -> %d\n",
1739 __func__, o_tid, pri, TID_TO_WME_AC(o_tid));
1740#endif
1741 pri = TID_TO_WME_AC(o_tid);
1742 }
1743
1744 /*
1745 * If we're overiding the ADDBA destination, dump directly
1746 * into the hardware queue, right after any pending
1747 * frames to that node are.
1748 */
1749 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n",
1750 __func__, do_override);
1751
1752 if (do_override) {
1753 ATH_TXQ_LOCK(sc->sc_ac2q[pri]);
1754 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
1755 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]);
1756 } else {
1757 /* Queue to software queue */
1758 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf);
1759 }
1760
1761 return 0;
1762}
1763
1764/*
1765 * Send a raw frame.
1766 *
1767 * This can be called by net80211.
1768 */
1769int
1770ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1771 const struct ieee80211_bpf_params *params)
1772{
1773 struct ieee80211com *ic = ni->ni_ic;
1774 struct ifnet *ifp = ic->ic_ifp;
1775 struct ath_softc *sc = ifp->if_softc;
1776 struct ath_buf *bf;
1777 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *);
1778 int error = 0;
1779
1780 ATH_PCU_LOCK(sc);
1781 if (sc->sc_inreset_cnt > 0) {
1782 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n",
1783 __func__);
1784 error = EIO;
1785 ATH_PCU_UNLOCK(sc);
1786 goto bad0;
1787 }
1788 sc->sc_txstart_cnt++;
1789 ATH_PCU_UNLOCK(sc);
1790
1791 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
1792 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
1793 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
1794 "!running" : "invalid");
1795 m_freem(m);
1796 error = ENETDOWN;
1797 goto bad;
1798 }
1799
1800 /*
1801 * Enforce how deep the multicast queue can grow.
1802 *
1803 * XXX duplicated in ath_tx_start().
1804 */
1805 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1806 ATH_TXQ_LOCK(sc->sc_cabq);
1807
1808 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
1809 sc->sc_stats.ast_tx_mcastq_overflow++;
1810 error = ENOBUFS;
1811 }
1812
1813 ATH_TXQ_UNLOCK(sc->sc_cabq);
1814
1815 if (error != 0) {
1816 m_freem(m);
1817 goto bad;
1818 }
1819 }
1820
1821 /*
1822 * Grab a TX buffer and associated resources.
1823 */
1824 bf = ath_getbuf(sc);
1825 if (bf == NULL) {
1826 sc->sc_stats.ast_tx_nobuf++;
1827 m_freem(m);
1828 error = ENOBUFS;
1829 goto bad;
1830 }
1831
1832 if (params == NULL) {
1833 /*
1834 * Legacy path; interpret frame contents to decide
1835 * precisely how to send the frame.
1836 */
1837 if (ath_tx_start(sc, ni, bf, m)) {
1838 error = EIO; /* XXX */
1839 goto bad2;
1840 }
1841 } else {
1842 /*
1843 * Caller supplied explicit parameters to use in
1844 * sending the frame.
1845 */
1846 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
1847 error = EIO; /* XXX */
1848 goto bad2;
1849 }
1850 }
1851 sc->sc_wd_timer = 5;
1852 ifp->if_opackets++;
1853 sc->sc_stats.ast_tx_raw++;
1854
1855 ATH_PCU_LOCK(sc);
1856 sc->sc_txstart_cnt--;
1857 ATH_PCU_UNLOCK(sc);
1858
1859 return 0;
1860bad2:
1861 ATH_TXBUF_LOCK(sc);
1862 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1863 ATH_TXBUF_UNLOCK(sc);
1864bad:
1865 ATH_PCU_LOCK(sc);
1866 sc->sc_txstart_cnt--;
1867 ATH_PCU_UNLOCK(sc);
1868bad0:
1869 ifp->if_oerrors++;
1870 sc->sc_stats.ast_tx_raw_fail++;
1871 ieee80211_free_node(ni);
1872
1873 return error;
1874}
1875
1876/* Some helper functions */
1877
1878/*
1879 * ADDBA (and potentially others) need to be placed in the same
1880 * hardware queue as the TID/node it's relating to. This is so
1881 * it goes out after any pending non-aggregate frames to the
1882 * same node/TID.
1883 *
1884 * If this isn't done, the ADDBA can go out before the frames
1885 * queued in hardware. Even though these frames have a sequence
1886 * number -earlier- than the ADDBA can be transmitted (but
1887 * no frames whose sequence numbers are after the ADDBA should
1888 * be!) they'll arrive after the ADDBA - and the receiving end
1889 * will simply drop them as being out of the BAW.
1890 *
1891 * The frames can't be appended to the TID software queue - it'll
1892 * never be sent out. So these frames have to be directly
1893 * dispatched to the hardware, rather than queued in software.
1894 * So if this function returns true, the TXQ has to be
1895 * overridden and it has to be directly dispatched.
1896 *
1897 * It's a dirty hack, but someone's gotta do it.
1898 */
1899
1900/*
1901 * XXX doesn't belong here!
1902 */
1903static int
1904ieee80211_is_action(struct ieee80211_frame *wh)
1905{
1906 /* Type: Management frame? */
1907 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
1908 IEEE80211_FC0_TYPE_MGT)
1909 return 0;
1910
1911 /* Subtype: Action frame? */
1912 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) !=
1913 IEEE80211_FC0_SUBTYPE_ACTION)
1914 return 0;
1915
1916 return 1;
1917}
1918
1919#define MS(_v, _f) (((_v) & _f) >> _f##_S)
1920/*
1921 * Return an alternate TID for ADDBA request frames.
1922 *
1923 * Yes, this likely should be done in the net80211 layer.
1924 */
1925static int
1926ath_tx_action_frame_override_queue(struct ath_softc *sc,
1927 struct ieee80211_node *ni,
1928 struct mbuf *m0, int *tid)
1929{
1930 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1931 struct ieee80211_action_ba_addbarequest *ia;
1932 uint8_t *frm;
1933 uint16_t baparamset;
1934
1935 /* Not action frame? Bail */
1936 if (! ieee80211_is_action(wh))
1937 return 0;
1938
1939 /* XXX Not needed for frames we send? */
1940#if 0
1941 /* Correct length? */
1942 if (! ieee80211_parse_action(ni, m))
1943 return 0;
1944#endif
1945
1946 /* Extract out action frame */
1947 frm = (u_int8_t *)&wh[1];
1948 ia = (struct ieee80211_action_ba_addbarequest *) frm;
1949
1950 /* Not ADDBA? Bail */
1951 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA)
1952 return 0;
1953 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST)
1954 return 0;
1955
1956 /* Extract TID, return it */
1957 baparamset = le16toh(ia->rq_baparamset);
1958 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID);
1959
1960 return 1;
1961}
1962#undef MS
1963
1964/* Per-node software queue operations */
1965
1966/*
1967 * Add the current packet to the given BAW.
1968 * It is assumed that the current packet
1969 *
1970 * + fits inside the BAW;
1971 * + already has had a sequence number allocated.
1972 *
1973 * Since the BAW status may be modified by both the ath task and
1974 * the net80211/ifnet contexts, the TID must be locked.
1975 */
1976void
1977ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an,
1978 struct ath_tid *tid, struct ath_buf *bf)
1979{
1980 int index, cindex;
1981 struct ieee80211_tx_ampdu *tap;
1982
1983 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
1984
1985 if (bf->bf_state.bfs_isretried)
1986 return;
1987
|
| 1988 /*
1989 * If this occurs we're in a lot of trouble. We should try to
1990 * recover from this without the session hanging?
1991 */
1992 if (! bf->bf_state.bfs_seqno_assigned) {
1993 device_printf(sc->sc_dev,
1994 "%s: bf=%p, seqno_assigned is 0?!\n", __func__, bf);
1995 return;
1996 }
1997
|
1969 tap = ath_tx_get_tx_tid(an, tid->tid);
1970
1971 if (bf->bf_state.bfs_addedbaw)
1972 device_printf(sc->sc_dev,
| 1998 tap = ath_tx_get_tx_tid(an, tid->tid);
1999
2000 if (bf->bf_state.bfs_addedbaw)
2001 device_printf(sc->sc_dev,
|
1973 "%s: re-added? tid=%d, seqno %d; window %d:%d; "
| 2002 "%s: re-added? bf=%p, tid=%d, seqno %d; window %d:%d; "
|
1974 "baw head=%d tail=%d\n",
| 2003 "baw head=%d tail=%d\n",
|
1975 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
| 2004 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
|
1976 tap->txa_start, tap->txa_wnd, tid->baw_head,
1977 tid->baw_tail);
1978
1979 /*
| 2005 tap->txa_start, tap->txa_wnd, tid->baw_head,
2006 tid->baw_tail);
2007
2008 /*
|
| 2009 * Verify that the given sequence number is not outside of the
2010 * BAW. Complain loudly if that's the case.
2011 */
2012 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2013 SEQNO(bf->bf_state.bfs_seqno))) {
2014 device_printf(sc->sc_dev,
2015 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; "
2016 "baw head=%d tail=%d\n",
2017 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2018 tap->txa_start, tap->txa_wnd, tid->baw_head,
2019 tid->baw_tail);
2020
2021 }
2022
2023 /*
|
1980 * ni->ni_txseqs[] is the currently allocated seqno.
1981 * the txa state contains the current baw start.
1982 */
1983 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno));
1984 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1985 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
| 2024 * ni->ni_txseqs[] is the currently allocated seqno.
2025 * the txa state contains the current baw start.
2026 */
2027 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno));
2028 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2029 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
|
1986 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d "
| 2030 "%s: bf=%p, tid=%d, seqno %d; window %d:%d; index=%d cindex=%d "
|
1987 "baw head=%d tail=%d\n",
| 2031 "baw head=%d tail=%d\n",
|
1988 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
| 2032 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
|
1989 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head,
1990 tid->baw_tail);
1991
1992
1993#if 0
1994 assert(tid->tx_buf[cindex] == NULL);
1995#endif
1996 if (tid->tx_buf[cindex] != NULL) {
1997 device_printf(sc->sc_dev,
1998 "%s: ba packet dup (index=%d, cindex=%d, "
1999 "head=%d, tail=%d)\n",
2000 __func__, index, cindex, tid->baw_head, tid->baw_tail);
2001 device_printf(sc->sc_dev,
2002 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n",
2003 __func__,
2004 tid->tx_buf[cindex],
2005 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno),
2006 bf,
2007 SEQNO(bf->bf_state.bfs_seqno)
2008 );
2009 }
2010 tid->tx_buf[cindex] = bf;
2011
2012 if (index >= ((tid->baw_tail - tid->baw_head) &
2013 (ATH_TID_MAX_BUFS - 1))) {
2014 tid->baw_tail = cindex;
2015 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
2016 }
2017}
2018
2019/*
2020 * Flip the BAW buffer entry over from the existing one to the new one.
2021 *
2022 * When software retransmitting a (sub-)frame, it is entirely possible that
2023 * the frame ath_buf is marked as BUSY and can't be immediately reused.
2024 * In that instance the buffer is cloned and the new buffer is used for
2025 * retransmit. We thus need to update the ath_buf slot in the BAW buf
2026 * tracking array to maintain consistency.
2027 */
2028static void
2029ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an,
2030 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf)
2031{
2032 int index, cindex;
2033 struct ieee80211_tx_ampdu *tap;
2034 int seqno = SEQNO(old_bf->bf_state.bfs_seqno);
2035
2036 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2037
2038 tap = ath_tx_get_tx_tid(an, tid->tid);
2039 index = ATH_BA_INDEX(tap->txa_start, seqno);
2040 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2041
2042 /*
2043 * Just warn for now; if it happens then we should find out
2044 * about it. It's highly likely the aggregation session will
2045 * soon hang.
2046 */
2047 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) {
2048 device_printf(sc->sc_dev, "%s: retransmitted buffer"
2049 " has mismatching seqno's, BA session may hang.\n",
2050 __func__);
2051 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n",
2052 __func__,
2053 old_bf->bf_state.bfs_seqno,
2054 new_bf->bf_state.bfs_seqno);
2055 }
2056
2057 if (tid->tx_buf[cindex] != old_bf) {
2058 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; "
2059 " has m BA session may hang.\n",
2060 __func__);
2061 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n",
2062 __func__,
2063 old_bf, new_bf);
2064 }
2065
2066 tid->tx_buf[cindex] = new_bf;
2067}
2068
2069/*
2070 * seq_start - left edge of BAW
2071 * seq_next - current/next sequence number to allocate
2072 *
2073 * Since the BAW status may be modified by both the ath task and
2074 * the net80211/ifnet contexts, the TID must be locked.
2075 */
2076static void
2077ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an,
2078 struct ath_tid *tid, const struct ath_buf *bf)
2079{
2080 int index, cindex;
2081 struct ieee80211_tx_ampdu *tap;
2082 int seqno = SEQNO(bf->bf_state.bfs_seqno);
2083
2084 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2085
2086 tap = ath_tx_get_tx_tid(an, tid->tid);
2087 index = ATH_BA_INDEX(tap->txa_start, seqno);
2088 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2089
2090 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
| 2033 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head,
2034 tid->baw_tail);
2035
2036
2037#if 0
2038 assert(tid->tx_buf[cindex] == NULL);
2039#endif
2040 if (tid->tx_buf[cindex] != NULL) {
2041 device_printf(sc->sc_dev,
2042 "%s: ba packet dup (index=%d, cindex=%d, "
2043 "head=%d, tail=%d)\n",
2044 __func__, index, cindex, tid->baw_head, tid->baw_tail);
2045 device_printf(sc->sc_dev,
2046 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n",
2047 __func__,
2048 tid->tx_buf[cindex],
2049 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno),
2050 bf,
2051 SEQNO(bf->bf_state.bfs_seqno)
2052 );
2053 }
2054 tid->tx_buf[cindex] = bf;
2055
2056 if (index >= ((tid->baw_tail - tid->baw_head) &
2057 (ATH_TID_MAX_BUFS - 1))) {
2058 tid->baw_tail = cindex;
2059 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
2060 }
2061}
2062
2063/*
2064 * Flip the BAW buffer entry over from the existing one to the new one.
2065 *
2066 * When software retransmitting a (sub-)frame, it is entirely possible that
2067 * the frame ath_buf is marked as BUSY and can't be immediately reused.
2068 * In that instance the buffer is cloned and the new buffer is used for
2069 * retransmit. We thus need to update the ath_buf slot in the BAW buf
2070 * tracking array to maintain consistency.
2071 */
2072static void
2073ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an,
2074 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf)
2075{
2076 int index, cindex;
2077 struct ieee80211_tx_ampdu *tap;
2078 int seqno = SEQNO(old_bf->bf_state.bfs_seqno);
2079
2080 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2081
2082 tap = ath_tx_get_tx_tid(an, tid->tid);
2083 index = ATH_BA_INDEX(tap->txa_start, seqno);
2084 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2085
2086 /*
2087 * Just warn for now; if it happens then we should find out
2088 * about it. It's highly likely the aggregation session will
2089 * soon hang.
2090 */
2091 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) {
2092 device_printf(sc->sc_dev, "%s: retransmitted buffer"
2093 " has mismatching seqno's, BA session may hang.\n",
2094 __func__);
2095 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n",
2096 __func__,
2097 old_bf->bf_state.bfs_seqno,
2098 new_bf->bf_state.bfs_seqno);
2099 }
2100
2101 if (tid->tx_buf[cindex] != old_bf) {
2102 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; "
2103 " has m BA session may hang.\n",
2104 __func__);
2105 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n",
2106 __func__,
2107 old_bf, new_bf);
2108 }
2109
2110 tid->tx_buf[cindex] = new_bf;
2111}
2112
2113/*
2114 * seq_start - left edge of BAW
2115 * seq_next - current/next sequence number to allocate
2116 *
2117 * Since the BAW status may be modified by both the ath task and
2118 * the net80211/ifnet contexts, the TID must be locked.
2119 */
2120static void
2121ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an,
2122 struct ath_tid *tid, const struct ath_buf *bf)
2123{
2124 int index, cindex;
2125 struct ieee80211_tx_ampdu *tap;
2126 int seqno = SEQNO(bf->bf_state.bfs_seqno);
2127
2128 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2129
2130 tap = ath_tx_get_tx_tid(an, tid->tid);
2131 index = ATH_BA_INDEX(tap->txa_start, seqno);
2132 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2133
2134 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
|
2091 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, "
| 2135 "%s: bf=%p: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, "
|
2092 "baw head=%d, tail=%d\n",
| 2136 "baw head=%d, tail=%d\n",
|
2093 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index,
| 2137 __func__, bf, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index,
|
2094 cindex, tid->baw_head, tid->baw_tail);
2095
2096 /*
2097 * If this occurs then we have a big problem - something else
2098 * has slid tap->txa_start along without updating the BAW
2099 * tracking start/end pointers. Thus the TX BAW state is now
2100 * completely busted.
2101 *
2102 * But for now, since I haven't yet fixed TDMA and buffer cloning,
2103 * it's quite possible that a cloned buffer is making its way
2104 * here and causing it to fire off. Disable TDMA for now.
2105 */
2106 if (tid->tx_buf[cindex] != bf) {
2107 device_printf(sc->sc_dev,
2108 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n",
2109 __func__,
2110 bf, SEQNO(bf->bf_state.bfs_seqno),
2111 tid->tx_buf[cindex],
2112 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno));
2113 }
2114
2115 tid->tx_buf[cindex] = NULL;
2116
2117 while (tid->baw_head != tid->baw_tail &&
2118 !tid->tx_buf[tid->baw_head]) {
2119 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2120 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
2121 }
2122 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2123 "%s: baw is now %d:%d, baw head=%d\n",
2124 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head);
2125}
2126
2127/*
2128 * Mark the current node/TID as ready to TX.
2129 *
2130 * This is done to make it easy for the software scheduler to
2131 * find which nodes have data to send.
2132 *
2133 * The TXQ lock must be held.
2134 */
2135static void
2136ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid)
2137{
2138 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2139
2140 ATH_TXQ_LOCK_ASSERT(txq);
2141
2142 if (tid->paused)
2143 return; /* paused, can't schedule yet */
2144
2145 if (tid->sched)
2146 return; /* already scheduled */
2147
2148 tid->sched = 1;
2149
2150 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem);
2151}
2152
2153/*
2154 * Mark the current node as no longer needing to be polled for
2155 * TX packets.
2156 *
2157 * The TXQ lock must be held.
2158 */
2159static void
2160ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid)
2161{
2162 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2163
2164 ATH_TXQ_LOCK_ASSERT(txq);
2165
2166 if (tid->sched == 0)
2167 return;
2168
2169 tid->sched = 0;
2170 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem);
2171}
2172
2173/*
| 2138 cindex, tid->baw_head, tid->baw_tail);
2139
2140 /*
2141 * If this occurs then we have a big problem - something else
2142 * has slid tap->txa_start along without updating the BAW
2143 * tracking start/end pointers. Thus the TX BAW state is now
2144 * completely busted.
2145 *
2146 * But for now, since I haven't yet fixed TDMA and buffer cloning,
2147 * it's quite possible that a cloned buffer is making its way
2148 * here and causing it to fire off. Disable TDMA for now.
2149 */
2150 if (tid->tx_buf[cindex] != bf) {
2151 device_printf(sc->sc_dev,
2152 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n",
2153 __func__,
2154 bf, SEQNO(bf->bf_state.bfs_seqno),
2155 tid->tx_buf[cindex],
2156 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno));
2157 }
2158
2159 tid->tx_buf[cindex] = NULL;
2160
2161 while (tid->baw_head != tid->baw_tail &&
2162 !tid->tx_buf[tid->baw_head]) {
2163 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2164 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
2165 }
2166 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2167 "%s: baw is now %d:%d, baw head=%d\n",
2168 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head);
2169}
2170
2171/*
2172 * Mark the current node/TID as ready to TX.
2173 *
2174 * This is done to make it easy for the software scheduler to
2175 * find which nodes have data to send.
2176 *
2177 * The TXQ lock must be held.
2178 */
2179static void
2180ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid)
2181{
2182 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2183
2184 ATH_TXQ_LOCK_ASSERT(txq);
2185
2186 if (tid->paused)
2187 return; /* paused, can't schedule yet */
2188
2189 if (tid->sched)
2190 return; /* already scheduled */
2191
2192 tid->sched = 1;
2193
2194 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem);
2195}
2196
2197/*
2198 * Mark the current node as no longer needing to be polled for
2199 * TX packets.
2200 *
2201 * The TXQ lock must be held.
2202 */
2203static void
2204ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid)
2205{
2206 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2207
2208 ATH_TXQ_LOCK_ASSERT(txq);
2209
2210 if (tid->sched == 0)
2211 return;
2212
2213 tid->sched = 0;
2214 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem);
2215}
2216
2217/*
|
| 2218 * Return whether a sequence number is actually required.
2219 *
2220 * A sequence number must only be allocated at the time that a frame
2221 * is considered for addition to the BAW/aggregate and being TXed.
2222 * The sequence number must not be allocated before the frame
2223 * is added to the BAW (protected by the same lock instance)
2224 * otherwise a the multi-entrant TX path may result in a later seqno
2225 * being added to the BAW first. The subsequent addition of the
2226 * earlier seqno would then not go into the BAW as it's now outside
2227 * of said BAW.
2228 *
2229 * This routine is used by ath_tx_start() to mark whether the frame
2230 * should get a sequence number before adding it to the BAW.
2231 *
2232 * Then the actual aggregate TX routines will check whether this
2233 * flag is set and if the frame needs to go into the BAW, it'll
2234 * have a sequence number allocated for it.
2235 */
2236static int
2237ath_tx_seqno_required(struct ath_softc *sc, struct ieee80211_node *ni,
2238 struct ath_buf *bf, struct mbuf *m0)
2239{
2240 const struct ieee80211_frame *wh;
2241 uint8_t subtype;
2242
2243 wh = mtod(m0, const struct ieee80211_frame *);
2244 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2245
2246 /* XXX assert txq lock */
2247 /* XXX assert ampdu is set */
2248
2249 return ((IEEE80211_QOS_HAS_SEQ(wh) &&
2250 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL));
2251}
2252
2253/*
|
2174 * Assign a sequence number manually to the given frame.
2175 *
2176 * This should only be called for A-MPDU TX frames.
| 2254 * Assign a sequence number manually to the given frame.
2255 *
2256 * This should only be called for A-MPDU TX frames.
|
| 2257 *
2258 * If this is called after the initial frame setup, make sure you've flushed
2259 * the DMA map or you'll risk sending stale data to the NIC. This routine
2260 * updates the actual frame contents with the relevant seqno.
|
2177 */
| 2261 */
|
2178static ieee80211_seq
| 2262int
|
2179ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni,
2180 struct ath_buf *bf, struct mbuf *m0)
2181{
2182 struct ieee80211_frame *wh;
2183 int tid, pri;
2184 ieee80211_seq seqno;
2185 uint8_t subtype;
2186
2187 /* TID lookup */
2188 wh = mtod(m0, struct ieee80211_frame *);
2189 pri = M_WME_GETAC(m0); /* honor classification */
2190 tid = WME_AC_TO_TID(pri);
| 2263ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni,
2264 struct ath_buf *bf, struct mbuf *m0)
2265{
2266 struct ieee80211_frame *wh;
2267 int tid, pri;
2268 ieee80211_seq seqno;
2269 uint8_t subtype;
2270
2271 /* TID lookup */
2272 wh = mtod(m0, struct ieee80211_frame *);
2273 pri = M_WME_GETAC(m0); /* honor classification */
2274 tid = WME_AC_TO_TID(pri);
|
2191 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n",
2192 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
| 2275 DPRINTF(sc, ATH_DEBUG_SW_TX,
2276 "%s: bf=%p, pri=%d, tid=%d, qos has seq=%d\n",
2277 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
|
2193
| 2278
|
| 2279 if (! bf->bf_state.bfs_need_seqno) {
2280 device_printf(sc->sc_dev, "%s: bf=%p: need_seqno not set?!\n",
2281 __func__, bf);
2282 return -1;
2283 }
2284 /* XXX check for bfs_need_seqno? */
2285 if (bf->bf_state.bfs_seqno_assigned) {
2286 device_printf(sc->sc_dev,
2287 "%s: bf=%p: seqno already assigned (%d)?!\n",
2288 __func__, bf, SEQNO(bf->bf_state.bfs_seqno));
2289 return bf->bf_state.bfs_seqno >> IEEE80211_SEQ_SEQ_SHIFT;
2290 }
2291
|
2194 /* XXX Is it a control frame? Ignore */
2195
2196 /* Does the packet require a sequence number? */
2197 if (! IEEE80211_QOS_HAS_SEQ(wh))
2198 return -1;
2199
2200 /*
2201 * Is it a QOS NULL Data frame? Give it a sequence number from
2202 * the default TID (IEEE80211_NONQOS_TID.)
2203 *
2204 * The RX path of everything I've looked at doesn't include the NULL
2205 * data frame sequence number in the aggregation state updates, so
2206 * assigning it a sequence number there will cause a BAW hole on the
2207 * RX side.
2208 */
2209 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2210 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) {
2211 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID];
2212 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE);
2213 } else {
2214 /* Manually assign sequence number */
2215 seqno = ni->ni_txseqs[tid];
2216 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE);
2217 }
2218 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
2219 M_SEQNO_SET(m0, seqno);
| 2292 /* XXX Is it a control frame? Ignore */
2293
2294 /* Does the packet require a sequence number? */
2295 if (! IEEE80211_QOS_HAS_SEQ(wh))
2296 return -1;
2297
2298 /*
2299 * Is it a QOS NULL Data frame? Give it a sequence number from
2300 * the default TID (IEEE80211_NONQOS_TID.)
2301 *
2302 * The RX path of everything I've looked at doesn't include the NULL
2303 * data frame sequence number in the aggregation state updates, so
2304 * assigning it a sequence number there will cause a BAW hole on the
2305 * RX side.
2306 */
2307 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2308 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) {
2309 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID];
2310 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE);
2311 } else {
2312 /* Manually assign sequence number */
2313 seqno = ni->ni_txseqs[tid];
2314 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE);
2315 }
2316 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
2317 M_SEQNO_SET(m0, seqno);
|
| 2318 bf->bf_state.bfs_seqno = seqno << IEEE80211_SEQ_SEQ_SHIFT;
2319 bf->bf_state.bfs_seqno_assigned = 1;
|
2220
2221 /* Return so caller can do something with it if needed */
| 2320
2321 /* Return so caller can do something with it if needed */
|
2222 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno);
| 2322 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: -> seqno=%d\n",
2323 __func__,
2324 bf,
2325 seqno);
|
2223 return seqno;
2224}
2225
2226/*
2227 * Attempt to direct dispatch an aggregate frame to hardware.
2228 * If the frame is out of BAW, queue.
2229 * Otherwise, schedule it as a single frame.
2230 */
2231static void
2232ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, struct ath_buf *bf)
2233{
| 2326 return seqno;
2327}
2328
2329/*
2330 * Attempt to direct dispatch an aggregate frame to hardware.
2331 * If the frame is out of BAW, queue.
2332 * Otherwise, schedule it as a single frame.
2333 */
2334static void
2335ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, struct ath_buf *bf)
2336{
|
| 2337 struct ieee80211_node *ni = &an->an_node;
|
2234 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
2235 struct ath_txq *txq = bf->bf_state.bfs_txq;
2236 struct ieee80211_tx_ampdu *tap;
| 2338 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
2339 struct ath_txq *txq = bf->bf_state.bfs_txq;
2340 struct ieee80211_tx_ampdu *tap;
|
| 2341 int seqno;
|
2237
2238 ATH_TXQ_LOCK_ASSERT(txq);
2239
2240 tap = ath_tx_get_tx_tid(an, tid->tid);
2241
2242 /* paused? queue */
2243 if (tid->paused) {
2244 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list);
2245 return;
2246 }
2247
| 2342
2343 ATH_TXQ_LOCK_ASSERT(txq);
2344
2345 tap = ath_tx_get_tx_tid(an, tid->tid);
2346
2347 /* paused? queue */
2348 if (tid->paused) {
2349 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list);
2350 return;
2351 }
2352
|
| 2353 /*
2354 * TODO: If it's _before_ the BAW left edge, complain very loudly.
2355 * This means something (else) has slid the left edge along
2356 * before we got a chance to be TXed.
2357 */
2358
2359 /*
2360 * Is there space in this BAW for another frame?
2361 * If not, don't bother trying to schedule it; just
2362 * throw it back on the queue.
2363 *
2364 * If we allocate the sequence number before we add
2365 * it to the BAW, we risk racing with another TX
2366 * thread that gets in a frame into the BAW with
2367 * seqno greater than ours. We'd then fail the
2368 * below check and throw the frame on the tail of
2369 * the queue. The sender would then have a hole.
2370 *
2371 * XXX again, we're protecting ni->ni_txseqs[tid]
2372 * behind this hardware TXQ lock, like the rest of
2373 * the TIDs that map to it. Ugh.
2374 */
2375 if (bf->bf_state.bfs_dobaw) {
2376 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2377 ni->ni_txseqs[bf->bf_state.bfs_tid])) {
2378 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list);
2379 ath_tx_tid_sched(sc, tid);
2380 return;
2381 }
2382 if (! bf->bf_state.bfs_seqno_assigned) {
2383 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, bf->bf_m);
2384 if (seqno < 0) {
2385 device_printf(sc->sc_dev,
2386 "%s: bf=%p, huh, seqno=-1?\n",
2387 __func__,
2388 bf);
2389 /* XXX what can we even do here? */
2390 }
2391 /* Flush seqno update to RAM */
2392 /*
2393 * XXX This is required because the dmasetup
2394 * XXX is done early rather than at dispatch
2395 * XXX time. Ew, we should fix this!
2396 */
2397 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2398 BUS_DMASYNC_PREWRITE);
2399 }
2400 }
2401
|
2248 /* outside baw? queue */
2249 if (bf->bf_state.bfs_dobaw &&
2250 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2251 SEQNO(bf->bf_state.bfs_seqno)))) {
| 2402 /* outside baw? queue */
2403 if (bf->bf_state.bfs_dobaw &&
2404 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2405 SEQNO(bf->bf_state.bfs_seqno)))) {
|
| 2406 device_printf(sc->sc_dev,
2407 "%s: bf=%p, shouldn't be outside BAW now?!\n",
2408 __func__,
2409 bf);
|
2252 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list);
2253 ath_tx_tid_sched(sc, tid);
2254 return;
2255 }
2256
2257 /* Direct dispatch to hardware */
2258 ath_tx_do_ratelookup(sc, bf);
2259 ath_tx_rate_fill_rcflags(sc, bf);
2260 ath_tx_set_rtscts(sc, bf);
2261 ath_tx_setds(sc, bf);
2262 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
2263 ath_tx_chaindesclist(sc, bf);
2264
2265 /* Statistics */
2266 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++;
2267
2268 /* Track per-TID hardware queue depth correctly */
2269 tid->hwq_depth++;
2270
2271 /* Add to BAW */
2272 if (bf->bf_state.bfs_dobaw) {
2273 ath_tx_addto_baw(sc, an, tid, bf);
2274 bf->bf_state.bfs_addedbaw = 1;
2275 }
2276
2277 /* Set completion handler, multi-frame aggregate or not */
2278 bf->bf_comp = ath_tx_aggr_comp;
2279
2280 /* Hand off to hardware */
2281 ath_tx_handoff(sc, txq, bf);
2282}
2283
2284/*
2285 * Attempt to send the packet.
2286 * If the queue isn't busy, direct-dispatch.
2287 * If the queue is busy enough, queue the given packet on the
2288 * relevant software queue.
2289 */
2290void
2291ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq,
2292 struct ath_buf *bf)
2293{
2294 struct ath_node *an = ATH_NODE(ni);
2295 struct ieee80211_frame *wh;
2296 struct ath_tid *atid;
2297 int pri, tid;
2298 struct mbuf *m0 = bf->bf_m;
2299
2300 /* Fetch the TID - non-QoS frames get assigned to TID 16 */
2301 wh = mtod(m0, struct ieee80211_frame *);
2302 pri = ath_tx_getac(sc, m0);
2303 tid = ath_tx_gettid(sc, m0);
2304 atid = &an->an_tid[tid];
2305
| 2410 ATH_TXQ_INSERT_TAIL(tid, bf, bf_list);
2411 ath_tx_tid_sched(sc, tid);
2412 return;
2413 }
2414
2415 /* Direct dispatch to hardware */
2416 ath_tx_do_ratelookup(sc, bf);
2417 ath_tx_rate_fill_rcflags(sc, bf);
2418 ath_tx_set_rtscts(sc, bf);
2419 ath_tx_setds(sc, bf);
2420 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
2421 ath_tx_chaindesclist(sc, bf);
2422
2423 /* Statistics */
2424 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++;
2425
2426 /* Track per-TID hardware queue depth correctly */
2427 tid->hwq_depth++;
2428
2429 /* Add to BAW */
2430 if (bf->bf_state.bfs_dobaw) {
2431 ath_tx_addto_baw(sc, an, tid, bf);
2432 bf->bf_state.bfs_addedbaw = 1;
2433 }
2434
2435 /* Set completion handler, multi-frame aggregate or not */
2436 bf->bf_comp = ath_tx_aggr_comp;
2437
2438 /* Hand off to hardware */
2439 ath_tx_handoff(sc, txq, bf);
2440}
2441
2442/*
2443 * Attempt to send the packet.
2444 * If the queue isn't busy, direct-dispatch.
2445 * If the queue is busy enough, queue the given packet on the
2446 * relevant software queue.
2447 */
2448void
2449ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq,
2450 struct ath_buf *bf)
2451{
2452 struct ath_node *an = ATH_NODE(ni);
2453 struct ieee80211_frame *wh;
2454 struct ath_tid *atid;
2455 int pri, tid;
2456 struct mbuf *m0 = bf->bf_m;
2457
2458 /* Fetch the TID - non-QoS frames get assigned to TID 16 */
2459 wh = mtod(m0, struct ieee80211_frame *);
2460 pri = ath_tx_getac(sc, m0);
2461 tid = ath_tx_gettid(sc, m0);
2462 atid = &an->an_tid[tid];
2463
|
2306 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n",
2307 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
| 2464 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d, seqno=%d\n",
2465 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh), SEQNO(bf->bf_state.bfs_seqno));
|
2308
2309 /* Set local packet state, used to queue packets to hardware */
2310 bf->bf_state.bfs_tid = tid;
2311 bf->bf_state.bfs_txq = txq;
2312 bf->bf_state.bfs_pri = pri;
2313
2314 /*
2315 * If the hardware queue isn't busy, queue it directly.
2316 * If the hardware queue is busy, queue it.
2317 * If the TID is paused or the traffic it outside BAW, software
2318 * queue it.
2319 */
2320 ATH_TXQ_LOCK(txq);
2321 if (atid->paused) {
2322 /* TID is paused, queue */
| 2466
2467 /* Set local packet state, used to queue packets to hardware */
2468 bf->bf_state.bfs_tid = tid;
2469 bf->bf_state.bfs_txq = txq;
2470 bf->bf_state.bfs_pri = pri;
2471
2472 /*
2473 * If the hardware queue isn't busy, queue it directly.
2474 * If the hardware queue is busy, queue it.
2475 * If the TID is paused or the traffic it outside BAW, software
2476 * queue it.
2477 */
2478 ATH_TXQ_LOCK(txq);
2479 if (atid->paused) {
2480 /* TID is paused, queue */
|
2323 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__);
| 2481 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: paused\n", __func__, bf);
|
2324 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2325 } else if (ath_tx_ampdu_pending(sc, an, tid)) {
2326 /* AMPDU pending; queue */
| 2482 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2483 } else if (ath_tx_ampdu_pending(sc, an, tid)) {
2484 /* AMPDU pending; queue */
|
2327 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__);
| 2485 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: pending\n", __func__, bf);
|
2328 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2329 /* XXX sched? */
2330 } else if (ath_tx_ampdu_running(sc, an, tid)) {
2331 /* AMPDU running, attempt direct dispatch if possible */
2332 if (txq->axq_depth < sc->sc_hwq_limit) {
| 2486 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2487 /* XXX sched? */
2488 } else if (ath_tx_ampdu_running(sc, an, tid)) {
2489 /* AMPDU running, attempt direct dispatch if possible */
2490 if (txq->axq_depth < sc->sc_hwq_limit) {
|
2333 ath_tx_xmit_aggr(sc, an, bf);
| |
2334 DPRINTF(sc, ATH_DEBUG_SW_TX,
| 2491 DPRINTF(sc, ATH_DEBUG_SW_TX,
|
2335 "%s: xmit_aggr\n",
2336 __func__);
| 2492 "%s: bf=%p: xmit_aggr\n",
2493 __func__, bf);
2494 ath_tx_xmit_aggr(sc, an, bf);
|
2337 } else {
2338 DPRINTF(sc, ATH_DEBUG_SW_TX,
| 2495 } else {
2496 DPRINTF(sc, ATH_DEBUG_SW_TX,
|
2339 "%s: ampdu; swq'ing\n",
2340 __func__);
| 2497 "%s: bf=%p: ampdu; swq'ing\n",
2498 __func__, bf);
|
2341 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2342 ath_tx_tid_sched(sc, atid);
2343 }
2344 } else if (txq->axq_depth < sc->sc_hwq_limit) {
2345 /* AMPDU not running, attempt direct dispatch */
| 2499 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2500 ath_tx_tid_sched(sc, atid);
2501 }
2502 } else if (txq->axq_depth < sc->sc_hwq_limit) {
2503 /* AMPDU not running, attempt direct dispatch */
|
2346 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__);
| 2504 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: xmit_normal\n", __func__, bf);
|
2347 ath_tx_xmit_normal(sc, txq, bf);
2348 } else {
2349 /* Busy; queue */
| 2505 ath_tx_xmit_normal(sc, txq, bf);
2506 } else {
2507 /* Busy; queue */
|
2350 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__);
| 2508 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: swq'ing\n", __func__, bf);
|
2351 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2352 ath_tx_tid_sched(sc, atid);
2353 }
2354 ATH_TXQ_UNLOCK(txq);
2355}
2356
2357/*
2358 * Do the basic frame setup stuff that's required before the frame
2359 * is added to a software queue.
2360 *
2361 * All frames get mostly the same treatment and it's done once.
2362 * Retransmits fiddle with things like the rate control setup,
2363 * setting the retransmit bit in the packet; doing relevant DMA/bus
2364 * syncing and relinking it (back) into the hardware TX queue.
2365 *
2366 * Note that this may cause the mbuf to be reallocated, so
2367 * m0 may not be valid.
2368 */
2369
2370
2371/*
2372 * Configure the per-TID node state.
2373 *
2374 * This likely belongs in if_ath_node.c but I can't think of anywhere
2375 * else to put it just yet.
2376 *
2377 * This sets up the SLISTs and the mutex as appropriate.
2378 */
2379void
2380ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an)
2381{
2382 int i, j;
2383 struct ath_tid *atid;
2384
2385 for (i = 0; i < IEEE80211_TID_SIZE; i++) {
2386 atid = &an->an_tid[i];
2387 TAILQ_INIT(&atid->axq_q);
2388 atid->tid = i;
2389 atid->an = an;
2390 for (j = 0; j < ATH_TID_MAX_BUFS; j++)
2391 atid->tx_buf[j] = NULL;
2392 atid->baw_head = atid->baw_tail = 0;
2393 atid->paused = 0;
2394 atid->sched = 0;
2395 atid->hwq_depth = 0;
2396 atid->cleanup_inprogress = 0;
2397 if (i == IEEE80211_NONQOS_TID)
2398 atid->ac = WME_AC_BE;
2399 else
2400 atid->ac = TID_TO_WME_AC(i);
2401 }
2402}
2403
2404/*
2405 * Pause the current TID. This stops packets from being transmitted
2406 * on it.
2407 *
2408 * Since this is also called from upper layers as well as the driver,
2409 * it will get the TID lock.
2410 */
2411static void
2412ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid)
2413{
2414 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
2415 tid->paused++;
2416 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n",
2417 __func__, tid->paused);
2418 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
2419}
2420
2421/*
2422 * Unpause the current TID, and schedule it if needed.
2423 */
2424static void
2425ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid)
2426{
2427 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2428
2429 tid->paused--;
2430
2431 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n",
2432 __func__, tid->paused);
2433
2434 if (tid->paused || tid->axq_depth == 0) {
2435 return;
2436 }
2437
2438 ath_tx_tid_sched(sc, tid);
2439 /* Punt some frames to the hardware if needed */
2440 ath_txq_sched(sc, sc->sc_ac2q[tid->ac]);
2441}
2442
2443/*
2444 * Free any packets currently pending in the software TX queue.
2445 *
2446 * This will be called when a node is being deleted.
2447 *
2448 * It can also be called on an active node during an interface
2449 * reset or state transition.
2450 *
2451 * (From Linux/reference):
2452 *
2453 * TODO: For frame(s) that are in the retry state, we will reuse the
2454 * sequence number(s) without setting the retry bit. The
2455 * alternative is to give up on these and BAR the receiver's window
2456 * forward.
2457 */
2458static void
2459ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an,
2460 struct ath_tid *tid, ath_bufhead *bf_cq)
2461{
2462 struct ath_buf *bf;
2463 struct ieee80211_tx_ampdu *tap;
2464 struct ieee80211_node *ni = &an->an_node;
2465 int t = 0;
2466 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2467
2468 tap = ath_tx_get_tx_tid(an, tid->tid);
2469
2470 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2471
2472 /* Walk the queue, free frames */
2473 for (;;) {
2474 bf = TAILQ_FIRST(&tid->axq_q);
2475 if (bf == NULL) {
2476 break;
2477 }
2478
2479 if (t == 0) {
2480 device_printf(sc->sc_dev,
| 2509 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2510 ath_tx_tid_sched(sc, atid);
2511 }
2512 ATH_TXQ_UNLOCK(txq);
2513}
2514
2515/*
2516 * Do the basic frame setup stuff that's required before the frame
2517 * is added to a software queue.
2518 *
2519 * All frames get mostly the same treatment and it's done once.
2520 * Retransmits fiddle with things like the rate control setup,
2521 * setting the retransmit bit in the packet; doing relevant DMA/bus
2522 * syncing and relinking it (back) into the hardware TX queue.
2523 *
2524 * Note that this may cause the mbuf to be reallocated, so
2525 * m0 may not be valid.
2526 */
2527
2528
2529/*
2530 * Configure the per-TID node state.
2531 *
2532 * This likely belongs in if_ath_node.c but I can't think of anywhere
2533 * else to put it just yet.
2534 *
2535 * This sets up the SLISTs and the mutex as appropriate.
2536 */
2537void
2538ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an)
2539{
2540 int i, j;
2541 struct ath_tid *atid;
2542
2543 for (i = 0; i < IEEE80211_TID_SIZE; i++) {
2544 atid = &an->an_tid[i];
2545 TAILQ_INIT(&atid->axq_q);
2546 atid->tid = i;
2547 atid->an = an;
2548 for (j = 0; j < ATH_TID_MAX_BUFS; j++)
2549 atid->tx_buf[j] = NULL;
2550 atid->baw_head = atid->baw_tail = 0;
2551 atid->paused = 0;
2552 atid->sched = 0;
2553 atid->hwq_depth = 0;
2554 atid->cleanup_inprogress = 0;
2555 if (i == IEEE80211_NONQOS_TID)
2556 atid->ac = WME_AC_BE;
2557 else
2558 atid->ac = TID_TO_WME_AC(i);
2559 }
2560}
2561
2562/*
2563 * Pause the current TID. This stops packets from being transmitted
2564 * on it.
2565 *
2566 * Since this is also called from upper layers as well as the driver,
2567 * it will get the TID lock.
2568 */
2569static void
2570ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid)
2571{
2572 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
2573 tid->paused++;
2574 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n",
2575 __func__, tid->paused);
2576 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
2577}
2578
2579/*
2580 * Unpause the current TID, and schedule it if needed.
2581 */
2582static void
2583ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid)
2584{
2585 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2586
2587 tid->paused--;
2588
2589 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n",
2590 __func__, tid->paused);
2591
2592 if (tid->paused || tid->axq_depth == 0) {
2593 return;
2594 }
2595
2596 ath_tx_tid_sched(sc, tid);
2597 /* Punt some frames to the hardware if needed */
2598 ath_txq_sched(sc, sc->sc_ac2q[tid->ac]);
2599}
2600
2601/*
2602 * Free any packets currently pending in the software TX queue.
2603 *
2604 * This will be called when a node is being deleted.
2605 *
2606 * It can also be called on an active node during an interface
2607 * reset or state transition.
2608 *
2609 * (From Linux/reference):
2610 *
2611 * TODO: For frame(s) that are in the retry state, we will reuse the
2612 * sequence number(s) without setting the retry bit. The
2613 * alternative is to give up on these and BAR the receiver's window
2614 * forward.
2615 */
2616static void
2617ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an,
2618 struct ath_tid *tid, ath_bufhead *bf_cq)
2619{
2620 struct ath_buf *bf;
2621 struct ieee80211_tx_ampdu *tap;
2622 struct ieee80211_node *ni = &an->an_node;
2623 int t = 0;
2624 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2625
2626 tap = ath_tx_get_tx_tid(an, tid->tid);
2627
2628 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2629
2630 /* Walk the queue, free frames */
2631 for (;;) {
2632 bf = TAILQ_FIRST(&tid->axq_q);
2633 if (bf == NULL) {
2634 break;
2635 }
2636
2637 if (t == 0) {
2638 device_printf(sc->sc_dev,
|
2481 "%s: node %p: tid %d: txq_depth=%d, "
| 2639 "%s: node %p: bf=%p: tid %d: txq_depth=%d, "
|
2482 "txq_aggr_depth=%d, sched=%d, paused=%d, "
2483 "hwq_depth=%d, incomp=%d, baw_head=%d, "
2484 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n",
| 2640 "txq_aggr_depth=%d, sched=%d, paused=%d, "
2641 "hwq_depth=%d, incomp=%d, baw_head=%d, "
2642 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n",
|
2485 __func__, ni, tid->tid, txq->axq_depth,
| 2643 __func__, ni, bf, tid->tid, txq->axq_depth,
|
2486 txq->axq_aggr_depth, tid->sched, tid->paused,
2487 tid->hwq_depth, tid->incomp, tid->baw_head,
2488 tid->baw_tail, tap == NULL ? -1 : tap->txa_start,
2489 ni->ni_txseqs[tid->tid]);
2490
2491 /* XXX Dump the frame, see what it is? */
2492 ieee80211_dump_pkt(ni->ni_ic,
2493 mtod(bf->bf_m, const uint8_t *),
2494 bf->bf_m->m_len, 0, -1);
2495
| 2644 txq->axq_aggr_depth, tid->sched, tid->paused,
2645 tid->hwq_depth, tid->incomp, tid->baw_head,
2646 tid->baw_tail, tap == NULL ? -1 : tap->txa_start,
2647 ni->ni_txseqs[tid->tid]);
2648
2649 /* XXX Dump the frame, see what it is? */
2650 ieee80211_dump_pkt(ni->ni_ic,
2651 mtod(bf->bf_m, const uint8_t *),
2652 bf->bf_m->m_len, 0, -1);
2653
|
2496 t = 1;
| 2654 //t = 1;
|
2497 }
2498
2499
2500 /*
2501 * If the current TID is running AMPDU, update
2502 * the BAW.
2503 */
2504 if (ath_tx_ampdu_running(sc, an, tid->tid) &&
2505 bf->bf_state.bfs_dobaw) {
2506 /*
2507 * Only remove the frame from the BAW if it's
2508 * been transmitted at least once; this means
2509 * the frame was in the BAW to begin with.
2510 */
2511 if (bf->bf_state.bfs_retries > 0) {
2512 ath_tx_update_baw(sc, an, tid, bf);
2513 bf->bf_state.bfs_dobaw = 0;
2514 }
2515 /*
2516 * This has become a non-fatal error now
2517 */
2518 if (! bf->bf_state.bfs_addedbaw)
2519 device_printf(sc->sc_dev,
2520 "%s: wasn't added: seqno %d\n",
2521 __func__, SEQNO(bf->bf_state.bfs_seqno));
2522 }
2523 ATH_TXQ_REMOVE(tid, bf, bf_list);
2524 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list);
2525 }
2526
2527 /*
2528 * Now that it's completed, grab the TID lock and update
2529 * the sequence number and BAW window.
2530 * Because sequence numbers have been assigned to frames
2531 * that haven't been sent yet, it's entirely possible
2532 * we'll be called with some pending frames that have not
2533 * been transmitted.
2534 *
2535 * The cleaner solution is to do the sequence number allocation
2536 * when the packet is first transmitted - and thus the "retries"
2537 * check above would be enough to update the BAW/seqno.
2538 */
2539
2540 /* But don't do it for non-QoS TIDs */
2541 if (tap) {
2542#if 0
2543 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2544 "%s: node %p: TID %d: sliding BAW left edge to %d\n",
2545 __func__, an, tid->tid, tap->txa_start);
2546#endif
2547 ni->ni_txseqs[tid->tid] = tap->txa_start;
2548 tid->baw_tail = tid->baw_head;
2549 }
2550}
2551
2552/*
2553 * Flush all software queued packets for the given node.
2554 *
2555 * This occurs when a completion handler frees the last buffer
2556 * for a node, and the node is thus freed. This causes the node
2557 * to be cleaned up, which ends up calling ath_tx_node_flush.
2558 */
2559void
2560ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an)
2561{
2562 int tid;
2563 ath_bufhead bf_cq;
2564 struct ath_buf *bf;
2565
2566 TAILQ_INIT(&bf_cq);
2567
2568 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
2569 struct ath_tid *atid = &an->an_tid[tid];
2570 struct ath_txq *txq = sc->sc_ac2q[atid->ac];
2571
2572 /* Remove this tid from the list of active tids */
2573 ATH_TXQ_LOCK(txq);
2574 ath_tx_tid_unsched(sc, atid);
2575
2576 /* Free packets */
2577 ath_tx_tid_drain(sc, an, atid, &bf_cq);
2578 ATH_TXQ_UNLOCK(txq);
2579 }
2580
2581 /* Handle completed frames */
2582 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
2583 TAILQ_REMOVE(&bf_cq, bf, bf_list);
2584 ath_tx_default_comp(sc, bf, 0);
2585 }
2586}
2587
2588/*
2589 * Drain all the software TXQs currently with traffic queued.
2590 */
2591void
2592ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq)
2593{
2594 struct ath_tid *tid;
2595 ath_bufhead bf_cq;
2596 struct ath_buf *bf;
2597
2598 TAILQ_INIT(&bf_cq);
2599 ATH_TXQ_LOCK(txq);
2600
2601 /*
2602 * Iterate over all active tids for the given txq,
2603 * flushing and unsched'ing them
2604 */
2605 while (! TAILQ_EMPTY(&txq->axq_tidq)) {
2606 tid = TAILQ_FIRST(&txq->axq_tidq);
2607 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq);
2608 ath_tx_tid_unsched(sc, tid);
2609 }
2610
2611 ATH_TXQ_UNLOCK(txq);
2612
2613 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
2614 TAILQ_REMOVE(&bf_cq, bf, bf_list);
2615 ath_tx_default_comp(sc, bf, 0);
2616 }
2617}
2618
2619/*
2620 * Handle completion of non-aggregate session frames.
2621 */
2622void
2623ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
2624{
2625 struct ieee80211_node *ni = bf->bf_node;
2626 struct ath_node *an = ATH_NODE(ni);
2627 int tid = bf->bf_state.bfs_tid;
2628 struct ath_tid *atid = &an->an_tid[tid];
2629 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
2630
2631 /* The TID state is protected behind the TXQ lock */
2632 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2633
2634 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n",
2635 __func__, bf, fail, atid->hwq_depth - 1);
2636
2637 atid->hwq_depth--;
2638 if (atid->hwq_depth < 0)
2639 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
2640 __func__, atid->hwq_depth);
2641 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2642
2643 /*
2644 * punt to rate control if we're not being cleaned up
2645 * during a hw queue drain and the frame wanted an ACK.
2646 */
2647 if (fail == 0 && ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0))
2648 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
2649 ts, bf->bf_state.bfs_pktlen,
2650 1, (ts->ts_status == 0) ? 0 : 1);
2651
2652 ath_tx_default_comp(sc, bf, fail);
2653}
2654
2655/*
2656 * Handle cleanup of aggregate session packets that aren't
2657 * an A-MPDU.
2658 *
2659 * There's no need to update the BAW here - the session is being
2660 * torn down.
2661 */
2662static void
2663ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf)
2664{
2665 struct ieee80211_node *ni = bf->bf_node;
2666 struct ath_node *an = ATH_NODE(ni);
2667 int tid = bf->bf_state.bfs_tid;
2668 struct ath_tid *atid = &an->an_tid[tid];
2669
2670 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n",
2671 __func__, tid, atid->incomp);
2672
2673 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2674 atid->incomp--;
2675 if (atid->incomp == 0) {
2676 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2677 "%s: TID %d: cleaned up! resume!\n",
2678 __func__, tid);
2679 atid->cleanup_inprogress = 0;
2680 ath_tx_tid_resume(sc, atid);
2681 }
2682 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2683
2684 ath_tx_default_comp(sc, bf, 0);
2685}
2686
2687/*
2688 * Performs transmit side cleanup when TID changes from aggregated to
2689 * unaggregated.
2690 *
2691 * - Discard all retry frames from the s/w queue.
2692 * - Fix the tx completion function for all buffers in s/w queue.
2693 * - Count the number of unacked frames, and let transmit completion
2694 * handle it later.
2695 *
2696 * The caller is responsible for pausing the TID.
2697 */
2698static void
2699ath_tx_cleanup(struct ath_softc *sc, struct ath_node *an, int tid)
2700{
2701 struct ath_tid *atid = &an->an_tid[tid];
2702 struct ieee80211_tx_ampdu *tap;
2703 struct ath_buf *bf, *bf_next;
2704 ath_bufhead bf_cq;
2705
2706 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2707 "%s: TID %d: called\n", __func__, tid);
2708
2709 TAILQ_INIT(&bf_cq);
2710 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2711
2712 /*
2713 * Update the frames in the software TX queue:
2714 *
2715 * + Discard retry frames in the queue
2716 * + Fix the completion function to be non-aggregate
2717 */
2718 bf = TAILQ_FIRST(&atid->axq_q);
2719 while (bf) {
2720 if (bf->bf_state.bfs_isretried) {
2721 bf_next = TAILQ_NEXT(bf, bf_list);
2722 TAILQ_REMOVE(&atid->axq_q, bf, bf_list);
2723 atid->axq_depth--;
2724 if (bf->bf_state.bfs_dobaw) {
2725 ath_tx_update_baw(sc, an, atid, bf);
2726 if (! bf->bf_state.bfs_addedbaw)
2727 device_printf(sc->sc_dev,
2728 "%s: wasn't added: seqno %d\n",
2729 __func__,
2730 SEQNO(bf->bf_state.bfs_seqno));
2731 }
2732 bf->bf_state.bfs_dobaw = 0;
2733 /*
2734 * Call the default completion handler with "fail" just
2735 * so upper levels are suitably notified about this.
2736 */
2737 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
2738 bf = bf_next;
2739 continue;
2740 }
2741 /* Give these the default completion handler */
2742 bf->bf_comp = ath_tx_normal_comp;
2743 bf = TAILQ_NEXT(bf, bf_list);
2744 }
2745
2746 /* The caller is required to pause the TID */
2747#if 0
2748 /* Pause the TID */
2749 ath_tx_tid_pause(sc, atid);
2750#endif
2751
2752 /*
2753 * Calculate what hardware-queued frames exist based
2754 * on the current BAW size. Ie, what frames have been
2755 * added to the TX hardware queue for this TID but
2756 * not yet ACKed.
2757 */
2758 tap = ath_tx_get_tx_tid(an, tid);
2759 /* Need the lock - fiddling with BAW */
2760 while (atid->baw_head != atid->baw_tail) {
2761 if (atid->tx_buf[atid->baw_head]) {
2762 atid->incomp++;
2763 atid->cleanup_inprogress = 1;
2764 atid->tx_buf[atid->baw_head] = NULL;
2765 }
2766 INCR(atid->baw_head, ATH_TID_MAX_BUFS);
2767 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2768 }
2769
2770 /*
2771 * If cleanup is required, defer TID scheduling
2772 * until all the HW queued packets have been
2773 * sent.
2774 */
2775 if (! atid->cleanup_inprogress)
2776 ath_tx_tid_resume(sc, atid);
2777
2778 if (atid->cleanup_inprogress)
2779 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2780 "%s: TID %d: cleanup needed: %d packets\n",
2781 __func__, tid, atid->incomp);
2782 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2783
2784 /* Handle completing frames and fail them */
2785 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
2786 TAILQ_REMOVE(&bf_cq, bf, bf_list);
2787 ath_tx_default_comp(sc, bf, 1);
2788 }
2789}
2790
2791static void
2792ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
2793{
2794 struct ieee80211_frame *wh;
2795
2796 wh = mtod(bf->bf_m, struct ieee80211_frame *);
2797 /* Only update/resync if needed */
2798 if (bf->bf_state.bfs_isretried == 0) {
2799 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
2800 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2801 BUS_DMASYNC_PREWRITE);
2802 }
2803 sc->sc_stats.ast_tx_swretries++;
2804 bf->bf_state.bfs_isretried = 1;
2805 bf->bf_state.bfs_retries ++;
2806}
2807
2808static struct ath_buf *
2809ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an,
2810 struct ath_tid *tid, struct ath_buf *bf)
2811{
2812 struct ath_buf *nbf;
2813 int error;
2814
2815 nbf = ath_buf_clone(sc, bf);
2816
2817#if 0
2818 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n",
2819 __func__);
2820#endif
2821
2822 if (nbf == NULL) {
2823 /* Failed to clone */
2824 device_printf(sc->sc_dev,
2825 "%s: failed to clone a busy buffer\n",
2826 __func__);
2827 return NULL;
2828 }
2829
2830 /* Setup the dma for the new buffer */
2831 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m);
2832 if (error != 0) {
2833 device_printf(sc->sc_dev,
2834 "%s: failed to setup dma for clone\n",
2835 __func__);
2836 /*
2837 * Put this at the head of the list, not tail;
2838 * that way it doesn't interfere with the
2839 * busy buffer logic (which uses the tail of
2840 * the list.)
2841 */
2842 ATH_TXBUF_LOCK(sc);
2843 TAILQ_INSERT_HEAD(&sc->sc_txbuf, nbf, bf_list);
2844 ATH_TXBUF_UNLOCK(sc);
2845 return NULL;
2846 }
2847
2848 /* Update BAW if required, before we free the original buf */
2849 if (bf->bf_state.bfs_dobaw)
2850 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf);
2851
2852 /* Free current buffer; return the older buffer */
2853 bf->bf_m = NULL;
2854 bf->bf_node = NULL;
2855 ath_freebuf(sc, bf);
2856 return nbf;
2857}
2858
2859/*
2860 * Handle retrying an unaggregate frame in an aggregate
2861 * session.
2862 *
2863 * If too many retries occur, pause the TID, wait for
2864 * any further retransmits (as there's no reason why
2865 * non-aggregate frames in an aggregate session are
2866 * transmitted in-order; they just have to be in-BAW)
2867 * and then queue a BAR.
2868 */
2869static void
2870ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf)
2871{
2872 struct ieee80211_node *ni = bf->bf_node;
2873 struct ath_node *an = ATH_NODE(ni);
2874 int tid = bf->bf_state.bfs_tid;
2875 struct ath_tid *atid = &an->an_tid[tid];
2876 struct ieee80211_tx_ampdu *tap;
2877 int txseq;
2878
2879 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2880
2881 tap = ath_tx_get_tx_tid(an, tid);
2882
2883 /*
2884 * If the buffer is marked as busy, we can't directly
2885 * reuse it. Instead, try to clone the buffer.
2886 * If the clone is successful, recycle the old buffer.
2887 * If the clone is unsuccessful, set bfs_retries to max
2888 * to force the next bit of code to free the buffer
2889 * for us.
2890 */
2891 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
2892 (bf->bf_flags & ATH_BUF_BUSY)) {
2893 struct ath_buf *nbf;
2894 nbf = ath_tx_retry_clone(sc, an, atid, bf);
2895 if (nbf)
2896 /* bf has been freed at this point */
2897 bf = nbf;
2898 else
2899 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
2900 }
2901
2902 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
2903 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
2904 "%s: exceeded retries; seqno %d\n",
2905 __func__, SEQNO(bf->bf_state.bfs_seqno));
2906 sc->sc_stats.ast_tx_swretrymax++;
2907
2908 /* Update BAW anyway */
2909 if (bf->bf_state.bfs_dobaw) {
2910 ath_tx_update_baw(sc, an, atid, bf);
2911 if (! bf->bf_state.bfs_addedbaw)
2912 device_printf(sc->sc_dev,
2913 "%s: wasn't added: seqno %d\n",
2914 __func__, SEQNO(bf->bf_state.bfs_seqno));
2915 }
2916 bf->bf_state.bfs_dobaw = 0;
2917
2918 /* Send BAR frame */
2919 /*
2920 * This'll end up going into net80211 and back out
2921 * again, via ic->ic_raw_xmit().
2922 */
2923 txseq = tap->txa_start;
2924 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2925
2926 device_printf(sc->sc_dev,
2927 "%s: TID %d: send BAR; seq %d\n", __func__, tid, txseq);
2928
2929 /* XXX TODO: send BAR */
2930
2931 /* Free buffer, bf is free after this call */
2932 ath_tx_default_comp(sc, bf, 0);
2933 return;
2934 }
2935
2936 /*
2937 * This increments the retry counter as well as
2938 * sets the retry flag in the ath_buf and packet
2939 * body.
2940 */
2941 ath_tx_set_retry(sc, bf);
2942
2943 /*
2944 * Insert this at the head of the queue, so it's
2945 * retried before any current/subsequent frames.
2946 */
2947 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list);
2948 ath_tx_tid_sched(sc, atid);
2949
2950 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2951}
2952
2953/*
2954 * Common code for aggregate excessive retry/subframe retry.
2955 * If retrying, queues buffers to bf_q. If not, frees the
2956 * buffers.
2957 *
2958 * XXX should unify this with ath_tx_aggr_retry_unaggr()
2959 */
2960static int
2961ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf,
2962 ath_bufhead *bf_q)
2963{
2964 struct ieee80211_node *ni = bf->bf_node;
2965 struct ath_node *an = ATH_NODE(ni);
2966 int tid = bf->bf_state.bfs_tid;
2967 struct ath_tid *atid = &an->an_tid[tid];
2968
2969 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]);
2970
2971 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
2972 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0);
2973 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */
2974
2975 /*
2976 * If the buffer is marked as busy, we can't directly
2977 * reuse it. Instead, try to clone the buffer.
2978 * If the clone is successful, recycle the old buffer.
2979 * If the clone is unsuccessful, set bfs_retries to max
2980 * to force the next bit of code to free the buffer
2981 * for us.
2982 */
2983 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
2984 (bf->bf_flags & ATH_BUF_BUSY)) {
2985 struct ath_buf *nbf;
2986 nbf = ath_tx_retry_clone(sc, an, atid, bf);
2987 if (nbf)
2988 /* bf has been freed at this point */
2989 bf = nbf;
2990 else
2991 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
2992 }
2993
2994 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
2995 sc->sc_stats.ast_tx_swretrymax++;
2996 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
2997 "%s: max retries: seqno %d\n",
2998 __func__, SEQNO(bf->bf_state.bfs_seqno));
2999 ath_tx_update_baw(sc, an, atid, bf);
3000 if (! bf->bf_state.bfs_addedbaw)
3001 device_printf(sc->sc_dev,
3002 "%s: wasn't added: seqno %d\n",
3003 __func__, SEQNO(bf->bf_state.bfs_seqno));
3004 bf->bf_state.bfs_dobaw = 0;
3005 return 1;
3006 }
3007
3008 ath_tx_set_retry(sc, bf);
3009 bf->bf_next = NULL; /* Just to make sure */
3010
3011 TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3012 return 0;
3013}
3014
3015/*
3016 * error pkt completion for an aggregate destination
3017 */
3018static void
3019ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first,
3020 struct ath_tid *tid)
3021{
3022 struct ieee80211_node *ni = bf_first->bf_node;
3023 struct ath_node *an = ATH_NODE(ni);
3024 struct ath_buf *bf_next, *bf;
3025 ath_bufhead bf_q;
3026 int drops = 0;
3027 struct ieee80211_tx_ampdu *tap;
3028 ath_bufhead bf_cq;
3029
3030 TAILQ_INIT(&bf_q);
3031 TAILQ_INIT(&bf_cq);
3032
3033 /*
3034 * Update rate control - all frames have failed.
3035 *
3036 * XXX use the length in the first frame in the series;
3037 * XXX just so things are consistent for now.
3038 */
3039 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc,
3040 &bf_first->bf_status.ds_txstat,
3041 bf_first->bf_state.bfs_pktlen,
3042 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes);
3043
3044 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
3045 tap = ath_tx_get_tx_tid(an, tid->tid);
3046 sc->sc_stats.ast_tx_aggr_failall++;
3047
3048 /* Retry all subframes */
3049 bf = bf_first;
3050 while (bf) {
3051 bf_next = bf->bf_next;
3052 bf->bf_next = NULL; /* Remove it from the aggr list */
3053 sc->sc_stats.ast_tx_aggr_fail++;
3054 if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
3055 drops++;
3056 bf->bf_next = NULL;
3057 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3058 }
3059 bf = bf_next;
3060 }
3061
3062 /* Prepend all frames to the beginning of the queue */
3063 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
3064 TAILQ_REMOVE(&bf_q, bf, bf_list);
3065 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list);
3066 }
3067
3068 ath_tx_tid_sched(sc, tid);
3069
3070 /*
3071 * send bar if we dropped any frames
3072 *
3073 * Keep the txq lock held for now, as we need to ensure
3074 * that ni_txseqs[] is consistent (as it's being updated
3075 * in the ifnet TX context or raw TX context.)
3076 */
3077 if (drops) {
3078 int txseq = tap->txa_start;
3079 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
3080 device_printf(sc->sc_dev,
3081 "%s: TID %d: send BAR; seq %d\n",
3082 __func__, tid->tid, txseq);
3083
3084 /* XXX TODO: send BAR */
3085 } else {
3086 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
3087 }
3088
3089 /* Complete frames which errored out */
3090 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3091 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3092 ath_tx_default_comp(sc, bf, 0);
3093 }
3094}
3095
3096/*
3097 * Handle clean-up of packets from an aggregate list.
3098 *
3099 * There's no need to update the BAW here - the session is being
3100 * torn down.
3101 */
3102static void
3103ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first)
3104{
3105 struct ath_buf *bf, *bf_next;
3106 struct ieee80211_node *ni = bf_first->bf_node;
3107 struct ath_node *an = ATH_NODE(ni);
3108 int tid = bf_first->bf_state.bfs_tid;
3109 struct ath_tid *atid = &an->an_tid[tid];
3110
3111 bf = bf_first;
3112
3113 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3114
3115 /* update incomp */
3116 while (bf) {
3117 atid->incomp--;
3118 bf = bf->bf_next;
3119 }
3120
3121 if (atid->incomp == 0) {
3122 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3123 "%s: TID %d: cleaned up! resume!\n",
3124 __func__, tid);
3125 atid->cleanup_inprogress = 0;
3126 ath_tx_tid_resume(sc, atid);
3127 }
3128 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3129
3130 /* Handle frame completion */
3131 while (bf) {
3132 bf_next = bf->bf_next;
3133 ath_tx_default_comp(sc, bf, 1);
3134 bf = bf_next;
3135 }
3136}
3137
3138/*
3139 * Handle completion of an set of aggregate frames.
3140 *
3141 * XXX for now, simply complete each sub-frame.
3142 *
3143 * Note: the completion handler is the last descriptor in the aggregate,
3144 * not the last descriptor in the first frame.
3145 */
3146static void
3147ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first,
3148 int fail)
3149{
3150 //struct ath_desc *ds = bf->bf_lastds;
3151 struct ieee80211_node *ni = bf_first->bf_node;
3152 struct ath_node *an = ATH_NODE(ni);
3153 int tid = bf_first->bf_state.bfs_tid;
3154 struct ath_tid *atid = &an->an_tid[tid];
3155 struct ath_tx_status ts;
3156 struct ieee80211_tx_ampdu *tap;
3157 ath_bufhead bf_q;
3158 ath_bufhead bf_cq;
3159 int seq_st, tx_ok;
3160 int hasba, isaggr;
3161 uint32_t ba[2];
3162 struct ath_buf *bf, *bf_next;
3163 int ba_index;
3164 int drops = 0;
3165 int nframes = 0, nbad = 0, nf;
3166 int pktlen;
3167 /* XXX there's too much on the stack? */
3168 struct ath_rc_series rc[4];
3169 int txseq;
3170
3171 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n",
3172 __func__, atid->hwq_depth);
3173
3174 /* The TID state is kept behind the TXQ lock */
3175 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3176
3177 atid->hwq_depth--;
3178 if (atid->hwq_depth < 0)
3179 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3180 __func__, atid->hwq_depth);
3181
3182 /*
3183 * Punt cleanup to the relevant function, not our problem now
3184 */
3185 if (atid->cleanup_inprogress) {
3186 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3187 ath_tx_comp_cleanup_aggr(sc, bf_first);
3188 return;
3189 }
3190
3191 /*
3192 * Take a copy; this may be needed -after- bf_first
3193 * has been completed and freed.
3194 */
3195 ts = bf_first->bf_status.ds_txstat;
3196 /*
3197 * XXX for now, use the first frame in the aggregate for
3198 * XXX rate control completion; it's at least consistent.
3199 */
3200 pktlen = bf_first->bf_state.bfs_pktlen;
3201
3202 /*
3203 * handle errors first
3204 */
3205 if (ts.ts_status & HAL_TXERR_XRETRY) {
3206 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3207 ath_tx_comp_aggr_error(sc, bf_first, atid);
3208 return;
3209 }
3210
3211 TAILQ_INIT(&bf_q);
3212 TAILQ_INIT(&bf_cq);
3213 tap = ath_tx_get_tx_tid(an, tid);
3214
3215 /*
3216 * extract starting sequence and block-ack bitmap
3217 */
3218 /* XXX endian-ness of seq_st, ba? */
3219 seq_st = ts.ts_seqnum;
3220 hasba = !! (ts.ts_flags & HAL_TX_BA);
3221 tx_ok = (ts.ts_status == 0);
3222 isaggr = bf_first->bf_state.bfs_aggr;
3223 ba[0] = ts.ts_ba_low;
3224 ba[1] = ts.ts_ba_high;
3225
3226 /*
3227 * Copy the TX completion status and the rate control
3228 * series from the first descriptor, as it may be freed
3229 * before the rate control code can get its grubby fingers
3230 * into things.
3231 */
3232 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc));
3233
3234 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3235 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, "
3236 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n",
3237 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags,
3238 isaggr, seq_st, hasba, ba[0], ba[1]);
3239
3240 /* Occasionally, the MAC sends a tx status for the wrong TID. */
3241 if (tid != ts.ts_tid) {
3242 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n",
3243 __func__, tid, ts.ts_tid);
3244 tx_ok = 0;
3245 }
3246
3247 /* AR5416 BA bug; this requires an interface reset */
3248 if (isaggr && tx_ok && (! hasba)) {
3249 device_printf(sc->sc_dev,
3250 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, "
3251 "seq_st=%d\n",
3252 __func__, hasba, tx_ok, isaggr, seq_st);
3253 /* XXX TODO: schedule an interface reset */
3254 }
3255
3256 /*
3257 * Walk the list of frames, figure out which ones were correctly
3258 * sent and which weren't.
3259 */
3260 bf = bf_first;
3261 nf = bf_first->bf_state.bfs_nframes;
3262
3263 /* bf_first is going to be invalid once this list is walked */
3264 bf_first = NULL;
3265
3266 /*
3267 * Walk the list of completed frames and determine
3268 * which need to be completed and which need to be
3269 * retransmitted.
3270 *
3271 * For completed frames, the completion functions need
3272 * to be called at the end of this function as the last
3273 * node reference may free the node.
3274 *
3275 * Finally, since the TXQ lock can't be held during the
3276 * completion callback (to avoid lock recursion),
3277 * the completion calls have to be done outside of the
3278 * lock.
3279 */
3280 while (bf) {
3281 nframes++;
3282 ba_index = ATH_BA_INDEX(seq_st,
3283 SEQNO(bf->bf_state.bfs_seqno));
3284 bf_next = bf->bf_next;
3285 bf->bf_next = NULL; /* Remove it from the aggr list */
3286
3287 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3288 "%s: checking bf=%p seqno=%d; ack=%d\n",
3289 __func__, bf, SEQNO(bf->bf_state.bfs_seqno),
3290 ATH_BA_ISSET(ba, ba_index));
3291
3292 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
3293 sc->sc_stats.ast_tx_aggr_ok++;
3294 ath_tx_update_baw(sc, an, atid, bf);
3295 bf->bf_state.bfs_dobaw = 0;
3296 if (! bf->bf_state.bfs_addedbaw)
3297 device_printf(sc->sc_dev,
3298 "%s: wasn't added: seqno %d\n",
3299 __func__, SEQNO(bf->bf_state.bfs_seqno));
3300 bf->bf_next = NULL;
3301 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3302 } else {
3303 sc->sc_stats.ast_tx_aggr_fail++;
3304 if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
3305 drops++;
3306 bf->bf_next = NULL;
3307 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3308 }
3309 nbad++;
3310 }
3311 bf = bf_next;
3312 }
3313
3314 /*
3315 * Now that the BAW updates have been done, unlock
3316 *
3317 * txseq is grabbed before the lock is released so we
3318 * have a consistent view of what -was- in the BAW.
3319 * Anything after this point will not yet have been
3320 * TXed.
3321 */
3322 txseq = tap->txa_start;
3323 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3324
3325 if (nframes != nf)
3326 device_printf(sc->sc_dev,
3327 "%s: num frames seen=%d; bf nframes=%d\n",
3328 __func__, nframes, nf);
3329
3330 /*
3331 * Now we know how many frames were bad, call the rate
3332 * control code.
3333 */
3334 if (fail == 0)
3335 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes,
3336 nbad);
3337
3338 /*
3339 * send bar if we dropped any frames
3340 */
3341 if (drops) {
3342 device_printf(sc->sc_dev,
3343 "%s: TID %d: send BAR; seq %d\n", __func__, tid, txseq);
3344 /* XXX TODO: send BAR */
3345 }
3346
3347 /* Prepend all frames to the beginning of the queue */
3348 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3349 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
3350 TAILQ_REMOVE(&bf_q, bf, bf_list);
3351 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list);
3352 }
3353 ath_tx_tid_sched(sc, atid);
3354 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3355
3356 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3357 "%s: txa_start now %d\n", __func__, tap->txa_start);
3358
3359 /* Do deferred completion */
3360 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3361 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3362 ath_tx_default_comp(sc, bf, 0);
3363 }
3364}
3365
3366/*
3367 * Handle completion of unaggregated frames in an ADDBA
3368 * session.
3369 *
3370 * Fail is set to 1 if the entry is being freed via a call to
3371 * ath_tx_draintxq().
3372 */
3373static void
3374ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail)
3375{
3376 struct ieee80211_node *ni = bf->bf_node;
3377 struct ath_node *an = ATH_NODE(ni);
3378 int tid = bf->bf_state.bfs_tid;
3379 struct ath_tid *atid = &an->an_tid[tid];
3380 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3381
3382 /*
3383 * Update rate control status here, before we possibly
3384 * punt to retry or cleanup.
3385 *
3386 * Do it outside of the TXQ lock.
3387 */
3388 if (fail == 0 && ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0))
3389 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
3390 &bf->bf_status.ds_txstat,
3391 bf->bf_state.bfs_pktlen,
3392 1, (ts->ts_status == 0) ? 0 : 1);
3393
3394 /*
3395 * This is called early so atid->hwq_depth can be tracked.
3396 * This unfortunately means that it's released and regrabbed
3397 * during retry and cleanup. That's rather inefficient.
3398 */
3399 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3400
3401 if (tid == IEEE80211_NONQOS_TID)
3402 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__);
3403
3404 DPRINTF(sc, ATH_DEBUG_SW_TX,
3405 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n",
3406 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth,
3407 SEQNO(bf->bf_state.bfs_seqno));
3408
3409 atid->hwq_depth--;
3410 if (atid->hwq_depth < 0)
3411 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3412 __func__, atid->hwq_depth);
3413
3414 /*
3415 * If a cleanup is in progress, punt to comp_cleanup;
3416 * rather than handling it here. It's thus their
3417 * responsibility to clean up, call the completion
3418 * function in net80211, etc.
3419 */
3420 if (atid->cleanup_inprogress) {
3421 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3422 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n",
3423 __func__);
3424 ath_tx_comp_cleanup_unaggr(sc, bf);
3425 return;
3426 }
3427
3428 /*
3429 * Don't bother with the retry check if all frames
3430 * are being failed (eg during queue deletion.)
3431 */
3432 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) {
3433 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3434 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n",
3435 __func__);
3436 ath_tx_aggr_retry_unaggr(sc, bf);
3437 return;
3438 }
3439
3440 /* Success? Complete */
3441 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n",
3442 __func__, tid, SEQNO(bf->bf_state.bfs_seqno));
3443 if (bf->bf_state.bfs_dobaw) {
3444 ath_tx_update_baw(sc, an, atid, bf);
3445 bf->bf_state.bfs_dobaw = 0;
3446 if (! bf->bf_state.bfs_addedbaw)
3447 device_printf(sc->sc_dev,
3448 "%s: wasn't added: seqno %d\n",
3449 __func__, SEQNO(bf->bf_state.bfs_seqno));
3450 }
3451
3452 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3453
3454 ath_tx_default_comp(sc, bf, fail);
3455 /* bf is freed at this point */
3456}
3457
3458void
3459ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3460{
3461 if (bf->bf_state.bfs_aggr)
3462 ath_tx_aggr_comp_aggr(sc, bf, fail);
3463 else
3464 ath_tx_aggr_comp_unaggr(sc, bf, fail);
3465}
3466
3467/*
3468 * Schedule some packets from the given node/TID to the hardware.
3469 *
3470 * This is the aggregate version.
3471 */
3472void
3473ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an,
3474 struct ath_tid *tid)
3475{
3476 struct ath_buf *bf;
3477 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
3478 struct ieee80211_tx_ampdu *tap;
3479 struct ieee80211_node *ni = &an->an_node;
3480 ATH_AGGR_STATUS status;
3481 ath_bufhead bf_q;
3482
3483 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid);
3484 ATH_TXQ_LOCK_ASSERT(txq);
3485
3486 tap = ath_tx_get_tx_tid(an, tid->tid);
3487
3488 if (tid->tid == IEEE80211_NONQOS_TID)
3489 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n",
3490 __func__);
3491
3492 for (;;) {
3493 status = ATH_AGGR_DONE;
3494
3495 /*
3496 * If the upper layer has paused the TID, don't
3497 * queue any further packets.
3498 *
3499 * This can also occur from the completion task because
3500 * of packet loss; but as its serialised with this code,
3501 * it won't "appear" half way through queuing packets.
3502 */
3503 if (tid->paused)
3504 break;
3505
3506 bf = TAILQ_FIRST(&tid->axq_q);
3507 if (bf == NULL) {
3508 break;
3509 }
3510
3511 /*
3512 * If the packet doesn't fall within the BAW (eg a NULL
3513 * data frame), schedule it directly; continue.
3514 */
3515 if (! bf->bf_state.bfs_dobaw) {
3516 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3517 "%s: non-baw packet\n",
3518 __func__);
3519 ATH_TXQ_REMOVE(tid, bf, bf_list);
3520 bf->bf_state.bfs_aggr = 0;
3521 ath_tx_do_ratelookup(sc, bf);
3522 ath_tx_rate_fill_rcflags(sc, bf);
3523 ath_tx_set_rtscts(sc, bf);
3524 ath_tx_setds(sc, bf);
3525 ath_tx_chaindesclist(sc, bf);
3526 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
3527 ath_tx_set_ratectrl(sc, ni, bf);
3528
3529 sc->sc_aggr_stats.aggr_nonbaw_pkt++;
3530
3531 /* Queue the packet; continue */
3532 goto queuepkt;
3533 }
3534
3535 TAILQ_INIT(&bf_q);
3536
3537 /*
3538 * Do a rate control lookup on the first frame in the
3539 * list. The rate control code needs that to occur
3540 * before it can determine whether to TX.
3541 * It's inaccurate because the rate control code doesn't
3542 * really "do" aggregate lookups, so it only considers
3543 * the size of the first frame.
3544 */
3545 ath_tx_do_ratelookup(sc, bf);
3546 bf->bf_state.bfs_rc[3].rix = 0;
3547 bf->bf_state.bfs_rc[3].tries = 0;
3548 ath_tx_rate_fill_rcflags(sc, bf);
3549
3550 status = ath_tx_form_aggr(sc, an, tid, &bf_q);
3551
3552 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3553 "%s: ath_tx_form_aggr() status=%d\n", __func__, status);
3554
3555 /*
3556 * No frames to be picked up - out of BAW
3557 */
3558 if (TAILQ_EMPTY(&bf_q))
3559 break;
3560
3561 /*
3562 * This assumes that the descriptor list in the ath_bufhead
3563 * are already linked together via bf_next pointers.
3564 */
3565 bf = TAILQ_FIRST(&bf_q);
3566
3567 /*
3568 * If it's the only frame send as non-aggregate
3569 * assume that ath_tx_form_aggr() has checked
3570 * whether it's in the BAW and added it appropriately.
3571 */
3572 if (bf->bf_state.bfs_nframes == 1) {
3573 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3574 "%s: single-frame aggregate\n", __func__);
3575 bf->bf_state.bfs_aggr = 0;
3576 ath_tx_set_rtscts(sc, bf);
3577 ath_tx_setds(sc, bf);
3578 ath_tx_chaindesclist(sc, bf);
3579 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
3580 ath_tx_set_ratectrl(sc, ni, bf);
3581 if (status == ATH_AGGR_BAW_CLOSED)
3582 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++;
3583 else
3584 sc->sc_aggr_stats.aggr_single_pkt++;
3585 } else {
3586 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3587 "%s: multi-frame aggregate: %d frames, "
3588 "length %d\n",
3589 __func__, bf->bf_state.bfs_nframes,
3590 bf->bf_state.bfs_al);
3591 bf->bf_state.bfs_aggr = 1;
3592 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++;
3593 sc->sc_aggr_stats.aggr_aggr_pkt++;
3594
3595 /*
3596 * Update the rate and rtscts information based on the
3597 * rate decision made by the rate control code;
3598 * the first frame in the aggregate needs it.
3599 */
3600 ath_tx_set_rtscts(sc, bf);
3601
3602 /*
3603 * Setup the relevant descriptor fields
3604 * for aggregation. The first descriptor
3605 * already points to the rest in the chain.
3606 */
3607 ath_tx_setds_11n(sc, bf);
3608
3609 /*
3610 * setup first desc with rate and aggr info
3611 */
3612 ath_tx_set_ratectrl(sc, ni, bf);
3613 }
3614 queuepkt:
3615 //txq = bf->bf_state.bfs_txq;
3616
3617 /* Set completion handler, multi-frame aggregate or not */
3618 bf->bf_comp = ath_tx_aggr_comp;
3619
3620 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID)
3621 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__);
3622
3623 /* Punt to txq */
3624 ath_tx_handoff(sc, txq, bf);
3625
3626 /* Track outstanding buffer count to hardware */
3627 /* aggregates are "one" buffer */
3628 tid->hwq_depth++;
3629
3630 /*
3631 * Break out if ath_tx_form_aggr() indicated
3632 * there can't be any further progress (eg BAW is full.)
3633 * Checking for an empty txq is done above.
3634 *
3635 * XXX locking on txq here?
3636 */
3637 if (txq->axq_aggr_depth >= sc->sc_hwq_limit ||
3638 status == ATH_AGGR_BAW_CLOSED)
3639 break;
3640 }
3641}
3642
3643/*
3644 * Schedule some packets from the given node/TID to the hardware.
3645 */
3646void
3647ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an,
3648 struct ath_tid *tid)
3649{
3650 struct ath_buf *bf;
3651 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
3652 struct ieee80211_node *ni = &an->an_node;
3653
3654 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n",
3655 __func__, an, tid->tid);
3656
3657 ATH_TXQ_LOCK_ASSERT(txq);
3658
3659 /* Check - is AMPDU pending or running? then print out something */
3660 if (ath_tx_ampdu_pending(sc, an, tid->tid))
3661 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n",
3662 __func__, tid->tid);
3663 if (ath_tx_ampdu_running(sc, an, tid->tid))
3664 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n",
3665 __func__, tid->tid);
3666
3667 for (;;) {
3668
3669 /*
3670 * If the upper layers have paused the TID, don't
3671 * queue any further packets.
3672 */
3673 if (tid->paused)
3674 break;
3675
3676 bf = TAILQ_FIRST(&tid->axq_q);
3677 if (bf == NULL) {
3678 break;
3679 }
3680
3681 ATH_TXQ_REMOVE(tid, bf, bf_list);
3682
3683 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n"));
3684
3685 /* Sanity check! */
3686 if (tid->tid != bf->bf_state.bfs_tid) {
3687 device_printf(sc->sc_dev, "%s: bfs_tid %d !="
3688 " tid %d\n",
3689 __func__, bf->bf_state.bfs_tid, tid->tid);
3690 }
3691 /* Normal completion handler */
3692 bf->bf_comp = ath_tx_normal_comp;
3693
3694 /* Program descriptors + rate control */
3695 ath_tx_do_ratelookup(sc, bf);
3696 ath_tx_rate_fill_rcflags(sc, bf);
3697 ath_tx_set_rtscts(sc, bf);
3698 ath_tx_setds(sc, bf);
3699 ath_tx_chaindesclist(sc, bf);
3700 ath_tx_set_ratectrl(sc, ni, bf);
3701
3702 /* Track outstanding buffer count to hardware */
3703 /* aggregates are "one" buffer */
3704 tid->hwq_depth++;
3705
3706 /* Punt to hardware or software txq */
3707 ath_tx_handoff(sc, txq, bf);
3708 }
3709}
3710
3711/*
3712 * Schedule some packets to the given hardware queue.
3713 *
3714 * This function walks the list of TIDs (ie, ath_node TIDs
3715 * with queued traffic) and attempts to schedule traffic
3716 * from them.
3717 *
3718 * TID scheduling is implemented as a FIFO, with TIDs being
3719 * added to the end of the queue after some frames have been
3720 * scheduled.
3721 */
3722void
3723ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq)
3724{
3725 struct ath_tid *tid, *next, *last;
3726
3727 ATH_TXQ_LOCK_ASSERT(txq);
3728
3729 /*
3730 * Don't schedule if the hardware queue is busy.
3731 * This (hopefully) gives some more time to aggregate
3732 * some packets in the aggregation queue.
3733 */
3734 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
3735 sc->sc_aggr_stats.aggr_sched_nopkt++;
3736 return;
3737 }
3738
3739 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s);
3740
3741 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) {
3742 /*
3743 * Suspend paused queues here; they'll be resumed
3744 * once the addba completes or times out.
3745 */
3746 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n",
3747 __func__, tid->tid, tid->paused);
3748 ath_tx_tid_unsched(sc, tid);
3749 if (tid->paused) {
3750 continue;
3751 }
3752 if (ath_tx_ampdu_running(sc, tid->an, tid->tid))
3753 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid);
3754 else
3755 ath_tx_tid_hw_queue_norm(sc, tid->an, tid);
3756
3757 /* Not empty? Re-schedule */
3758 if (tid->axq_depth != 0)
3759 ath_tx_tid_sched(sc, tid);
3760
3761 /* Give the software queue time to aggregate more packets */
3762 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
3763 break;
3764 }
3765
3766 /*
3767 * If this was the last entry on the original list, stop.
3768 * Otherwise nodes that have been rescheduled onto the end
3769 * of the TID FIFO list will just keep being rescheduled.
3770 */
3771 if (tid == last)
3772 break;
3773 }
3774}
3775
3776/*
3777 * TX addba handling
3778 */
3779
3780/*
3781 * Return net80211 TID struct pointer, or NULL for none
3782 */
3783struct ieee80211_tx_ampdu *
3784ath_tx_get_tx_tid(struct ath_node *an, int tid)
3785{
3786 struct ieee80211_node *ni = &an->an_node;
3787 struct ieee80211_tx_ampdu *tap;
3788 int ac;
3789
3790 if (tid == IEEE80211_NONQOS_TID)
3791 return NULL;
3792
3793 ac = TID_TO_WME_AC(tid);
3794
3795 tap = &ni->ni_tx_ampdu[ac];
3796 return tap;
3797}
3798
3799/*
3800 * Is AMPDU-TX running?
3801 */
3802static int
3803ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid)
3804{
3805 struct ieee80211_tx_ampdu *tap;
3806
3807 if (tid == IEEE80211_NONQOS_TID)
3808 return 0;
3809
3810 tap = ath_tx_get_tx_tid(an, tid);
3811 if (tap == NULL)
3812 return 0; /* Not valid; default to not running */
3813
3814 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING);
3815}
3816
3817/*
3818 * Is AMPDU-TX negotiation pending?
3819 */
3820static int
3821ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid)
3822{
3823 struct ieee80211_tx_ampdu *tap;
3824
3825 if (tid == IEEE80211_NONQOS_TID)
3826 return 0;
3827
3828 tap = ath_tx_get_tx_tid(an, tid);
3829 if (tap == NULL)
3830 return 0; /* Not valid; default to not pending */
3831
3832 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND);
3833}
3834
3835/*
3836 * Is AMPDU-TX pending for the given TID?
3837 */
3838
3839
3840/*
3841 * Method to handle sending an ADDBA request.
3842 *
3843 * We tap this so the relevant flags can be set to pause the TID
3844 * whilst waiting for the response.
3845 *
3846 * XXX there's no timeout handler we can override?
3847 */
3848int
3849ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
3850 int dialogtoken, int baparamset, int batimeout)
3851{
3852 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
3853 int tid = WME_AC_TO_TID(tap->txa_ac);
3854 struct ath_node *an = ATH_NODE(ni);
3855 struct ath_tid *atid = &an->an_tid[tid];
3856
3857 /*
3858 * XXX danger Will Robinson!
3859 *
3860 * Although the taskqueue may be running and scheduling some more
3861 * packets, these should all be _before_ the addba sequence number.
3862 * However, net80211 will keep self-assigning sequence numbers
3863 * until addba has been negotiated.
3864 *
3865 * In the past, these packets would be "paused" (which still works
3866 * fine, as they're being scheduled to the driver in the same
3867 * serialised method which is calling the addba request routine)
3868 * and when the aggregation session begins, they'll be dequeued
3869 * as aggregate packets and added to the BAW. However, now there's
3870 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these
3871 * packets. Thus they never get included in the BAW tracking and
3872 * this can cause the initial burst of packets after the addba
3873 * negotiation to "hang", as they quickly fall outside the BAW.
3874 *
3875 * The "eventual" solution should be to tag these packets with
3876 * dobaw. Although net80211 has given us a sequence number,
3877 * it'll be "after" the left edge of the BAW and thus it'll
3878 * fall within it.
3879 */
3880 ath_tx_tid_pause(sc, atid);
3881
3882 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3883 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n",
3884 __func__, dialogtoken, baparamset, batimeout);
3885 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3886 "%s: txa_start=%d, ni_txseqs=%d\n",
3887 __func__, tap->txa_start, ni->ni_txseqs[tid]);
3888
3889 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
3890 batimeout);
3891}
3892
3893/*
3894 * Handle an ADDBA response.
3895 *
3896 * We unpause the queue so TX'ing can resume.
3897 *
3898 * Any packets TX'ed from this point should be "aggregate" (whether
3899 * aggregate or not) so the BAW is updated.
3900 *
3901 * Note! net80211 keeps self-assigning sequence numbers until
3902 * ampdu is negotiated. This means the initially-negotiated BAW left
3903 * edge won't match the ni->ni_txseq.
3904 *
3905 * So, being very dirty, the BAW left edge is "slid" here to match
3906 * ni->ni_txseq.
3907 *
3908 * What likely SHOULD happen is that all packets subsequent to the
3909 * addba request should be tagged as aggregate and queued as non-aggregate
3910 * frames; thus updating the BAW. For now though, I'll just slide the
3911 * window.
3912 */
3913int
3914ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
3915 int status, int code, int batimeout)
3916{
3917 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
3918 int tid = WME_AC_TO_TID(tap->txa_ac);
3919 struct ath_node *an = ATH_NODE(ni);
3920 struct ath_tid *atid = &an->an_tid[tid];
3921 int r;
3922
3923 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3924 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__,
3925 status, code, batimeout);
3926
3927 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3928 "%s: txa_start=%d, ni_txseqs=%d\n",
3929 __func__, tap->txa_start, ni->ni_txseqs[tid]);
3930
3931 /*
3932 * Call this first, so the interface flags get updated
3933 * before the TID is unpaused. Otherwise a race condition
3934 * exists where the unpaused TID still doesn't yet have
3935 * IEEE80211_AGGR_RUNNING set.
3936 */
3937 r = sc->sc_addba_response(ni, tap, status, code, batimeout);
3938
3939 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3940 /*
3941 * XXX dirty!
3942 * Slide the BAW left edge to wherever net80211 left it for us.
3943 * Read above for more information.
3944 */
3945 tap->txa_start = ni->ni_txseqs[tid];
3946 ath_tx_tid_resume(sc, atid);
3947 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3948 return r;
3949}
3950
3951
3952/*
3953 * Stop ADDBA on a queue.
3954 */
3955void
3956ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
3957{
3958 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
3959 int tid = WME_AC_TO_TID(tap->txa_ac);
3960 struct ath_node *an = ATH_NODE(ni);
3961 struct ath_tid *atid = &an->an_tid[tid];
3962
3963 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__);
3964
3965 /* Pause TID traffic early, so there aren't any races */
3966 ath_tx_tid_pause(sc, atid);
3967
3968 /* There's no need to hold the TXQ lock here */
3969 sc->sc_addba_stop(ni, tap);
3970
3971 /*
3972 * ath_tx_cleanup will resume the TID if possible, otherwise
3973 * it'll set the cleanup flag, and it'll be unpaused once
3974 * things have been cleaned up.
3975 */
3976 ath_tx_cleanup(sc, an, tid);
3977}
3978
3979/*
3980 * Note: net80211 bar_timeout() doesn't call this function on BAR failure;
3981 * it simply tears down the aggregation session. Ew.
3982 *
3983 * It however will call ieee80211_ampdu_stop() which will call
3984 * ic->ic_addba_stop().
3985 *
3986 * XXX This uses a hard-coded max BAR count value; the whole
3987 * XXX BAR TX success or failure should be better handled!
3988 */
3989void
3990ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
3991 int status)
3992{
3993 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
3994 int tid = WME_AC_TO_TID(tap->txa_ac);
3995 struct ath_node *an = ATH_NODE(ni);
3996 struct ath_tid *atid = &an->an_tid[tid];
3997 int attempts = tap->txa_attempts;
3998
3999 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4000 "%s: called; status=%d\n", __func__, status);
4001
4002 /* Note: This may update the BAW details */
4003 sc->sc_bar_response(ni, tap, status);
4004
4005 /* Unpause the TID */
4006 /*
4007 * XXX if this is attempt=50, the TID will be downgraded
4008 * XXX to a non-aggregate session. So we must unpause the
4009 * XXX TID here or it'll never be done.
4010 */
4011 if (status == 0 || attempts == 50) {
4012 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4013 ath_tx_tid_resume(sc, atid);
4014 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4015 }
4016}
4017
4018/*
4019 * This is called whenever the pending ADDBA request times out.
4020 * Unpause and reschedule the TID.
4021 */
4022void
4023ath_addba_response_timeout(struct ieee80211_node *ni,
4024 struct ieee80211_tx_ampdu *tap)
4025{
4026 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4027 int tid = WME_AC_TO_TID(tap->txa_ac);
4028 struct ath_node *an = ATH_NODE(ni);
4029 struct ath_tid *atid = &an->an_tid[tid];
4030
4031 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4032 "%s: called; resuming\n", __func__);
4033
4034 /* Note: This updates the aggregate state to (again) pending */
4035 sc->sc_addba_response_timeout(ni, tap);
4036
4037 /* Unpause the TID; which reschedules it */
4038 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4039 ath_tx_tid_resume(sc, atid);
4040 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4041}
| 2655 }
2656
2657
2658 /*
2659 * If the current TID is running AMPDU, update
2660 * the BAW.
2661 */
2662 if (ath_tx_ampdu_running(sc, an, tid->tid) &&
2663 bf->bf_state.bfs_dobaw) {
2664 /*
2665 * Only remove the frame from the BAW if it's
2666 * been transmitted at least once; this means
2667 * the frame was in the BAW to begin with.
2668 */
2669 if (bf->bf_state.bfs_retries > 0) {
2670 ath_tx_update_baw(sc, an, tid, bf);
2671 bf->bf_state.bfs_dobaw = 0;
2672 }
2673 /*
2674 * This has become a non-fatal error now
2675 */
2676 if (! bf->bf_state.bfs_addedbaw)
2677 device_printf(sc->sc_dev,
2678 "%s: wasn't added: seqno %d\n",
2679 __func__, SEQNO(bf->bf_state.bfs_seqno));
2680 }
2681 ATH_TXQ_REMOVE(tid, bf, bf_list);
2682 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list);
2683 }
2684
2685 /*
2686 * Now that it's completed, grab the TID lock and update
2687 * the sequence number and BAW window.
2688 * Because sequence numbers have been assigned to frames
2689 * that haven't been sent yet, it's entirely possible
2690 * we'll be called with some pending frames that have not
2691 * been transmitted.
2692 *
2693 * The cleaner solution is to do the sequence number allocation
2694 * when the packet is first transmitted - and thus the "retries"
2695 * check above would be enough to update the BAW/seqno.
2696 */
2697
2698 /* But don't do it for non-QoS TIDs */
2699 if (tap) {
2700#if 0
2701 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2702 "%s: node %p: TID %d: sliding BAW left edge to %d\n",
2703 __func__, an, tid->tid, tap->txa_start);
2704#endif
2705 ni->ni_txseqs[tid->tid] = tap->txa_start;
2706 tid->baw_tail = tid->baw_head;
2707 }
2708}
2709
2710/*
2711 * Flush all software queued packets for the given node.
2712 *
2713 * This occurs when a completion handler frees the last buffer
2714 * for a node, and the node is thus freed. This causes the node
2715 * to be cleaned up, which ends up calling ath_tx_node_flush.
2716 */
2717void
2718ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an)
2719{
2720 int tid;
2721 ath_bufhead bf_cq;
2722 struct ath_buf *bf;
2723
2724 TAILQ_INIT(&bf_cq);
2725
2726 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
2727 struct ath_tid *atid = &an->an_tid[tid];
2728 struct ath_txq *txq = sc->sc_ac2q[atid->ac];
2729
2730 /* Remove this tid from the list of active tids */
2731 ATH_TXQ_LOCK(txq);
2732 ath_tx_tid_unsched(sc, atid);
2733
2734 /* Free packets */
2735 ath_tx_tid_drain(sc, an, atid, &bf_cq);
2736 ATH_TXQ_UNLOCK(txq);
2737 }
2738
2739 /* Handle completed frames */
2740 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
2741 TAILQ_REMOVE(&bf_cq, bf, bf_list);
2742 ath_tx_default_comp(sc, bf, 0);
2743 }
2744}
2745
2746/*
2747 * Drain all the software TXQs currently with traffic queued.
2748 */
2749void
2750ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq)
2751{
2752 struct ath_tid *tid;
2753 ath_bufhead bf_cq;
2754 struct ath_buf *bf;
2755
2756 TAILQ_INIT(&bf_cq);
2757 ATH_TXQ_LOCK(txq);
2758
2759 /*
2760 * Iterate over all active tids for the given txq,
2761 * flushing and unsched'ing them
2762 */
2763 while (! TAILQ_EMPTY(&txq->axq_tidq)) {
2764 tid = TAILQ_FIRST(&txq->axq_tidq);
2765 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq);
2766 ath_tx_tid_unsched(sc, tid);
2767 }
2768
2769 ATH_TXQ_UNLOCK(txq);
2770
2771 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
2772 TAILQ_REMOVE(&bf_cq, bf, bf_list);
2773 ath_tx_default_comp(sc, bf, 0);
2774 }
2775}
2776
2777/*
2778 * Handle completion of non-aggregate session frames.
2779 */
2780void
2781ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
2782{
2783 struct ieee80211_node *ni = bf->bf_node;
2784 struct ath_node *an = ATH_NODE(ni);
2785 int tid = bf->bf_state.bfs_tid;
2786 struct ath_tid *atid = &an->an_tid[tid];
2787 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
2788
2789 /* The TID state is protected behind the TXQ lock */
2790 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2791
2792 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n",
2793 __func__, bf, fail, atid->hwq_depth - 1);
2794
2795 atid->hwq_depth--;
2796 if (atid->hwq_depth < 0)
2797 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
2798 __func__, atid->hwq_depth);
2799 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2800
2801 /*
2802 * punt to rate control if we're not being cleaned up
2803 * during a hw queue drain and the frame wanted an ACK.
2804 */
2805 if (fail == 0 && ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0))
2806 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
2807 ts, bf->bf_state.bfs_pktlen,
2808 1, (ts->ts_status == 0) ? 0 : 1);
2809
2810 ath_tx_default_comp(sc, bf, fail);
2811}
2812
2813/*
2814 * Handle cleanup of aggregate session packets that aren't
2815 * an A-MPDU.
2816 *
2817 * There's no need to update the BAW here - the session is being
2818 * torn down.
2819 */
2820static void
2821ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf)
2822{
2823 struct ieee80211_node *ni = bf->bf_node;
2824 struct ath_node *an = ATH_NODE(ni);
2825 int tid = bf->bf_state.bfs_tid;
2826 struct ath_tid *atid = &an->an_tid[tid];
2827
2828 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n",
2829 __func__, tid, atid->incomp);
2830
2831 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2832 atid->incomp--;
2833 if (atid->incomp == 0) {
2834 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2835 "%s: TID %d: cleaned up! resume!\n",
2836 __func__, tid);
2837 atid->cleanup_inprogress = 0;
2838 ath_tx_tid_resume(sc, atid);
2839 }
2840 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2841
2842 ath_tx_default_comp(sc, bf, 0);
2843}
2844
2845/*
2846 * Performs transmit side cleanup when TID changes from aggregated to
2847 * unaggregated.
2848 *
2849 * - Discard all retry frames from the s/w queue.
2850 * - Fix the tx completion function for all buffers in s/w queue.
2851 * - Count the number of unacked frames, and let transmit completion
2852 * handle it later.
2853 *
2854 * The caller is responsible for pausing the TID.
2855 */
2856static void
2857ath_tx_cleanup(struct ath_softc *sc, struct ath_node *an, int tid)
2858{
2859 struct ath_tid *atid = &an->an_tid[tid];
2860 struct ieee80211_tx_ampdu *tap;
2861 struct ath_buf *bf, *bf_next;
2862 ath_bufhead bf_cq;
2863
2864 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2865 "%s: TID %d: called\n", __func__, tid);
2866
2867 TAILQ_INIT(&bf_cq);
2868 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
2869
2870 /*
2871 * Update the frames in the software TX queue:
2872 *
2873 * + Discard retry frames in the queue
2874 * + Fix the completion function to be non-aggregate
2875 */
2876 bf = TAILQ_FIRST(&atid->axq_q);
2877 while (bf) {
2878 if (bf->bf_state.bfs_isretried) {
2879 bf_next = TAILQ_NEXT(bf, bf_list);
2880 TAILQ_REMOVE(&atid->axq_q, bf, bf_list);
2881 atid->axq_depth--;
2882 if (bf->bf_state.bfs_dobaw) {
2883 ath_tx_update_baw(sc, an, atid, bf);
2884 if (! bf->bf_state.bfs_addedbaw)
2885 device_printf(sc->sc_dev,
2886 "%s: wasn't added: seqno %d\n",
2887 __func__,
2888 SEQNO(bf->bf_state.bfs_seqno));
2889 }
2890 bf->bf_state.bfs_dobaw = 0;
2891 /*
2892 * Call the default completion handler with "fail" just
2893 * so upper levels are suitably notified about this.
2894 */
2895 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
2896 bf = bf_next;
2897 continue;
2898 }
2899 /* Give these the default completion handler */
2900 bf->bf_comp = ath_tx_normal_comp;
2901 bf = TAILQ_NEXT(bf, bf_list);
2902 }
2903
2904 /* The caller is required to pause the TID */
2905#if 0
2906 /* Pause the TID */
2907 ath_tx_tid_pause(sc, atid);
2908#endif
2909
2910 /*
2911 * Calculate what hardware-queued frames exist based
2912 * on the current BAW size. Ie, what frames have been
2913 * added to the TX hardware queue for this TID but
2914 * not yet ACKed.
2915 */
2916 tap = ath_tx_get_tx_tid(an, tid);
2917 /* Need the lock - fiddling with BAW */
2918 while (atid->baw_head != atid->baw_tail) {
2919 if (atid->tx_buf[atid->baw_head]) {
2920 atid->incomp++;
2921 atid->cleanup_inprogress = 1;
2922 atid->tx_buf[atid->baw_head] = NULL;
2923 }
2924 INCR(atid->baw_head, ATH_TID_MAX_BUFS);
2925 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2926 }
2927
2928 /*
2929 * If cleanup is required, defer TID scheduling
2930 * until all the HW queued packets have been
2931 * sent.
2932 */
2933 if (! atid->cleanup_inprogress)
2934 ath_tx_tid_resume(sc, atid);
2935
2936 if (atid->cleanup_inprogress)
2937 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
2938 "%s: TID %d: cleanup needed: %d packets\n",
2939 __func__, tid, atid->incomp);
2940 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
2941
2942 /* Handle completing frames and fail them */
2943 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
2944 TAILQ_REMOVE(&bf_cq, bf, bf_list);
2945 ath_tx_default_comp(sc, bf, 1);
2946 }
2947}
2948
2949static void
2950ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
2951{
2952 struct ieee80211_frame *wh;
2953
2954 wh = mtod(bf->bf_m, struct ieee80211_frame *);
2955 /* Only update/resync if needed */
2956 if (bf->bf_state.bfs_isretried == 0) {
2957 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
2958 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2959 BUS_DMASYNC_PREWRITE);
2960 }
2961 sc->sc_stats.ast_tx_swretries++;
2962 bf->bf_state.bfs_isretried = 1;
2963 bf->bf_state.bfs_retries ++;
2964}
2965
2966static struct ath_buf *
2967ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an,
2968 struct ath_tid *tid, struct ath_buf *bf)
2969{
2970 struct ath_buf *nbf;
2971 int error;
2972
2973 nbf = ath_buf_clone(sc, bf);
2974
2975#if 0
2976 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n",
2977 __func__);
2978#endif
2979
2980 if (nbf == NULL) {
2981 /* Failed to clone */
2982 device_printf(sc->sc_dev,
2983 "%s: failed to clone a busy buffer\n",
2984 __func__);
2985 return NULL;
2986 }
2987
2988 /* Setup the dma for the new buffer */
2989 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m);
2990 if (error != 0) {
2991 device_printf(sc->sc_dev,
2992 "%s: failed to setup dma for clone\n",
2993 __func__);
2994 /*
2995 * Put this at the head of the list, not tail;
2996 * that way it doesn't interfere with the
2997 * busy buffer logic (which uses the tail of
2998 * the list.)
2999 */
3000 ATH_TXBUF_LOCK(sc);
3001 TAILQ_INSERT_HEAD(&sc->sc_txbuf, nbf, bf_list);
3002 ATH_TXBUF_UNLOCK(sc);
3003 return NULL;
3004 }
3005
3006 /* Update BAW if required, before we free the original buf */
3007 if (bf->bf_state.bfs_dobaw)
3008 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf);
3009
3010 /* Free current buffer; return the older buffer */
3011 bf->bf_m = NULL;
3012 bf->bf_node = NULL;
3013 ath_freebuf(sc, bf);
3014 return nbf;
3015}
3016
3017/*
3018 * Handle retrying an unaggregate frame in an aggregate
3019 * session.
3020 *
3021 * If too many retries occur, pause the TID, wait for
3022 * any further retransmits (as there's no reason why
3023 * non-aggregate frames in an aggregate session are
3024 * transmitted in-order; they just have to be in-BAW)
3025 * and then queue a BAR.
3026 */
3027static void
3028ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf)
3029{
3030 struct ieee80211_node *ni = bf->bf_node;
3031 struct ath_node *an = ATH_NODE(ni);
3032 int tid = bf->bf_state.bfs_tid;
3033 struct ath_tid *atid = &an->an_tid[tid];
3034 struct ieee80211_tx_ampdu *tap;
3035 int txseq;
3036
3037 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3038
3039 tap = ath_tx_get_tx_tid(an, tid);
3040
3041 /*
3042 * If the buffer is marked as busy, we can't directly
3043 * reuse it. Instead, try to clone the buffer.
3044 * If the clone is successful, recycle the old buffer.
3045 * If the clone is unsuccessful, set bfs_retries to max
3046 * to force the next bit of code to free the buffer
3047 * for us.
3048 */
3049 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
3050 (bf->bf_flags & ATH_BUF_BUSY)) {
3051 struct ath_buf *nbf;
3052 nbf = ath_tx_retry_clone(sc, an, atid, bf);
3053 if (nbf)
3054 /* bf has been freed at this point */
3055 bf = nbf;
3056 else
3057 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
3058 }
3059
3060 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
3061 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
3062 "%s: exceeded retries; seqno %d\n",
3063 __func__, SEQNO(bf->bf_state.bfs_seqno));
3064 sc->sc_stats.ast_tx_swretrymax++;
3065
3066 /* Update BAW anyway */
3067 if (bf->bf_state.bfs_dobaw) {
3068 ath_tx_update_baw(sc, an, atid, bf);
3069 if (! bf->bf_state.bfs_addedbaw)
3070 device_printf(sc->sc_dev,
3071 "%s: wasn't added: seqno %d\n",
3072 __func__, SEQNO(bf->bf_state.bfs_seqno));
3073 }
3074 bf->bf_state.bfs_dobaw = 0;
3075
3076 /* Send BAR frame */
3077 /*
3078 * This'll end up going into net80211 and back out
3079 * again, via ic->ic_raw_xmit().
3080 */
3081 txseq = tap->txa_start;
3082 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3083
3084 device_printf(sc->sc_dev,
3085 "%s: TID %d: send BAR; seq %d\n", __func__, tid, txseq);
3086
3087 /* XXX TODO: send BAR */
3088
3089 /* Free buffer, bf is free after this call */
3090 ath_tx_default_comp(sc, bf, 0);
3091 return;
3092 }
3093
3094 /*
3095 * This increments the retry counter as well as
3096 * sets the retry flag in the ath_buf and packet
3097 * body.
3098 */
3099 ath_tx_set_retry(sc, bf);
3100
3101 /*
3102 * Insert this at the head of the queue, so it's
3103 * retried before any current/subsequent frames.
3104 */
3105 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list);
3106 ath_tx_tid_sched(sc, atid);
3107
3108 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3109}
3110
3111/*
3112 * Common code for aggregate excessive retry/subframe retry.
3113 * If retrying, queues buffers to bf_q. If not, frees the
3114 * buffers.
3115 *
3116 * XXX should unify this with ath_tx_aggr_retry_unaggr()
3117 */
3118static int
3119ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf,
3120 ath_bufhead *bf_q)
3121{
3122 struct ieee80211_node *ni = bf->bf_node;
3123 struct ath_node *an = ATH_NODE(ni);
3124 int tid = bf->bf_state.bfs_tid;
3125 struct ath_tid *atid = &an->an_tid[tid];
3126
3127 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]);
3128
3129 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
3130 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0);
3131 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */
3132
3133 /*
3134 * If the buffer is marked as busy, we can't directly
3135 * reuse it. Instead, try to clone the buffer.
3136 * If the clone is successful, recycle the old buffer.
3137 * If the clone is unsuccessful, set bfs_retries to max
3138 * to force the next bit of code to free the buffer
3139 * for us.
3140 */
3141 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
3142 (bf->bf_flags & ATH_BUF_BUSY)) {
3143 struct ath_buf *nbf;
3144 nbf = ath_tx_retry_clone(sc, an, atid, bf);
3145 if (nbf)
3146 /* bf has been freed at this point */
3147 bf = nbf;
3148 else
3149 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
3150 }
3151
3152 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
3153 sc->sc_stats.ast_tx_swretrymax++;
3154 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
3155 "%s: max retries: seqno %d\n",
3156 __func__, SEQNO(bf->bf_state.bfs_seqno));
3157 ath_tx_update_baw(sc, an, atid, bf);
3158 if (! bf->bf_state.bfs_addedbaw)
3159 device_printf(sc->sc_dev,
3160 "%s: wasn't added: seqno %d\n",
3161 __func__, SEQNO(bf->bf_state.bfs_seqno));
3162 bf->bf_state.bfs_dobaw = 0;
3163 return 1;
3164 }
3165
3166 ath_tx_set_retry(sc, bf);
3167 bf->bf_next = NULL; /* Just to make sure */
3168
3169 TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3170 return 0;
3171}
3172
3173/*
3174 * error pkt completion for an aggregate destination
3175 */
3176static void
3177ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first,
3178 struct ath_tid *tid)
3179{
3180 struct ieee80211_node *ni = bf_first->bf_node;
3181 struct ath_node *an = ATH_NODE(ni);
3182 struct ath_buf *bf_next, *bf;
3183 ath_bufhead bf_q;
3184 int drops = 0;
3185 struct ieee80211_tx_ampdu *tap;
3186 ath_bufhead bf_cq;
3187
3188 TAILQ_INIT(&bf_q);
3189 TAILQ_INIT(&bf_cq);
3190
3191 /*
3192 * Update rate control - all frames have failed.
3193 *
3194 * XXX use the length in the first frame in the series;
3195 * XXX just so things are consistent for now.
3196 */
3197 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc,
3198 &bf_first->bf_status.ds_txstat,
3199 bf_first->bf_state.bfs_pktlen,
3200 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes);
3201
3202 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
3203 tap = ath_tx_get_tx_tid(an, tid->tid);
3204 sc->sc_stats.ast_tx_aggr_failall++;
3205
3206 /* Retry all subframes */
3207 bf = bf_first;
3208 while (bf) {
3209 bf_next = bf->bf_next;
3210 bf->bf_next = NULL; /* Remove it from the aggr list */
3211 sc->sc_stats.ast_tx_aggr_fail++;
3212 if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
3213 drops++;
3214 bf->bf_next = NULL;
3215 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3216 }
3217 bf = bf_next;
3218 }
3219
3220 /* Prepend all frames to the beginning of the queue */
3221 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
3222 TAILQ_REMOVE(&bf_q, bf, bf_list);
3223 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list);
3224 }
3225
3226 ath_tx_tid_sched(sc, tid);
3227
3228 /*
3229 * send bar if we dropped any frames
3230 *
3231 * Keep the txq lock held for now, as we need to ensure
3232 * that ni_txseqs[] is consistent (as it's being updated
3233 * in the ifnet TX context or raw TX context.)
3234 */
3235 if (drops) {
3236 int txseq = tap->txa_start;
3237 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
3238 device_printf(sc->sc_dev,
3239 "%s: TID %d: send BAR; seq %d\n",
3240 __func__, tid->tid, txseq);
3241
3242 /* XXX TODO: send BAR */
3243 } else {
3244 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
3245 }
3246
3247 /* Complete frames which errored out */
3248 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3249 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3250 ath_tx_default_comp(sc, bf, 0);
3251 }
3252}
3253
3254/*
3255 * Handle clean-up of packets from an aggregate list.
3256 *
3257 * There's no need to update the BAW here - the session is being
3258 * torn down.
3259 */
3260static void
3261ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first)
3262{
3263 struct ath_buf *bf, *bf_next;
3264 struct ieee80211_node *ni = bf_first->bf_node;
3265 struct ath_node *an = ATH_NODE(ni);
3266 int tid = bf_first->bf_state.bfs_tid;
3267 struct ath_tid *atid = &an->an_tid[tid];
3268
3269 bf = bf_first;
3270
3271 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3272
3273 /* update incomp */
3274 while (bf) {
3275 atid->incomp--;
3276 bf = bf->bf_next;
3277 }
3278
3279 if (atid->incomp == 0) {
3280 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3281 "%s: TID %d: cleaned up! resume!\n",
3282 __func__, tid);
3283 atid->cleanup_inprogress = 0;
3284 ath_tx_tid_resume(sc, atid);
3285 }
3286 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3287
3288 /* Handle frame completion */
3289 while (bf) {
3290 bf_next = bf->bf_next;
3291 ath_tx_default_comp(sc, bf, 1);
3292 bf = bf_next;
3293 }
3294}
3295
3296/*
3297 * Handle completion of an set of aggregate frames.
3298 *
3299 * XXX for now, simply complete each sub-frame.
3300 *
3301 * Note: the completion handler is the last descriptor in the aggregate,
3302 * not the last descriptor in the first frame.
3303 */
3304static void
3305ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first,
3306 int fail)
3307{
3308 //struct ath_desc *ds = bf->bf_lastds;
3309 struct ieee80211_node *ni = bf_first->bf_node;
3310 struct ath_node *an = ATH_NODE(ni);
3311 int tid = bf_first->bf_state.bfs_tid;
3312 struct ath_tid *atid = &an->an_tid[tid];
3313 struct ath_tx_status ts;
3314 struct ieee80211_tx_ampdu *tap;
3315 ath_bufhead bf_q;
3316 ath_bufhead bf_cq;
3317 int seq_st, tx_ok;
3318 int hasba, isaggr;
3319 uint32_t ba[2];
3320 struct ath_buf *bf, *bf_next;
3321 int ba_index;
3322 int drops = 0;
3323 int nframes = 0, nbad = 0, nf;
3324 int pktlen;
3325 /* XXX there's too much on the stack? */
3326 struct ath_rc_series rc[4];
3327 int txseq;
3328
3329 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n",
3330 __func__, atid->hwq_depth);
3331
3332 /* The TID state is kept behind the TXQ lock */
3333 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3334
3335 atid->hwq_depth--;
3336 if (atid->hwq_depth < 0)
3337 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3338 __func__, atid->hwq_depth);
3339
3340 /*
3341 * Punt cleanup to the relevant function, not our problem now
3342 */
3343 if (atid->cleanup_inprogress) {
3344 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3345 ath_tx_comp_cleanup_aggr(sc, bf_first);
3346 return;
3347 }
3348
3349 /*
3350 * Take a copy; this may be needed -after- bf_first
3351 * has been completed and freed.
3352 */
3353 ts = bf_first->bf_status.ds_txstat;
3354 /*
3355 * XXX for now, use the first frame in the aggregate for
3356 * XXX rate control completion; it's at least consistent.
3357 */
3358 pktlen = bf_first->bf_state.bfs_pktlen;
3359
3360 /*
3361 * handle errors first
3362 */
3363 if (ts.ts_status & HAL_TXERR_XRETRY) {
3364 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3365 ath_tx_comp_aggr_error(sc, bf_first, atid);
3366 return;
3367 }
3368
3369 TAILQ_INIT(&bf_q);
3370 TAILQ_INIT(&bf_cq);
3371 tap = ath_tx_get_tx_tid(an, tid);
3372
3373 /*
3374 * extract starting sequence and block-ack bitmap
3375 */
3376 /* XXX endian-ness of seq_st, ba? */
3377 seq_st = ts.ts_seqnum;
3378 hasba = !! (ts.ts_flags & HAL_TX_BA);
3379 tx_ok = (ts.ts_status == 0);
3380 isaggr = bf_first->bf_state.bfs_aggr;
3381 ba[0] = ts.ts_ba_low;
3382 ba[1] = ts.ts_ba_high;
3383
3384 /*
3385 * Copy the TX completion status and the rate control
3386 * series from the first descriptor, as it may be freed
3387 * before the rate control code can get its grubby fingers
3388 * into things.
3389 */
3390 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc));
3391
3392 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3393 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, "
3394 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n",
3395 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags,
3396 isaggr, seq_st, hasba, ba[0], ba[1]);
3397
3398 /* Occasionally, the MAC sends a tx status for the wrong TID. */
3399 if (tid != ts.ts_tid) {
3400 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n",
3401 __func__, tid, ts.ts_tid);
3402 tx_ok = 0;
3403 }
3404
3405 /* AR5416 BA bug; this requires an interface reset */
3406 if (isaggr && tx_ok && (! hasba)) {
3407 device_printf(sc->sc_dev,
3408 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, "
3409 "seq_st=%d\n",
3410 __func__, hasba, tx_ok, isaggr, seq_st);
3411 /* XXX TODO: schedule an interface reset */
3412 }
3413
3414 /*
3415 * Walk the list of frames, figure out which ones were correctly
3416 * sent and which weren't.
3417 */
3418 bf = bf_first;
3419 nf = bf_first->bf_state.bfs_nframes;
3420
3421 /* bf_first is going to be invalid once this list is walked */
3422 bf_first = NULL;
3423
3424 /*
3425 * Walk the list of completed frames and determine
3426 * which need to be completed and which need to be
3427 * retransmitted.
3428 *
3429 * For completed frames, the completion functions need
3430 * to be called at the end of this function as the last
3431 * node reference may free the node.
3432 *
3433 * Finally, since the TXQ lock can't be held during the
3434 * completion callback (to avoid lock recursion),
3435 * the completion calls have to be done outside of the
3436 * lock.
3437 */
3438 while (bf) {
3439 nframes++;
3440 ba_index = ATH_BA_INDEX(seq_st,
3441 SEQNO(bf->bf_state.bfs_seqno));
3442 bf_next = bf->bf_next;
3443 bf->bf_next = NULL; /* Remove it from the aggr list */
3444
3445 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3446 "%s: checking bf=%p seqno=%d; ack=%d\n",
3447 __func__, bf, SEQNO(bf->bf_state.bfs_seqno),
3448 ATH_BA_ISSET(ba, ba_index));
3449
3450 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
3451 sc->sc_stats.ast_tx_aggr_ok++;
3452 ath_tx_update_baw(sc, an, atid, bf);
3453 bf->bf_state.bfs_dobaw = 0;
3454 if (! bf->bf_state.bfs_addedbaw)
3455 device_printf(sc->sc_dev,
3456 "%s: wasn't added: seqno %d\n",
3457 __func__, SEQNO(bf->bf_state.bfs_seqno));
3458 bf->bf_next = NULL;
3459 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3460 } else {
3461 sc->sc_stats.ast_tx_aggr_fail++;
3462 if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
3463 drops++;
3464 bf->bf_next = NULL;
3465 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3466 }
3467 nbad++;
3468 }
3469 bf = bf_next;
3470 }
3471
3472 /*
3473 * Now that the BAW updates have been done, unlock
3474 *
3475 * txseq is grabbed before the lock is released so we
3476 * have a consistent view of what -was- in the BAW.
3477 * Anything after this point will not yet have been
3478 * TXed.
3479 */
3480 txseq = tap->txa_start;
3481 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3482
3483 if (nframes != nf)
3484 device_printf(sc->sc_dev,
3485 "%s: num frames seen=%d; bf nframes=%d\n",
3486 __func__, nframes, nf);
3487
3488 /*
3489 * Now we know how many frames were bad, call the rate
3490 * control code.
3491 */
3492 if (fail == 0)
3493 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes,
3494 nbad);
3495
3496 /*
3497 * send bar if we dropped any frames
3498 */
3499 if (drops) {
3500 device_printf(sc->sc_dev,
3501 "%s: TID %d: send BAR; seq %d\n", __func__, tid, txseq);
3502 /* XXX TODO: send BAR */
3503 }
3504
3505 /* Prepend all frames to the beginning of the queue */
3506 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3507 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
3508 TAILQ_REMOVE(&bf_q, bf, bf_list);
3509 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list);
3510 }
3511 ath_tx_tid_sched(sc, atid);
3512 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3513
3514 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3515 "%s: txa_start now %d\n", __func__, tap->txa_start);
3516
3517 /* Do deferred completion */
3518 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3519 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3520 ath_tx_default_comp(sc, bf, 0);
3521 }
3522}
3523
3524/*
3525 * Handle completion of unaggregated frames in an ADDBA
3526 * session.
3527 *
3528 * Fail is set to 1 if the entry is being freed via a call to
3529 * ath_tx_draintxq().
3530 */
3531static void
3532ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail)
3533{
3534 struct ieee80211_node *ni = bf->bf_node;
3535 struct ath_node *an = ATH_NODE(ni);
3536 int tid = bf->bf_state.bfs_tid;
3537 struct ath_tid *atid = &an->an_tid[tid];
3538 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3539
3540 /*
3541 * Update rate control status here, before we possibly
3542 * punt to retry or cleanup.
3543 *
3544 * Do it outside of the TXQ lock.
3545 */
3546 if (fail == 0 && ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0))
3547 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
3548 &bf->bf_status.ds_txstat,
3549 bf->bf_state.bfs_pktlen,
3550 1, (ts->ts_status == 0) ? 0 : 1);
3551
3552 /*
3553 * This is called early so atid->hwq_depth can be tracked.
3554 * This unfortunately means that it's released and regrabbed
3555 * during retry and cleanup. That's rather inefficient.
3556 */
3557 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3558
3559 if (tid == IEEE80211_NONQOS_TID)
3560 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__);
3561
3562 DPRINTF(sc, ATH_DEBUG_SW_TX,
3563 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n",
3564 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth,
3565 SEQNO(bf->bf_state.bfs_seqno));
3566
3567 atid->hwq_depth--;
3568 if (atid->hwq_depth < 0)
3569 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3570 __func__, atid->hwq_depth);
3571
3572 /*
3573 * If a cleanup is in progress, punt to comp_cleanup;
3574 * rather than handling it here. It's thus their
3575 * responsibility to clean up, call the completion
3576 * function in net80211, etc.
3577 */
3578 if (atid->cleanup_inprogress) {
3579 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3580 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n",
3581 __func__);
3582 ath_tx_comp_cleanup_unaggr(sc, bf);
3583 return;
3584 }
3585
3586 /*
3587 * Don't bother with the retry check if all frames
3588 * are being failed (eg during queue deletion.)
3589 */
3590 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) {
3591 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3592 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n",
3593 __func__);
3594 ath_tx_aggr_retry_unaggr(sc, bf);
3595 return;
3596 }
3597
3598 /* Success? Complete */
3599 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n",
3600 __func__, tid, SEQNO(bf->bf_state.bfs_seqno));
3601 if (bf->bf_state.bfs_dobaw) {
3602 ath_tx_update_baw(sc, an, atid, bf);
3603 bf->bf_state.bfs_dobaw = 0;
3604 if (! bf->bf_state.bfs_addedbaw)
3605 device_printf(sc->sc_dev,
3606 "%s: wasn't added: seqno %d\n",
3607 __func__, SEQNO(bf->bf_state.bfs_seqno));
3608 }
3609
3610 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3611
3612 ath_tx_default_comp(sc, bf, fail);
3613 /* bf is freed at this point */
3614}
3615
3616void
3617ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3618{
3619 if (bf->bf_state.bfs_aggr)
3620 ath_tx_aggr_comp_aggr(sc, bf, fail);
3621 else
3622 ath_tx_aggr_comp_unaggr(sc, bf, fail);
3623}
3624
3625/*
3626 * Schedule some packets from the given node/TID to the hardware.
3627 *
3628 * This is the aggregate version.
3629 */
3630void
3631ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an,
3632 struct ath_tid *tid)
3633{
3634 struct ath_buf *bf;
3635 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
3636 struct ieee80211_tx_ampdu *tap;
3637 struct ieee80211_node *ni = &an->an_node;
3638 ATH_AGGR_STATUS status;
3639 ath_bufhead bf_q;
3640
3641 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid);
3642 ATH_TXQ_LOCK_ASSERT(txq);
3643
3644 tap = ath_tx_get_tx_tid(an, tid->tid);
3645
3646 if (tid->tid == IEEE80211_NONQOS_TID)
3647 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n",
3648 __func__);
3649
3650 for (;;) {
3651 status = ATH_AGGR_DONE;
3652
3653 /*
3654 * If the upper layer has paused the TID, don't
3655 * queue any further packets.
3656 *
3657 * This can also occur from the completion task because
3658 * of packet loss; but as its serialised with this code,
3659 * it won't "appear" half way through queuing packets.
3660 */
3661 if (tid->paused)
3662 break;
3663
3664 bf = TAILQ_FIRST(&tid->axq_q);
3665 if (bf == NULL) {
3666 break;
3667 }
3668
3669 /*
3670 * If the packet doesn't fall within the BAW (eg a NULL
3671 * data frame), schedule it directly; continue.
3672 */
3673 if (! bf->bf_state.bfs_dobaw) {
3674 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3675 "%s: non-baw packet\n",
3676 __func__);
3677 ATH_TXQ_REMOVE(tid, bf, bf_list);
3678 bf->bf_state.bfs_aggr = 0;
3679 ath_tx_do_ratelookup(sc, bf);
3680 ath_tx_rate_fill_rcflags(sc, bf);
3681 ath_tx_set_rtscts(sc, bf);
3682 ath_tx_setds(sc, bf);
3683 ath_tx_chaindesclist(sc, bf);
3684 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
3685 ath_tx_set_ratectrl(sc, ni, bf);
3686
3687 sc->sc_aggr_stats.aggr_nonbaw_pkt++;
3688
3689 /* Queue the packet; continue */
3690 goto queuepkt;
3691 }
3692
3693 TAILQ_INIT(&bf_q);
3694
3695 /*
3696 * Do a rate control lookup on the first frame in the
3697 * list. The rate control code needs that to occur
3698 * before it can determine whether to TX.
3699 * It's inaccurate because the rate control code doesn't
3700 * really "do" aggregate lookups, so it only considers
3701 * the size of the first frame.
3702 */
3703 ath_tx_do_ratelookup(sc, bf);
3704 bf->bf_state.bfs_rc[3].rix = 0;
3705 bf->bf_state.bfs_rc[3].tries = 0;
3706 ath_tx_rate_fill_rcflags(sc, bf);
3707
3708 status = ath_tx_form_aggr(sc, an, tid, &bf_q);
3709
3710 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3711 "%s: ath_tx_form_aggr() status=%d\n", __func__, status);
3712
3713 /*
3714 * No frames to be picked up - out of BAW
3715 */
3716 if (TAILQ_EMPTY(&bf_q))
3717 break;
3718
3719 /*
3720 * This assumes that the descriptor list in the ath_bufhead
3721 * are already linked together via bf_next pointers.
3722 */
3723 bf = TAILQ_FIRST(&bf_q);
3724
3725 /*
3726 * If it's the only frame send as non-aggregate
3727 * assume that ath_tx_form_aggr() has checked
3728 * whether it's in the BAW and added it appropriately.
3729 */
3730 if (bf->bf_state.bfs_nframes == 1) {
3731 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3732 "%s: single-frame aggregate\n", __func__);
3733 bf->bf_state.bfs_aggr = 0;
3734 ath_tx_set_rtscts(sc, bf);
3735 ath_tx_setds(sc, bf);
3736 ath_tx_chaindesclist(sc, bf);
3737 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
3738 ath_tx_set_ratectrl(sc, ni, bf);
3739 if (status == ATH_AGGR_BAW_CLOSED)
3740 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++;
3741 else
3742 sc->sc_aggr_stats.aggr_single_pkt++;
3743 } else {
3744 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3745 "%s: multi-frame aggregate: %d frames, "
3746 "length %d\n",
3747 __func__, bf->bf_state.bfs_nframes,
3748 bf->bf_state.bfs_al);
3749 bf->bf_state.bfs_aggr = 1;
3750 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++;
3751 sc->sc_aggr_stats.aggr_aggr_pkt++;
3752
3753 /*
3754 * Update the rate and rtscts information based on the
3755 * rate decision made by the rate control code;
3756 * the first frame in the aggregate needs it.
3757 */
3758 ath_tx_set_rtscts(sc, bf);
3759
3760 /*
3761 * Setup the relevant descriptor fields
3762 * for aggregation. The first descriptor
3763 * already points to the rest in the chain.
3764 */
3765 ath_tx_setds_11n(sc, bf);
3766
3767 /*
3768 * setup first desc with rate and aggr info
3769 */
3770 ath_tx_set_ratectrl(sc, ni, bf);
3771 }
3772 queuepkt:
3773 //txq = bf->bf_state.bfs_txq;
3774
3775 /* Set completion handler, multi-frame aggregate or not */
3776 bf->bf_comp = ath_tx_aggr_comp;
3777
3778 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID)
3779 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__);
3780
3781 /* Punt to txq */
3782 ath_tx_handoff(sc, txq, bf);
3783
3784 /* Track outstanding buffer count to hardware */
3785 /* aggregates are "one" buffer */
3786 tid->hwq_depth++;
3787
3788 /*
3789 * Break out if ath_tx_form_aggr() indicated
3790 * there can't be any further progress (eg BAW is full.)
3791 * Checking for an empty txq is done above.
3792 *
3793 * XXX locking on txq here?
3794 */
3795 if (txq->axq_aggr_depth >= sc->sc_hwq_limit ||
3796 status == ATH_AGGR_BAW_CLOSED)
3797 break;
3798 }
3799}
3800
3801/*
3802 * Schedule some packets from the given node/TID to the hardware.
3803 */
3804void
3805ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an,
3806 struct ath_tid *tid)
3807{
3808 struct ath_buf *bf;
3809 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
3810 struct ieee80211_node *ni = &an->an_node;
3811
3812 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n",
3813 __func__, an, tid->tid);
3814
3815 ATH_TXQ_LOCK_ASSERT(txq);
3816
3817 /* Check - is AMPDU pending or running? then print out something */
3818 if (ath_tx_ampdu_pending(sc, an, tid->tid))
3819 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n",
3820 __func__, tid->tid);
3821 if (ath_tx_ampdu_running(sc, an, tid->tid))
3822 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n",
3823 __func__, tid->tid);
3824
3825 for (;;) {
3826
3827 /*
3828 * If the upper layers have paused the TID, don't
3829 * queue any further packets.
3830 */
3831 if (tid->paused)
3832 break;
3833
3834 bf = TAILQ_FIRST(&tid->axq_q);
3835 if (bf == NULL) {
3836 break;
3837 }
3838
3839 ATH_TXQ_REMOVE(tid, bf, bf_list);
3840
3841 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n"));
3842
3843 /* Sanity check! */
3844 if (tid->tid != bf->bf_state.bfs_tid) {
3845 device_printf(sc->sc_dev, "%s: bfs_tid %d !="
3846 " tid %d\n",
3847 __func__, bf->bf_state.bfs_tid, tid->tid);
3848 }
3849 /* Normal completion handler */
3850 bf->bf_comp = ath_tx_normal_comp;
3851
3852 /* Program descriptors + rate control */
3853 ath_tx_do_ratelookup(sc, bf);
3854 ath_tx_rate_fill_rcflags(sc, bf);
3855 ath_tx_set_rtscts(sc, bf);
3856 ath_tx_setds(sc, bf);
3857 ath_tx_chaindesclist(sc, bf);
3858 ath_tx_set_ratectrl(sc, ni, bf);
3859
3860 /* Track outstanding buffer count to hardware */
3861 /* aggregates are "one" buffer */
3862 tid->hwq_depth++;
3863
3864 /* Punt to hardware or software txq */
3865 ath_tx_handoff(sc, txq, bf);
3866 }
3867}
3868
3869/*
3870 * Schedule some packets to the given hardware queue.
3871 *
3872 * This function walks the list of TIDs (ie, ath_node TIDs
3873 * with queued traffic) and attempts to schedule traffic
3874 * from them.
3875 *
3876 * TID scheduling is implemented as a FIFO, with TIDs being
3877 * added to the end of the queue after some frames have been
3878 * scheduled.
3879 */
3880void
3881ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq)
3882{
3883 struct ath_tid *tid, *next, *last;
3884
3885 ATH_TXQ_LOCK_ASSERT(txq);
3886
3887 /*
3888 * Don't schedule if the hardware queue is busy.
3889 * This (hopefully) gives some more time to aggregate
3890 * some packets in the aggregation queue.
3891 */
3892 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
3893 sc->sc_aggr_stats.aggr_sched_nopkt++;
3894 return;
3895 }
3896
3897 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s);
3898
3899 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) {
3900 /*
3901 * Suspend paused queues here; they'll be resumed
3902 * once the addba completes or times out.
3903 */
3904 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n",
3905 __func__, tid->tid, tid->paused);
3906 ath_tx_tid_unsched(sc, tid);
3907 if (tid->paused) {
3908 continue;
3909 }
3910 if (ath_tx_ampdu_running(sc, tid->an, tid->tid))
3911 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid);
3912 else
3913 ath_tx_tid_hw_queue_norm(sc, tid->an, tid);
3914
3915 /* Not empty? Re-schedule */
3916 if (tid->axq_depth != 0)
3917 ath_tx_tid_sched(sc, tid);
3918
3919 /* Give the software queue time to aggregate more packets */
3920 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
3921 break;
3922 }
3923
3924 /*
3925 * If this was the last entry on the original list, stop.
3926 * Otherwise nodes that have been rescheduled onto the end
3927 * of the TID FIFO list will just keep being rescheduled.
3928 */
3929 if (tid == last)
3930 break;
3931 }
3932}
3933
3934/*
3935 * TX addba handling
3936 */
3937
3938/*
3939 * Return net80211 TID struct pointer, or NULL for none
3940 */
3941struct ieee80211_tx_ampdu *
3942ath_tx_get_tx_tid(struct ath_node *an, int tid)
3943{
3944 struct ieee80211_node *ni = &an->an_node;
3945 struct ieee80211_tx_ampdu *tap;
3946 int ac;
3947
3948 if (tid == IEEE80211_NONQOS_TID)
3949 return NULL;
3950
3951 ac = TID_TO_WME_AC(tid);
3952
3953 tap = &ni->ni_tx_ampdu[ac];
3954 return tap;
3955}
3956
3957/*
3958 * Is AMPDU-TX running?
3959 */
3960static int
3961ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid)
3962{
3963 struct ieee80211_tx_ampdu *tap;
3964
3965 if (tid == IEEE80211_NONQOS_TID)
3966 return 0;
3967
3968 tap = ath_tx_get_tx_tid(an, tid);
3969 if (tap == NULL)
3970 return 0; /* Not valid; default to not running */
3971
3972 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING);
3973}
3974
3975/*
3976 * Is AMPDU-TX negotiation pending?
3977 */
3978static int
3979ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid)
3980{
3981 struct ieee80211_tx_ampdu *tap;
3982
3983 if (tid == IEEE80211_NONQOS_TID)
3984 return 0;
3985
3986 tap = ath_tx_get_tx_tid(an, tid);
3987 if (tap == NULL)
3988 return 0; /* Not valid; default to not pending */
3989
3990 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND);
3991}
3992
3993/*
3994 * Is AMPDU-TX pending for the given TID?
3995 */
3996
3997
3998/*
3999 * Method to handle sending an ADDBA request.
4000 *
4001 * We tap this so the relevant flags can be set to pause the TID
4002 * whilst waiting for the response.
4003 *
4004 * XXX there's no timeout handler we can override?
4005 */
4006int
4007ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
4008 int dialogtoken, int baparamset, int batimeout)
4009{
4010 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4011 int tid = WME_AC_TO_TID(tap->txa_ac);
4012 struct ath_node *an = ATH_NODE(ni);
4013 struct ath_tid *atid = &an->an_tid[tid];
4014
4015 /*
4016 * XXX danger Will Robinson!
4017 *
4018 * Although the taskqueue may be running and scheduling some more
4019 * packets, these should all be _before_ the addba sequence number.
4020 * However, net80211 will keep self-assigning sequence numbers
4021 * until addba has been negotiated.
4022 *
4023 * In the past, these packets would be "paused" (which still works
4024 * fine, as they're being scheduled to the driver in the same
4025 * serialised method which is calling the addba request routine)
4026 * and when the aggregation session begins, they'll be dequeued
4027 * as aggregate packets and added to the BAW. However, now there's
4028 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these
4029 * packets. Thus they never get included in the BAW tracking and
4030 * this can cause the initial burst of packets after the addba
4031 * negotiation to "hang", as they quickly fall outside the BAW.
4032 *
4033 * The "eventual" solution should be to tag these packets with
4034 * dobaw. Although net80211 has given us a sequence number,
4035 * it'll be "after" the left edge of the BAW and thus it'll
4036 * fall within it.
4037 */
4038 ath_tx_tid_pause(sc, atid);
4039
4040 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4041 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n",
4042 __func__, dialogtoken, baparamset, batimeout);
4043 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4044 "%s: txa_start=%d, ni_txseqs=%d\n",
4045 __func__, tap->txa_start, ni->ni_txseqs[tid]);
4046
4047 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
4048 batimeout);
4049}
4050
4051/*
4052 * Handle an ADDBA response.
4053 *
4054 * We unpause the queue so TX'ing can resume.
4055 *
4056 * Any packets TX'ed from this point should be "aggregate" (whether
4057 * aggregate or not) so the BAW is updated.
4058 *
4059 * Note! net80211 keeps self-assigning sequence numbers until
4060 * ampdu is negotiated. This means the initially-negotiated BAW left
4061 * edge won't match the ni->ni_txseq.
4062 *
4063 * So, being very dirty, the BAW left edge is "slid" here to match
4064 * ni->ni_txseq.
4065 *
4066 * What likely SHOULD happen is that all packets subsequent to the
4067 * addba request should be tagged as aggregate and queued as non-aggregate
4068 * frames; thus updating the BAW. For now though, I'll just slide the
4069 * window.
4070 */
4071int
4072ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
4073 int status, int code, int batimeout)
4074{
4075 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4076 int tid = WME_AC_TO_TID(tap->txa_ac);
4077 struct ath_node *an = ATH_NODE(ni);
4078 struct ath_tid *atid = &an->an_tid[tid];
4079 int r;
4080
4081 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4082 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__,
4083 status, code, batimeout);
4084
4085 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4086 "%s: txa_start=%d, ni_txseqs=%d\n",
4087 __func__, tap->txa_start, ni->ni_txseqs[tid]);
4088
4089 /*
4090 * Call this first, so the interface flags get updated
4091 * before the TID is unpaused. Otherwise a race condition
4092 * exists where the unpaused TID still doesn't yet have
4093 * IEEE80211_AGGR_RUNNING set.
4094 */
4095 r = sc->sc_addba_response(ni, tap, status, code, batimeout);
4096
4097 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4098 /*
4099 * XXX dirty!
4100 * Slide the BAW left edge to wherever net80211 left it for us.
4101 * Read above for more information.
4102 */
4103 tap->txa_start = ni->ni_txseqs[tid];
4104 ath_tx_tid_resume(sc, atid);
4105 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4106 return r;
4107}
4108
4109
4110/*
4111 * Stop ADDBA on a queue.
4112 */
4113void
4114ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
4115{
4116 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4117 int tid = WME_AC_TO_TID(tap->txa_ac);
4118 struct ath_node *an = ATH_NODE(ni);
4119 struct ath_tid *atid = &an->an_tid[tid];
4120
4121 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__);
4122
4123 /* Pause TID traffic early, so there aren't any races */
4124 ath_tx_tid_pause(sc, atid);
4125
4126 /* There's no need to hold the TXQ lock here */
4127 sc->sc_addba_stop(ni, tap);
4128
4129 /*
4130 * ath_tx_cleanup will resume the TID if possible, otherwise
4131 * it'll set the cleanup flag, and it'll be unpaused once
4132 * things have been cleaned up.
4133 */
4134 ath_tx_cleanup(sc, an, tid);
4135}
4136
4137/*
4138 * Note: net80211 bar_timeout() doesn't call this function on BAR failure;
4139 * it simply tears down the aggregation session. Ew.
4140 *
4141 * It however will call ieee80211_ampdu_stop() which will call
4142 * ic->ic_addba_stop().
4143 *
4144 * XXX This uses a hard-coded max BAR count value; the whole
4145 * XXX BAR TX success or failure should be better handled!
4146 */
4147void
4148ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
4149 int status)
4150{
4151 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4152 int tid = WME_AC_TO_TID(tap->txa_ac);
4153 struct ath_node *an = ATH_NODE(ni);
4154 struct ath_tid *atid = &an->an_tid[tid];
4155 int attempts = tap->txa_attempts;
4156
4157 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4158 "%s: called; status=%d\n", __func__, status);
4159
4160 /* Note: This may update the BAW details */
4161 sc->sc_bar_response(ni, tap, status);
4162
4163 /* Unpause the TID */
4164 /*
4165 * XXX if this is attempt=50, the TID will be downgraded
4166 * XXX to a non-aggregate session. So we must unpause the
4167 * XXX TID here or it'll never be done.
4168 */
4169 if (status == 0 || attempts == 50) {
4170 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4171 ath_tx_tid_resume(sc, atid);
4172 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4173 }
4174}
4175
4176/*
4177 * This is called whenever the pending ADDBA request times out.
4178 * Unpause and reschedule the TID.
4179 */
4180void
4181ath_addba_response_timeout(struct ieee80211_node *ni,
4182 struct ieee80211_tx_ampdu *tap)
4183{
4184 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4185 int tid = WME_AC_TO_TID(tap->txa_ac);
4186 struct ath_node *an = ATH_NODE(ni);
4187 struct ath_tid *atid = &an->an_tid[tid];
4188
4189 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4190 "%s: called; resuming\n", __func__);
4191
4192 /* Note: This updates the aggregate state to (again) pending */
4193 sc->sc_addba_response_timeout(ni, tap);
4194
4195 /* Unpause the TID; which reschedules it */
4196 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4197 ath_tx_tid_resume(sc, atid);
4198 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4199}
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