1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14 * redistribution must be conditioned upon including a substantially
15 * similar Disclaimer requirement for further binary redistribution.
16 *
17 * NO WARRANTY
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGES.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_tx.c 240592 2012-09-17 03:17:42Z adrian $");
33
34/*
35 * Driver for the Atheros Wireless LAN controller.
36 *
37 * This software is derived from work of Atsushi Onoe; his contribution
38 * is greatly appreciated.
39 */
40
41#include "opt_inet.h"
42#include "opt_ath.h"
43#include "opt_wlan.h"
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/sysctl.h>
48#include <sys/mbuf.h>
49#include <sys/malloc.h>
50#include <sys/lock.h>
51#include <sys/mutex.h>
52#include <sys/kernel.h>
53#include <sys/socket.h>
54#include <sys/sockio.h>
55#include <sys/errno.h>
56#include <sys/callout.h>
57#include <sys/bus.h>
58#include <sys/endian.h>
59#include <sys/kthread.h>
60#include <sys/taskqueue.h>
61#include <sys/priv.h>
62
63#include <machine/bus.h>
64
65#include <net/if.h>
66#include <net/if_dl.h>
67#include <net/if_media.h>
68#include <net/if_types.h>
69#include <net/if_arp.h>
70#include <net/ethernet.h>
71#include <net/if_llc.h>
72
73#include <net80211/ieee80211_var.h>
74#include <net80211/ieee80211_regdomain.h>
75#ifdef IEEE80211_SUPPORT_SUPERG
76#include <net80211/ieee80211_superg.h>
77#endif
78#ifdef IEEE80211_SUPPORT_TDMA
79#include <net80211/ieee80211_tdma.h>
80#endif
81#include <net80211/ieee80211_ht.h>
82
83#include <net/bpf.h>
84
85#ifdef INET
86#include <netinet/in.h>
87#include <netinet/if_ether.h>
88#endif
89
90#include <dev/ath/if_athvar.h>
91#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
92#include <dev/ath/ath_hal/ah_diagcodes.h>
93
94#include <dev/ath/if_ath_debug.h>
95
96#ifdef ATH_TX99_DIAG
97#include <dev/ath/ath_tx99/ath_tx99.h>
98#endif
99
100#include <dev/ath/if_ath_misc.h>
101#include <dev/ath/if_ath_tx.h>
102#include <dev/ath/if_ath_tx_ht.h>
103
104/*
105 * How many retries to perform in software
106 */
107#define SWMAX_RETRIES 10
108
109static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an,
110 int tid);
111static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an,
112 int tid);
113static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc,
114 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0);
115static int ath_tx_action_frame_override_queue(struct ath_softc *sc,
116 struct ieee80211_node *ni, struct mbuf *m0, int *tid);
117
118/*
119 * Whether to use the 11n rate scenario functions or not
120 */
121static inline int
122ath_tx_is_11n(struct ath_softc *sc)
123{
124 return ((sc->sc_ah->ah_magic == 0x20065416) ||
125 (sc->sc_ah->ah_magic == 0x19741014));
126}
127
128/*
129 * Obtain the current TID from the given frame.
130 *
131 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.)
132 * This has implications for which AC/priority the packet is placed
133 * in.
134 */
135static int
136ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0)
137{
138 const struct ieee80211_frame *wh;
139 int pri = M_WME_GETAC(m0);
140
141 wh = mtod(m0, const struct ieee80211_frame *);
142 if (! IEEE80211_QOS_HAS_SEQ(wh))
143 return IEEE80211_NONQOS_TID;
144 else
145 return WME_AC_TO_TID(pri);
146}
147
148/*
149 * Determine what the correct AC queue for the given frame
150 * should be.
151 *
152 * This code assumes that the TIDs map consistently to
153 * the underlying hardware (or software) ath_txq.
154 * Since the sender may try to set an AC which is
155 * arbitrary, non-QoS TIDs may end up being put on
156 * completely different ACs. There's no way to put a
157 * TID into multiple ath_txq's for scheduling, so
158 * for now we override the AC/TXQ selection and set
159 * non-QOS TID frames into the BE queue.
160 *
161 * This may be completely incorrect - specifically,
162 * some management frames may end up out of order
163 * compared to the QoS traffic they're controlling.
164 * I'll look into this later.
165 */
166static int
167ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0)
168{
169 const struct ieee80211_frame *wh;
170 int pri = M_WME_GETAC(m0);
171 wh = mtod(m0, const struct ieee80211_frame *);
172 if (IEEE80211_QOS_HAS_SEQ(wh))
173 return pri;
174
175 return WME_AC_BE;
176}
177
178void
179ath_txfrag_cleanup(struct ath_softc *sc,
180 ath_bufhead *frags, struct ieee80211_node *ni)
181{
182 struct ath_buf *bf, *next;
183
184 ATH_TXBUF_LOCK_ASSERT(sc);
185
186 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
187 /* NB: bf assumed clean */
188 TAILQ_REMOVE(frags, bf, bf_list);
189 ath_returnbuf_head(sc, bf);
190 ieee80211_node_decref(ni);
191 }
192}
193
194/*
195 * Setup xmit of a fragmented frame. Allocate a buffer
196 * for each frag and bump the node reference count to
197 * reflect the held reference to be setup by ath_tx_start.
198 */
199int
200ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
201 struct mbuf *m0, struct ieee80211_node *ni)
202{
203 struct mbuf *m;
204 struct ath_buf *bf;
205
206 ATH_TXBUF_LOCK(sc);
207 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
208 /* XXX non-management? */
209 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
210 if (bf == NULL) { /* out of buffers, cleanup */
211 device_printf(sc->sc_dev, "%s: no buffer?\n",
212 __func__);
213 ath_txfrag_cleanup(sc, frags, ni);
214 break;
215 }
216 ieee80211_node_incref(ni);
217 TAILQ_INSERT_TAIL(frags, bf, bf_list);
218 }
219 ATH_TXBUF_UNLOCK(sc);
220
221 return !TAILQ_EMPTY(frags);
222}
223
224/*
225 * Reclaim mbuf resources. For fragmented frames we
226 * need to claim each frag chained with m_nextpkt.
227 */
228void
229ath_freetx(struct mbuf *m)
230{
231 struct mbuf *next;
232
233 do {
234 next = m->m_nextpkt;
235 m->m_nextpkt = NULL;
236 m_freem(m);
237 } while ((m = next) != NULL);
238}
239
240static int
241ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
242{
243 struct mbuf *m;
244 int error;
245
246 /*
247 * Load the DMA map so any coalescing is done. This
248 * also calculates the number of descriptors we need.
249 */
250 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
251 bf->bf_segs, &bf->bf_nseg,
252 BUS_DMA_NOWAIT);
253 if (error == EFBIG) {
254 /* XXX packet requires too many descriptors */
255 bf->bf_nseg = ATH_TXDESC+1;
256 } else if (error != 0) {
257 sc->sc_stats.ast_tx_busdma++;
258 ath_freetx(m0);
259 return error;
260 }
261 /*
262 * Discard null packets and check for packets that
263 * require too many TX descriptors. We try to convert
264 * the latter to a cluster.
265 */
266 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
267 sc->sc_stats.ast_tx_linear++;
268 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
269 if (m == NULL) {
270 ath_freetx(m0);
271 sc->sc_stats.ast_tx_nombuf++;
272 return ENOMEM;
273 }
274 m0 = m;
275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
276 bf->bf_segs, &bf->bf_nseg,
277 BUS_DMA_NOWAIT);
278 if (error != 0) {
279 sc->sc_stats.ast_tx_busdma++;
280 ath_freetx(m0);
281 return error;
282 }
283 KASSERT(bf->bf_nseg <= ATH_TXDESC,
284 ("too many segments after defrag; nseg %u", bf->bf_nseg));
285 } else if (bf->bf_nseg == 0) { /* null packet, discard */
286 sc->sc_stats.ast_tx_nodata++;
287 ath_freetx(m0);
288 return EIO;
289 }
290 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
291 __func__, m0, m0->m_pkthdr.len);
292 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
293 bf->bf_m = m0;
294
295 return 0;
296}
297
298/*
299 * Chain together segments+descriptors for a non-11n frame.
300 */
301static void
302ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf)
303{
304 struct ath_hal *ah = sc->sc_ah;
305 char *ds, *ds0;
306 int i, bp, dsp;
307 HAL_DMA_ADDR bufAddrList[4];
308 uint32_t segLenList[4];
309 int numTxMaps = 1;
310 int isFirstDesc = 1;
311 int qnum;
312
313 /*
314 * XXX There's txdma and txdma_mgmt; the descriptor
315 * sizes must match.
316 */
317 struct ath_descdma *dd = &sc->sc_txdma;
318
319 /*
320 * Fillin the remainder of the descriptor info.
321 */
322
323 /*
324 * For now the HAL doesn't implement halNumTxMaps for non-EDMA
325 * (ie it's 0.) So just work around it.
326 *
327 * XXX TODO: populate halNumTxMaps for each HAL chip and
328 * then undo this hack.
329 */
330 if (sc->sc_ah->ah_magic == 0x19741014)
331 numTxMaps = 4;
332
333 /*
334 * For EDMA and later chips ensure the TX map is fully populated
335 * before advancing to the next descriptor.
336 */
337 ds0 = ds = (char *) bf->bf_desc;
338 bp = dsp = 0;
339 bzero(bufAddrList, sizeof(bufAddrList));
340 bzero(segLenList, sizeof(segLenList));
341 for (i = 0; i < bf->bf_nseg; i++) {
342 bufAddrList[bp] = bf->bf_segs[i].ds_addr;
343 segLenList[bp] = bf->bf_segs[i].ds_len;
344 bp++;
345
346 /*
347 * Go to the next segment if this isn't the last segment
348 * and there's space in the current TX map.
349 */
350 if ((i != bf->bf_nseg - 1) && (bp < numTxMaps))
351 continue;
352
353 /*
354 * Last segment or we're out of buffer pointers.
355 */
356 bp = 0;
357
358 if (i == bf->bf_nseg - 1)
359 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0);
360 else
361 ath_hal_settxdesclink(ah, (struct ath_desc *) ds,
362 bf->bf_daddr + dd->dd_descsize * (dsp + 1));
363
364 /*
365 * XXX this assumes that bfs_txq is the actual destination
366 * hardware queue at this point. It may not have been assigned,
367 * it may actually be pointing to the multicast software
368 * TXQ id. These must be fixed!
369 */
370 qnum = bf->bf_state.bfs_txq->axq_qnum;
371
372 ath_hal_filltxdesc(ah, (struct ath_desc *) ds
373 , bufAddrList
374 , segLenList
375 , bf->bf_descid /* XXX desc id */
376 , qnum
377 , isFirstDesc /* first segment */
378 , i == bf->bf_nseg - 1 /* last segment */
379 , (struct ath_desc *) ds0 /* first descriptor */
380 );
381
382 /* Make sure the 11n aggregate fields are cleared */
383 if (ath_tx_is_11n(sc))
384 ath_hal_clr11n_aggr(sc->sc_ah, (struct ath_desc *) ds);
385
386 isFirstDesc = 0;
387#ifdef ATH_DEBUG
388 if (sc->sc_debug & ATH_DEBUG_XMIT)
389 ath_printtxbuf(sc, bf, qnum, 0, 0);
390#endif
391 bf->bf_lastds = (struct ath_desc *) ds;
392
393 /*
394 * Don't forget to skip to the next descriptor.
395 */
396 ds += sc->sc_tx_desclen;
397 dsp++;
398
399 /*
400 * .. and don't forget to blank these out!
401 */
402 bzero(bufAddrList, sizeof(bufAddrList));
403 bzero(segLenList, sizeof(segLenList));
404 }
405 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
406}
407
408/*
409 * Fill in the descriptor list for a aggregate subframe.
410 *
411 * The subframe is returned with the ds_link field in the last subframe
412 * pointing to 0.
413 */
414static void
415ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf)
416{
417 struct ath_hal *ah = sc->sc_ah;
418 struct ath_desc *ds, *ds0;
419 int i;
420 HAL_DMA_ADDR bufAddrList[4];
421 uint32_t segLenList[4];
422
423 /*
424 * XXX There's txdma and txdma_mgmt; the descriptor
425 * sizes must match.
426 */
427 struct ath_descdma *dd = &sc->sc_txdma;
428
429 ds0 = ds = bf->bf_desc;
430
431 /*
432 * There's no need to call ath_hal_setupfirsttxdesc here;
433 * That's only going to occur for the first frame in an aggregate.
434 */
435 for (i = 0; i < bf->bf_nseg; i++, ds++) {
436 bzero(bufAddrList, sizeof(bufAddrList));
437 bzero(segLenList, sizeof(segLenList));
438 if (i == bf->bf_nseg - 1)
439 ath_hal_settxdesclink(ah, ds, 0);
440 else
441 ath_hal_settxdesclink(ah, ds,
442 bf->bf_daddr + dd->dd_descsize * (i + 1));
443
444 bufAddrList[0] = bf->bf_segs[i].ds_addr;
445 segLenList[0] = bf->bf_segs[i].ds_len;
446
447 /*
448 * This performs the setup for an aggregate frame.
449 * This includes enabling the aggregate flags if needed.
450 */
451 ath_hal_chaintxdesc(ah, ds,
452 bufAddrList,
453 segLenList,
454 bf->bf_state.bfs_pktlen,
455 bf->bf_state.bfs_hdrlen,
456 HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */
457 bf->bf_state.bfs_keyix,
458 0, /* cipher, calculated from keyix */
459 bf->bf_state.bfs_ndelim,
460 i == 0, /* first segment */
461 i == bf->bf_nseg - 1, /* last segment */
462 bf->bf_next == NULL /* last sub-frame in aggr */
463 );
464
465 DPRINTF(sc, ATH_DEBUG_XMIT,
466 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
467 __func__, i, ds->ds_link, ds->ds_data,
468 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
469 bf->bf_lastds = ds;
470 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
471 BUS_DMASYNC_PREWRITE);
472 }
473}
474
475/*
476 * Set the rate control fields in the given descriptor based on
477 * the bf_state fields and node state.
478 *
479 * The bfs fields should already be set with the relevant rate
480 * control information, including whether MRR is to be enabled.
481 *
482 * Since the FreeBSD HAL currently sets up the first TX rate
483 * in ath_hal_setuptxdesc(), this will setup the MRR
484 * conditionally for the pre-11n chips, and call ath_buf_set_rate
485 * unconditionally for 11n chips. These require the 11n rate
486 * scenario to be set if MCS rates are enabled, so it's easier
487 * to just always call it. The caller can then only set rates 2, 3
488 * and 4 if multi-rate retry is needed.
489 */
490static void
491ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
492 struct ath_buf *bf)
493{
494 struct ath_rc_series *rc = bf->bf_state.bfs_rc;
495
496 /* If mrr is disabled, blank tries 1, 2, 3 */
497 if (! bf->bf_state.bfs_ismrr)
498 rc[1].tries = rc[2].tries = rc[3].tries = 0;
499
500 /*
501 * Always call - that way a retried descriptor will
502 * have the MRR fields overwritten.
503 *
504 * XXX TODO: see if this is really needed - setting up
505 * the first descriptor should set the MRR fields to 0
506 * for us anyway.
507 */
508 if (ath_tx_is_11n(sc)) {
509 ath_buf_set_rate(sc, ni, bf);
510 } else {
511 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc
512 , rc[1].ratecode, rc[1].tries
513 , rc[2].ratecode, rc[2].tries
514 , rc[3].ratecode, rc[3].tries
515 );
516 }
517}
518
519/*
520 * Setup segments+descriptors for an 11n aggregate.
521 * bf_first is the first buffer in the aggregate.
522 * The descriptor list must already been linked together using
523 * bf->bf_next.
524 */
525static void
526ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first)
527{
528 struct ath_buf *bf, *bf_prev = NULL;
529
530 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n",
531 __func__, bf_first->bf_state.bfs_nframes,
532 bf_first->bf_state.bfs_al);
533
534 /*
535 * Setup all descriptors of all subframes.
536 */
537 bf = bf_first;
538 while (bf != NULL) {
539 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
540 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n",
541 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen,
542 SEQNO(bf->bf_state.bfs_seqno));
543
544 /* Sub-frame setup */
545 ath_tx_chaindesclist_subframe(sc, bf);
546
547 /*
548 * Link the last descriptor of the previous frame
549 * to the beginning descriptor of this frame.
550 */
551 if (bf_prev != NULL)
552 ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds,
553 bf->bf_daddr);
554
555 /* Save a copy so we can link the next descriptor in */
556 bf_prev = bf;
557 bf = bf->bf_next;
558 }
559
560 /*
561 * Setup first descriptor of first frame.
562 * chaintxdesc() overwrites the descriptor entries;
563 * setupfirsttxdesc() merges in things.
564 * Otherwise various fields aren't set correctly (eg flags).
565 */
566 ath_hal_setupfirsttxdesc(sc->sc_ah,
567 bf_first->bf_desc,
568 bf_first->bf_state.bfs_al,
569 bf_first->bf_state.bfs_txflags | HAL_TXDESC_INTREQ,
570 bf_first->bf_state.bfs_txpower,
571 bf_first->bf_state.bfs_txrate0,
572 bf_first->bf_state.bfs_try0,
573 bf_first->bf_state.bfs_txantenna,
574 bf_first->bf_state.bfs_ctsrate,
575 bf_first->bf_state.bfs_ctsduration);
576
577 /*
578 * Set the first descriptor bf_lastds field to point to
579 * the last descriptor in the last subframe, that's where
580 * the status update will occur.
581 */
582 bf_first->bf_lastds = bf_prev->bf_lastds;
583
584 /*
585 * And bf_last in the first descriptor points to the end of
586 * the aggregate list.
587 */
588 bf_first->bf_last = bf_prev;
589
590 /*
591 * setup first desc with rate and aggr info
592 */
593 ath_tx_set_ratectrl(sc, bf_first->bf_node, bf_first);
594
595 /*
596 * Setup the last descriptor in the list.
597 *
598 * bf_first->bf_lastds already points to it; the rate
599 * control information needs to be squirreled away here
600 * as well ans clearing the moreaggr/paddelim fields.
601 */
602 ath_hal_setuplasttxdesc(sc->sc_ah, bf_first->bf_lastds,
603 bf_first->bf_desc);
604
605 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__);
606}
607
608/*
609 * Hand-off a frame to the multicast TX queue.
610 *
611 * This is a software TXQ which will be appended to the CAB queue
612 * during the beacon setup code.
613 *
614 * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID
615 * as part of the TX descriptor, bf_state.bfs_txq must be updated
616 * with the actual hardware txq, or all of this will fall apart.
617 *
618 * XXX It may not be a bad idea to just stuff the QCU ID into bf_state
619 * and retire bfs_txq; then make sure the CABQ QCU ID is populated
620 * correctly.
621 */
622static void
623ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
624 struct ath_buf *bf)
625{
626 ATH_TXQ_LOCK_ASSERT(txq);
627 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
628 ("%s: busy status 0x%x", __func__, bf->bf_flags));
629 if (txq->axq_link != NULL) {
630 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s);
631 struct ieee80211_frame *wh;
632
633 /* mark previous frame */
634 wh = mtod(last->bf_m, struct ieee80211_frame *);
635 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
636 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
637 BUS_DMASYNC_PREWRITE);
638
639 /* link descriptor */
640 *txq->axq_link = bf->bf_daddr;
641 }
642 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
643 ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link);
644}
645
646/*
647 * Hand-off packet to a hardware queue.
648 */
649static void
650ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
651 struct ath_buf *bf)
652{
653 struct ath_hal *ah = sc->sc_ah;
654
655 /*
656 * Insert the frame on the outbound list and pass it on
657 * to the hardware. Multicast frames buffered for power
658 * save stations and transmit from the CAB queue are stored
659 * on a s/w only queue and loaded on to the CAB queue in
660 * the SWBA handler since frames only go out on DTIM and
661 * to avoid possible races.
662 */
663 ATH_TXQ_LOCK_ASSERT(txq);
664 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
665 ("%s: busy status 0x%x", __func__, bf->bf_flags));
666 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ,
667 ("ath_tx_handoff_hw called for mcast queue"));
668
669#if 0
670 /*
671 * This causes a LOR. Find out where the PCU lock is being
672 * held whilst the TXQ lock is grabbed - that shouldn't
673 * be occuring.
674 */
675 ATH_PCU_LOCK(sc);
676 if (sc->sc_inreset_cnt) {
677 ATH_PCU_UNLOCK(sc);
678 DPRINTF(sc, ATH_DEBUG_RESET,
679 "%s: called with sc_in_reset != 0\n",
680 __func__);
681 DPRINTF(sc, ATH_DEBUG_XMIT,
682 "%s: queued: TXDP[%u] = %p (%p) depth %d\n",
683 __func__, txq->axq_qnum,
684 (caddr_t)bf->bf_daddr, bf->bf_desc,
685 txq->axq_depth);
686 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
687 if (bf->bf_state.bfs_aggr)
688 txq->axq_aggr_depth++;
689 /*
690 * There's no need to update axq_link; the hardware
691 * is in reset and once the reset is complete, any
692 * non-empty queues will simply have DMA restarted.
693 */
694 return;
695 }
696 ATH_PCU_UNLOCK(sc);
697#endif
698
699 /* For now, so not to generate whitespace diffs */
700 if (1) {
701#ifdef IEEE80211_SUPPORT_TDMA
702 int qbusy;
703
704 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
705 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
706 if (txq->axq_link == NULL) {
707 /*
708 * Be careful writing the address to TXDP. If
709 * the tx q is enabled then this write will be
710 * ignored. Normally this is not an issue but
711 * when tdma is in use and the q is beacon gated
712 * this race can occur. If the q is busy then
713 * defer the work to later--either when another
714 * packet comes along or when we prepare a beacon
715 * frame at SWBA.
716 */
717 if (!qbusy) {
718 ath_hal_puttxbuf(ah, txq->axq_qnum,
719 bf->bf_daddr);
720 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
721 DPRINTF(sc, ATH_DEBUG_XMIT,
722 "%s: TXDP[%u] = %p (%p) depth %d\n",
723 __func__, txq->axq_qnum,
724 (caddr_t)bf->bf_daddr, bf->bf_desc,
725 txq->axq_depth);
726 } else {
727 txq->axq_flags |= ATH_TXQ_PUTPENDING;
728 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
729 "%s: Q%u busy, defer enable\n", __func__,
730 txq->axq_qnum);
731 }
732 } else {
733 *txq->axq_link = bf->bf_daddr;
734 DPRINTF(sc, ATH_DEBUG_XMIT,
735 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
736 txq->axq_qnum, txq->axq_link,
737 (caddr_t)bf->bf_daddr, bf->bf_desc,
738 txq->axq_depth);
739 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
740 /*
741 * The q was busy when we previously tried
742 * to write the address of the first buffer
743 * in the chain. Since it's not busy now
744 * handle this chore. We are certain the
745 * buffer at the front is the right one since
746 * axq_link is NULL only when the buffer list
747 * is/was empty.
748 */
749 ath_hal_puttxbuf(ah, txq->axq_qnum,
750 TAILQ_FIRST(&txq->axq_q)->bf_daddr);
751 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
752 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
753 "%s: Q%u restarted\n", __func__,
754 txq->axq_qnum);
755 }
756 }
757#else
758 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
759 if (txq->axq_link == NULL) {
760 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
761 DPRINTF(sc, ATH_DEBUG_XMIT,
762 "%s: TXDP[%u] = %p (%p) depth %d\n",
763 __func__, txq->axq_qnum,
764 (caddr_t)bf->bf_daddr, bf->bf_desc,
765 txq->axq_depth);
766 } else {
767 *txq->axq_link = bf->bf_daddr;
768 DPRINTF(sc, ATH_DEBUG_XMIT,
769 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
770 txq->axq_qnum, txq->axq_link,
771 (caddr_t)bf->bf_daddr, bf->bf_desc,
772 txq->axq_depth);
773 }
774#endif /* IEEE80211_SUPPORT_TDMA */
775 if (bf->bf_state.bfs_aggr)
776 txq->axq_aggr_depth++;
777 ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link);
778 ath_hal_txstart(ah, txq->axq_qnum);
779 }
780}
781
782/*
783 * Restart TX DMA for the given TXQ.
784 *
785 * This must be called whether the queue is empty or not.
786 */
787static void
788ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
789{
790 struct ath_hal *ah = sc->sc_ah;
791 struct ath_buf *bf, *bf_last;
792
793 ATH_TXQ_LOCK_ASSERT(txq);
794
795 /* This is always going to be cleared, empty or not */
796 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
797
798 /* XXX make this ATH_TXQ_FIRST */
799 bf = TAILQ_FIRST(&txq->axq_q);
800 bf_last = ATH_TXQ_LAST(txq, axq_q_s);
801
802 if (bf == NULL)
803 return;
804
805 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
806 ath_hal_gettxdesclinkptr(ah, bf_last->bf_lastds, &txq->axq_link);
807 ath_hal_txstart(ah, txq->axq_qnum);
808}
809
810/*
811 * Hand off a packet to the hardware (or mcast queue.)
812 *
813 * The relevant hardware txq should be locked.
814 */
815static void
816ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
817 struct ath_buf *bf)
818{
819 ATH_TXQ_LOCK_ASSERT(txq);
820
821 if (txq->axq_qnum == ATH_TXQ_SWQ)
822 ath_tx_handoff_mcast(sc, txq, bf);
823 else
824 ath_tx_handoff_hw(sc, txq, bf);
825}
826
827static int
828ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni,
829 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen,
830 int *keyix)
831{
832 DPRINTF(sc, ATH_DEBUG_XMIT,
833 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n",
834 __func__,
835 *hdrlen,
836 *pktlen,
837 isfrag,
838 iswep,
839 m0);
840
841 if (iswep) {
842 const struct ieee80211_cipher *cip;
843 struct ieee80211_key *k;
844
845 /*
846 * Construct the 802.11 header+trailer for an encrypted
847 * frame. The only reason this can fail is because of an
848 * unknown or unsupported cipher/key type.
849 */
850 k = ieee80211_crypto_encap(ni, m0);
851 if (k == NULL) {
852 /*
853 * This can happen when the key is yanked after the
854 * frame was queued. Just discard the frame; the
855 * 802.11 layer counts failures and provides
856 * debugging/diagnostics.
857 */
858 return (0);
859 }
860 /*
861 * Adjust the packet + header lengths for the crypto
862 * additions and calculate the h/w key index. When
863 * a s/w mic is done the frame will have had any mic
864 * added to it prior to entry so m0->m_pkthdr.len will
865 * account for it. Otherwise we need to add it to the
866 * packet length.
867 */
868 cip = k->wk_cipher;
869 (*hdrlen) += cip->ic_header;
870 (*pktlen) += cip->ic_header + cip->ic_trailer;
871 /* NB: frags always have any TKIP MIC done in s/w */
872 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
873 (*pktlen) += cip->ic_miclen;
874 (*keyix) = k->wk_keyix;
875 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
876 /*
877 * Use station key cache slot, if assigned.
878 */
879 (*keyix) = ni->ni_ucastkey.wk_keyix;
880 if ((*keyix) == IEEE80211_KEYIX_NONE)
881 (*keyix) = HAL_TXKEYIX_INVALID;
882 } else
883 (*keyix) = HAL_TXKEYIX_INVALID;
884
885 return (1);
886}
887
888/*
889 * Calculate whether interoperability protection is required for
890 * this frame.
891 *
892 * This requires the rate control information be filled in,
893 * as the protection requirement depends upon the current
894 * operating mode / PHY.
895 */
896static void
897ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf)
898{
899 struct ieee80211_frame *wh;
900 uint8_t rix;
901 uint16_t flags;
902 int shortPreamble;
903 const HAL_RATE_TABLE *rt = sc->sc_currates;
904 struct ifnet *ifp = sc->sc_ifp;
905 struct ieee80211com *ic = ifp->if_l2com;
906
907 flags = bf->bf_state.bfs_txflags;
908 rix = bf->bf_state.bfs_rc[0].rix;
909 shortPreamble = bf->bf_state.bfs_shpream;
910 wh = mtod(bf->bf_m, struct ieee80211_frame *);
911
912 /*
913 * If 802.11g protection is enabled, determine whether
914 * to use RTS/CTS or just CTS. Note that this is only
915 * done for OFDM unicast frames.
916 */
917 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
918 rt->info[rix].phy == IEEE80211_T_OFDM &&
919 (flags & HAL_TXDESC_NOACK) == 0) {
920 bf->bf_state.bfs_doprot = 1;
921 /* XXX fragments must use CCK rates w/ protection */
922 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
923 flags |= HAL_TXDESC_RTSENA;
924 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
925 flags |= HAL_TXDESC_CTSENA;
926 }
927 /*
928 * For frags it would be desirable to use the
929 * highest CCK rate for RTS/CTS. But stations
930 * farther away may detect it at a lower CCK rate
931 * so use the configured protection rate instead
932 * (for now).
933 */
934 sc->sc_stats.ast_tx_protect++;
935 }
936
937 /*
938 * If 11n protection is enabled and it's a HT frame,
939 * enable RTS.
940 *
941 * XXX ic_htprotmode or ic_curhtprotmode?
942 * XXX should it_htprotmode only matter if ic_curhtprotmode
943 * XXX indicates it's not a HT pure environment?
944 */
945 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) &&
946 rt->info[rix].phy == IEEE80211_T_HT &&
947 (flags & HAL_TXDESC_NOACK) == 0) {
948 flags |= HAL_TXDESC_RTSENA;
949 sc->sc_stats.ast_tx_htprotect++;
950 }
951 bf->bf_state.bfs_txflags = flags;
952}
953
954/*
955 * Update the frame duration given the currently selected rate.
956 *
957 * This also updates the frame duration value, so it will require
958 * a DMA flush.
959 */
960static void
961ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf)
962{
963 struct ieee80211_frame *wh;
964 uint8_t rix;
965 uint16_t flags;
966 int shortPreamble;
967 struct ath_hal *ah = sc->sc_ah;
968 const HAL_RATE_TABLE *rt = sc->sc_currates;
969 int isfrag = bf->bf_m->m_flags & M_FRAG;
970
971 flags = bf->bf_state.bfs_txflags;
972 rix = bf->bf_state.bfs_rc[0].rix;
973 shortPreamble = bf->bf_state.bfs_shpream;
974 wh = mtod(bf->bf_m, struct ieee80211_frame *);
975
976 /*
977 * Calculate duration. This logically belongs in the 802.11
978 * layer but it lacks sufficient information to calculate it.
979 */
980 if ((flags & HAL_TXDESC_NOACK) == 0 &&
981 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
982 u_int16_t dur;
983 if (shortPreamble)
984 dur = rt->info[rix].spAckDuration;
985 else
986 dur = rt->info[rix].lpAckDuration;
987 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
988 dur += dur; /* additional SIFS+ACK */
989 KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment"));
990 /*
991 * Include the size of next fragment so NAV is
992 * updated properly. The last fragment uses only
993 * the ACK duration
994 */
995 dur += ath_hal_computetxtime(ah, rt,
996 bf->bf_m->m_nextpkt->m_pkthdr.len,
997 rix, shortPreamble);
998 }
999 if (isfrag) {
1000 /*
1001 * Force hardware to use computed duration for next
1002 * fragment by disabling multi-rate retry which updates
1003 * duration based on the multi-rate duration table.
1004 */
1005 bf->bf_state.bfs_ismrr = 0;
1006 bf->bf_state.bfs_try0 = ATH_TXMGTTRY;
1007 /* XXX update bfs_rc[0].try? */
1008 }
1009
1010 /* Update the duration field itself */
1011 *(u_int16_t *)wh->i_dur = htole16(dur);
1012 }
1013}
1014
1015static uint8_t
1016ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
1017 int cix, int shortPreamble)
1018{
1019 uint8_t ctsrate;
1020
1021 /*
1022 * CTS transmit rate is derived from the transmit rate
1023 * by looking in the h/w rate table. We must also factor
1024 * in whether or not a short preamble is to be used.
1025 */
1026 /* NB: cix is set above where RTS/CTS is enabled */
1027 KASSERT(cix != 0xff, ("cix not setup"));
1028 ctsrate = rt->info[cix].rateCode;
1029
1030 /* XXX this should only matter for legacy rates */
1031 if (shortPreamble)
1032 ctsrate |= rt->info[cix].shortPreamble;
1033
1034 return (ctsrate);
1035}
1036
1037/*
1038 * Calculate the RTS/CTS duration for legacy frames.
1039 */
1040static int
1041ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix,
1042 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt,
1043 int flags)
1044{
1045 int ctsduration = 0;
1046
1047 /* This mustn't be called for HT modes */
1048 if (rt->info[cix].phy == IEEE80211_T_HT) {
1049 printf("%s: HT rate where it shouldn't be (0x%x)\n",
1050 __func__, rt->info[cix].rateCode);
1051 return (-1);
1052 }
1053
1054 /*
1055 * Compute the transmit duration based on the frame
1056 * size and the size of an ACK frame. We call into the
1057 * HAL to do the computation since it depends on the
1058 * characteristics of the actual PHY being used.
1059 *
1060 * NB: CTS is assumed the same size as an ACK so we can
1061 * use the precalculated ACK durations.
1062 */
1063 if (shortPreamble) {
1064 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1065 ctsduration += rt->info[cix].spAckDuration;
1066 ctsduration += ath_hal_computetxtime(ah,
1067 rt, pktlen, rix, AH_TRUE);
1068 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1069 ctsduration += rt->info[rix].spAckDuration;
1070 } else {
1071 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1072 ctsduration += rt->info[cix].lpAckDuration;
1073 ctsduration += ath_hal_computetxtime(ah,
1074 rt, pktlen, rix, AH_FALSE);
1075 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1076 ctsduration += rt->info[rix].lpAckDuration;
1077 }
1078
1079 return (ctsduration);
1080}
1081
1082/*
1083 * Update the given ath_buf with updated rts/cts setup and duration
1084 * values.
1085 *
1086 * To support rate lookups for each software retry, the rts/cts rate
1087 * and cts duration must be re-calculated.
1088 *
1089 * This function assumes the RTS/CTS flags have been set as needed;
1090 * mrr has been disabled; and the rate control lookup has been done.
1091 *
1092 * XXX TODO: MRR need only be disabled for the pre-11n NICs.
1093 * XXX The 11n NICs support per-rate RTS/CTS configuration.
1094 */
1095static void
1096ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf)
1097{
1098 uint16_t ctsduration = 0;
1099 uint8_t ctsrate = 0;
1100 uint8_t rix = bf->bf_state.bfs_rc[0].rix;
1101 uint8_t cix = 0;
1102 const HAL_RATE_TABLE *rt = sc->sc_currates;
1103
1104 /*
1105 * No RTS/CTS enabled? Don't bother.
1106 */
1107 if ((bf->bf_state.bfs_txflags &
1108 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) {
1109 /* XXX is this really needed? */
1110 bf->bf_state.bfs_ctsrate = 0;
1111 bf->bf_state.bfs_ctsduration = 0;
1112 return;
1113 }
1114
1115 /*
1116 * If protection is enabled, use the protection rix control
1117 * rate. Otherwise use the rate0 control rate.
1118 */
1119 if (bf->bf_state.bfs_doprot)
1120 rix = sc->sc_protrix;
1121 else
1122 rix = bf->bf_state.bfs_rc[0].rix;
1123
1124 /*
1125 * If the raw path has hard-coded ctsrate0 to something,
1126 * use it.
1127 */
1128 if (bf->bf_state.bfs_ctsrate0 != 0)
1129 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0);
1130 else
1131 /* Control rate from above */
1132 cix = rt->info[rix].controlRate;
1133
1134 /* Calculate the rtscts rate for the given cix */
1135 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix,
1136 bf->bf_state.bfs_shpream);
1137
1138 /* The 11n chipsets do ctsduration calculations for you */
1139 if (! ath_tx_is_11n(sc))
1140 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix,
1141 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen,
1142 rt, bf->bf_state.bfs_txflags);
1143
1144 /* Squirrel away in ath_buf */
1145 bf->bf_state.bfs_ctsrate = ctsrate;
1146 bf->bf_state.bfs_ctsduration = ctsduration;
1147
1148 /*
1149 * Must disable multi-rate retry when using RTS/CTS.
1150 */
1151 if (!sc->sc_mrrprot) {
1152 bf->bf_state.bfs_ismrr = 0;
1153 bf->bf_state.bfs_try0 =
1154 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */
1155 }
1156}
1157
1158/*
1159 * Setup the descriptor chain for a normal or fast-frame
1160 * frame.
1161 *
1162 * XXX TODO: extend to include the destination hardware QCU ID.
1163 * Make sure that is correct. Make sure that when being added
1164 * to the mcastq, the CABQ QCUID is set or things will get a bit
1165 * odd.
1166 */
1167static void
1168ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf)
1169{
1170 struct ath_desc *ds = bf->bf_desc;
1171 struct ath_hal *ah = sc->sc_ah;
1172
1173 ath_hal_setuptxdesc(ah, ds
1174 , bf->bf_state.bfs_pktlen /* packet length */
1175 , bf->bf_state.bfs_hdrlen /* header length */
1176 , bf->bf_state.bfs_atype /* Atheros packet type */
1177 , bf->bf_state.bfs_txpower /* txpower */
1178 , bf->bf_state.bfs_txrate0
1179 , bf->bf_state.bfs_try0 /* series 0 rate/tries */
1180 , bf->bf_state.bfs_keyix /* key cache index */
1181 , bf->bf_state.bfs_txantenna /* antenna mode */
1182 , bf->bf_state.bfs_txflags /* flags */
1183 , bf->bf_state.bfs_ctsrate /* rts/cts rate */
1184 , bf->bf_state.bfs_ctsduration /* rts/cts duration */
1185 );
1186
1187 /*
1188 * This will be overriden when the descriptor chain is written.
1189 */
1190 bf->bf_lastds = ds;
1191 bf->bf_last = bf;
1192
1193 /* Set rate control and descriptor chain for this frame */
1194 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
1195 ath_tx_chaindesclist(sc, bf);
1196}
1197
1198/*
1199 * Do a rate lookup.
1200 *
1201 * This performs a rate lookup for the given ath_buf only if it's required.
1202 * Non-data frames and raw frames don't require it.
1203 *
1204 * This populates the primary and MRR entries; MRR values are
1205 * then disabled later on if something requires it (eg RTS/CTS on
1206 * pre-11n chipsets.
1207 *
1208 * This needs to be done before the RTS/CTS fields are calculated
1209 * as they may depend upon the rate chosen.
1210 */
1211static void
1212ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf)
1213{
1214 uint8_t rate, rix;
1215 int try0;
1216
1217 if (! bf->bf_state.bfs_doratelookup)
1218 return;
1219
1220 /* Get rid of any previous state */
1221 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1222
1223 ATH_NODE_LOCK(ATH_NODE(bf->bf_node));
1224 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream,
1225 bf->bf_state.bfs_pktlen, &rix, &try0, &rate);
1226
1227 /* In case MRR is disabled, make sure rc[0] is setup correctly */
1228 bf->bf_state.bfs_rc[0].rix = rix;
1229 bf->bf_state.bfs_rc[0].ratecode = rate;
1230 bf->bf_state.bfs_rc[0].tries = try0;
1231
1232 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY)
1233 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix,
1234 bf->bf_state.bfs_rc);
1235 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node));
1236
1237 sc->sc_txrix = rix; /* for LED blinking */
1238 sc->sc_lastdatarix = rix; /* for fast frames */
1239 bf->bf_state.bfs_try0 = try0;
1240 bf->bf_state.bfs_txrate0 = rate;
1241}
1242
1243/*
1244 * Transmit the given frame to the hardware.
1245 *
1246 * The frame must already be setup; rate control must already have
1247 * been done.
1248 *
1249 * XXX since the TXQ lock is being held here (and I dislike holding
1250 * it for this long when not doing software aggregation), later on
1251 * break this function into "setup_normal" and "xmit_normal". The
1252 * lock only needs to be held for the ath_tx_handoff call.
1253 */
1254static void
1255ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq,
1256 struct ath_buf *bf)
1257{
1258
1259 ATH_TXQ_LOCK_ASSERT(txq);
1260
1261 /* Setup the descriptor before handoff */
1262 ath_tx_do_ratelookup(sc, bf);
1263 ath_tx_calc_duration(sc, bf);
1264 ath_tx_calc_protection(sc, bf);
1265 ath_tx_set_rtscts(sc, bf);
1266 ath_tx_rate_fill_rcflags(sc, bf);
1267 ath_tx_setds(sc, bf);
1268
1269 /* Hand off to hardware */
1270 ath_tx_handoff(sc, txq, bf);
1271}
1272
1273
1274
1275static int
1276ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
1277 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq)
1278{
1279 struct ieee80211vap *vap = ni->ni_vap;
1280 struct ath_hal *ah = sc->sc_ah;
1281 struct ifnet *ifp = sc->sc_ifp;
1282 struct ieee80211com *ic = ifp->if_l2com;
1283 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
1284 int error, iswep, ismcast, isfrag, ismrr;
1285 int keyix, hdrlen, pktlen, try0 = 0;
1286 u_int8_t rix = 0, txrate = 0;
1287 struct ath_desc *ds;
1288 struct ieee80211_frame *wh;
1289 u_int subtype, flags;
1290 HAL_PKT_TYPE atype;
1291 const HAL_RATE_TABLE *rt;
1292 HAL_BOOL shortPreamble;
1293 struct ath_node *an;
1294 u_int pri;
1295
1296 /*
1297 * To ensure that both sequence numbers and the CCMP PN handling
1298 * is "correct", make sure that the relevant TID queue is locked.
1299 * Otherwise the CCMP PN and seqno may appear out of order, causing
1300 * re-ordered frames to have out of order CCMP PN's, resulting
1301 * in many, many frame drops.
1302 */
1303 ATH_TXQ_LOCK_ASSERT(txq);
1304
1305 wh = mtod(m0, struct ieee80211_frame *);
1306 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1307 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1308 isfrag = m0->m_flags & M_FRAG;
1309 hdrlen = ieee80211_anyhdrsize(wh);
1310 /*
1311 * Packet length must not include any
1312 * pad bytes; deduct them here.
1313 */
1314 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
1315
1316 /* Handle encryption twiddling if needed */
1317 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen,
1318 &pktlen, &keyix)) {
1319 ath_freetx(m0);
1320 return EIO;
1321 }
1322
1323 /* packet header may have moved, reset our local pointer */
1324 wh = mtod(m0, struct ieee80211_frame *);
1325
1326 pktlen += IEEE80211_CRC_LEN;
1327
1328 /*
1329 * Load the DMA map so any coalescing is done. This
1330 * also calculates the number of descriptors we need.
1331 */
1332 error = ath_tx_dmasetup(sc, bf, m0);
1333 if (error != 0)
1334 return error;
1335 bf->bf_node = ni; /* NB: held reference */
1336 m0 = bf->bf_m; /* NB: may have changed */
1337 wh = mtod(m0, struct ieee80211_frame *);
1338
1339 /* setup descriptors */
1340 ds = bf->bf_desc;
1341 rt = sc->sc_currates;
1342 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1343
1344 /*
1345 * NB: the 802.11 layer marks whether or not we should
1346 * use short preamble based on the current mode and
1347 * negotiated parameters.
1348 */
1349 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1350 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
1351 shortPreamble = AH_TRUE;
1352 sc->sc_stats.ast_tx_shortpre++;
1353 } else {
1354 shortPreamble = AH_FALSE;
1355 }
1356
1357 an = ATH_NODE(ni);
1358 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1359 ismrr = 0; /* default no multi-rate retry*/
1360 pri = M_WME_GETAC(m0); /* honor classification */
1361 /* XXX use txparams instead of fixed values */
1362 /*
1363 * Calculate Atheros packet type from IEEE80211 packet header,
1364 * setup for rate calculations, and select h/w transmit queue.
1365 */
1366 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1367 case IEEE80211_FC0_TYPE_MGT:
1368 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1369 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
1370 atype = HAL_PKT_TYPE_BEACON;
1371 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1372 atype = HAL_PKT_TYPE_PROBE_RESP;
1373 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1374 atype = HAL_PKT_TYPE_ATIM;
1375 else
1376 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
1377 rix = an->an_mgmtrix;
1378 txrate = rt->info[rix].rateCode;
1379 if (shortPreamble)
1380 txrate |= rt->info[rix].shortPreamble;
1381 try0 = ATH_TXMGTTRY;
1382 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1383 break;
1384 case IEEE80211_FC0_TYPE_CTL:
1385 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
1386 rix = an->an_mgmtrix;
1387 txrate = rt->info[rix].rateCode;
1388 if (shortPreamble)
1389 txrate |= rt->info[rix].shortPreamble;
1390 try0 = ATH_TXMGTTRY;
1391 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1392 break;
1393 case IEEE80211_FC0_TYPE_DATA:
1394 atype = HAL_PKT_TYPE_NORMAL; /* default */
1395 /*
1396 * Data frames: multicast frames go out at a fixed rate,
1397 * EAPOL frames use the mgmt frame rate; otherwise consult
1398 * the rate control module for the rate to use.
1399 */
1400 if (ismcast) {
1401 rix = an->an_mcastrix;
1402 txrate = rt->info[rix].rateCode;
1403 if (shortPreamble)
1404 txrate |= rt->info[rix].shortPreamble;
1405 try0 = 1;
1406 } else if (m0->m_flags & M_EAPOL) {
1407 /* XXX? maybe always use long preamble? */
1408 rix = an->an_mgmtrix;
1409 txrate = rt->info[rix].rateCode;
1410 if (shortPreamble)
1411 txrate |= rt->info[rix].shortPreamble;
1412 try0 = ATH_TXMAXTRY; /* XXX?too many? */
1413 } else {
1414 /*
1415 * Do rate lookup on each TX, rather than using
1416 * the hard-coded TX information decided here.
1417 */
1418 ismrr = 1;
1419 bf->bf_state.bfs_doratelookup = 1;
1420 }
1421 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
1422 flags |= HAL_TXDESC_NOACK;
1423 break;
1424 default:
1425 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
1426 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
1427 /* XXX statistic */
1428 ath_freetx(m0);
1429 return EIO;
1430 }
1431
1432 /*
1433 * There are two known scenarios where the frame AC doesn't match
1434 * what the destination TXQ is.
1435 *
1436 * + non-QoS frames (eg management?) that the net80211 stack has
1437 * assigned a higher AC to, but since it's a non-QoS TID, it's
1438 * being thrown into TID 16. TID 16 gets the AC_BE queue.
1439 * It's quite possible that management frames should just be
1440 * direct dispatched to hardware rather than go via the software
1441 * queue; that should be investigated in the future. There are
1442 * some specific scenarios where this doesn't make sense, mostly
1443 * surrounding ADDBA request/response - hence why that is special
1444 * cased.
1445 *
1446 * + Multicast frames going into the VAP mcast queue. That shows up
1447 * as "TXQ 11".
1448 *
1449 * This driver should eventually support separate TID and TXQ locking,
1450 * allowing for arbitrary AC frames to appear on arbitrary software
1451 * queues, being queued to the "correct" hardware queue when needed.
1452 */
1453#if 0
1454 if (txq != sc->sc_ac2q[pri]) {
1455 device_printf(sc->sc_dev,
1456 "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n",
1457 __func__,
1458 txq,
1459 txq->axq_qnum,
1460 pri,
1461 sc->sc_ac2q[pri],
1462 sc->sc_ac2q[pri]->axq_qnum);
1463 }
1464#endif
1465
1466 /*
1467 * Calculate miscellaneous flags.
1468 */
1469 if (ismcast) {
1470 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
1471 } else if (pktlen > vap->iv_rtsthreshold &&
1472 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
1473 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
1474 sc->sc_stats.ast_tx_rts++;
1475 }
1476 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
1477 sc->sc_stats.ast_tx_noack++;
1478#ifdef IEEE80211_SUPPORT_TDMA
1479 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
1480 DPRINTF(sc, ATH_DEBUG_TDMA,
1481 "%s: discard frame, ACK required w/ TDMA\n", __func__);
1482 sc->sc_stats.ast_tdma_ack++;
1483 ath_freetx(m0);
1484 return EIO;
1485 }
1486#endif
1487
1488 /*
1489 * Determine if a tx interrupt should be generated for
1490 * this descriptor. We take a tx interrupt to reap
1491 * descriptors when the h/w hits an EOL condition or
1492 * when the descriptor is specifically marked to generate
1493 * an interrupt. We periodically mark descriptors in this
1494 * way to insure timely replenishing of the supply needed
1495 * for sending frames. Defering interrupts reduces system
1496 * load and potentially allows more concurrent work to be
1497 * done but if done to aggressively can cause senders to
1498 * backup.
1499 *
1500 * NB: use >= to deal with sc_txintrperiod changing
1501 * dynamically through sysctl.
1502 */
1503 if (flags & HAL_TXDESC_INTREQ) {
1504 txq->axq_intrcnt = 0;
1505 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
1506 flags |= HAL_TXDESC_INTREQ;
1507 txq->axq_intrcnt = 0;
1508 }
1509
1510 /* This point forward is actual TX bits */
1511
1512 /*
1513 * At this point we are committed to sending the frame
1514 * and we don't need to look at m_nextpkt; clear it in
1515 * case this frame is part of frag chain.
1516 */
1517 m0->m_nextpkt = NULL;
1518
1519 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1520 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
1521 sc->sc_hwmap[rix].ieeerate, -1);
1522
1523 if (ieee80211_radiotap_active_vap(vap)) {
1524 u_int64_t tsf = ath_hal_gettsf64(ah);
1525
1526 sc->sc_tx_th.wt_tsf = htole64(tsf);
1527 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1528 if (iswep)
1529 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1530 if (isfrag)
1531 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1532 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1533 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1534 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1535
1536 ieee80211_radiotap_tx(vap, m0);
1537 }
1538
1539 /* Blank the legacy rate array */
1540 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1541
1542 /*
1543 * ath_buf_set_rate needs at least one rate/try to setup
1544 * the rate scenario.
1545 */
1546 bf->bf_state.bfs_rc[0].rix = rix;
1547 bf->bf_state.bfs_rc[0].tries = try0;
1548 bf->bf_state.bfs_rc[0].ratecode = txrate;
1549
1550 /* Store the decided rate index values away */
1551 bf->bf_state.bfs_pktlen = pktlen;
1552 bf->bf_state.bfs_hdrlen = hdrlen;
1553 bf->bf_state.bfs_atype = atype;
1554 bf->bf_state.bfs_txpower = ni->ni_txpower;
1555 bf->bf_state.bfs_txrate0 = txrate;
1556 bf->bf_state.bfs_try0 = try0;
1557 bf->bf_state.bfs_keyix = keyix;
1558 bf->bf_state.bfs_txantenna = sc->sc_txantenna;
1559 bf->bf_state.bfs_txflags = flags;
1560 bf->bf_state.bfs_shpream = shortPreamble;
1561
1562 /* XXX this should be done in ath_tx_setrate() */
1563 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */
1564 bf->bf_state.bfs_ctsrate = 0; /* calculated later */
1565 bf->bf_state.bfs_ctsduration = 0;
1566 bf->bf_state.bfs_ismrr = ismrr;
1567
1568 return 0;
1569}
1570
1571/*
1572 * Direct-dispatch the current frame to the hardware.
1573 *
1574 * This can be called by the net80211 code.
1575 *
1576 * XXX what about locking? Or, push the seqno assign into the
1577 * XXX aggregate scheduler so its serialised?
1578 */
1579int
1580ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
1581 struct ath_buf *bf, struct mbuf *m0)
1582{
1583 struct ieee80211vap *vap = ni->ni_vap;
1584 struct ath_vap *avp = ATH_VAP(vap);
1585 int r = 0;
1586 u_int pri;
1587 int tid;
1588 struct ath_txq *txq;
1589 int ismcast;
1590 const struct ieee80211_frame *wh;
1591 int is_ampdu, is_ampdu_tx, is_ampdu_pending;
1592 ieee80211_seq seqno;
1593 uint8_t type, subtype;
1594
1595 /*
1596 * Determine the target hardware queue.
1597 *
1598 * For multicast frames, the txq gets overridden appropriately
1599 * depending upon the state of PS.
1600 *
1601 * For any other frame, we do a TID/QoS lookup inside the frame
1602 * to see what the TID should be. If it's a non-QoS frame, the
1603 * AC and TID are overridden. The TID/TXQ code assumes the
1604 * TID is on a predictable hardware TXQ, so we don't support
1605 * having a node TID queued to multiple hardware TXQs.
1606 * This may change in the future but would require some locking
1607 * fudgery.
1608 */
1609 pri = ath_tx_getac(sc, m0);
1610 tid = ath_tx_gettid(sc, m0);
1611
1612 txq = sc->sc_ac2q[pri];
1613 wh = mtod(m0, struct ieee80211_frame *);
1614 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1615 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1616 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1617
1618 /*
1619 * Enforce how deep the multicast queue can grow.
1620 *
1621 * XXX duplicated in ath_raw_xmit().
1622 */
1623 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1624 ATH_TXQ_LOCK(sc->sc_cabq);
1625
1626 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
1627 sc->sc_stats.ast_tx_mcastq_overflow++;
1628 r = ENOBUFS;
1629 }
1630
1631 ATH_TXQ_UNLOCK(sc->sc_cabq);
1632
1633 if (r != 0) {
1634 m_freem(m0);
1635 return r;
1636 }
1637 }
1638
1639 /* A-MPDU TX */
1640 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid);
1641 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid);
1642 is_ampdu = is_ampdu_tx | is_ampdu_pending;
1643
1644 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n",
1645 __func__, tid, pri, is_ampdu);
1646
1647 /* Set local packet state, used to queue packets to hardware */
1648 bf->bf_state.bfs_tid = tid;
1649 bf->bf_state.bfs_txq = txq;
1650 bf->bf_state.bfs_pri = pri;
1651
1652 /*
1653 * When servicing one or more stations in power-save mode
1654 * (or) if there is some mcast data waiting on the mcast
1655 * queue (to prevent out of order delivery) multicast frames
1656 * must be bufferd until after the beacon.
1657 *
1658 * TODO: we should lock the mcastq before we check the length.
1659 */
1660 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) {
1661 txq = &avp->av_mcastq;
1662 /*
1663 * Mark the frame as eventually belonging on the CAB
1664 * queue, so the descriptor setup functions will
1665 * correctly initialise the descriptor 'qcuId' field.
1666 */
1667 bf->bf_state.bfs_txq = sc->sc_cabq;
1668 }
1669
1670 /* Do the generic frame setup */
1671 /* XXX should just bzero the bf_state? */
1672 bf->bf_state.bfs_dobaw = 0;
1673
1674 /*
1675 * Acquire the TXQ lock early, so both the encap and seqno
1676 * are allocated together.
1677 *
1678 * XXX should TXQ for CABQ traffic be the multicast queue,
1679 * or the TXQ the given PRI would allocate from? (eg for
1680 * sequence number allocation locking.)
1681 */
1682 ATH_TXQ_LOCK(txq);
1683
1684 /* A-MPDU TX? Manually set sequence number */
1685 /*
1686 * Don't do it whilst pending; the net80211 layer still
1687 * assigns them.
1688 */
1689 if (is_ampdu_tx) {
1690 /*
1691 * Always call; this function will
1692 * handle making sure that null data frames
1693 * don't get a sequence number from the current
1694 * TID and thus mess with the BAW.
1695 */
1696 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0);
1697
1698 /*
1699 * Don't add QoS NULL frames to the BAW.
1700 */
1701 if (IEEE80211_QOS_HAS_SEQ(wh) &&
1702 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) {
1703 bf->bf_state.bfs_dobaw = 1;
1704 }
1705 }
1706
1707 /*
1708 * If needed, the sequence number has been assigned.
1709 * Squirrel it away somewhere easy to get to.
1710 */
1711 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT;
1712
1713 /* Is ampdu pending? fetch the seqno and print it out */
1714 if (is_ampdu_pending)
1715 DPRINTF(sc, ATH_DEBUG_SW_TX,
1716 "%s: tid %d: ampdu pending, seqno %d\n",
1717 __func__, tid, M_SEQNO_GET(m0));
1718
1719 /* This also sets up the DMA map */
1720 r = ath_tx_normal_setup(sc, ni, bf, m0, txq);
1721
1722 if (r != 0)
1723 goto done;
1724
1725 /* At this point m0 could have changed! */
1726 m0 = bf->bf_m;
1727
1728#if 1
1729 /*
1730 * If it's a multicast frame, do a direct-dispatch to the
1731 * destination hardware queue. Don't bother software
1732 * queuing it.
1733 */
1734 /*
1735 * If it's a BAR frame, do a direct dispatch to the
1736 * destination hardware queue. Don't bother software
1737 * queuing it, as the TID will now be paused.
1738 * Sending a BAR frame can occur from the net80211 txa timer
1739 * (ie, retries) or from the ath txtask (completion call.)
1740 * It queues directly to hardware because the TID is paused
1741 * at this point (and won't be unpaused until the BAR has
1742 * either been TXed successfully or max retries has been
1743 * reached.)
1744 */
1745 if (txq == &avp->av_mcastq) {
1746 DPRINTF(sc, ATH_DEBUG_SW_TX,
1747 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf);
1748 ath_tx_xmit_normal(sc, txq, bf);
1749 } else if (type == IEEE80211_FC0_TYPE_CTL &&
1750 subtype == IEEE80211_FC0_SUBTYPE_BAR) {
1751 DPRINTF(sc, ATH_DEBUG_SW_TX,
1752 "%s: BAR: TX'ing direct\n", __func__);
1753 ath_tx_xmit_normal(sc, txq, bf);
1754 } else {
1755 /* add to software queue */
1756 DPRINTF(sc, ATH_DEBUG_SW_TX,
1757 "%s: bf=%p: swq: TX'ing\n", __func__, bf);
1758 ath_tx_swq(sc, ni, txq, bf);
1759 }
1760#else
1761 /*
1762 * For now, since there's no software queue,
1763 * direct-dispatch to the hardware.
1764 */
1765 ath_tx_xmit_normal(sc, txq, bf);
1766#endif
1767done:
1768 ATH_TXQ_UNLOCK(txq);
1769
1770 return 0;
1771}
1772
1773static int
1774ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
1775 struct ath_buf *bf, struct mbuf *m0,
1776 const struct ieee80211_bpf_params *params)
1777{
1778 struct ifnet *ifp = sc->sc_ifp;
1779 struct ieee80211com *ic = ifp->if_l2com;
1780 struct ath_hal *ah = sc->sc_ah;
1781 struct ieee80211vap *vap = ni->ni_vap;
1782 int error, ismcast, ismrr;
1783 int keyix, hdrlen, pktlen, try0, txantenna;
1784 u_int8_t rix, txrate;
1785 struct ieee80211_frame *wh;
1786 u_int flags;
1787 HAL_PKT_TYPE atype;
1788 const HAL_RATE_TABLE *rt;
1789 struct ath_desc *ds;
1790 u_int pri;
1791 int o_tid = -1;
1792 int do_override;
1793
1794 wh = mtod(m0, struct ieee80211_frame *);
1795 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1796 hdrlen = ieee80211_anyhdrsize(wh);
1797 /*
1798 * Packet length must not include any
1799 * pad bytes; deduct them here.
1800 */
1801 /* XXX honor IEEE80211_BPF_DATAPAD */
1802 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
1803
1804 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n",
1805 __func__, ismcast);
1806
1807 pri = params->ibp_pri & 3;
1808 /* Override pri if the frame isn't a QoS one */
1809 if (! IEEE80211_QOS_HAS_SEQ(wh))
1810 pri = ath_tx_getac(sc, m0);
1811
1812 /* XXX If it's an ADDBA, override the correct queue */
1813 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid);
1814
1815 /* Map ADDBA to the correct priority */
1816 if (do_override) {
1817#if 0
1818 device_printf(sc->sc_dev,
1819 "%s: overriding tid %d pri %d -> %d\n",
1820 __func__, o_tid, pri, TID_TO_WME_AC(o_tid));
1821#endif
1822 pri = TID_TO_WME_AC(o_tid);
1823 }
1824
1825 ATH_TXQ_LOCK(sc->sc_ac2q[pri]);
1826
1827 /* Handle encryption twiddling if needed */
1828 if (! ath_tx_tag_crypto(sc, ni,
1829 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0,
1830 &hdrlen, &pktlen, &keyix)) {
1831 ath_freetx(m0);
1832 return EIO;
1833 }
1834 /* packet header may have moved, reset our local pointer */
1835 wh = mtod(m0, struct ieee80211_frame *);
1836
1837 /* Do the generic frame setup */
1838 /* XXX should just bzero the bf_state? */
1839 bf->bf_state.bfs_dobaw = 0;
1840
1841 error = ath_tx_dmasetup(sc, bf, m0);
1842 if (error != 0)
1843 return error;
1844 m0 = bf->bf_m; /* NB: may have changed */
1845 wh = mtod(m0, struct ieee80211_frame *);
1846 bf->bf_node = ni; /* NB: held reference */
1847
1848 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1849 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1850 if (params->ibp_flags & IEEE80211_BPF_RTS)
1851 flags |= HAL_TXDESC_RTSENA;
1852 else if (params->ibp_flags & IEEE80211_BPF_CTS) {
1853 /* XXX assume 11g/11n protection? */
1854 bf->bf_state.bfs_doprot = 1;
1855 flags |= HAL_TXDESC_CTSENA;
1856 }
1857 /* XXX leave ismcast to injector? */
1858 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
1859 flags |= HAL_TXDESC_NOACK;
1860
1861 rt = sc->sc_currates;
1862 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1863 rix = ath_tx_findrix(sc, params->ibp_rate0);
1864 txrate = rt->info[rix].rateCode;
1865 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
1866 txrate |= rt->info[rix].shortPreamble;
1867 sc->sc_txrix = rix;
1868 try0 = params->ibp_try0;
1869 ismrr = (params->ibp_try1 != 0);
1870 txantenna = params->ibp_pri >> 2;
1871 if (txantenna == 0) /* XXX? */
1872 txantenna = sc->sc_txantenna;
1873
1874 /*
1875 * Since ctsrate is fixed, store it away for later
1876 * use when the descriptor fields are being set.
1877 */
1878 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA))
1879 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate;
1880
1881 /*
1882 * NB: we mark all packets as type PSPOLL so the h/w won't
1883 * set the sequence number, duration, etc.
1884 */
1885 atype = HAL_PKT_TYPE_PSPOLL;
1886
1887 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1888 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
1889 sc->sc_hwmap[rix].ieeerate, -1);
1890
1891 if (ieee80211_radiotap_active_vap(vap)) {
1892 u_int64_t tsf = ath_hal_gettsf64(ah);
1893
1894 sc->sc_tx_th.wt_tsf = htole64(tsf);
1895 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1896 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
1897 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1898 if (m0->m_flags & M_FRAG)
1899 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1900 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1901 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1902 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1903
1904 ieee80211_radiotap_tx(vap, m0);
1905 }
1906
1907 /*
1908 * Formulate first tx descriptor with tx controls.
1909 */
1910 ds = bf->bf_desc;
1911 /* XXX check return value? */
1912
1913 /* Store the decided rate index values away */
1914 bf->bf_state.bfs_pktlen = pktlen;
1915 bf->bf_state.bfs_hdrlen = hdrlen;
1916 bf->bf_state.bfs_atype = atype;
1917 bf->bf_state.bfs_txpower = params->ibp_power;
1918 bf->bf_state.bfs_txrate0 = txrate;
1919 bf->bf_state.bfs_try0 = try0;
1920 bf->bf_state.bfs_keyix = keyix;
1921 bf->bf_state.bfs_txantenna = txantenna;
1922 bf->bf_state.bfs_txflags = flags;
1923 bf->bf_state.bfs_shpream =
1924 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE);
1925
1926 /* Set local packet state, used to queue packets to hardware */
1927 bf->bf_state.bfs_tid = WME_AC_TO_TID(pri);
1928 bf->bf_state.bfs_txq = sc->sc_ac2q[pri];
1929 bf->bf_state.bfs_pri = pri;
1930
1931 /* XXX this should be done in ath_tx_setrate() */
1932 bf->bf_state.bfs_ctsrate = 0;
1933 bf->bf_state.bfs_ctsduration = 0;
1934 bf->bf_state.bfs_ismrr = ismrr;
1935
1936 /* Blank the legacy rate array */
1937 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1938
1939 bf->bf_state.bfs_rc[0].rix =
1940 ath_tx_findrix(sc, params->ibp_rate0);
1941 bf->bf_state.bfs_rc[0].tries = try0;
1942 bf->bf_state.bfs_rc[0].ratecode = txrate;
1943
1944 if (ismrr) {
1945 int rix;
1946
1947 rix = ath_tx_findrix(sc, params->ibp_rate1);
1948 bf->bf_state.bfs_rc[1].rix = rix;
1949 bf->bf_state.bfs_rc[1].tries = params->ibp_try1;
1950
1951 rix = ath_tx_findrix(sc, params->ibp_rate2);
1952 bf->bf_state.bfs_rc[2].rix = rix;
1953 bf->bf_state.bfs_rc[2].tries = params->ibp_try2;
1954
1955 rix = ath_tx_findrix(sc, params->ibp_rate3);
1956 bf->bf_state.bfs_rc[3].rix = rix;
1957 bf->bf_state.bfs_rc[3].tries = params->ibp_try3;
1958 }
1959 /*
1960 * All the required rate control decisions have been made;
1961 * fill in the rc flags.
1962 */
1963 ath_tx_rate_fill_rcflags(sc, bf);
1964
1965 /* NB: no buffered multicast in power save support */
1966
1967 /*
1968 * If we're overiding the ADDBA destination, dump directly
1969 * into the hardware queue, right after any pending
1970 * frames to that node are.
1971 */
1972 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n",
1973 __func__, do_override);
1974
1975 if (do_override) {
1976 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
1977 } else {
1978 /* Queue to software queue */
1979 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf);
1980 }
1981 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]);
1982
1983 return 0;
1984}
1985
1986/*
1987 * Send a raw frame.
1988 *
1989 * This can be called by net80211.
1990 */
1991int
1992ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1993 const struct ieee80211_bpf_params *params)
1994{
1995 struct ieee80211com *ic = ni->ni_ic;
1996 struct ifnet *ifp = ic->ic_ifp;
1997 struct ath_softc *sc = ifp->if_softc;
1998 struct ath_buf *bf;
1999 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *);
2000 int error = 0;
2001
2002 ATH_PCU_LOCK(sc);
2003 if (sc->sc_inreset_cnt > 0) {
2004 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n",
2005 __func__);
2006 error = EIO;
2007 ATH_PCU_UNLOCK(sc);
2008 goto bad0;
2009 }
2010 sc->sc_txstart_cnt++;
2011 ATH_PCU_UNLOCK(sc);
2012
2013 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
2014 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
2015 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
2016 "!running" : "invalid");
2017 m_freem(m);
2018 error = ENETDOWN;
2019 goto bad;
2020 }
2021
2022 /*
2023 * Enforce how deep the multicast queue can grow.
2024 *
2025 * XXX duplicated in ath_tx_start().
2026 */
2027 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2028 ATH_TXQ_LOCK(sc->sc_cabq);
2029
2030 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
2031 sc->sc_stats.ast_tx_mcastq_overflow++;
2032 error = ENOBUFS;
2033 }
2034
2035 ATH_TXQ_UNLOCK(sc->sc_cabq);
2036
2037 if (error != 0) {
2038 m_freem(m);
2039 goto bad;
2040 }
2041 }
2042
2043 /*
2044 * Grab a TX buffer and associated resources.
2045 */
2046 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
2047 if (bf == NULL) {
2048 sc->sc_stats.ast_tx_nobuf++;
2049 m_freem(m);
2050 error = ENOBUFS;
2051 goto bad;
2052 }
2053
2054 if (params == NULL) {
2055 /*
2056 * Legacy path; interpret frame contents to decide
2057 * precisely how to send the frame.
2058 */
2059 if (ath_tx_start(sc, ni, bf, m)) {
2060 error = EIO; /* XXX */
2061 goto bad2;
2062 }
2063 } else {
2064 /*
2065 * Caller supplied explicit parameters to use in
2066 * sending the frame.
2067 */
2068 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
2069 error = EIO; /* XXX */
2070 goto bad2;
2071 }
2072 }
2073 sc->sc_wd_timer = 5;
2074 ifp->if_opackets++;
2075 sc->sc_stats.ast_tx_raw++;
2076
2077 ATH_PCU_LOCK(sc);
2078 sc->sc_txstart_cnt--;
2079 ATH_PCU_UNLOCK(sc);
2080
2081 return 0;
2082bad2:
2083 ATH_TXBUF_LOCK(sc);
2084 ath_returnbuf_head(sc, bf);
2085 ATH_TXBUF_UNLOCK(sc);
2086bad:
2087 ATH_PCU_LOCK(sc);
2088 sc->sc_txstart_cnt--;
2089 ATH_PCU_UNLOCK(sc);
2090bad0:
2091 ifp->if_oerrors++;
2092 sc->sc_stats.ast_tx_raw_fail++;
2093 ieee80211_free_node(ni);
2094
2095 return error;
2096}
2097
2098/* Some helper functions */
2099
2100/*
2101 * ADDBA (and potentially others) need to be placed in the same
2102 * hardware queue as the TID/node it's relating to. This is so
2103 * it goes out after any pending non-aggregate frames to the
2104 * same node/TID.
2105 *
2106 * If this isn't done, the ADDBA can go out before the frames
2107 * queued in hardware. Even though these frames have a sequence
2108 * number -earlier- than the ADDBA can be transmitted (but
2109 * no frames whose sequence numbers are after the ADDBA should
2110 * be!) they'll arrive after the ADDBA - and the receiving end
2111 * will simply drop them as being out of the BAW.
2112 *
2113 * The frames can't be appended to the TID software queue - it'll
2114 * never be sent out. So these frames have to be directly
2115 * dispatched to the hardware, rather than queued in software.
2116 * So if this function returns true, the TXQ has to be
2117 * overridden and it has to be directly dispatched.
2118 *
2119 * It's a dirty hack, but someone's gotta do it.
2120 */
2121
2122/*
2123 * XXX doesn't belong here!
2124 */
2125static int
2126ieee80211_is_action(struct ieee80211_frame *wh)
2127{
2128 /* Type: Management frame? */
2129 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
2130 IEEE80211_FC0_TYPE_MGT)
2131 return 0;
2132
2133 /* Subtype: Action frame? */
2134 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) !=
2135 IEEE80211_FC0_SUBTYPE_ACTION)
2136 return 0;
2137
2138 return 1;
2139}
2140
2141#define MS(_v, _f) (((_v) & _f) >> _f##_S)
2142/*
2143 * Return an alternate TID for ADDBA request frames.
2144 *
2145 * Yes, this likely should be done in the net80211 layer.
2146 */
2147static int
2148ath_tx_action_frame_override_queue(struct ath_softc *sc,
2149 struct ieee80211_node *ni,
2150 struct mbuf *m0, int *tid)
2151{
2152 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
2153 struct ieee80211_action_ba_addbarequest *ia;
2154 uint8_t *frm;
2155 uint16_t baparamset;
2156
2157 /* Not action frame? Bail */
2158 if (! ieee80211_is_action(wh))
2159 return 0;
2160
2161 /* XXX Not needed for frames we send? */
2162#if 0
2163 /* Correct length? */
2164 if (! ieee80211_parse_action(ni, m))
2165 return 0;
2166#endif
2167
2168 /* Extract out action frame */
2169 frm = (u_int8_t *)&wh[1];
2170 ia = (struct ieee80211_action_ba_addbarequest *) frm;
2171
2172 /* Not ADDBA? Bail */
2173 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA)
2174 return 0;
2175 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST)
2176 return 0;
2177
2178 /* Extract TID, return it */
2179 baparamset = le16toh(ia->rq_baparamset);
2180 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID);
2181
2182 return 1;
2183}
2184#undef MS
2185
2186/* Per-node software queue operations */
2187
2188/*
2189 * Add the current packet to the given BAW.
2190 * It is assumed that the current packet
2191 *
2192 * + fits inside the BAW;
2193 * + already has had a sequence number allocated.
2194 *
2195 * Since the BAW status may be modified by both the ath task and
2196 * the net80211/ifnet contexts, the TID must be locked.
2197 */
2198void
2199ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an,
2200 struct ath_tid *tid, struct ath_buf *bf)
2201{
2202 int index, cindex;
2203 struct ieee80211_tx_ampdu *tap;
2204
2205 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2206 ATH_TID_LOCK_ASSERT(sc, tid);
2207
2208 if (bf->bf_state.bfs_isretried)
2209 return;
2210
2211 tap = ath_tx_get_tx_tid(an, tid->tid);
2212
2213 if (! bf->bf_state.bfs_dobaw) {
2214 device_printf(sc->sc_dev,
2215 "%s: dobaw=0, seqno=%d, window %d:%d\n",
2216 __func__,
2217 SEQNO(bf->bf_state.bfs_seqno),
2218 tap->txa_start,
2219 tap->txa_wnd);
2220 }
2221
2222 if (bf->bf_state.bfs_addedbaw)
2223 device_printf(sc->sc_dev,
2224 "%s: re-added? tid=%d, seqno %d; window %d:%d; "
2225 "baw head=%d tail=%d\n",
2226 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2227 tap->txa_start, tap->txa_wnd, tid->baw_head,
2228 tid->baw_tail);
2229
2230 /*
2231 * Verify that the given sequence number is not outside of the
2232 * BAW. Complain loudly if that's the case.
2233 */
2234 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2235 SEQNO(bf->bf_state.bfs_seqno))) {
2236 device_printf(sc->sc_dev,
2237 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; "
2238 "baw head=%d tail=%d\n",
2239 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2240 tap->txa_start, tap->txa_wnd, tid->baw_head,
2241 tid->baw_tail);
2242 }
2243
2244 /*
2245 * ni->ni_txseqs[] is the currently allocated seqno.
2246 * the txa state contains the current baw start.
2247 */
2248 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno));
2249 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2250 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2251 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d "
2252 "baw head=%d tail=%d\n",
2253 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2254 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head,
2255 tid->baw_tail);
2256
2257
2258#if 0
2259 assert(tid->tx_buf[cindex] == NULL);
2260#endif
2261 if (tid->tx_buf[cindex] != NULL) {
2262 device_printf(sc->sc_dev,
2263 "%s: ba packet dup (index=%d, cindex=%d, "
2264 "head=%d, tail=%d)\n",
2265 __func__, index, cindex, tid->baw_head, tid->baw_tail);
2266 device_printf(sc->sc_dev,
2267 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n",
2268 __func__,
2269 tid->tx_buf[cindex],
2270 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno),
2271 bf,
2272 SEQNO(bf->bf_state.bfs_seqno)
2273 );
2274 }
2275 tid->tx_buf[cindex] = bf;
2276
2277 if (index >= ((tid->baw_tail - tid->baw_head) &
2278 (ATH_TID_MAX_BUFS - 1))) {
2279 tid->baw_tail = cindex;
2280 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
2281 }
2282}
2283
2284/*
2285 * Flip the BAW buffer entry over from the existing one to the new one.
2286 *
2287 * When software retransmitting a (sub-)frame, it is entirely possible that
2288 * the frame ath_buf is marked as BUSY and can't be immediately reused.
2289 * In that instance the buffer is cloned and the new buffer is used for
2290 * retransmit. We thus need to update the ath_buf slot in the BAW buf
2291 * tracking array to maintain consistency.
2292 */
2293static void
2294ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an,
2295 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf)
2296{
2297 int index, cindex;
2298 struct ieee80211_tx_ampdu *tap;
2299 int seqno = SEQNO(old_bf->bf_state.bfs_seqno);
2300
2301 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2302 ATH_TID_LOCK_ASSERT(sc, tid);
2303
2304 tap = ath_tx_get_tx_tid(an, tid->tid);
2305 index = ATH_BA_INDEX(tap->txa_start, seqno);
2306 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2307
2308 /*
2309 * Just warn for now; if it happens then we should find out
2310 * about it. It's highly likely the aggregation session will
2311 * soon hang.
2312 */
2313 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) {
2314 device_printf(sc->sc_dev, "%s: retransmitted buffer"
2315 " has mismatching seqno's, BA session may hang.\n",
2316 __func__);
2317 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n",
2318 __func__,
2319 old_bf->bf_state.bfs_seqno,
2320 new_bf->bf_state.bfs_seqno);
2321 }
2322
2323 if (tid->tx_buf[cindex] != old_bf) {
2324 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; "
2325 " has m BA session may hang.\n",
2326 __func__);
2327 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n",
2328 __func__,
2329 old_bf, new_bf);
2330 }
2331
2332 tid->tx_buf[cindex] = new_bf;
2333}
2334
2335/*
2336 * seq_start - left edge of BAW
2337 * seq_next - current/next sequence number to allocate
2338 *
2339 * Since the BAW status may be modified by both the ath task and
2340 * the net80211/ifnet contexts, the TID must be locked.
2341 */
2342static void
2343ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an,
2344 struct ath_tid *tid, const struct ath_buf *bf)
2345{
2346 int index, cindex;
2347 struct ieee80211_tx_ampdu *tap;
2348 int seqno = SEQNO(bf->bf_state.bfs_seqno);
2349
2350 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2351 ATH_TID_LOCK_ASSERT(sc, tid);
2352
2353 tap = ath_tx_get_tx_tid(an, tid->tid);
2354 index = ATH_BA_INDEX(tap->txa_start, seqno);
2355 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2356
2357 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2358 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, "
2359 "baw head=%d, tail=%d\n",
2360 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index,
2361 cindex, tid->baw_head, tid->baw_tail);
2362
2363 /*
2364 * If this occurs then we have a big problem - something else
2365 * has slid tap->txa_start along without updating the BAW
2366 * tracking start/end pointers. Thus the TX BAW state is now
2367 * completely busted.
2368 *
2369 * But for now, since I haven't yet fixed TDMA and buffer cloning,
2370 * it's quite possible that a cloned buffer is making its way
2371 * here and causing it to fire off. Disable TDMA for now.
2372 */
2373 if (tid->tx_buf[cindex] != bf) {
2374 device_printf(sc->sc_dev,
2375 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n",
2376 __func__,
2377 bf, SEQNO(bf->bf_state.bfs_seqno),
2378 tid->tx_buf[cindex],
2379 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno));
2380 }
2381
2382 tid->tx_buf[cindex] = NULL;
2383
2384 while (tid->baw_head != tid->baw_tail &&
2385 !tid->tx_buf[tid->baw_head]) {
2386 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2387 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
2388 }
2389 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2390 "%s: baw is now %d:%d, baw head=%d\n",
2391 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head);
2392}
2393
2394/*
2395 * Mark the current node/TID as ready to TX.
2396 *
2397 * This is done to make it easy for the software scheduler to
2398 * find which nodes have data to send.
2399 *
2400 * The TXQ lock must be held.
2401 */
2402static void
2403ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid)
2404{
2405 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2406
2407 ATH_TXQ_LOCK_ASSERT(txq);
2408
2409 if (tid->paused)
2410 return; /* paused, can't schedule yet */
2411
2412 if (tid->sched)
2413 return; /* already scheduled */
2414
2415 tid->sched = 1;
2416
2417 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem);
2418}
2419
2420/*
2421 * Mark the current node as no longer needing to be polled for
2422 * TX packets.
2423 *
2424 * The TXQ lock must be held.
2425 */
2426static void
2427ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid)
2428{
2429 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2430
2431 ATH_TXQ_LOCK_ASSERT(txq);
2432
2433 if (tid->sched == 0)
2434 return;
2435
2436 tid->sched = 0;
2437 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem);
2438}
2439
2440/*
2441 * Assign a sequence number manually to the given frame.
2442 *
2443 * This should only be called for A-MPDU TX frames.
2444 */
2445static ieee80211_seq
2446ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni,
2447 struct ath_buf *bf, struct mbuf *m0)
2448{
2449 struct ieee80211_frame *wh;
2450 int tid, pri;
2451 ieee80211_seq seqno;
2452 uint8_t subtype;
2453
2454 /* TID lookup */
2455 wh = mtod(m0, struct ieee80211_frame *);
2456 pri = M_WME_GETAC(m0); /* honor classification */
2457 tid = WME_AC_TO_TID(pri);
2458 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n",
2459 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
2460
2461 /* XXX Is it a control frame? Ignore */
2462
2463 /* Does the packet require a sequence number? */
2464 if (! IEEE80211_QOS_HAS_SEQ(wh))
2465 return -1;
2466
2467 ATH_TID_LOCK_ASSERT(sc, &(ATH_NODE(ni)->an_tid[tid]));
2468
2469 /*
2470 * Is it a QOS NULL Data frame? Give it a sequence number from
2471 * the default TID (IEEE80211_NONQOS_TID.)
2472 *
2473 * The RX path of everything I've looked at doesn't include the NULL
2474 * data frame sequence number in the aggregation state updates, so
2475 * assigning it a sequence number there will cause a BAW hole on the
2476 * RX side.
2477 */
2478 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2479 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) {
2480 /* XXX no locking for this TID? This is a bit of a problem. */
2481 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID];
2482 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE);
2483 } else {
2484 /* Manually assign sequence number */
2485 seqno = ni->ni_txseqs[tid];
2486 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE);
2487 }
2488 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
2489 M_SEQNO_SET(m0, seqno);
2490
2491 /* Return so caller can do something with it if needed */
2492 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno);
2493 return seqno;
2494}
2495
2496/*
2497 * Attempt to direct dispatch an aggregate frame to hardware.
2498 * If the frame is out of BAW, queue.
2499 * Otherwise, schedule it as a single frame.
2500 */
2501static void
2502ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an,
2503 struct ath_txq *txq, struct ath_buf *bf)
2504{
2505 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
2506// struct ath_txq *txq = bf->bf_state.bfs_txq;
2507 struct ieee80211_tx_ampdu *tap;
2508
2509 if (txq != bf->bf_state.bfs_txq) {
2510 device_printf(sc->sc_dev, "%s: txq %d != bfs_txq %d!\n",
2511 __func__,
2512 txq->axq_qnum,
2513 bf->bf_state.bfs_txq->axq_qnum);
2514 }
2515
2516 ATH_TXQ_LOCK_ASSERT(txq);
2517 ATH_TID_LOCK_ASSERT(sc, tid);
2518
2519 tap = ath_tx_get_tx_tid(an, tid->tid);
2520
2521 /* paused? queue */
2522 if (tid->paused) {
2523 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list);
2524 /* XXX don't sched - we're paused! */
2525 return;
2526 }
2527
2528 /* outside baw? queue */
2529 if (bf->bf_state.bfs_dobaw &&
2530 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2531 SEQNO(bf->bf_state.bfs_seqno)))) {
2532 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list);
2533 ath_tx_tid_sched(sc, tid);
2534 return;
2535 }
2536
2537 /*
2538 * This is a temporary check and should be removed once
2539 * all the relevant code paths have been fixed.
2540 *
2541 * During aggregate retries, it's possible that the head
2542 * frame will fail (which has the bfs_aggr and bfs_nframes
2543 * fields set for said aggregate) and will be retried as
2544 * a single frame. In this instance, the values should
2545 * be reset or the completion code will get upset with you.
2546 */
2547 if (bf->bf_state.bfs_aggr != 0 || bf->bf_state.bfs_nframes > 1) {
2548 device_printf(sc->sc_dev, "%s: bfs_aggr=%d, bfs_nframes=%d\n",
2549 __func__,
2550 bf->bf_state.bfs_aggr,
2551 bf->bf_state.bfs_nframes);
2552 bf->bf_state.bfs_aggr = 0;
2553 bf->bf_state.bfs_nframes = 1;
2554 }
2555
2556 /* Direct dispatch to hardware */
2557 ath_tx_do_ratelookup(sc, bf);
2558 ath_tx_calc_duration(sc, bf);
2559 ath_tx_calc_protection(sc, bf);
2560 ath_tx_set_rtscts(sc, bf);
2561 ath_tx_rate_fill_rcflags(sc, bf);
2562 ath_tx_setds(sc, bf);
2563
2564 /* Statistics */
2565 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++;
2566
2567 /* Track per-TID hardware queue depth correctly */
2568 tid->hwq_depth++;
2569
2570 /* Add to BAW */
2571 if (bf->bf_state.bfs_dobaw) {
2572 ath_tx_addto_baw(sc, an, tid, bf);
2573 bf->bf_state.bfs_addedbaw = 1;
2574 }
2575
2576 /* Set completion handler, multi-frame aggregate or not */
2577 bf->bf_comp = ath_tx_aggr_comp;
2578
2579 /* Hand off to hardware */
2580 ath_tx_handoff(sc, txq, bf);
2581}
2582
2583/*
2584 * Attempt to send the packet.
2585 * If the queue isn't busy, direct-dispatch.
2586 * If the queue is busy enough, queue the given packet on the
2587 * relevant software queue.
2588 */
2589void
2590ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq,
2591 struct ath_buf *bf)
2592{
2593 struct ath_node *an = ATH_NODE(ni);
2594 struct ieee80211_frame *wh;
2595 struct ath_tid *atid;
2596 int pri, tid;
2597 struct mbuf *m0 = bf->bf_m;
2598
2599 ATH_TXQ_LOCK_ASSERT(txq);
2600
2601 /* Fetch the TID - non-QoS frames get assigned to TID 16 */
2602 wh = mtod(m0, struct ieee80211_frame *);
2603 pri = ath_tx_getac(sc, m0);
2604 tid = ath_tx_gettid(sc, m0);
2605 atid = &an->an_tid[tid];
2606
2607 ATH_TID_LOCK_ASSERT(sc, atid);
2608
2609 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n",
2610 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
2611
2612 /* Set local packet state, used to queue packets to hardware */
2613 /* XXX potentially duplicate info, re-check */
2614 /* XXX remember, txq must be the hardware queue, not the av_mcastq */
2615 bf->bf_state.bfs_tid = tid;
2616 bf->bf_state.bfs_txq = txq;
2617 bf->bf_state.bfs_pri = pri;
2618
2619 /*
2620 * If the hardware queue isn't busy, queue it directly.
2621 * If the hardware queue is busy, queue it.
2622 * If the TID is paused or the traffic it outside BAW, software
2623 * queue it.
2624 */
2625 if (atid->paused) {
2626 /* TID is paused, queue */
2627 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__);
2628 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2629 } else if (ath_tx_ampdu_pending(sc, an, tid)) {
2630 /* AMPDU pending; queue */
2631 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__);
2632 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2633 /* XXX sched? */
2634 } else if (ath_tx_ampdu_running(sc, an, tid)) {
2635 /* AMPDU running, attempt direct dispatch if possible */
2636
2637 /*
2638 * Always queue the frame to the tail of the list.
2639 */
2640 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2641
2642 /*
2643 * If the hardware queue isn't busy, direct dispatch
2644 * the head frame in the list. Don't schedule the
2645 * TID - let it build some more frames first?
2646 *
2647 * Otherwise, schedule the TID.
2648 */
2649 if (txq->axq_depth < sc->sc_hwq_limit) {
2650 bf = TAILQ_FIRST(&atid->axq_q);
2651 ATH_TXQ_REMOVE(atid, bf, bf_list);
2652
2653 /*
2654 * Ensure it's definitely treated as a non-AMPDU
2655 * frame - this information may have been left
2656 * over from a previous attempt.
2657 */
2658 bf->bf_state.bfs_aggr = 0;
2659 bf->bf_state.bfs_nframes = 1;
2660
2661 /* Queue to the hardware */
2662 ath_tx_xmit_aggr(sc, an, txq, bf);
2663 DPRINTF(sc, ATH_DEBUG_SW_TX,
2664 "%s: xmit_aggr\n",
2665 __func__);
2666 } else {
2667 DPRINTF(sc, ATH_DEBUG_SW_TX,
2668 "%s: ampdu; swq'ing\n",
2669 __func__);
2670 ath_tx_tid_sched(sc, atid);
2671 }
2672 } else if (txq->axq_depth < sc->sc_hwq_limit) {
2673 /* AMPDU not running, attempt direct dispatch */
2674 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__);
2675 ath_tx_xmit_normal(sc, txq, bf);
2676 } else {
2677 /* Busy; queue */
2678 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__);
2679 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list);
2680 ath_tx_tid_sched(sc, atid);
2681 }
2682}
2683
2684/*
2685 * Do the basic frame setup stuff that's required before the frame
2686 * is added to a software queue.
2687 *
2688 * All frames get mostly the same treatment and it's done once.
2689 * Retransmits fiddle with things like the rate control setup,
2690 * setting the retransmit bit in the packet; doing relevant DMA/bus
2691 * syncing and relinking it (back) into the hardware TX queue.
2692 *
2693 * Note that this may cause the mbuf to be reallocated, so
2694 * m0 may not be valid.
2695 */
2696
2697
2698/*
2699 * Configure the per-TID node state.
2700 *
2701 * This likely belongs in if_ath_node.c but I can't think of anywhere
2702 * else to put it just yet.
2703 *
2704 * This sets up the SLISTs and the mutex as appropriate.
2705 */
2706void
2707ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an)
2708{
2709 int i, j;
2710 struct ath_tid *atid;
2711
2712 for (i = 0; i < IEEE80211_TID_SIZE; i++) {
2713 atid = &an->an_tid[i];
2714 TAILQ_INIT(&atid->axq_q);
2715 atid->tid = i;
2716 atid->an = an;
2717 for (j = 0; j < ATH_TID_MAX_BUFS; j++)
2718 atid->tx_buf[j] = NULL;
2719 atid->baw_head = atid->baw_tail = 0;
2720 atid->paused = 0;
2721 atid->sched = 0;
2722 atid->hwq_depth = 0;
2723 atid->cleanup_inprogress = 0;
2724 if (i == IEEE80211_NONQOS_TID)
2725 atid->ac = WME_AC_BE;
2726 else
2727 atid->ac = TID_TO_WME_AC(i);
2728 }
2729}
2730
2731/*
2732 * Pause the current TID. This stops packets from being transmitted
2733 * on it.
2734 *
2735 * Since this is also called from upper layers as well as the driver,
2736 * it will get the TID lock.
2737 */
2738static void
2739ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid)
2740{
2741
2742 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2743 tid->paused++;
2744 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n",
2745 __func__, tid->paused);
2746}
2747
2748/*
2749 * Unpause the current TID, and schedule it if needed.
2750 */
2751static void
2752ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid)
2753{
2754 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2755
2756 tid->paused--;
2757
2758 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n",
2759 __func__, tid->paused);
2760
2761 if (tid->paused || tid->axq_depth == 0) {
2762 return;
2763 }
2764
2765 ath_tx_tid_sched(sc, tid);
2766 /* Punt some frames to the hardware if needed */
2767 //ath_txq_sched(sc, sc->sc_ac2q[tid->ac]);
2768 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
2769}
2770
2771/*
2772 * Suspend the queue because we need to TX a BAR.
2773 */
2774static void
2775ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid)
2776{
2777 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2778
2779 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
2780 "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n",
2781 __func__,
2782 tid,
2783 tid->bar_wait,
2784 tid->bar_tx);
2785
2786 /* We shouldn't be called when bar_tx is 1 */
2787 if (tid->bar_tx) {
2788 device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n",
2789 __func__);
2790 }
2791
2792 /* If we've already been called, just be patient. */
2793 if (tid->bar_wait)
2794 return;
2795
2796 /* Wait! */
2797 tid->bar_wait = 1;
2798
2799 /* Only one pause, no matter how many frames fail */
2800 ath_tx_tid_pause(sc, tid);
2801}
2802
2803/*
2804 * We've finished with BAR handling - either we succeeded or
2805 * failed. Either way, unsuspend TX.
2806 */
2807static void
2808ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid)
2809{
2810 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2811
2812 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
2813 "%s: tid=%p, called\n",
2814 __func__,
2815 tid);
2816
2817 if (tid->bar_tx == 0 || tid->bar_wait == 0) {
2818 device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n",
2819 __func__, tid->bar_tx, tid->bar_wait);
2820 }
2821
2822 tid->bar_tx = tid->bar_wait = 0;
2823 ath_tx_tid_resume(sc, tid);
2824}
2825
2826/*
2827 * Return whether we're ready to TX a BAR frame.
2828 *
2829 * Requires the TID lock be held.
2830 */
2831static int
2832ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid)
2833{
2834
2835 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2836
2837 if (tid->bar_wait == 0 || tid->hwq_depth > 0)
2838 return (0);
2839
2840 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n",
2841 __func__, tid, tid->tid);
2842
2843 return (1);
2844}
2845
2846/*
2847 * Check whether the current TID is ready to have a BAR
2848 * TXed and if so, do the TX.
2849 *
2850 * Since the TID/TXQ lock can't be held during a call to
2851 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it,
2852 * sending the BAR and locking it again.
2853 *
2854 * Eventually, the code to send the BAR should be broken out
2855 * from this routine so the lock doesn't have to be reacquired
2856 * just to be immediately dropped by the caller.
2857 */
2858static void
2859ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid)
2860{
2861 struct ieee80211_tx_ampdu *tap;
2862
2863 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2864
2865 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
2866 "%s: tid=%p, called\n",
2867 __func__,
2868 tid);
2869
2870 tap = ath_tx_get_tx_tid(tid->an, tid->tid);
2871
2872 /*
2873 * This is an error condition!
2874 */
2875 if (tid->bar_wait == 0 || tid->bar_tx == 1) {
2876 device_printf(sc->sc_dev,
2877 "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n",
2878 __func__,
2879 tid,
2880 tid->bar_tx,
2881 tid->bar_wait);
2882 return;
2883 }
2884
2885 /* Don't do anything if we still have pending frames */
2886 if (tid->hwq_depth > 0) {
2887 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
2888 "%s: tid=%p, hwq_depth=%d, waiting\n",
2889 __func__,
2890 tid,
2891 tid->hwq_depth);
2892 return;
2893 }
2894
2895 /* We're now about to TX */
2896 tid->bar_tx = 1;
2897
2898 /*
2899 * Calculate new BAW left edge, now that all frames have either
2900 * succeeded or failed.
2901 *
2902 * XXX verify this is _actually_ the valid value to begin at!
2903 */
2904 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
2905 "%s: tid=%p, new BAW left edge=%d\n",
2906 __func__,
2907 tid,
2908 tap->txa_start);
2909
2910 /* Try sending the BAR frame */
2911 /* We can't hold the lock here! */
2912
2913 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
2914 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) {
2915 /* Success? Now we wait for notification that it's done */
2916 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
2917 return;
2918 }
2919
2920 /* Failure? For now, warn loudly and continue */
2921 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
2922 device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n",
2923 __func__, tid);
2924 ath_tx_tid_bar_unsuspend(sc, tid);
2925}
2926
2927
2928/*
2929 * Free any packets currently pending in the software TX queue.
2930 *
2931 * This will be called when a node is being deleted.
2932 *
2933 * It can also be called on an active node during an interface
2934 * reset or state transition.
2935 *
2936 * (From Linux/reference):
2937 *
2938 * TODO: For frame(s) that are in the retry state, we will reuse the
2939 * sequence number(s) without setting the retry bit. The
2940 * alternative is to give up on these and BAR the receiver's window
2941 * forward.
2942 */
2943static void
2944ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an,
2945 struct ath_tid *tid, ath_bufhead *bf_cq)
2946{
2947 struct ath_buf *bf;
2948 struct ieee80211_tx_ampdu *tap;
2949 struct ieee80211_node *ni = &an->an_node;
2950 int t = 0;
2951 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2952
2953 tap = ath_tx_get_tx_tid(an, tid->tid);
2954
2955 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]);
2956
2957 /* Walk the queue, free frames */
2958 for (;;) {
2959 bf = TAILQ_FIRST(&tid->axq_q);
2960 if (bf == NULL) {
2961 break;
2962 }
2963
2964 if (t == 0) {
2965 device_printf(sc->sc_dev,
2966 "%s: node %p: bf=%p: addbaw=%d, dobaw=%d, "
2967 "seqno=%d, retry=%d\n",
2968 __func__, ni, bf,
2969 bf->bf_state.bfs_addedbaw,
2970 bf->bf_state.bfs_dobaw,
2971 SEQNO(bf->bf_state.bfs_seqno),
2972 bf->bf_state.bfs_retries);
2973 device_printf(sc->sc_dev,
2974 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d\n",
2975 __func__, ni, bf,
2976 tid->axq_depth,
2977 tid->hwq_depth,
2978 tid->bar_wait);
2979 device_printf(sc->sc_dev,
2980 "%s: node %p: tid %d: txq_depth=%d, "
2981 "txq_aggr_depth=%d, sched=%d, paused=%d, "
2982 "hwq_depth=%d, incomp=%d, baw_head=%d, "
2983 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n",
2984 __func__, ni, tid->tid, txq->axq_depth,
2985 txq->axq_aggr_depth, tid->sched, tid->paused,
2986 tid->hwq_depth, tid->incomp, tid->baw_head,
2987 tid->baw_tail, tap == NULL ? -1 : tap->txa_start,
2988 ni->ni_txseqs[tid->tid]);
2989
2990 /* XXX Dump the frame, see what it is? */
2991 ieee80211_dump_pkt(ni->ni_ic,
2992 mtod(bf->bf_m, const uint8_t *),
2993 bf->bf_m->m_len, 0, -1);
2994
2995 t = 1;
2996 }
2997
2998
2999 /*
3000 * If the current TID is running AMPDU, update
3001 * the BAW.
3002 */
3003 if (ath_tx_ampdu_running(sc, an, tid->tid) &&
3004 bf->bf_state.bfs_dobaw) {
3005 /*
3006 * Only remove the frame from the BAW if it's
3007 * been transmitted at least once; this means
3008 * the frame was in the BAW to begin with.
3009 */
3010 if (bf->bf_state.bfs_retries > 0) {
3011 ath_tx_update_baw(sc, an, tid, bf);
3012 bf->bf_state.bfs_dobaw = 0;
3013 }
3014 /*
3015 * This has become a non-fatal error now
3016 */
3017 if (! bf->bf_state.bfs_addedbaw)
3018 device_printf(sc->sc_dev,
3019 "%s: wasn't added: seqno %d\n",
3020 __func__, SEQNO(bf->bf_state.bfs_seqno));
3021 }
3022 ATH_TXQ_REMOVE(tid, bf, bf_list);
3023 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list);
3024 }
3025
3026 /*
3027 * Now that it's completed, grab the TID lock and update
3028 * the sequence number and BAW window.
3029 * Because sequence numbers have been assigned to frames
3030 * that haven't been sent yet, it's entirely possible
3031 * we'll be called with some pending frames that have not
3032 * been transmitted.
3033 *
3034 * The cleaner solution is to do the sequence number allocation
3035 * when the packet is first transmitted - and thus the "retries"
3036 * check above would be enough to update the BAW/seqno.
3037 */
3038
3039 /* But don't do it for non-QoS TIDs */
3040 if (tap) {
3041#if 0
3042 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3043 "%s: node %p: TID %d: sliding BAW left edge to %d\n",
3044 __func__, an, tid->tid, tap->txa_start);
3045#endif
3046 ni->ni_txseqs[tid->tid] = tap->txa_start;
3047 tid->baw_tail = tid->baw_head;
3048 }
3049}
3050
3051/*
3052 * Flush all software queued packets for the given node.
3053 *
3054 * This occurs when a completion handler frees the last buffer
3055 * for a node, and the node is thus freed. This causes the node
3056 * to be cleaned up, which ends up calling ath_tx_node_flush.
3057 */
3058void
3059ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an)
3060{
3061 int tid;
3062 ath_bufhead bf_cq;
3063 struct ath_buf *bf;
3064
3065 TAILQ_INIT(&bf_cq);
3066
3067 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
3068 struct ath_tid *atid = &an->an_tid[tid];
3069 struct ath_txq *txq = sc->sc_ac2q[atid->ac];
3070
3071 /* Remove this tid from the list of active tids */
3072 ATH_TXQ_LOCK(txq);
3073 ath_tx_tid_unsched(sc, atid);
3074
3075 /* Free packets */
3076 ath_tx_tid_drain(sc, an, atid, &bf_cq);
3077 ATH_TXQ_UNLOCK(txq);
3078 }
3079
3080 /* Handle completed frames */
3081 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3082 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3083 ath_tx_default_comp(sc, bf, 0);
3084 }
3085}
3086
3087/*
3088 * Drain all the software TXQs currently with traffic queued.
3089 */
3090void
3091ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq)
3092{
3093 struct ath_tid *tid;
3094 ath_bufhead bf_cq;
3095 struct ath_buf *bf;
3096
3097 TAILQ_INIT(&bf_cq);
3098 ATH_TXQ_LOCK(txq);
3099
3100 /*
3101 * Iterate over all active tids for the given txq,
3102 * flushing and unsched'ing them
3103 */
3104 while (! TAILQ_EMPTY(&txq->axq_tidq)) {
3105 tid = TAILQ_FIRST(&txq->axq_tidq);
3106 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq);
3107 ath_tx_tid_unsched(sc, tid);
3108 }
3109
3110 ATH_TXQ_UNLOCK(txq);
3111
3112 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3113 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3114 ath_tx_default_comp(sc, bf, 0);
3115 }
3116}
3117
3118/*
3119 * Handle completion of non-aggregate session frames.
3120 */
3121void
3122ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3123{
3124 struct ieee80211_node *ni = bf->bf_node;
3125 struct ath_node *an = ATH_NODE(ni);
3126 int tid = bf->bf_state.bfs_tid;
3127 struct ath_tid *atid = &an->an_tid[tid];
3128 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3129
3130 /* The TID state is protected behind the TXQ lock */
3131 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3132
3133 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n",
3134 __func__, bf, fail, atid->hwq_depth - 1);
3135
3136 atid->hwq_depth--;
3137 if (atid->hwq_depth < 0)
3138 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3139 __func__, atid->hwq_depth);
3140 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3141
3142 /*
3143 * punt to rate control if we're not being cleaned up
3144 * during a hw queue drain and the frame wanted an ACK.
3145 */
3146 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0))
3147 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
3148 ts, bf->bf_state.bfs_pktlen,
3149 1, (ts->ts_status == 0) ? 0 : 1);
3150
3151 ath_tx_default_comp(sc, bf, fail);
3152}
3153
3154/*
3155 * Handle cleanup of aggregate session packets that aren't
3156 * an A-MPDU.
3157 *
3158 * There's no need to update the BAW here - the session is being
3159 * torn down.
3160 */
3161static void
3162ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf)
3163{
3164 struct ieee80211_node *ni = bf->bf_node;
3165 struct ath_node *an = ATH_NODE(ni);
3166 int tid = bf->bf_state.bfs_tid;
3167 struct ath_tid *atid = &an->an_tid[tid];
3168
3169 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n",
3170 __func__, tid, atid->incomp);
3171
3172 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3173 atid->incomp--;
3174 if (atid->incomp == 0) {
3175 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3176 "%s: TID %d: cleaned up! resume!\n",
3177 __func__, tid);
3178 atid->cleanup_inprogress = 0;
3179 ath_tx_tid_resume(sc, atid);
3180 }
3181 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3182
3183 ath_tx_default_comp(sc, bf, 0);
3184}
3185
3186/*
3187 * Performs transmit side cleanup when TID changes from aggregated to
3188 * unaggregated.
3189 *
3190 * - Discard all retry frames from the s/w queue.
3191 * - Fix the tx completion function for all buffers in s/w queue.
3192 * - Count the number of unacked frames, and let transmit completion
3193 * handle it later.
3194 *
3195 * The caller is responsible for pausing the TID.
3196 */
3197static void
3198ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid)
3199{
3200 struct ath_tid *atid = &an->an_tid[tid];
3201 struct ieee80211_tx_ampdu *tap;
3202 struct ath_buf *bf, *bf_next;
3203 ath_bufhead bf_cq;
3204
3205 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
3206 "%s: TID %d: called\n", __func__, tid);
3207
3208 TAILQ_INIT(&bf_cq);
3209 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3210
3211 /*
3212 * Update the frames in the software TX queue:
3213 *
3214 * + Discard retry frames in the queue
3215 * + Fix the completion function to be non-aggregate
3216 */
3217 bf = TAILQ_FIRST(&atid->axq_q);
3218 while (bf) {
3219 if (bf->bf_state.bfs_isretried) {
3220 bf_next = TAILQ_NEXT(bf, bf_list);
3221 TAILQ_REMOVE(&atid->axq_q, bf, bf_list);
3222 atid->axq_depth--;
3223 if (bf->bf_state.bfs_dobaw) {
3224 ath_tx_update_baw(sc, an, atid, bf);
3225 if (! bf->bf_state.bfs_addedbaw)
3226 device_printf(sc->sc_dev,
3227 "%s: wasn't added: seqno %d\n",
3228 __func__,
3229 SEQNO(bf->bf_state.bfs_seqno));
3230 }
3231 bf->bf_state.bfs_dobaw = 0;
3232 /*
3233 * Call the default completion handler with "fail" just
3234 * so upper levels are suitably notified about this.
3235 */
3236 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3237 bf = bf_next;
3238 continue;
3239 }
3240 /* Give these the default completion handler */
3241 bf->bf_comp = ath_tx_normal_comp;
3242 bf = TAILQ_NEXT(bf, bf_list);
3243 }
3244
3245 /* The caller is required to pause the TID */
3246#if 0
3247 /* Pause the TID */
3248 ath_tx_tid_pause(sc, atid);
3249#endif
3250
3251 /*
3252 * Calculate what hardware-queued frames exist based
3253 * on the current BAW size. Ie, what frames have been
3254 * added to the TX hardware queue for this TID but
3255 * not yet ACKed.
3256 */
3257 tap = ath_tx_get_tx_tid(an, tid);
3258 /* Need the lock - fiddling with BAW */
3259 while (atid->baw_head != atid->baw_tail) {
3260 if (atid->tx_buf[atid->baw_head]) {
3261 atid->incomp++;
3262 atid->cleanup_inprogress = 1;
3263 atid->tx_buf[atid->baw_head] = NULL;
3264 }
3265 INCR(atid->baw_head, ATH_TID_MAX_BUFS);
3266 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
3267 }
3268
3269 /*
3270 * If cleanup is required, defer TID scheduling
3271 * until all the HW queued packets have been
3272 * sent.
3273 */
3274 if (! atid->cleanup_inprogress)
3275 ath_tx_tid_resume(sc, atid);
3276
3277 if (atid->cleanup_inprogress)
3278 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3279 "%s: TID %d: cleanup needed: %d packets\n",
3280 __func__, tid, atid->incomp);
3281 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3282
3283 /* Handle completing frames and fail them */
3284 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3285 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3286 ath_tx_default_comp(sc, bf, 1);
3287 }
3288}
3289
3290static void
3291ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
3292{
3293 struct ieee80211_frame *wh;
3294
3295 wh = mtod(bf->bf_m, struct ieee80211_frame *);
3296 /* Only update/resync if needed */
3297 if (bf->bf_state.bfs_isretried == 0) {
3298 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
3299 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3300 BUS_DMASYNC_PREWRITE);
3301 }
3302 sc->sc_stats.ast_tx_swretries++;
3303 bf->bf_state.bfs_isretried = 1;
3304 bf->bf_state.bfs_retries ++;
3305}
3306
3307static struct ath_buf *
3308ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an,
3309 struct ath_tid *tid, struct ath_buf *bf)
3310{
3311 struct ath_buf *nbf;
3312 int error;
3313
3314 nbf = ath_buf_clone(sc, bf);
3315
3316#if 0
3317 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n",
3318 __func__);
3319#endif
3320
3321 if (nbf == NULL) {
3322 /* Failed to clone */
3323 device_printf(sc->sc_dev,
3324 "%s: failed to clone a busy buffer\n",
3325 __func__);
3326 return NULL;
3327 }
3328
3329 /* Setup the dma for the new buffer */
3330 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m);
3331 if (error != 0) {
3332 device_printf(sc->sc_dev,
3333 "%s: failed to setup dma for clone\n",
3334 __func__);
3335 /*
3336 * Put this at the head of the list, not tail;
3337 * that way it doesn't interfere with the
3338 * busy buffer logic (which uses the tail of
3339 * the list.)
3340 */
3341 ATH_TXBUF_LOCK(sc);
3342 ath_returnbuf_head(sc, nbf);
3343 ATH_TXBUF_UNLOCK(sc);
3344 return NULL;
3345 }
3346
3347 /* Update BAW if required, before we free the original buf */
3348 if (bf->bf_state.bfs_dobaw)
3349 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf);
3350
3351 /* Free current buffer; return the older buffer */
3352 bf->bf_m = NULL;
3353 bf->bf_node = NULL;
3354 ath_freebuf(sc, bf);
3355 return nbf;
3356}
3357
3358/*
3359 * Handle retrying an unaggregate frame in an aggregate
3360 * session.
3361 *
3362 * If too many retries occur, pause the TID, wait for
3363 * any further retransmits (as there's no reason why
3364 * non-aggregate frames in an aggregate session are
3365 * transmitted in-order; they just have to be in-BAW)
3366 * and then queue a BAR.
3367 */
3368static void
3369ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf)
3370{
3371 struct ieee80211_node *ni = bf->bf_node;
3372 struct ath_node *an = ATH_NODE(ni);
3373 int tid = bf->bf_state.bfs_tid;
3374 struct ath_tid *atid = &an->an_tid[tid];
3375 struct ieee80211_tx_ampdu *tap;
3376
3377 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3378
3379 tap = ath_tx_get_tx_tid(an, tid);
3380
3381 /*
3382 * If the buffer is marked as busy, we can't directly
3383 * reuse it. Instead, try to clone the buffer.
3384 * If the clone is successful, recycle the old buffer.
3385 * If the clone is unsuccessful, set bfs_retries to max
3386 * to force the next bit of code to free the buffer
3387 * for us.
3388 */
3389 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
3390 (bf->bf_flags & ATH_BUF_BUSY)) {
3391 struct ath_buf *nbf;
3392 nbf = ath_tx_retry_clone(sc, an, atid, bf);
3393 if (nbf)
3394 /* bf has been freed at this point */
3395 bf = nbf;
3396 else
3397 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
3398 }
3399
3400 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
3401 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
3402 "%s: exceeded retries; seqno %d\n",
3403 __func__, SEQNO(bf->bf_state.bfs_seqno));
3404 sc->sc_stats.ast_tx_swretrymax++;
3405
3406 /* Update BAW anyway */
3407 if (bf->bf_state.bfs_dobaw) {
3408 ath_tx_update_baw(sc, an, atid, bf);
3409 if (! bf->bf_state.bfs_addedbaw)
3410 device_printf(sc->sc_dev,
3411 "%s: wasn't added: seqno %d\n",
3412 __func__, SEQNO(bf->bf_state.bfs_seqno));
3413 }
3414 bf->bf_state.bfs_dobaw = 0;
3415
3416 /* Suspend the TX queue and get ready to send the BAR */
3417 ath_tx_tid_bar_suspend(sc, atid);
3418
3419 /* Send the BAR if there are no other frames waiting */
3420 if (ath_tx_tid_bar_tx_ready(sc, atid))
3421 ath_tx_tid_bar_tx(sc, atid);
3422
3423 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3424
3425 /* Free buffer, bf is free after this call */
3426 ath_tx_default_comp(sc, bf, 0);
3427 return;
3428 }
3429
3430 /*
3431 * This increments the retry counter as well as
3432 * sets the retry flag in the ath_buf and packet
3433 * body.
3434 */
3435 ath_tx_set_retry(sc, bf);
3436
3437 /*
3438 * Insert this at the head of the queue, so it's
3439 * retried before any current/subsequent frames.
3440 */
3441 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list);
3442 ath_tx_tid_sched(sc, atid);
3443 /* Send the BAR if there are no other frames waiting */
3444 if (ath_tx_tid_bar_tx_ready(sc, atid))
3445 ath_tx_tid_bar_tx(sc, atid);
3446
3447 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3448}
3449
3450/*
3451 * Common code for aggregate excessive retry/subframe retry.
3452 * If retrying, queues buffers to bf_q. If not, frees the
3453 * buffers.
3454 *
3455 * XXX should unify this with ath_tx_aggr_retry_unaggr()
3456 */
3457static int
3458ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf,
3459 ath_bufhead *bf_q)
3460{
3461 struct ieee80211_node *ni = bf->bf_node;
3462 struct ath_node *an = ATH_NODE(ni);
3463 int tid = bf->bf_state.bfs_tid;
3464 struct ath_tid *atid = &an->an_tid[tid];
3465
3466 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]);
3467
3468 /* XXX clr11naggr should be done for all subframes */
3469 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
3470 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0);
3471 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */
3472
3473 /*
3474 * If the buffer is marked as busy, we can't directly
3475 * reuse it. Instead, try to clone the buffer.
3476 * If the clone is successful, recycle the old buffer.
3477 * If the clone is unsuccessful, set bfs_retries to max
3478 * to force the next bit of code to free the buffer
3479 * for us.
3480 */
3481 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
3482 (bf->bf_flags & ATH_BUF_BUSY)) {
3483 struct ath_buf *nbf;
3484 nbf = ath_tx_retry_clone(sc, an, atid, bf);
3485 if (nbf)
3486 /* bf has been freed at this point */
3487 bf = nbf;
3488 else
3489 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
3490 }
3491
3492 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
3493 sc->sc_stats.ast_tx_swretrymax++;
3494 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
3495 "%s: max retries: seqno %d\n",
3496 __func__, SEQNO(bf->bf_state.bfs_seqno));
3497 ath_tx_update_baw(sc, an, atid, bf);
3498 if (! bf->bf_state.bfs_addedbaw)
3499 device_printf(sc->sc_dev,
3500 "%s: wasn't added: seqno %d\n",
3501 __func__, SEQNO(bf->bf_state.bfs_seqno));
3502 bf->bf_state.bfs_dobaw = 0;
3503 return 1;
3504 }
3505
3506 ath_tx_set_retry(sc, bf);
3507 bf->bf_next = NULL; /* Just to make sure */
3508
3509 /* Clear the aggregate state */
3510 bf->bf_state.bfs_aggr = 0;
3511 bf->bf_state.bfs_ndelim = 0; /* ??? needed? */
3512 bf->bf_state.bfs_nframes = 1;
3513
3514 TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3515 return 0;
3516}
3517
3518/*
3519 * error pkt completion for an aggregate destination
3520 */
3521static void
3522ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first,
3523 struct ath_tid *tid)
3524{
3525 struct ieee80211_node *ni = bf_first->bf_node;
3526 struct ath_node *an = ATH_NODE(ni);
3527 struct ath_buf *bf_next, *bf;
3528 ath_bufhead bf_q;
3529 int drops = 0;
3530 struct ieee80211_tx_ampdu *tap;
3531 ath_bufhead bf_cq;
3532
3533 TAILQ_INIT(&bf_q);
3534 TAILQ_INIT(&bf_cq);
3535
3536 /*
3537 * Update rate control - all frames have failed.
3538 *
3539 * XXX use the length in the first frame in the series;
3540 * XXX just so things are consistent for now.
3541 */
3542 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc,
3543 &bf_first->bf_status.ds_txstat,
3544 bf_first->bf_state.bfs_pktlen,
3545 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes);
3546
3547 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]);
3548 tap = ath_tx_get_tx_tid(an, tid->tid);
3549 sc->sc_stats.ast_tx_aggr_failall++;
3550
3551 /* Retry all subframes */
3552 bf = bf_first;
3553 while (bf) {
3554 bf_next = bf->bf_next;
3555 bf->bf_next = NULL; /* Remove it from the aggr list */
3556 sc->sc_stats.ast_tx_aggr_fail++;
3557 if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
3558 drops++;
3559 bf->bf_next = NULL;
3560 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3561 }
3562 bf = bf_next;
3563 }
3564
3565 /* Prepend all frames to the beginning of the queue */
3566 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
3567 TAILQ_REMOVE(&bf_q, bf, bf_list);
3568 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list);
3569 }
3570
3571 /*
3572 * Schedule the TID to be re-tried.
3573 */
3574 ath_tx_tid_sched(sc, tid);
3575
3576 /*
3577 * send bar if we dropped any frames
3578 *
3579 * Keep the txq lock held for now, as we need to ensure
3580 * that ni_txseqs[] is consistent (as it's being updated
3581 * in the ifnet TX context or raw TX context.)
3582 */
3583 if (drops) {
3584 /* Suspend the TX queue and get ready to send the BAR */
3585 ath_tx_tid_bar_suspend(sc, tid);
3586 }
3587
3588 /*
3589 * Send BAR if required
3590 */
3591 if (ath_tx_tid_bar_tx_ready(sc, tid))
3592 ath_tx_tid_bar_tx(sc, tid);
3593 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]);
3594
3595 /* Complete frames which errored out */
3596 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3597 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3598 ath_tx_default_comp(sc, bf, 0);
3599 }
3600}
3601
3602/*
3603 * Handle clean-up of packets from an aggregate list.
3604 *
3605 * There's no need to update the BAW here - the session is being
3606 * torn down.
3607 */
3608static void
3609ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first)
3610{
3611 struct ath_buf *bf, *bf_next;
3612 struct ieee80211_node *ni = bf_first->bf_node;
3613 struct ath_node *an = ATH_NODE(ni);
3614 int tid = bf_first->bf_state.bfs_tid;
3615 struct ath_tid *atid = &an->an_tid[tid];
3616
3617 bf = bf_first;
3618
3619 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3620
3621 /* update incomp */
3622 while (bf) {
3623 atid->incomp--;
3624 bf = bf->bf_next;
3625 }
3626
3627 if (atid->incomp == 0) {
3628 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3629 "%s: TID %d: cleaned up! resume!\n",
3630 __func__, tid);
3631 atid->cleanup_inprogress = 0;
3632 ath_tx_tid_resume(sc, atid);
3633 }
3634
3635 /* Send BAR if required */
3636 if (ath_tx_tid_bar_tx_ready(sc, atid))
3637 ath_tx_tid_bar_tx(sc, atid);
3638 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3639
3640 /* Handle frame completion */
3641 while (bf) {
3642 bf_next = bf->bf_next;
3643 ath_tx_default_comp(sc, bf, 1);
3644 bf = bf_next;
3645 }
3646}
3647
3648/*
3649 * Handle completion of an set of aggregate frames.
3650 *
3651 * XXX for now, simply complete each sub-frame.
3652 *
3653 * Note: the completion handler is the last descriptor in the aggregate,
3654 * not the last descriptor in the first frame.
3655 */
3656static void
3657ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first,
3658 int fail)
3659{
3660 //struct ath_desc *ds = bf->bf_lastds;
3661 struct ieee80211_node *ni = bf_first->bf_node;
3662 struct ath_node *an = ATH_NODE(ni);
3663 int tid = bf_first->bf_state.bfs_tid;
3664 struct ath_tid *atid = &an->an_tid[tid];
3665 struct ath_tx_status ts;
3666 struct ieee80211_tx_ampdu *tap;
3667 ath_bufhead bf_q;
3668 ath_bufhead bf_cq;
3669 int seq_st, tx_ok;
3670 int hasba, isaggr;
3671 uint32_t ba[2];
3672 struct ath_buf *bf, *bf_next;
3673 int ba_index;
3674 int drops = 0;
3675 int nframes = 0, nbad = 0, nf;
3676 int pktlen;
3677 /* XXX there's too much on the stack? */
3678 struct ath_rc_series rc[ATH_RC_NUM];
3679 int txseq;
3680
3681 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n",
3682 __func__, atid->hwq_depth);
3683
3684 /* The TID state is kept behind the TXQ lock */
3685 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3686
3687 atid->hwq_depth--;
3688 if (atid->hwq_depth < 0)
3689 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3690 __func__, atid->hwq_depth);
3691
3692 /*
3693 * Punt cleanup to the relevant function, not our problem now
3694 */
3695 if (atid->cleanup_inprogress) {
3696 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3697 ath_tx_comp_cleanup_aggr(sc, bf_first);
3698 return;
3699 }
3700
3701 /*
3702 * Take a copy; this may be needed -after- bf_first
3703 * has been completed and freed.
3704 */
3705 ts = bf_first->bf_status.ds_txstat;
3706 /*
3707 * XXX for now, use the first frame in the aggregate for
3708 * XXX rate control completion; it's at least consistent.
3709 */
3710 pktlen = bf_first->bf_state.bfs_pktlen;
3711
3712 /*
3713 * Handle errors first!
3714 *
3715 * Here, handle _any_ error as a "exceeded retries" error.
3716 * Later on (when filtered frames are to be specially handled)
3717 * it'll have to be expanded.
3718 */
3719#if 0
3720 if (ts.ts_status & HAL_TXERR_XRETRY) {
3721#endif
3722 if (ts.ts_status != 0) {
3723 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3724 ath_tx_comp_aggr_error(sc, bf_first, atid);
3725 return;
3726 }
3727
3728 TAILQ_INIT(&bf_q);
3729 TAILQ_INIT(&bf_cq);
3730 tap = ath_tx_get_tx_tid(an, tid);
3731
3732 /*
3733 * extract starting sequence and block-ack bitmap
3734 */
3735 /* XXX endian-ness of seq_st, ba? */
3736 seq_st = ts.ts_seqnum;
3737 hasba = !! (ts.ts_flags & HAL_TX_BA);
3738 tx_ok = (ts.ts_status == 0);
3739 isaggr = bf_first->bf_state.bfs_aggr;
3740 ba[0] = ts.ts_ba_low;
3741 ba[1] = ts.ts_ba_high;
3742
3743 /*
3744 * Copy the TX completion status and the rate control
3745 * series from the first descriptor, as it may be freed
3746 * before the rate control code can get its grubby fingers
3747 * into things.
3748 */
3749 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc));
3750
3751 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3752 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, "
3753 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n",
3754 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags,
3755 isaggr, seq_st, hasba, ba[0], ba[1]);
3756
3757 /* Occasionally, the MAC sends a tx status for the wrong TID. */
3758 if (tid != ts.ts_tid) {
3759 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n",
3760 __func__, tid, ts.ts_tid);
3761 tx_ok = 0;
3762 }
3763
3764 /* AR5416 BA bug; this requires an interface reset */
3765 if (isaggr && tx_ok && (! hasba)) {
3766 device_printf(sc->sc_dev,
3767 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, "
3768 "seq_st=%d\n",
3769 __func__, hasba, tx_ok, isaggr, seq_st);
3770 /* XXX TODO: schedule an interface reset */
3771#ifdef ATH_DEBUG
3772 ath_printtxbuf(sc, bf_first,
3773 sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0);
3774#endif
3775 }
3776
3777 /*
3778 * Walk the list of frames, figure out which ones were correctly
3779 * sent and which weren't.
3780 */
3781 bf = bf_first;
3782 nf = bf_first->bf_state.bfs_nframes;
3783
3784 /* bf_first is going to be invalid once this list is walked */
3785 bf_first = NULL;
3786
3787 /*
3788 * Walk the list of completed frames and determine
3789 * which need to be completed and which need to be
3790 * retransmitted.
3791 *
3792 * For completed frames, the completion functions need
3793 * to be called at the end of this function as the last
3794 * node reference may free the node.
3795 *
3796 * Finally, since the TXQ lock can't be held during the
3797 * completion callback (to avoid lock recursion),
3798 * the completion calls have to be done outside of the
3799 * lock.
3800 */
3801 while (bf) {
3802 nframes++;
3803 ba_index = ATH_BA_INDEX(seq_st,
3804 SEQNO(bf->bf_state.bfs_seqno));
3805 bf_next = bf->bf_next;
3806 bf->bf_next = NULL; /* Remove it from the aggr list */
3807
3808 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3809 "%s: checking bf=%p seqno=%d; ack=%d\n",
3810 __func__, bf, SEQNO(bf->bf_state.bfs_seqno),
3811 ATH_BA_ISSET(ba, ba_index));
3812
3813 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
3814 sc->sc_stats.ast_tx_aggr_ok++;
3815 ath_tx_update_baw(sc, an, atid, bf);
3816 bf->bf_state.bfs_dobaw = 0;
3817 if (! bf->bf_state.bfs_addedbaw)
3818 device_printf(sc->sc_dev,
3819 "%s: wasn't added: seqno %d\n",
3820 __func__, SEQNO(bf->bf_state.bfs_seqno));
3821 bf->bf_next = NULL;
3822 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3823 } else {
3824 sc->sc_stats.ast_tx_aggr_fail++;
3825 if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
3826 drops++;
3827 bf->bf_next = NULL;
3828 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3829 }
3830 nbad++;
3831 }
3832 bf = bf_next;
3833 }
3834
3835 /*
3836 * Now that the BAW updates have been done, unlock
3837 *
3838 * txseq is grabbed before the lock is released so we
3839 * have a consistent view of what -was- in the BAW.
3840 * Anything after this point will not yet have been
3841 * TXed.
3842 */
3843 txseq = tap->txa_start;
3844 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3845
3846 if (nframes != nf)
3847 device_printf(sc->sc_dev,
3848 "%s: num frames seen=%d; bf nframes=%d\n",
3849 __func__, nframes, nf);
3850
3851 /*
3852 * Now we know how many frames were bad, call the rate
3853 * control code.
3854 */
3855 if (fail == 0)
3856 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes,
3857 nbad);
3858
3859 /*
3860 * send bar if we dropped any frames
3861 */
3862 if (drops) {
3863 /* Suspend the TX queue and get ready to send the BAR */
3864 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3865 ath_tx_tid_bar_suspend(sc, atid);
3866 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3867 }
3868
3869 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
3870 "%s: txa_start now %d\n", __func__, tap->txa_start);
3871
3872 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3873
3874 /* Prepend all frames to the beginning of the queue */
3875 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
3876 TAILQ_REMOVE(&bf_q, bf, bf_list);
3877 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list);
3878 }
3879
3880 /*
3881 * Reschedule to grab some further frames.
3882 */
3883 ath_tx_tid_sched(sc, atid);
3884
3885 /*
3886 * Send BAR if required
3887 */
3888 if (ath_tx_tid_bar_tx_ready(sc, atid))
3889 ath_tx_tid_bar_tx(sc, atid);
3890
3891 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3892
3893 /* Do deferred completion */
3894 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3895 TAILQ_REMOVE(&bf_cq, bf, bf_list);
3896 ath_tx_default_comp(sc, bf, 0);
3897 }
3898}
3899
3900/*
3901 * Handle completion of unaggregated frames in an ADDBA
3902 * session.
3903 *
3904 * Fail is set to 1 if the entry is being freed via a call to
3905 * ath_tx_draintxq().
3906 */
3907static void
3908ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail)
3909{
3910 struct ieee80211_node *ni = bf->bf_node;
3911 struct ath_node *an = ATH_NODE(ni);
3912 int tid = bf->bf_state.bfs_tid;
3913 struct ath_tid *atid = &an->an_tid[tid];
3914 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3915
3916 /*
3917 * Update rate control status here, before we possibly
3918 * punt to retry or cleanup.
3919 *
3920 * Do it outside of the TXQ lock.
3921 */
3922 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0))
3923 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
3924 &bf->bf_status.ds_txstat,
3925 bf->bf_state.bfs_pktlen,
3926 1, (ts->ts_status == 0) ? 0 : 1);
3927
3928 /*
3929 * This is called early so atid->hwq_depth can be tracked.
3930 * This unfortunately means that it's released and regrabbed
3931 * during retry and cleanup. That's rather inefficient.
3932 */
3933 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
3934
3935 if (tid == IEEE80211_NONQOS_TID)
3936 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__);
3937
3938 DPRINTF(sc, ATH_DEBUG_SW_TX,
3939 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n",
3940 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth,
3941 SEQNO(bf->bf_state.bfs_seqno));
3942
3943 atid->hwq_depth--;
3944 if (atid->hwq_depth < 0)
3945 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3946 __func__, atid->hwq_depth);
3947
3948 /*
3949 * If a cleanup is in progress, punt to comp_cleanup;
3950 * rather than handling it here. It's thus their
3951 * responsibility to clean up, call the completion
3952 * function in net80211, etc.
3953 */
3954 if (atid->cleanup_inprogress) {
3955 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3956 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n",
3957 __func__);
3958 ath_tx_comp_cleanup_unaggr(sc, bf);
3959 return;
3960 }
3961
3962 /*
3963 * Don't bother with the retry check if all frames
3964 * are being failed (eg during queue deletion.)
3965 */
3966#if 0
3967 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) {
3968#endif
3969 if (fail == 0 && ts->ts_status != 0) {
3970 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3971 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n",
3972 __func__);
3973 ath_tx_aggr_retry_unaggr(sc, bf);
3974 return;
3975 }
3976
3977 /* Success? Complete */
3978 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n",
3979 __func__, tid, SEQNO(bf->bf_state.bfs_seqno));
3980 if (bf->bf_state.bfs_dobaw) {
3981 ath_tx_update_baw(sc, an, atid, bf);
3982 bf->bf_state.bfs_dobaw = 0;
3983 if (! bf->bf_state.bfs_addedbaw)
3984 device_printf(sc->sc_dev,
3985 "%s: wasn't added: seqno %d\n",
3986 __func__, SEQNO(bf->bf_state.bfs_seqno));
3987 }
3988
3989 /*
3990 * Send BAR if required
3991 */
3992 if (ath_tx_tid_bar_tx_ready(sc, atid))
3993 ath_tx_tid_bar_tx(sc, atid);
3994
3995 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
3996
3997 ath_tx_default_comp(sc, bf, fail);
3998 /* bf is freed at this point */
3999}
4000
4001void
4002ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4003{
4004 if (bf->bf_state.bfs_aggr)
4005 ath_tx_aggr_comp_aggr(sc, bf, fail);
4006 else
4007 ath_tx_aggr_comp_unaggr(sc, bf, fail);
4008}
4009
4010/*
4011 * Schedule some packets from the given node/TID to the hardware.
4012 *
4013 * This is the aggregate version.
4014 */
4015void
4016ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an,
4017 struct ath_tid *tid)
4018{
4019 struct ath_buf *bf;
4020 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
4021 struct ieee80211_tx_ampdu *tap;
4022 ATH_AGGR_STATUS status;
4023 ath_bufhead bf_q;
4024
4025 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid);
4026 ATH_TXQ_LOCK_ASSERT(txq);
4027
4028 tap = ath_tx_get_tx_tid(an, tid->tid);
4029
4030 if (tid->tid == IEEE80211_NONQOS_TID)
4031 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n",
4032 __func__);
4033
4034 for (;;) {
4035 status = ATH_AGGR_DONE;
4036
4037 /*
4038 * If the upper layer has paused the TID, don't
4039 * queue any further packets.
4040 *
4041 * This can also occur from the completion task because
4042 * of packet loss; but as its serialised with this code,
4043 * it won't "appear" half way through queuing packets.
4044 */
4045 if (tid->paused)
4046 break;
4047
4048 bf = TAILQ_FIRST(&tid->axq_q);
4049 if (bf == NULL) {
4050 break;
4051 }
4052
4053 /*
4054 * If the packet doesn't fall within the BAW (eg a NULL
4055 * data frame), schedule it directly; continue.
4056 */
4057 if (! bf->bf_state.bfs_dobaw) {
4058 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4059 "%s: non-baw packet\n",
4060 __func__);
4061 ATH_TXQ_REMOVE(tid, bf, bf_list);
4062
4063 if (bf->bf_state.bfs_nframes > 1)
4064 device_printf(sc->sc_dev,
4065 "%s: aggr=%d, nframes=%d\n",
4066 __func__,
4067 bf->bf_state.bfs_aggr,
4068 bf->bf_state.bfs_nframes);
4069
4070 /*
4071 * This shouldn't happen - such frames shouldn't
4072 * ever have been queued as an aggregate in the
4073 * first place. However, make sure the fields
4074 * are correctly setup just to be totally sure.
4075 */
4076 bf->bf_state.bfs_aggr = 0;
4077 bf->bf_state.bfs_nframes = 1;
4078
4079 ath_tx_do_ratelookup(sc, bf);
4080 ath_tx_calc_duration(sc, bf);
4081 ath_tx_calc_protection(sc, bf);
4082 ath_tx_set_rtscts(sc, bf);
4083 ath_tx_rate_fill_rcflags(sc, bf);
4084 ath_tx_setds(sc, bf);
4085 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
4086
4087 sc->sc_aggr_stats.aggr_nonbaw_pkt++;
4088
4089 /* Queue the packet; continue */
4090 goto queuepkt;
4091 }
4092
4093 TAILQ_INIT(&bf_q);
4094
4095 /*
4096 * Do a rate control lookup on the first frame in the
4097 * list. The rate control code needs that to occur
4098 * before it can determine whether to TX.
4099 * It's inaccurate because the rate control code doesn't
4100 * really "do" aggregate lookups, so it only considers
4101 * the size of the first frame.
4102 */
4103 ath_tx_do_ratelookup(sc, bf);
4104 bf->bf_state.bfs_rc[3].rix = 0;
4105 bf->bf_state.bfs_rc[3].tries = 0;
4106
4107 ath_tx_calc_duration(sc, bf);
4108 ath_tx_calc_protection(sc, bf);
4109
4110 ath_tx_set_rtscts(sc, bf);
4111 ath_tx_rate_fill_rcflags(sc, bf);
4112
4113 status = ath_tx_form_aggr(sc, an, tid, &bf_q);
4114
4115 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4116 "%s: ath_tx_form_aggr() status=%d\n", __func__, status);
4117
4118 /*
4119 * No frames to be picked up - out of BAW
4120 */
4121 if (TAILQ_EMPTY(&bf_q))
4122 break;
4123
4124 /*
4125 * This assumes that the descriptor list in the ath_bufhead
4126 * are already linked together via bf_next pointers.
4127 */
4128 bf = TAILQ_FIRST(&bf_q);
4129
4130 if (status == ATH_AGGR_8K_LIMITED)
4131 sc->sc_aggr_stats.aggr_rts_aggr_limited++;
4132
4133 /*
4134 * If it's the only frame send as non-aggregate
4135 * assume that ath_tx_form_aggr() has checked
4136 * whether it's in the BAW and added it appropriately.
4137 */
4138 if (bf->bf_state.bfs_nframes == 1) {
4139 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4140 "%s: single-frame aggregate\n", __func__);
4141 bf->bf_state.bfs_aggr = 0;
4142 bf->bf_state.bfs_ndelim = 0;
4143 ath_tx_setds(sc, bf);
4144 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
4145 if (status == ATH_AGGR_BAW_CLOSED)
4146 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++;
4147 else
4148 sc->sc_aggr_stats.aggr_single_pkt++;
4149 } else {
4150 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4151 "%s: multi-frame aggregate: %d frames, "
4152 "length %d\n",
4153 __func__, bf->bf_state.bfs_nframes,
4154 bf->bf_state.bfs_al);
4155 bf->bf_state.bfs_aggr = 1;
4156 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++;
4157 sc->sc_aggr_stats.aggr_aggr_pkt++;
4158
4159 /*
4160 * Calculate the duration/protection as required.
4161 */
4162 ath_tx_calc_duration(sc, bf);
4163 ath_tx_calc_protection(sc, bf);
4164
4165 /*
4166 * Update the rate and rtscts information based on the
4167 * rate decision made by the rate control code;
4168 * the first frame in the aggregate needs it.
4169 */
4170 ath_tx_set_rtscts(sc, bf);
4171
4172 /*
4173 * Setup the relevant descriptor fields
4174 * for aggregation. The first descriptor
4175 * already points to the rest in the chain.
4176 */
4177 ath_tx_setds_11n(sc, bf);
4178
4179 }
4180 queuepkt:
4181 //txq = bf->bf_state.bfs_txq;
4182
4183 /* Set completion handler, multi-frame aggregate or not */
4184 bf->bf_comp = ath_tx_aggr_comp;
4185
4186 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID)
4187 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__);
4188
4189 /* Punt to txq */
4190 ath_tx_handoff(sc, txq, bf);
4191
4192 /* Track outstanding buffer count to hardware */
4193 /* aggregates are "one" buffer */
4194 tid->hwq_depth++;
4195
4196 /*
4197 * Break out if ath_tx_form_aggr() indicated
4198 * there can't be any further progress (eg BAW is full.)
4199 * Checking for an empty txq is done above.
4200 *
4201 * XXX locking on txq here?
4202 */
4203 if (txq->axq_aggr_depth >= sc->sc_hwq_limit ||
4204 status == ATH_AGGR_BAW_CLOSED)
4205 break;
4206 }
4207}
4208
4209/*
4210 * Schedule some packets from the given node/TID to the hardware.
4211 */
4212void
4213ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an,
4214 struct ath_tid *tid)
4215{
4216 struct ath_buf *bf;
4217 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
4218
4219 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n",
4220 __func__, an, tid->tid);
4221
4222 ATH_TXQ_LOCK_ASSERT(txq);
4223
4224 /* Check - is AMPDU pending or running? then print out something */
4225 if (ath_tx_ampdu_pending(sc, an, tid->tid))
4226 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n",
4227 __func__, tid->tid);
4228 if (ath_tx_ampdu_running(sc, an, tid->tid))
4229 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n",
4230 __func__, tid->tid);
4231
4232 for (;;) {
4233
4234 /*
4235 * If the upper layers have paused the TID, don't
4236 * queue any further packets.
4237 */
4238 if (tid->paused)
4239 break;
4240
4241 bf = TAILQ_FIRST(&tid->axq_q);
4242 if (bf == NULL) {
4243 break;
4244 }
4245
4246 ATH_TXQ_REMOVE(tid, bf, bf_list);
4247
4248 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n"));
4249
4250 /* Sanity check! */
4251 if (tid->tid != bf->bf_state.bfs_tid) {
4252 device_printf(sc->sc_dev, "%s: bfs_tid %d !="
4253 " tid %d\n",
4254 __func__, bf->bf_state.bfs_tid, tid->tid);
4255 }
4256 /* Normal completion handler */
4257 bf->bf_comp = ath_tx_normal_comp;
4258
4259 /* Program descriptors + rate control */
4260 ath_tx_do_ratelookup(sc, bf);
4261 ath_tx_calc_duration(sc, bf);
4262 ath_tx_calc_protection(sc, bf);
4263 ath_tx_set_rtscts(sc, bf);
4264 ath_tx_rate_fill_rcflags(sc, bf);
4265 ath_tx_setds(sc, bf);
4266
4267 /* Track outstanding buffer count to hardware */
4268 /* aggregates are "one" buffer */
4269 tid->hwq_depth++;
4270
4271 /* Punt to hardware or software txq */
4272 ath_tx_handoff(sc, txq, bf);
4273 }
4274}
4275
4276/*
4277 * Schedule some packets to the given hardware queue.
4278 *
4279 * This function walks the list of TIDs (ie, ath_node TIDs
4280 * with queued traffic) and attempts to schedule traffic
4281 * from them.
4282 *
4283 * TID scheduling is implemented as a FIFO, with TIDs being
4284 * added to the end of the queue after some frames have been
4285 * scheduled.
4286 */
4287void
4288ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq)
4289{
4290 struct ath_tid *tid, *next, *last;
4291
4292 ATH_TXQ_LOCK_ASSERT(txq);
4293
4294 /*
4295 * Don't schedule if the hardware queue is busy.
4296 * This (hopefully) gives some more time to aggregate
4297 * some packets in the aggregation queue.
4298 */
4299 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
4300 sc->sc_aggr_stats.aggr_sched_nopkt++;
4301 return;
4302 }
4303
4304 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s);
4305
4306 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) {
4307 /*
4308 * Suspend paused queues here; they'll be resumed
4309 * once the addba completes or times out.
4310 */
4311 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n",
4312 __func__, tid->tid, tid->paused);
4313 ath_tx_tid_unsched(sc, tid);
4314 if (tid->paused) {
4315 continue;
4316 }
4317 if (ath_tx_ampdu_running(sc, tid->an, tid->tid))
4318 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid);
4319 else
4320 ath_tx_tid_hw_queue_norm(sc, tid->an, tid);
4321
4322 /* Not empty? Re-schedule */
4323 if (tid->axq_depth != 0)
4324 ath_tx_tid_sched(sc, tid);
4325
4326 /* Give the software queue time to aggregate more packets */
4327 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
4328 break;
4329 }
4330
4331 /*
4332 * If this was the last entry on the original list, stop.
4333 * Otherwise nodes that have been rescheduled onto the end
4334 * of the TID FIFO list will just keep being rescheduled.
4335 */
4336 if (tid == last)
4337 break;
4338 }
4339}
4340
4341/*
4342 * TX addba handling
4343 */
4344
4345/*
4346 * Return net80211 TID struct pointer, or NULL for none
4347 */
4348struct ieee80211_tx_ampdu *
4349ath_tx_get_tx_tid(struct ath_node *an, int tid)
4350{
4351 struct ieee80211_node *ni = &an->an_node;
4352 struct ieee80211_tx_ampdu *tap;
4353
4354 if (tid == IEEE80211_NONQOS_TID)
4355 return NULL;
4356
4357 tap = &ni->ni_tx_ampdu[tid];
4358 return tap;
4359}
4360
4361/*
4362 * Is AMPDU-TX running?
4363 */
4364static int
4365ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid)
4366{
4367 struct ieee80211_tx_ampdu *tap;
4368
4369 if (tid == IEEE80211_NONQOS_TID)
4370 return 0;
4371
4372 tap = ath_tx_get_tx_tid(an, tid);
4373 if (tap == NULL)
4374 return 0; /* Not valid; default to not running */
4375
4376 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING);
4377}
4378
4379/*
4380 * Is AMPDU-TX negotiation pending?
4381 */
4382static int
4383ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid)
4384{
4385 struct ieee80211_tx_ampdu *tap;
4386
4387 if (tid == IEEE80211_NONQOS_TID)
4388 return 0;
4389
4390 tap = ath_tx_get_tx_tid(an, tid);
4391 if (tap == NULL)
4392 return 0; /* Not valid; default to not pending */
4393
4394 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND);
4395}
4396
4397/*
4398 * Is AMPDU-TX pending for the given TID?
4399 */
4400
4401
4402/*
4403 * Method to handle sending an ADDBA request.
4404 *
4405 * We tap this so the relevant flags can be set to pause the TID
4406 * whilst waiting for the response.
4407 *
4408 * XXX there's no timeout handler we can override?
4409 */
4410int
4411ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
4412 int dialogtoken, int baparamset, int batimeout)
4413{
4414 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4415 int tid = tap->txa_tid;
4416 struct ath_node *an = ATH_NODE(ni);
4417 struct ath_tid *atid = &an->an_tid[tid];
4418
4419 /*
4420 * XXX danger Will Robinson!
4421 *
4422 * Although the taskqueue may be running and scheduling some more
4423 * packets, these should all be _before_ the addba sequence number.
4424 * However, net80211 will keep self-assigning sequence numbers
4425 * until addba has been negotiated.
4426 *
4427 * In the past, these packets would be "paused" (which still works
4428 * fine, as they're being scheduled to the driver in the same
4429 * serialised method which is calling the addba request routine)
4430 * and when the aggregation session begins, they'll be dequeued
4431 * as aggregate packets and added to the BAW. However, now there's
4432 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these
4433 * packets. Thus they never get included in the BAW tracking and
4434 * this can cause the initial burst of packets after the addba
4435 * negotiation to "hang", as they quickly fall outside the BAW.
4436 *
4437 * The "eventual" solution should be to tag these packets with
4438 * dobaw. Although net80211 has given us a sequence number,
4439 * it'll be "after" the left edge of the BAW and thus it'll
4440 * fall within it.
4441 */
4442 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4443 /*
4444 * This is a bit annoying. Until net80211 HT code inherits some
4445 * (any) locking, we may have this called in parallel BUT only
4446 * one response/timeout will be called. Grr.
4447 */
4448 if (atid->addba_tx_pending == 0) {
4449 ath_tx_tid_pause(sc, atid);
4450 atid->addba_tx_pending = 1;
4451 }
4452 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4453
4454 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4455 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n",
4456 __func__, dialogtoken, baparamset, batimeout);
4457 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4458 "%s: txa_start=%d, ni_txseqs=%d\n",
4459 __func__, tap->txa_start, ni->ni_txseqs[tid]);
4460
4461 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
4462 batimeout);
4463}
4464
4465/*
4466 * Handle an ADDBA response.
4467 *
4468 * We unpause the queue so TX'ing can resume.
4469 *
4470 * Any packets TX'ed from this point should be "aggregate" (whether
4471 * aggregate or not) so the BAW is updated.
4472 *
4473 * Note! net80211 keeps self-assigning sequence numbers until
4474 * ampdu is negotiated. This means the initially-negotiated BAW left
4475 * edge won't match the ni->ni_txseq.
4476 *
4477 * So, being very dirty, the BAW left edge is "slid" here to match
4478 * ni->ni_txseq.
4479 *
4480 * What likely SHOULD happen is that all packets subsequent to the
4481 * addba request should be tagged as aggregate and queued as non-aggregate
4482 * frames; thus updating the BAW. For now though, I'll just slide the
4483 * window.
4484 */
4485int
4486ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
4487 int status, int code, int batimeout)
4488{
4489 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4490 int tid = tap->txa_tid;
4491 struct ath_node *an = ATH_NODE(ni);
4492 struct ath_tid *atid = &an->an_tid[tid];
4493 int r;
4494
4495 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4496 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__,
4497 status, code, batimeout);
4498
4499 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4500 "%s: txa_start=%d, ni_txseqs=%d\n",
4501 __func__, tap->txa_start, ni->ni_txseqs[tid]);
4502
4503 /*
4504 * Call this first, so the interface flags get updated
4505 * before the TID is unpaused. Otherwise a race condition
4506 * exists where the unpaused TID still doesn't yet have
4507 * IEEE80211_AGGR_RUNNING set.
4508 */
4509 r = sc->sc_addba_response(ni, tap, status, code, batimeout);
4510
4511 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4512 atid->addba_tx_pending = 0;
4513 /*
4514 * XXX dirty!
4515 * Slide the BAW left edge to wherever net80211 left it for us.
4516 * Read above for more information.
4517 */
4518 tap->txa_start = ni->ni_txseqs[tid];
4519 ath_tx_tid_resume(sc, atid);
4520 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4521 return r;
4522}
4523
4524
4525/*
4526 * Stop ADDBA on a queue.
4527 *
4528 * This can be called whilst BAR TX is currently active on the queue,
4529 * so make sure this is unblocked before continuing.
4530 */
4531void
4532ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
4533{
4534 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4535 int tid = tap->txa_tid;
4536 struct ath_node *an = ATH_NODE(ni);
4537 struct ath_tid *atid = &an->an_tid[tid];
4538
4539 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__);
4540
4541 /*
4542 * Pause TID traffic early, so there aren't any races
4543 * Unblock the pending BAR held traffic, if it's currently paused.
4544 */
4545 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4546 ath_tx_tid_pause(sc, atid);
4547 if (atid->bar_wait) {
4548 /*
4549 * bar_unsuspend() expects bar_tx == 1, as it should be
4550 * called from the TX completion path. This quietens
4551 * the warning. It's cleared for us anyway.
4552 */
4553 atid->bar_tx = 1;
4554 ath_tx_tid_bar_unsuspend(sc, atid);
4555 }
4556 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4557
4558 /* There's no need to hold the TXQ lock here */
4559 sc->sc_addba_stop(ni, tap);
4560
4561 /*
4562 * ath_tx_tid_cleanup will resume the TID if possible, otherwise
4563 * it'll set the cleanup flag, and it'll be unpaused once
4564 * things have been cleaned up.
4565 */
4566 ath_tx_tid_cleanup(sc, an, tid);
4567}
4568
4569/*
4570 * Note: net80211 bar_timeout() doesn't call this function on BAR failure;
4571 * it simply tears down the aggregation session. Ew.
4572 *
4573 * It however will call ieee80211_ampdu_stop() which will call
4574 * ic->ic_addba_stop().
4575 *
4576 * XXX This uses a hard-coded max BAR count value; the whole
4577 * XXX BAR TX success or failure should be better handled!
4578 */
4579void
4580ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
4581 int status)
4582{
4583 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4584 int tid = tap->txa_tid;
4585 struct ath_node *an = ATH_NODE(ni);
4586 struct ath_tid *atid = &an->an_tid[tid];
4587 int attempts = tap->txa_attempts;
4588
4589 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
4590 "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n",
4591 __func__,
4592 tap,
4593 atid,
4594 tap->txa_tid,
4595 atid->tid,
4596 status,
4597 attempts);
4598
4599 /* Note: This may update the BAW details */
4600 sc->sc_bar_response(ni, tap, status);
4601
4602 /* Unpause the TID */
4603 /*
4604 * XXX if this is attempt=50, the TID will be downgraded
4605 * XXX to a non-aggregate session. So we must unpause the
4606 * XXX TID here or it'll never be done.
4607 */
4608 if (status == 0 || attempts == 50) {
4609 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4610 ath_tx_tid_bar_unsuspend(sc, atid);
4611 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4612 }
4613}
4614
4615/*
4616 * This is called whenever the pending ADDBA request times out.
4617 * Unpause and reschedule the TID.
4618 */
4619void
4620ath_addba_response_timeout(struct ieee80211_node *ni,
4621 struct ieee80211_tx_ampdu *tap)
4622{
4623 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
4624 int tid = tap->txa_tid;
4625 struct ath_node *an = ATH_NODE(ni);
4626 struct ath_tid *atid = &an->an_tid[tid];
4627
4628 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4629 "%s: called; resuming\n", __func__);
4630
4631 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4632 atid->addba_tx_pending = 0;
4633 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4634
4635 /* Note: This updates the aggregate state to (again) pending */
4636 sc->sc_addba_response_timeout(ni, tap);
4637
4638 /* Unpause the TID; which reschedules it */
4639 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]);
4640 ath_tx_tid_resume(sc, atid);
4641 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]);
4642}
4643
4644static int
4645ath_legacy_dma_txsetup(struct ath_softc *sc)
4646{
4647
4648 /* nothing new needed */
4649 return (0);
4650}
4651
4652static int
4653ath_legacy_dma_txteardown(struct ath_softc *sc)
4654{
4655
4656 /* nothing new needed */
4657 return (0);
4658}
4659
4660void
4661ath_xmit_setup_legacy(struct ath_softc *sc)
4662{
4663 /*
4664 * For now, just set the descriptor length to sizeof(ath_desc);
4665 * worry about extracting the real length out of the HAL later.
4666 */
4667 sc->sc_tx_desclen = sizeof(struct ath_desc);
4668 sc->sc_tx_statuslen = 0;
4669 sc->sc_tx_nmaps = 1; /* only one buffer per TX desc */
4670
4671 sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup;
4672 sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown;
4673 sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func;
4674
4675 sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart;
4676 sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff;
4677
4678 sc->sc_tx.xmit_drain = ath_legacy_tx_drain;
4679}