32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42/*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49#include "opt_ah.h"
50#include "opt_wlan.h"
51
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/sysctl.h>
55#include <sys/mbuf.h>
56#include <sys/malloc.h>
57#include <sys/lock.h>
58#include <sys/mutex.h>
59#include <sys/kernel.h>
60#include <sys/socket.h>
61#include <sys/sockio.h>
62#include <sys/errno.h>
63#include <sys/callout.h>
64#include <sys/bus.h>
65#include <sys/endian.h>
66#include <sys/kthread.h>
67#include <sys/taskqueue.h>
68#include <sys/priv.h>
69#include <sys/module.h>
70#include <sys/ktr.h>
71#include <sys/smp.h> /* for mp_ncpus */
72
73#include <machine/bus.h>
74
75#include <net/if.h>
76#include <net/if_dl.h>
77#include <net/if_media.h>
78#include <net/if_types.h>
79#include <net/if_arp.h>
80#include <net/ethernet.h>
81#include <net/if_llc.h>
82
83#include <net80211/ieee80211_var.h>
84#include <net80211/ieee80211_regdomain.h>
85#ifdef IEEE80211_SUPPORT_SUPERG
86#include <net80211/ieee80211_superg.h>
87#endif
88#ifdef IEEE80211_SUPPORT_TDMA
89#include <net80211/ieee80211_tdma.h>
90#endif
91
92#include <net/bpf.h>
93
94#ifdef INET
95#include <netinet/in.h>
96#include <netinet/if_ether.h>
97#endif
98
99#include <dev/ath/if_athvar.h>
100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101#include <dev/ath/ath_hal/ah_diagcodes.h>
102
103#include <dev/ath/if_ath_debug.h>
104#include <dev/ath/if_ath_misc.h>
105#include <dev/ath/if_ath_tsf.h>
106#include <dev/ath/if_ath_tx.h>
107#include <dev/ath/if_ath_sysctl.h>
108#include <dev/ath/if_ath_led.h>
109#include <dev/ath/if_ath_keycache.h>
110#include <dev/ath/if_ath_rx.h>
111#include <dev/ath/if_ath_beacon.h>
112#include <dev/ath/if_athdfs.h>
113
114#ifdef ATH_TX99_DIAG
115#include <dev/ath/ath_tx99/ath_tx99.h>
116#endif
117
118#ifdef ATH_DEBUG_ALQ
119#include <dev/ath/if_ath_alq.h>
120#endif
121
122/*
123 * Calculate the receive filter according to the
124 * operating mode and state:
125 *
126 * o always accept unicast, broadcast, and multicast traffic
127 * o accept PHY error frames when hardware doesn't have MIB support
128 * to count and we need them for ANI (sta mode only until recently)
129 * and we are not scanning (ANI is disabled)
130 * NB: older hal's add rx filter bits out of sight and we need to
131 * blindly preserve them
132 * o probe request frames are accepted only when operating in
133 * hostap, adhoc, mesh, or monitor modes
134 * o enable promiscuous mode
135 * - when in monitor mode
136 * - if interface marked PROMISC (assumes bridge setting is filtered)
137 * o accept beacons:
138 * - when operating in station mode for collecting rssi data when
139 * the station is otherwise quiet, or
140 * - when operating in adhoc mode so the 802.11 layer creates
141 * node table entries for peers,
142 * - when scanning
143 * - when doing s/w beacon miss (e.g. for ap+sta)
144 * - when operating in ap mode in 11g to detect overlapping bss that
145 * require protection
146 * - when operating in mesh mode to detect neighbors
147 * o accept control frames:
148 * - when in monitor mode
149 * XXX HT protection for 11n
150 */
151u_int32_t
152ath_calcrxfilter(struct ath_softc *sc)
153{
154 struct ifnet *ifp = sc->sc_ifp;
155 struct ieee80211com *ic = ifp->if_l2com;
156 u_int32_t rfilt;
157
158 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
159 if (!sc->sc_needmib && !sc->sc_scanning)
160 rfilt |= HAL_RX_FILTER_PHYERR;
161 if (ic->ic_opmode != IEEE80211_M_STA)
162 rfilt |= HAL_RX_FILTER_PROBEREQ;
163 /* XXX ic->ic_monvaps != 0? */
164 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
165 rfilt |= HAL_RX_FILTER_PROM;
166 if (ic->ic_opmode == IEEE80211_M_STA ||
167 ic->ic_opmode == IEEE80211_M_IBSS ||
168 sc->sc_swbmiss || sc->sc_scanning)
169 rfilt |= HAL_RX_FILTER_BEACON;
170 /*
171 * NB: We don't recalculate the rx filter when
172 * ic_protmode changes; otherwise we could do
173 * this only when ic_protmode != NONE.
174 */
175 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
176 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
177 rfilt |= HAL_RX_FILTER_BEACON;
178
179 /*
180 * Enable hardware PS-POLL RX only for hostap mode;
181 * STA mode sends PS-POLL frames but never
182 * receives them.
183 */
184 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
185 0, NULL) == HAL_OK &&
186 ic->ic_opmode == IEEE80211_M_HOSTAP)
187 rfilt |= HAL_RX_FILTER_PSPOLL;
188
189 if (sc->sc_nmeshvaps) {
190 rfilt |= HAL_RX_FILTER_BEACON;
191 if (sc->sc_hasbmatch)
192 rfilt |= HAL_RX_FILTER_BSSID;
193 else
194 rfilt |= HAL_RX_FILTER_PROM;
195 }
196 if (ic->ic_opmode == IEEE80211_M_MONITOR)
197 rfilt |= HAL_RX_FILTER_CONTROL;
198
199 /*
200 * Enable RX of compressed BAR frames only when doing
201 * 802.11n. Required for A-MPDU.
202 */
203 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
204 rfilt |= HAL_RX_FILTER_COMPBAR;
205
206 /*
207 * Enable radar PHY errors if requested by the
208 * DFS module.
209 */
210 if (sc->sc_dodfs)
211 rfilt |= HAL_RX_FILTER_PHYRADAR;
212
213 /*
214 * Enable spectral PHY errors if requested by the
215 * spectral module.
216 */
217 if (sc->sc_dospectral)
218 rfilt |= HAL_RX_FILTER_PHYRADAR;
219
220 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
221 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
222 return rfilt;
223}
224
225static int
226ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
227{
228 struct ath_hal *ah = sc->sc_ah;
229 int error;
230 struct mbuf *m;
231 struct ath_desc *ds;
232
233 m = bf->bf_m;
234 if (m == NULL) {
235 /*
236 * NB: by assigning a page to the rx dma buffer we
237 * implicitly satisfy the Atheros requirement that
238 * this buffer be cache-line-aligned and sized to be
239 * multiple of the cache line size. Not doing this
240 * causes weird stuff to happen (for the 5210 at least).
241 */
242 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
243 if (m == NULL) {
244 DPRINTF(sc, ATH_DEBUG_ANY,
245 "%s: no mbuf/cluster\n", __func__);
246 sc->sc_stats.ast_rx_nombuf++;
247 return ENOMEM;
248 }
249 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
250
251 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
252 bf->bf_dmamap, m,
253 bf->bf_segs, &bf->bf_nseg,
254 BUS_DMA_NOWAIT);
255 if (error != 0) {
256 DPRINTF(sc, ATH_DEBUG_ANY,
257 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
258 __func__, error);
259 sc->sc_stats.ast_rx_busdma++;
260 m_freem(m);
261 return error;
262 }
263 KASSERT(bf->bf_nseg == 1,
264 ("multi-segment packet; nseg %u", bf->bf_nseg));
265 bf->bf_m = m;
266 }
267 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
268
269 /*
270 * Setup descriptors. For receive we always terminate
271 * the descriptor list with a self-linked entry so we'll
272 * not get overrun under high load (as can happen with a
273 * 5212 when ANI processing enables PHY error frames).
274 *
275 * To insure the last descriptor is self-linked we create
276 * each descriptor as self-linked and add it to the end. As
277 * each additional descriptor is added the previous self-linked
278 * entry is ``fixed'' naturally. This should be safe even
279 * if DMA is happening. When processing RX interrupts we
280 * never remove/process the last, self-linked, entry on the
281 * descriptor list. This insures the hardware always has
282 * someplace to write a new frame.
283 */
284 /*
285 * 11N: we can no longer afford to self link the last descriptor.
286 * MAC acknowledges BA status as long as it copies frames to host
287 * buffer (or rx fifo). This can incorrectly acknowledge packets
288 * to a sender if last desc is self-linked.
289 */
290 ds = bf->bf_desc;
291 if (sc->sc_rxslink)
292 ds->ds_link = bf->bf_daddr; /* link to self */
293 else
294 ds->ds_link = 0; /* terminate the list */
295 ds->ds_data = bf->bf_segs[0].ds_addr;
296 ath_hal_setuprxdesc(ah, ds
297 , m->m_len /* buffer size */
298 , 0
299 );
300
301 if (sc->sc_rxlink != NULL)
302 *sc->sc_rxlink = bf->bf_daddr;
303 sc->sc_rxlink = &ds->ds_link;
304 return 0;
305}
306
307/*
308 * Intercept management frames to collect beacon rssi data
309 * and to do ibss merges.
310 */
311void
312ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
313 int subtype, int rssi, int nf)
314{
315 struct ieee80211vap *vap = ni->ni_vap;
316 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
317
318 /*
319 * Call up first so subsequent work can use information
320 * potentially stored in the node (e.g. for ibss merge).
321 */
322 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
323 switch (subtype) {
324 case IEEE80211_FC0_SUBTYPE_BEACON:
325 /* update rssi statistics for use by the hal */
326 /* XXX unlocked check against vap->iv_bss? */
327 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
328 if (sc->sc_syncbeacon &&
329 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
330 /*
331 * Resync beacon timers using the tsf of the beacon
332 * frame we just received.
333 */
334 ath_beacon_config(sc, vap);
335 }
336 /* fall thru... */
337 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
338 if (vap->iv_opmode == IEEE80211_M_IBSS &&
339 vap->iv_state == IEEE80211_S_RUN) {
340 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
341 uint64_t tsf = ath_extend_tsf(sc, rstamp,
342 ath_hal_gettsf64(sc->sc_ah));
343 /*
344 * Handle ibss merge as needed; check the tsf on the
345 * frame before attempting the merge. The 802.11 spec
346 * says the station should change it's bssid to match
347 * the oldest station with the same ssid, where oldest
348 * is determined by the tsf. Note that hardware
349 * reconfiguration happens through callback to
350 * ath_newstate as the state machine will go from
351 * RUN -> RUN when this happens.
352 */
353 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
354 DPRINTF(sc, ATH_DEBUG_STATE,
355 "ibss merge, rstamp %u tsf %ju "
356 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
357 (uintmax_t)ni->ni_tstamp.tsf);
358 (void) ieee80211_ibss_merge(ni);
359 }
360 }
361 break;
362 }
363}
364
365#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
366static void
367ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m,
368 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
369{
370 struct ath_softc *sc = ifp->if_softc;
371
372 /* Fill in the extension bitmap */
373 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
374
375 /* Fill in the vendor header */
376 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
377 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
378 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
379
380 /* XXX what should this be? */
381 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
382 sc->sc_rx_th.wr_vh.vh_skip_len =
383 htole16(sizeof(struct ath_radiotap_vendor_hdr));
384
385 /* General version info */
386 sc->sc_rx_th.wr_v.vh_version = 1;
387
388 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
389
390 /* rssi */
391 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
392 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
393 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
394 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
395 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
396 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
397
398 /* evm */
399 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
400 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
401 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
402 /* These are only populated from the AR9300 or later */
403 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
404 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
405
| 32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42/*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49#include "opt_ah.h"
50#include "opt_wlan.h"
51
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/sysctl.h>
55#include <sys/mbuf.h>
56#include <sys/malloc.h>
57#include <sys/lock.h>
58#include <sys/mutex.h>
59#include <sys/kernel.h>
60#include <sys/socket.h>
61#include <sys/sockio.h>
62#include <sys/errno.h>
63#include <sys/callout.h>
64#include <sys/bus.h>
65#include <sys/endian.h>
66#include <sys/kthread.h>
67#include <sys/taskqueue.h>
68#include <sys/priv.h>
69#include <sys/module.h>
70#include <sys/ktr.h>
71#include <sys/smp.h> /* for mp_ncpus */
72
73#include <machine/bus.h>
74
75#include <net/if.h>
76#include <net/if_dl.h>
77#include <net/if_media.h>
78#include <net/if_types.h>
79#include <net/if_arp.h>
80#include <net/ethernet.h>
81#include <net/if_llc.h>
82
83#include <net80211/ieee80211_var.h>
84#include <net80211/ieee80211_regdomain.h>
85#ifdef IEEE80211_SUPPORT_SUPERG
86#include <net80211/ieee80211_superg.h>
87#endif
88#ifdef IEEE80211_SUPPORT_TDMA
89#include <net80211/ieee80211_tdma.h>
90#endif
91
92#include <net/bpf.h>
93
94#ifdef INET
95#include <netinet/in.h>
96#include <netinet/if_ether.h>
97#endif
98
99#include <dev/ath/if_athvar.h>
100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101#include <dev/ath/ath_hal/ah_diagcodes.h>
102
103#include <dev/ath/if_ath_debug.h>
104#include <dev/ath/if_ath_misc.h>
105#include <dev/ath/if_ath_tsf.h>
106#include <dev/ath/if_ath_tx.h>
107#include <dev/ath/if_ath_sysctl.h>
108#include <dev/ath/if_ath_led.h>
109#include <dev/ath/if_ath_keycache.h>
110#include <dev/ath/if_ath_rx.h>
111#include <dev/ath/if_ath_beacon.h>
112#include <dev/ath/if_athdfs.h>
113
114#ifdef ATH_TX99_DIAG
115#include <dev/ath/ath_tx99/ath_tx99.h>
116#endif
117
118#ifdef ATH_DEBUG_ALQ
119#include <dev/ath/if_ath_alq.h>
120#endif
121
122/*
123 * Calculate the receive filter according to the
124 * operating mode and state:
125 *
126 * o always accept unicast, broadcast, and multicast traffic
127 * o accept PHY error frames when hardware doesn't have MIB support
128 * to count and we need them for ANI (sta mode only until recently)
129 * and we are not scanning (ANI is disabled)
130 * NB: older hal's add rx filter bits out of sight and we need to
131 * blindly preserve them
132 * o probe request frames are accepted only when operating in
133 * hostap, adhoc, mesh, or monitor modes
134 * o enable promiscuous mode
135 * - when in monitor mode
136 * - if interface marked PROMISC (assumes bridge setting is filtered)
137 * o accept beacons:
138 * - when operating in station mode for collecting rssi data when
139 * the station is otherwise quiet, or
140 * - when operating in adhoc mode so the 802.11 layer creates
141 * node table entries for peers,
142 * - when scanning
143 * - when doing s/w beacon miss (e.g. for ap+sta)
144 * - when operating in ap mode in 11g to detect overlapping bss that
145 * require protection
146 * - when operating in mesh mode to detect neighbors
147 * o accept control frames:
148 * - when in monitor mode
149 * XXX HT protection for 11n
150 */
151u_int32_t
152ath_calcrxfilter(struct ath_softc *sc)
153{
154 struct ifnet *ifp = sc->sc_ifp;
155 struct ieee80211com *ic = ifp->if_l2com;
156 u_int32_t rfilt;
157
158 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
159 if (!sc->sc_needmib && !sc->sc_scanning)
160 rfilt |= HAL_RX_FILTER_PHYERR;
161 if (ic->ic_opmode != IEEE80211_M_STA)
162 rfilt |= HAL_RX_FILTER_PROBEREQ;
163 /* XXX ic->ic_monvaps != 0? */
164 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
165 rfilt |= HAL_RX_FILTER_PROM;
166 if (ic->ic_opmode == IEEE80211_M_STA ||
167 ic->ic_opmode == IEEE80211_M_IBSS ||
168 sc->sc_swbmiss || sc->sc_scanning)
169 rfilt |= HAL_RX_FILTER_BEACON;
170 /*
171 * NB: We don't recalculate the rx filter when
172 * ic_protmode changes; otherwise we could do
173 * this only when ic_protmode != NONE.
174 */
175 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
176 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
177 rfilt |= HAL_RX_FILTER_BEACON;
178
179 /*
180 * Enable hardware PS-POLL RX only for hostap mode;
181 * STA mode sends PS-POLL frames but never
182 * receives them.
183 */
184 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
185 0, NULL) == HAL_OK &&
186 ic->ic_opmode == IEEE80211_M_HOSTAP)
187 rfilt |= HAL_RX_FILTER_PSPOLL;
188
189 if (sc->sc_nmeshvaps) {
190 rfilt |= HAL_RX_FILTER_BEACON;
191 if (sc->sc_hasbmatch)
192 rfilt |= HAL_RX_FILTER_BSSID;
193 else
194 rfilt |= HAL_RX_FILTER_PROM;
195 }
196 if (ic->ic_opmode == IEEE80211_M_MONITOR)
197 rfilt |= HAL_RX_FILTER_CONTROL;
198
199 /*
200 * Enable RX of compressed BAR frames only when doing
201 * 802.11n. Required for A-MPDU.
202 */
203 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
204 rfilt |= HAL_RX_FILTER_COMPBAR;
205
206 /*
207 * Enable radar PHY errors if requested by the
208 * DFS module.
209 */
210 if (sc->sc_dodfs)
211 rfilt |= HAL_RX_FILTER_PHYRADAR;
212
213 /*
214 * Enable spectral PHY errors if requested by the
215 * spectral module.
216 */
217 if (sc->sc_dospectral)
218 rfilt |= HAL_RX_FILTER_PHYRADAR;
219
220 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
221 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
222 return rfilt;
223}
224
225static int
226ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
227{
228 struct ath_hal *ah = sc->sc_ah;
229 int error;
230 struct mbuf *m;
231 struct ath_desc *ds;
232
233 m = bf->bf_m;
234 if (m == NULL) {
235 /*
236 * NB: by assigning a page to the rx dma buffer we
237 * implicitly satisfy the Atheros requirement that
238 * this buffer be cache-line-aligned and sized to be
239 * multiple of the cache line size. Not doing this
240 * causes weird stuff to happen (for the 5210 at least).
241 */
242 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
243 if (m == NULL) {
244 DPRINTF(sc, ATH_DEBUG_ANY,
245 "%s: no mbuf/cluster\n", __func__);
246 sc->sc_stats.ast_rx_nombuf++;
247 return ENOMEM;
248 }
249 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
250
251 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
252 bf->bf_dmamap, m,
253 bf->bf_segs, &bf->bf_nseg,
254 BUS_DMA_NOWAIT);
255 if (error != 0) {
256 DPRINTF(sc, ATH_DEBUG_ANY,
257 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
258 __func__, error);
259 sc->sc_stats.ast_rx_busdma++;
260 m_freem(m);
261 return error;
262 }
263 KASSERT(bf->bf_nseg == 1,
264 ("multi-segment packet; nseg %u", bf->bf_nseg));
265 bf->bf_m = m;
266 }
267 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
268
269 /*
270 * Setup descriptors. For receive we always terminate
271 * the descriptor list with a self-linked entry so we'll
272 * not get overrun under high load (as can happen with a
273 * 5212 when ANI processing enables PHY error frames).
274 *
275 * To insure the last descriptor is self-linked we create
276 * each descriptor as self-linked and add it to the end. As
277 * each additional descriptor is added the previous self-linked
278 * entry is ``fixed'' naturally. This should be safe even
279 * if DMA is happening. When processing RX interrupts we
280 * never remove/process the last, self-linked, entry on the
281 * descriptor list. This insures the hardware always has
282 * someplace to write a new frame.
283 */
284 /*
285 * 11N: we can no longer afford to self link the last descriptor.
286 * MAC acknowledges BA status as long as it copies frames to host
287 * buffer (or rx fifo). This can incorrectly acknowledge packets
288 * to a sender if last desc is self-linked.
289 */
290 ds = bf->bf_desc;
291 if (sc->sc_rxslink)
292 ds->ds_link = bf->bf_daddr; /* link to self */
293 else
294 ds->ds_link = 0; /* terminate the list */
295 ds->ds_data = bf->bf_segs[0].ds_addr;
296 ath_hal_setuprxdesc(ah, ds
297 , m->m_len /* buffer size */
298 , 0
299 );
300
301 if (sc->sc_rxlink != NULL)
302 *sc->sc_rxlink = bf->bf_daddr;
303 sc->sc_rxlink = &ds->ds_link;
304 return 0;
305}
306
307/*
308 * Intercept management frames to collect beacon rssi data
309 * and to do ibss merges.
310 */
311void
312ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
313 int subtype, int rssi, int nf)
314{
315 struct ieee80211vap *vap = ni->ni_vap;
316 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
317
318 /*
319 * Call up first so subsequent work can use information
320 * potentially stored in the node (e.g. for ibss merge).
321 */
322 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
323 switch (subtype) {
324 case IEEE80211_FC0_SUBTYPE_BEACON:
325 /* update rssi statistics for use by the hal */
326 /* XXX unlocked check against vap->iv_bss? */
327 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
328 if (sc->sc_syncbeacon &&
329 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
330 /*
331 * Resync beacon timers using the tsf of the beacon
332 * frame we just received.
333 */
334 ath_beacon_config(sc, vap);
335 }
336 /* fall thru... */
337 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
338 if (vap->iv_opmode == IEEE80211_M_IBSS &&
339 vap->iv_state == IEEE80211_S_RUN) {
340 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
341 uint64_t tsf = ath_extend_tsf(sc, rstamp,
342 ath_hal_gettsf64(sc->sc_ah));
343 /*
344 * Handle ibss merge as needed; check the tsf on the
345 * frame before attempting the merge. The 802.11 spec
346 * says the station should change it's bssid to match
347 * the oldest station with the same ssid, where oldest
348 * is determined by the tsf. Note that hardware
349 * reconfiguration happens through callback to
350 * ath_newstate as the state machine will go from
351 * RUN -> RUN when this happens.
352 */
353 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
354 DPRINTF(sc, ATH_DEBUG_STATE,
355 "ibss merge, rstamp %u tsf %ju "
356 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
357 (uintmax_t)ni->ni_tstamp.tsf);
358 (void) ieee80211_ibss_merge(ni);
359 }
360 }
361 break;
362 }
363}
364
365#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
366static void
367ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m,
368 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
369{
370 struct ath_softc *sc = ifp->if_softc;
371
372 /* Fill in the extension bitmap */
373 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
374
375 /* Fill in the vendor header */
376 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
377 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
378 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
379
380 /* XXX what should this be? */
381 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
382 sc->sc_rx_th.wr_vh.vh_skip_len =
383 htole16(sizeof(struct ath_radiotap_vendor_hdr));
384
385 /* General version info */
386 sc->sc_rx_th.wr_v.vh_version = 1;
387
388 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
389
390 /* rssi */
391 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
392 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
393 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
394 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
395 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
396 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
397
398 /* evm */
399 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
400 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
401 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
402 /* These are only populated from the AR9300 or later */
403 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
404 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
405
|
411 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
412 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
413}
414#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
415
416static void
417ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
418 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
419{
420#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
421#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
422#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
423#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
424 struct ath_softc *sc = ifp->if_softc;
425 const HAL_RATE_TABLE *rt;
426 uint8_t rix;
427
428 rt = sc->sc_currates;
429 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
430 rix = rt->rateCodeToIndex[rs->rs_rate];
431 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
432 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
433#ifdef AH_SUPPORT_AR5416
434 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
435 if (rs->rs_status & HAL_RXERR_PHY) {
436 /*
437 * PHY error - make sure the channel flags
438 * reflect the actual channel configuration,
439 * not the received frame.
440 */
441 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
442 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
443 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
444 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
445 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
446 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
447 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
448 struct ieee80211com *ic = ifp->if_l2com;
449
450 if ((rs->rs_flags & HAL_RX_2040) == 0)
451 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
452 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
453 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
454 else
455 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
456 if ((rs->rs_flags & HAL_RX_GI) == 0)
457 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
458 }
459
460#endif
461 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
462 if (rs->rs_status & HAL_RXERR_CRC)
463 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
464 /* XXX propagate other error flags from descriptor */
465 sc->sc_rx_th.wr_antnoise = nf;
466 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
467 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
468#undef CHAN_HT
469#undef CHAN_HT20
470#undef CHAN_HT40U
471#undef CHAN_HT40D
472}
473
474static void
475ath_handle_micerror(struct ieee80211com *ic,
476 struct ieee80211_frame *wh, int keyix)
477{
478 struct ieee80211_node *ni;
479
480 /* XXX recheck MIC to deal w/ chips that lie */
481 /* XXX discard MIC errors on !data frames */
482 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
483 if (ni != NULL) {
484 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
485 ieee80211_free_node(ni);
486 }
487}
488
489int
490ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
491 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf)
492{
493 struct ath_hal *ah = sc->sc_ah;
494 struct mbuf *m = bf->bf_m;
495 uint64_t rstamp;
496 int len, type;
497 struct ifnet *ifp = sc->sc_ifp;
498 struct ieee80211com *ic = ifp->if_l2com;
499 struct ieee80211_node *ni;
500 int is_good = 0;
501 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
502
503 /*
504 * Calculate the correct 64 bit TSF given
505 * the TSF64 register value and rs_tstamp.
506 */
507 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
508
509 /* These aren't specifically errors */
510#ifdef AH_SUPPORT_AR5416
511 if (rs->rs_flags & HAL_RX_GI)
512 sc->sc_stats.ast_rx_halfgi++;
513 if (rs->rs_flags & HAL_RX_2040)
514 sc->sc_stats.ast_rx_2040++;
515 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
516 sc->sc_stats.ast_rx_pre_crc_err++;
517 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
518 sc->sc_stats.ast_rx_post_crc_err++;
519 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
520 sc->sc_stats.ast_rx_decrypt_busy_err++;
521 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
522 sc->sc_stats.ast_rx_hi_rx_chain++;
523#endif /* AH_SUPPORT_AR5416 */
524
525 if (rs->rs_status != 0) {
526 if (rs->rs_status & HAL_RXERR_CRC)
527 sc->sc_stats.ast_rx_crcerr++;
528 if (rs->rs_status & HAL_RXERR_FIFO)
529 sc->sc_stats.ast_rx_fifoerr++;
530 if (rs->rs_status & HAL_RXERR_PHY) {
531 sc->sc_stats.ast_rx_phyerr++;
532 /* Process DFS radar events */
533 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
534 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
535 /* Since we're touching the frame data, sync it */
536 bus_dmamap_sync(sc->sc_dmat,
537 bf->bf_dmamap,
538 BUS_DMASYNC_POSTREAD);
539 /* Now pass it to the radar processing code */
540 ath_dfs_process_phy_err(sc, m, rstamp, rs);
541 }
542
543 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */
544 if (rs->rs_phyerr < 64)
545 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
546 goto rx_error; /* NB: don't count in ierrors */
547 }
548 if (rs->rs_status & HAL_RXERR_DECRYPT) {
549 /*
550 * Decrypt error. If the error occurred
551 * because there was no hardware key, then
552 * let the frame through so the upper layers
553 * can process it. This is necessary for 5210
554 * parts which have no way to setup a ``clear''
555 * key cache entry.
556 *
557 * XXX do key cache faulting
558 */
559 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
560 goto rx_accept;
561 sc->sc_stats.ast_rx_badcrypt++;
562 }
563 /*
564 * Similar as above - if the failure was a keymiss
565 * just punt it up to the upper layers for now.
566 */
567 if (rs->rs_status & HAL_RXERR_KEYMISS) {
568 sc->sc_stats.ast_rx_keymiss++;
569 goto rx_accept;
570 }
571 if (rs->rs_status & HAL_RXERR_MIC) {
572 sc->sc_stats.ast_rx_badmic++;
573 /*
574 * Do minimal work required to hand off
575 * the 802.11 header for notification.
576 */
577 /* XXX frag's and qos frames */
578 len = rs->rs_datalen;
579 if (len >= sizeof (struct ieee80211_frame)) {
580 bus_dmamap_sync(sc->sc_dmat,
581 bf->bf_dmamap,
582 BUS_DMASYNC_POSTREAD);
583 ath_handle_micerror(ic,
584 mtod(m, struct ieee80211_frame *),
585 sc->sc_splitmic ?
586 rs->rs_keyix-32 : rs->rs_keyix);
587 }
588 }
589 ifp->if_ierrors++;
590rx_error:
591 /*
592 * Cleanup any pending partial frame.
593 */
594 if (re->m_rxpending != NULL) {
595 m_freem(re->m_rxpending);
596 re->m_rxpending = NULL;
597 }
598 /*
599 * When a tap is present pass error frames
600 * that have been requested. By default we
601 * pass decrypt+mic errors but others may be
602 * interesting (e.g. crc).
603 */
604 if (ieee80211_radiotap_active(ic) &&
605 (rs->rs_status & sc->sc_monpass)) {
606 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
607 BUS_DMASYNC_POSTREAD);
608 /* NB: bpf needs the mbuf length setup */
609 len = rs->rs_datalen;
610 m->m_pkthdr.len = m->m_len = len;
611 bf->bf_m = NULL;
612 ath_rx_tap(ifp, m, rs, rstamp, nf);
613#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
614 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
615#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
616 ieee80211_radiotap_rx_all(ic, m);
617 m_freem(m);
618 }
619 /* XXX pass MIC errors up for s/w reclaculation */
620 goto rx_next;
621 }
622rx_accept:
623 /*
624 * Sync and unmap the frame. At this point we're
625 * committed to passing the mbuf somewhere so clear
626 * bf_m; this means a new mbuf must be allocated
627 * when the rx descriptor is setup again to receive
628 * another frame.
629 */
630 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
631 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
632 bf->bf_m = NULL;
633
634 len = rs->rs_datalen;
635 m->m_len = len;
636
637 if (rs->rs_more) {
638 /*
639 * Frame spans multiple descriptors; save
640 * it for the next completed descriptor, it
641 * will be used to construct a jumbogram.
642 */
643 if (re->m_rxpending != NULL) {
644 /* NB: max frame size is currently 2 clusters */
645 sc->sc_stats.ast_rx_toobig++;
646 m_freem(re->m_rxpending);
647 }
648 m->m_pkthdr.rcvif = ifp;
649 m->m_pkthdr.len = len;
650 re->m_rxpending = m;
651 goto rx_next;
652 } else if (re->m_rxpending != NULL) {
653 /*
654 * This is the second part of a jumbogram,
655 * chain it to the first mbuf, adjust the
656 * frame length, and clear the rxpending state.
657 */
658 re->m_rxpending->m_next = m;
659 re->m_rxpending->m_pkthdr.len += len;
660 m = re->m_rxpending;
661 re->m_rxpending = NULL;
662 } else {
663 /*
664 * Normal single-descriptor receive; setup
665 * the rcvif and packet length.
666 */
667 m->m_pkthdr.rcvif = ifp;
668 m->m_pkthdr.len = len;
669 }
670
671 /*
672 * Validate rs->rs_antenna.
673 *
674 * Some users w/ AR9285 NICs have reported crashes
675 * here because rs_antenna field is bogusly large.
676 * Let's enforce the maximum antenna limit of 8
677 * (and it shouldn't be hard coded, but that's a
678 * separate problem) and if there's an issue, print
679 * out an error and adjust rs_antenna to something
680 * sensible.
681 *
682 * This code should be removed once the actual
683 * root cause of the issue has been identified.
684 * For example, it may be that the rs_antenna
685 * field is only valid for the lsat frame of
686 * an aggregate and it just happens that it is
687 * "mostly" right. (This is a general statement -
688 * the majority of the statistics are only valid
689 * for the last frame in an aggregate.
690 */
691 if (rs->rs_antenna > 7) {
692 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
693 __func__, rs->rs_antenna);
694#ifdef ATH_DEBUG
695 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
696#endif /* ATH_DEBUG */
697 rs->rs_antenna = 0; /* XXX better than nothing */
698 }
699
700 ifp->if_ipackets++;
701 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
702
703 /*
704 * Populate the rx status block. When there are bpf
705 * listeners we do the additional work to provide
706 * complete status. Otherwise we fill in only the
707 * material required by ieee80211_input. Note that
708 * noise setting is filled in above.
709 */
710 if (ieee80211_radiotap_active(ic)) {
711 ath_rx_tap(ifp, m, rs, rstamp, nf);
712#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
713 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
714#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
715 }
716
717 /*
718 * From this point on we assume the frame is at least
719 * as large as ieee80211_frame_min; verify that.
720 */
721 if (len < IEEE80211_MIN_LEN) {
722 if (!ieee80211_radiotap_active(ic)) {
723 DPRINTF(sc, ATH_DEBUG_RECV,
724 "%s: short packet %d\n", __func__, len);
725 sc->sc_stats.ast_rx_tooshort++;
726 } else {
727 /* NB: in particular this captures ack's */
728 ieee80211_radiotap_rx_all(ic, m);
729 }
730 m_freem(m);
731 goto rx_next;
732 }
733
734 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
735 const HAL_RATE_TABLE *rt = sc->sc_currates;
736 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
737
738 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
739 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
740 }
741
742 m_adj(m, -IEEE80211_CRC_LEN);
743
744 /*
745 * Locate the node for sender, track state, and then
746 * pass the (referenced) node up to the 802.11 layer
747 * for its use.
748 */
749 ni = ieee80211_find_rxnode_withkey(ic,
750 mtod(m, const struct ieee80211_frame_min *),
751 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
752 IEEE80211_KEYIX_NONE : rs->rs_keyix);
753 sc->sc_lastrs = rs;
754
755#ifdef AH_SUPPORT_AR5416
756 if (rs->rs_isaggr)
757 sc->sc_stats.ast_rx_agg++;
758#endif /* AH_SUPPORT_AR5416 */
759
760 if (ni != NULL) {
761 /*
762 * Only punt packets for ampdu reorder processing for
763 * 11n nodes; net80211 enforces that M_AMPDU is only
764 * set for 11n nodes.
765 */
766 if (ni->ni_flags & IEEE80211_NODE_HT)
767 m->m_flags |= M_AMPDU;
768
769 /*
770 * Sending station is known, dispatch directly.
771 */
772 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
773 ieee80211_free_node(ni);
774 /*
775 * Arrange to update the last rx timestamp only for
776 * frames from our ap when operating in station mode.
777 * This assumes the rx key is always setup when
778 * associated.
779 */
780 if (ic->ic_opmode == IEEE80211_M_STA &&
781 rs->rs_keyix != HAL_RXKEYIX_INVALID)
782 is_good = 1;
783 } else {
784 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
785 }
786 /*
787 * Track rx rssi and do any rx antenna management.
788 */
789 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
790 if (sc->sc_diversity) {
791 /*
792 * When using fast diversity, change the default rx
793 * antenna if diversity chooses the other antenna 3
794 * times in a row.
795 */
796 if (sc->sc_defant != rs->rs_antenna) {
797 if (++sc->sc_rxotherant >= 3)
798 ath_setdefantenna(sc, rs->rs_antenna);
799 } else
800 sc->sc_rxotherant = 0;
801 }
802
803 /* Newer school diversity - kite specific for now */
804 /* XXX perhaps migrate the normal diversity code to this? */
805 if ((ah)->ah_rxAntCombDiversity)
806 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz);
807
808 if (sc->sc_softled) {
809 /*
810 * Blink for any data frame. Otherwise do a
811 * heartbeat-style blink when idle. The latter
812 * is mainly for station mode where we depend on
813 * periodic beacon frames to trigger the poll event.
814 */
815 if (type == IEEE80211_FC0_TYPE_DATA) {
816 const HAL_RATE_TABLE *rt = sc->sc_currates;
817 ath_led_event(sc,
818 rt->rateCodeToIndex[rs->rs_rate]);
819 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
820 ath_led_event(sc, 0);
821 }
822rx_next:
823 return (is_good);
824}
825
826#define ATH_RX_MAX 128
827
828static void
829ath_rx_proc(struct ath_softc *sc, int resched)
830{
831#define PA2DESC(_sc, _pa) \
832 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
833 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
834 struct ath_buf *bf;
835 struct ifnet *ifp = sc->sc_ifp;
836 struct ath_hal *ah = sc->sc_ah;
837#ifdef IEEE80211_SUPPORT_SUPERG
838 struct ieee80211com *ic = ifp->if_l2com;
839#endif
840 struct ath_desc *ds;
841 struct ath_rx_status *rs;
842 struct mbuf *m;
843 int ngood;
844 HAL_STATUS status;
845 int16_t nf;
846 u_int64_t tsf;
847 int npkts = 0;
848 int kickpcu = 0;
849
850 /* XXX we must not hold the ATH_LOCK here */
851 ATH_UNLOCK_ASSERT(sc);
852 ATH_PCU_UNLOCK_ASSERT(sc);
853
854 ATH_PCU_LOCK(sc);
855 sc->sc_rxproc_cnt++;
856 kickpcu = sc->sc_kickpcu;
857 ATH_PCU_UNLOCK(sc);
858
859 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
860 ngood = 0;
861 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
862 sc->sc_stats.ast_rx_noise = nf;
863 tsf = ath_hal_gettsf64(ah);
864 do {
865 /*
866 * Don't process too many packets at a time; give the
867 * TX thread time to also run - otherwise the TX
868 * latency can jump by quite a bit, causing throughput
869 * degredation.
870 */
871 if (!kickpcu && npkts >= ATH_RX_MAX)
872 break;
873
874 bf = TAILQ_FIRST(&sc->sc_rxbuf);
875 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
876 if_printf(ifp, "%s: no buffer!\n", __func__);
877 break;
878 } else if (bf == NULL) {
879 /*
880 * End of List:
881 * this can happen for non-self-linked RX chains
882 */
883 sc->sc_stats.ast_rx_hitqueueend++;
884 break;
885 }
886 m = bf->bf_m;
887 if (m == NULL) { /* NB: shouldn't happen */
888 /*
889 * If mbuf allocation failed previously there
890 * will be no mbuf; try again to re-populate it.
891 */
892 /* XXX make debug msg */
893 if_printf(ifp, "%s: no mbuf!\n", __func__);
894 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
895 goto rx_proc_next;
896 }
897 ds = bf->bf_desc;
898 if (ds->ds_link == bf->bf_daddr) {
899 /* NB: never process the self-linked entry at the end */
900 sc->sc_stats.ast_rx_hitqueueend++;
901 break;
902 }
903 /* XXX sync descriptor memory */
904 /*
905 * Must provide the virtual address of the current
906 * descriptor, the physical address, and the virtual
907 * address of the next descriptor in the h/w chain.
908 * This allows the HAL to look ahead to see if the
909 * hardware is done with a descriptor by checking the
910 * done bit in the following descriptor and the address
911 * of the current descriptor the DMA engine is working
912 * on. All this is necessary because of our use of
913 * a self-linked list to avoid rx overruns.
914 */
915 rs = &bf->bf_status.ds_rxstat;
916 status = ath_hal_rxprocdesc(ah, ds,
917 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
918#ifdef ATH_DEBUG
919 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
920 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
921#endif
922
923#ifdef ATH_DEBUG_ALQ
924 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
925 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
926 sc->sc_rx_statuslen, (char *) ds);
927#endif /* ATH_DEBUG_ALQ */
928
929 if (status == HAL_EINPROGRESS)
930 break;
931
932 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
933 npkts++;
934
935 /*
936 * Process a single frame.
937 */
938 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf))
939 ngood++;
940rx_proc_next:
941 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
942 } while (ath_rxbuf_init(sc, bf) == 0);
943
944 /* rx signal state monitoring */
945 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
946 if (ngood)
947 sc->sc_lastrx = tsf;
948
949 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
950 /* Queue DFS tasklet if needed */
951 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
952 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
953
954 /*
955 * Now that all the RX frames were handled that
956 * need to be handled, kick the PCU if there's
957 * been an RXEOL condition.
958 */
959 if (resched && kickpcu) {
960 ATH_PCU_LOCK(sc);
961 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
962 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
963 __func__, npkts);
964
965 /*
966 * Go through the process of fully tearing down
967 * the RX buffers and reinitialising them.
968 *
969 * There's a hardware bug that causes the RX FIFO
970 * to get confused under certain conditions and
971 * constantly write over the same frame, leading
972 * the RX driver code here to get heavily confused.
973 */
974#if 1
975 ath_startrecv(sc);
976#else
977 /*
978 * Disabled for now - it'd be nice to be able to do
979 * this in order to limit the amount of CPU time spent
980 * reinitialising the RX side (and thus minimise RX
981 * drops) however there's a hardware issue that
982 * causes things to get too far out of whack.
983 */
984 /*
985 * XXX can we hold the PCU lock here?
986 * Are there any net80211 buffer calls involved?
987 */
988 bf = TAILQ_FIRST(&sc->sc_rxbuf);
989 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
990 ath_hal_rxena(ah); /* enable recv descriptors */
991 ath_mode_init(sc); /* set filters, etc. */
992 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
993#endif
994
995 ath_hal_intrset(ah, sc->sc_imask);
996 sc->sc_kickpcu = 0;
997 ATH_PCU_UNLOCK(sc);
998 }
999
1000 /* XXX check this inside of IF_LOCK? */
1001 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
1002#ifdef IEEE80211_SUPPORT_SUPERG
1003 ieee80211_ff_age_all(ic, 100);
1004#endif
1005 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1006 ath_tx_kick(sc);
1007 }
1008#undef PA2DESC
1009
1010 /*
1011 * If we hit the maximum number of frames in this round,
1012 * reschedule for another immediate pass. This gives
1013 * the TX and TX completion routines time to run, which
1014 * will reduce latency.
1015 */
1016 if (npkts >= ATH_RX_MAX)
1017 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1018
1019 ATH_PCU_LOCK(sc);
1020 sc->sc_rxproc_cnt--;
1021 ATH_PCU_UNLOCK(sc);
1022}
1023
1024#undef ATH_RX_MAX
1025
1026/*
1027 * Only run the RX proc if it's not already running.
1028 * Since this may get run as part of the reset/flush path,
1029 * the task can't clash with an existing, running tasklet.
1030 */
1031static void
1032ath_legacy_rx_tasklet(void *arg, int npending)
1033{
1034 struct ath_softc *sc = arg;
1035
1036 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1037 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1038 ATH_PCU_LOCK(sc);
1039 if (sc->sc_inreset_cnt > 0) {
1040 device_printf(sc->sc_dev,
1041 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1042 ATH_PCU_UNLOCK(sc);
1043 return;
1044 }
1045 ATH_PCU_UNLOCK(sc);
1046
1047 ath_rx_proc(sc, 1);
1048}
1049
1050static void
1051ath_legacy_flushrecv(struct ath_softc *sc)
1052{
1053
1054 ath_rx_proc(sc, 0);
1055}
1056
1057/*
1058 * Disable the receive h/w in preparation for a reset.
1059 */
1060static void
1061ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1062{
1063#define PA2DESC(_sc, _pa) \
1064 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1065 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1066 struct ath_hal *ah = sc->sc_ah;
1067
1068 ath_hal_stoppcurecv(ah); /* disable PCU */
1069 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1070 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1071 /*
1072 * TODO: see if this particular DELAY() is required; it may be
1073 * masking some missing FIFO flush or DMA sync.
1074 */
1075#if 0
1076 if (dodelay)
1077#endif
1078 DELAY(3000); /* 3ms is long enough for 1 frame */
1079#ifdef ATH_DEBUG
1080 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1081 struct ath_buf *bf;
1082 u_int ix;
1083
1084 device_printf(sc->sc_dev,
1085 "%s: rx queue %p, link %p\n",
1086 __func__,
1087 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1088 sc->sc_rxlink);
1089 ix = 0;
1090 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1091 struct ath_desc *ds = bf->bf_desc;
1092 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1093 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1094 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1095 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1096 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1097 ix++;
1098 }
1099 }
1100#endif
1101 /*
1102 * Free both high/low RX pending, just in case.
1103 */
1104 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1105 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1106 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1107 }
1108 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1109 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1110 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1111 }
1112 sc->sc_rxlink = NULL; /* just in case */
1113#undef PA2DESC
1114}
1115
1116/*
1117 * Enable the receive h/w following a reset.
1118 */
1119static int
1120ath_legacy_startrecv(struct ath_softc *sc)
1121{
1122 struct ath_hal *ah = sc->sc_ah;
1123 struct ath_buf *bf;
1124
1125 sc->sc_rxlink = NULL;
1126 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1127 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1128 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1129 int error = ath_rxbuf_init(sc, bf);
1130 if (error != 0) {
1131 DPRINTF(sc, ATH_DEBUG_RECV,
1132 "%s: ath_rxbuf_init failed %d\n",
1133 __func__, error);
1134 return error;
1135 }
1136 }
1137
1138 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1139 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1140 ath_hal_rxena(ah); /* enable recv descriptors */
1141 ath_mode_init(sc); /* set filters, etc. */
1142 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1143 return 0;
1144}
1145
1146static int
1147ath_legacy_dma_rxsetup(struct ath_softc *sc)
1148{
1149 int error;
1150
1151 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1152 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1153 if (error != 0)
1154 return (error);
1155
1156 return (0);
1157}
1158
1159static int
1160ath_legacy_dma_rxteardown(struct ath_softc *sc)
1161{
1162
1163 if (sc->sc_rxdma.dd_desc_len != 0)
1164 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1165 return (0);
1166}
1167
1168void
1169ath_recv_setup_legacy(struct ath_softc *sc)
1170{
1171
1172 /* Sensible legacy defaults */
1173 /*
1174 * XXX this should be changed to properly support the
1175 * exact RX descriptor size for each HAL.
1176 */
1177 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1178
1179 sc->sc_rx.recv_start = ath_legacy_startrecv;
1180 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1181 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1182 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1183 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1184
1185 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1186 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1187}
| 427 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
428 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
429}
430#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
431
432static void
433ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
434 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
435{
436#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
437#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
438#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
439#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
440 struct ath_softc *sc = ifp->if_softc;
441 const HAL_RATE_TABLE *rt;
442 uint8_t rix;
443
444 rt = sc->sc_currates;
445 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
446 rix = rt->rateCodeToIndex[rs->rs_rate];
447 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
448 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
449#ifdef AH_SUPPORT_AR5416
450 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
451 if (rs->rs_status & HAL_RXERR_PHY) {
452 /*
453 * PHY error - make sure the channel flags
454 * reflect the actual channel configuration,
455 * not the received frame.
456 */
457 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
458 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
459 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
460 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
461 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
462 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
463 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
464 struct ieee80211com *ic = ifp->if_l2com;
465
466 if ((rs->rs_flags & HAL_RX_2040) == 0)
467 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
468 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
469 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
470 else
471 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
472 if ((rs->rs_flags & HAL_RX_GI) == 0)
473 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
474 }
475
476#endif
477 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
478 if (rs->rs_status & HAL_RXERR_CRC)
479 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
480 /* XXX propagate other error flags from descriptor */
481 sc->sc_rx_th.wr_antnoise = nf;
482 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
483 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
484#undef CHAN_HT
485#undef CHAN_HT20
486#undef CHAN_HT40U
487#undef CHAN_HT40D
488}
489
490static void
491ath_handle_micerror(struct ieee80211com *ic,
492 struct ieee80211_frame *wh, int keyix)
493{
494 struct ieee80211_node *ni;
495
496 /* XXX recheck MIC to deal w/ chips that lie */
497 /* XXX discard MIC errors on !data frames */
498 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
499 if (ni != NULL) {
500 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
501 ieee80211_free_node(ni);
502 }
503}
504
505int
506ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
507 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf)
508{
509 struct ath_hal *ah = sc->sc_ah;
510 struct mbuf *m = bf->bf_m;
511 uint64_t rstamp;
512 int len, type;
513 struct ifnet *ifp = sc->sc_ifp;
514 struct ieee80211com *ic = ifp->if_l2com;
515 struct ieee80211_node *ni;
516 int is_good = 0;
517 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
518
519 /*
520 * Calculate the correct 64 bit TSF given
521 * the TSF64 register value and rs_tstamp.
522 */
523 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
524
525 /* These aren't specifically errors */
526#ifdef AH_SUPPORT_AR5416
527 if (rs->rs_flags & HAL_RX_GI)
528 sc->sc_stats.ast_rx_halfgi++;
529 if (rs->rs_flags & HAL_RX_2040)
530 sc->sc_stats.ast_rx_2040++;
531 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
532 sc->sc_stats.ast_rx_pre_crc_err++;
533 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
534 sc->sc_stats.ast_rx_post_crc_err++;
535 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
536 sc->sc_stats.ast_rx_decrypt_busy_err++;
537 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
538 sc->sc_stats.ast_rx_hi_rx_chain++;
539#endif /* AH_SUPPORT_AR5416 */
540
541 if (rs->rs_status != 0) {
542 if (rs->rs_status & HAL_RXERR_CRC)
543 sc->sc_stats.ast_rx_crcerr++;
544 if (rs->rs_status & HAL_RXERR_FIFO)
545 sc->sc_stats.ast_rx_fifoerr++;
546 if (rs->rs_status & HAL_RXERR_PHY) {
547 sc->sc_stats.ast_rx_phyerr++;
548 /* Process DFS radar events */
549 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
550 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
551 /* Since we're touching the frame data, sync it */
552 bus_dmamap_sync(sc->sc_dmat,
553 bf->bf_dmamap,
554 BUS_DMASYNC_POSTREAD);
555 /* Now pass it to the radar processing code */
556 ath_dfs_process_phy_err(sc, m, rstamp, rs);
557 }
558
559 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */
560 if (rs->rs_phyerr < 64)
561 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
562 goto rx_error; /* NB: don't count in ierrors */
563 }
564 if (rs->rs_status & HAL_RXERR_DECRYPT) {
565 /*
566 * Decrypt error. If the error occurred
567 * because there was no hardware key, then
568 * let the frame through so the upper layers
569 * can process it. This is necessary for 5210
570 * parts which have no way to setup a ``clear''
571 * key cache entry.
572 *
573 * XXX do key cache faulting
574 */
575 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
576 goto rx_accept;
577 sc->sc_stats.ast_rx_badcrypt++;
578 }
579 /*
580 * Similar as above - if the failure was a keymiss
581 * just punt it up to the upper layers for now.
582 */
583 if (rs->rs_status & HAL_RXERR_KEYMISS) {
584 sc->sc_stats.ast_rx_keymiss++;
585 goto rx_accept;
586 }
587 if (rs->rs_status & HAL_RXERR_MIC) {
588 sc->sc_stats.ast_rx_badmic++;
589 /*
590 * Do minimal work required to hand off
591 * the 802.11 header for notification.
592 */
593 /* XXX frag's and qos frames */
594 len = rs->rs_datalen;
595 if (len >= sizeof (struct ieee80211_frame)) {
596 bus_dmamap_sync(sc->sc_dmat,
597 bf->bf_dmamap,
598 BUS_DMASYNC_POSTREAD);
599 ath_handle_micerror(ic,
600 mtod(m, struct ieee80211_frame *),
601 sc->sc_splitmic ?
602 rs->rs_keyix-32 : rs->rs_keyix);
603 }
604 }
605 ifp->if_ierrors++;
606rx_error:
607 /*
608 * Cleanup any pending partial frame.
609 */
610 if (re->m_rxpending != NULL) {
611 m_freem(re->m_rxpending);
612 re->m_rxpending = NULL;
613 }
614 /*
615 * When a tap is present pass error frames
616 * that have been requested. By default we
617 * pass decrypt+mic errors but others may be
618 * interesting (e.g. crc).
619 */
620 if (ieee80211_radiotap_active(ic) &&
621 (rs->rs_status & sc->sc_monpass)) {
622 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
623 BUS_DMASYNC_POSTREAD);
624 /* NB: bpf needs the mbuf length setup */
625 len = rs->rs_datalen;
626 m->m_pkthdr.len = m->m_len = len;
627 bf->bf_m = NULL;
628 ath_rx_tap(ifp, m, rs, rstamp, nf);
629#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
630 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
631#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
632 ieee80211_radiotap_rx_all(ic, m);
633 m_freem(m);
634 }
635 /* XXX pass MIC errors up for s/w reclaculation */
636 goto rx_next;
637 }
638rx_accept:
639 /*
640 * Sync and unmap the frame. At this point we're
641 * committed to passing the mbuf somewhere so clear
642 * bf_m; this means a new mbuf must be allocated
643 * when the rx descriptor is setup again to receive
644 * another frame.
645 */
646 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
647 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
648 bf->bf_m = NULL;
649
650 len = rs->rs_datalen;
651 m->m_len = len;
652
653 if (rs->rs_more) {
654 /*
655 * Frame spans multiple descriptors; save
656 * it for the next completed descriptor, it
657 * will be used to construct a jumbogram.
658 */
659 if (re->m_rxpending != NULL) {
660 /* NB: max frame size is currently 2 clusters */
661 sc->sc_stats.ast_rx_toobig++;
662 m_freem(re->m_rxpending);
663 }
664 m->m_pkthdr.rcvif = ifp;
665 m->m_pkthdr.len = len;
666 re->m_rxpending = m;
667 goto rx_next;
668 } else if (re->m_rxpending != NULL) {
669 /*
670 * This is the second part of a jumbogram,
671 * chain it to the first mbuf, adjust the
672 * frame length, and clear the rxpending state.
673 */
674 re->m_rxpending->m_next = m;
675 re->m_rxpending->m_pkthdr.len += len;
676 m = re->m_rxpending;
677 re->m_rxpending = NULL;
678 } else {
679 /*
680 * Normal single-descriptor receive; setup
681 * the rcvif and packet length.
682 */
683 m->m_pkthdr.rcvif = ifp;
684 m->m_pkthdr.len = len;
685 }
686
687 /*
688 * Validate rs->rs_antenna.
689 *
690 * Some users w/ AR9285 NICs have reported crashes
691 * here because rs_antenna field is bogusly large.
692 * Let's enforce the maximum antenna limit of 8
693 * (and it shouldn't be hard coded, but that's a
694 * separate problem) and if there's an issue, print
695 * out an error and adjust rs_antenna to something
696 * sensible.
697 *
698 * This code should be removed once the actual
699 * root cause of the issue has been identified.
700 * For example, it may be that the rs_antenna
701 * field is only valid for the lsat frame of
702 * an aggregate and it just happens that it is
703 * "mostly" right. (This is a general statement -
704 * the majority of the statistics are only valid
705 * for the last frame in an aggregate.
706 */
707 if (rs->rs_antenna > 7) {
708 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
709 __func__, rs->rs_antenna);
710#ifdef ATH_DEBUG
711 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
712#endif /* ATH_DEBUG */
713 rs->rs_antenna = 0; /* XXX better than nothing */
714 }
715
716 ifp->if_ipackets++;
717 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
718
719 /*
720 * Populate the rx status block. When there are bpf
721 * listeners we do the additional work to provide
722 * complete status. Otherwise we fill in only the
723 * material required by ieee80211_input. Note that
724 * noise setting is filled in above.
725 */
726 if (ieee80211_radiotap_active(ic)) {
727 ath_rx_tap(ifp, m, rs, rstamp, nf);
728#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
729 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
730#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
731 }
732
733 /*
734 * From this point on we assume the frame is at least
735 * as large as ieee80211_frame_min; verify that.
736 */
737 if (len < IEEE80211_MIN_LEN) {
738 if (!ieee80211_radiotap_active(ic)) {
739 DPRINTF(sc, ATH_DEBUG_RECV,
740 "%s: short packet %d\n", __func__, len);
741 sc->sc_stats.ast_rx_tooshort++;
742 } else {
743 /* NB: in particular this captures ack's */
744 ieee80211_radiotap_rx_all(ic, m);
745 }
746 m_freem(m);
747 goto rx_next;
748 }
749
750 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
751 const HAL_RATE_TABLE *rt = sc->sc_currates;
752 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
753
754 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
755 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
756 }
757
758 m_adj(m, -IEEE80211_CRC_LEN);
759
760 /*
761 * Locate the node for sender, track state, and then
762 * pass the (referenced) node up to the 802.11 layer
763 * for its use.
764 */
765 ni = ieee80211_find_rxnode_withkey(ic,
766 mtod(m, const struct ieee80211_frame_min *),
767 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
768 IEEE80211_KEYIX_NONE : rs->rs_keyix);
769 sc->sc_lastrs = rs;
770
771#ifdef AH_SUPPORT_AR5416
772 if (rs->rs_isaggr)
773 sc->sc_stats.ast_rx_agg++;
774#endif /* AH_SUPPORT_AR5416 */
775
776 if (ni != NULL) {
777 /*
778 * Only punt packets for ampdu reorder processing for
779 * 11n nodes; net80211 enforces that M_AMPDU is only
780 * set for 11n nodes.
781 */
782 if (ni->ni_flags & IEEE80211_NODE_HT)
783 m->m_flags |= M_AMPDU;
784
785 /*
786 * Sending station is known, dispatch directly.
787 */
788 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
789 ieee80211_free_node(ni);
790 /*
791 * Arrange to update the last rx timestamp only for
792 * frames from our ap when operating in station mode.
793 * This assumes the rx key is always setup when
794 * associated.
795 */
796 if (ic->ic_opmode == IEEE80211_M_STA &&
797 rs->rs_keyix != HAL_RXKEYIX_INVALID)
798 is_good = 1;
799 } else {
800 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
801 }
802 /*
803 * Track rx rssi and do any rx antenna management.
804 */
805 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
806 if (sc->sc_diversity) {
807 /*
808 * When using fast diversity, change the default rx
809 * antenna if diversity chooses the other antenna 3
810 * times in a row.
811 */
812 if (sc->sc_defant != rs->rs_antenna) {
813 if (++sc->sc_rxotherant >= 3)
814 ath_setdefantenna(sc, rs->rs_antenna);
815 } else
816 sc->sc_rxotherant = 0;
817 }
818
819 /* Newer school diversity - kite specific for now */
820 /* XXX perhaps migrate the normal diversity code to this? */
821 if ((ah)->ah_rxAntCombDiversity)
822 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz);
823
824 if (sc->sc_softled) {
825 /*
826 * Blink for any data frame. Otherwise do a
827 * heartbeat-style blink when idle. The latter
828 * is mainly for station mode where we depend on
829 * periodic beacon frames to trigger the poll event.
830 */
831 if (type == IEEE80211_FC0_TYPE_DATA) {
832 const HAL_RATE_TABLE *rt = sc->sc_currates;
833 ath_led_event(sc,
834 rt->rateCodeToIndex[rs->rs_rate]);
835 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
836 ath_led_event(sc, 0);
837 }
838rx_next:
839 return (is_good);
840}
841
842#define ATH_RX_MAX 128
843
844static void
845ath_rx_proc(struct ath_softc *sc, int resched)
846{
847#define PA2DESC(_sc, _pa) \
848 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
849 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
850 struct ath_buf *bf;
851 struct ifnet *ifp = sc->sc_ifp;
852 struct ath_hal *ah = sc->sc_ah;
853#ifdef IEEE80211_SUPPORT_SUPERG
854 struct ieee80211com *ic = ifp->if_l2com;
855#endif
856 struct ath_desc *ds;
857 struct ath_rx_status *rs;
858 struct mbuf *m;
859 int ngood;
860 HAL_STATUS status;
861 int16_t nf;
862 u_int64_t tsf;
863 int npkts = 0;
864 int kickpcu = 0;
865
866 /* XXX we must not hold the ATH_LOCK here */
867 ATH_UNLOCK_ASSERT(sc);
868 ATH_PCU_UNLOCK_ASSERT(sc);
869
870 ATH_PCU_LOCK(sc);
871 sc->sc_rxproc_cnt++;
872 kickpcu = sc->sc_kickpcu;
873 ATH_PCU_UNLOCK(sc);
874
875 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
876 ngood = 0;
877 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
878 sc->sc_stats.ast_rx_noise = nf;
879 tsf = ath_hal_gettsf64(ah);
880 do {
881 /*
882 * Don't process too many packets at a time; give the
883 * TX thread time to also run - otherwise the TX
884 * latency can jump by quite a bit, causing throughput
885 * degredation.
886 */
887 if (!kickpcu && npkts >= ATH_RX_MAX)
888 break;
889
890 bf = TAILQ_FIRST(&sc->sc_rxbuf);
891 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
892 if_printf(ifp, "%s: no buffer!\n", __func__);
893 break;
894 } else if (bf == NULL) {
895 /*
896 * End of List:
897 * this can happen for non-self-linked RX chains
898 */
899 sc->sc_stats.ast_rx_hitqueueend++;
900 break;
901 }
902 m = bf->bf_m;
903 if (m == NULL) { /* NB: shouldn't happen */
904 /*
905 * If mbuf allocation failed previously there
906 * will be no mbuf; try again to re-populate it.
907 */
908 /* XXX make debug msg */
909 if_printf(ifp, "%s: no mbuf!\n", __func__);
910 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
911 goto rx_proc_next;
912 }
913 ds = bf->bf_desc;
914 if (ds->ds_link == bf->bf_daddr) {
915 /* NB: never process the self-linked entry at the end */
916 sc->sc_stats.ast_rx_hitqueueend++;
917 break;
918 }
919 /* XXX sync descriptor memory */
920 /*
921 * Must provide the virtual address of the current
922 * descriptor, the physical address, and the virtual
923 * address of the next descriptor in the h/w chain.
924 * This allows the HAL to look ahead to see if the
925 * hardware is done with a descriptor by checking the
926 * done bit in the following descriptor and the address
927 * of the current descriptor the DMA engine is working
928 * on. All this is necessary because of our use of
929 * a self-linked list to avoid rx overruns.
930 */
931 rs = &bf->bf_status.ds_rxstat;
932 status = ath_hal_rxprocdesc(ah, ds,
933 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
934#ifdef ATH_DEBUG
935 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
936 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
937#endif
938
939#ifdef ATH_DEBUG_ALQ
940 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
941 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
942 sc->sc_rx_statuslen, (char *) ds);
943#endif /* ATH_DEBUG_ALQ */
944
945 if (status == HAL_EINPROGRESS)
946 break;
947
948 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
949 npkts++;
950
951 /*
952 * Process a single frame.
953 */
954 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf))
955 ngood++;
956rx_proc_next:
957 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
958 } while (ath_rxbuf_init(sc, bf) == 0);
959
960 /* rx signal state monitoring */
961 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
962 if (ngood)
963 sc->sc_lastrx = tsf;
964
965 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
966 /* Queue DFS tasklet if needed */
967 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
968 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
969
970 /*
971 * Now that all the RX frames were handled that
972 * need to be handled, kick the PCU if there's
973 * been an RXEOL condition.
974 */
975 if (resched && kickpcu) {
976 ATH_PCU_LOCK(sc);
977 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
978 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
979 __func__, npkts);
980
981 /*
982 * Go through the process of fully tearing down
983 * the RX buffers and reinitialising them.
984 *
985 * There's a hardware bug that causes the RX FIFO
986 * to get confused under certain conditions and
987 * constantly write over the same frame, leading
988 * the RX driver code here to get heavily confused.
989 */
990#if 1
991 ath_startrecv(sc);
992#else
993 /*
994 * Disabled for now - it'd be nice to be able to do
995 * this in order to limit the amount of CPU time spent
996 * reinitialising the RX side (and thus minimise RX
997 * drops) however there's a hardware issue that
998 * causes things to get too far out of whack.
999 */
1000 /*
1001 * XXX can we hold the PCU lock here?
1002 * Are there any net80211 buffer calls involved?
1003 */
1004 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1005 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1006 ath_hal_rxena(ah); /* enable recv descriptors */
1007 ath_mode_init(sc); /* set filters, etc. */
1008 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1009#endif
1010
1011 ath_hal_intrset(ah, sc->sc_imask);
1012 sc->sc_kickpcu = 0;
1013 ATH_PCU_UNLOCK(sc);
1014 }
1015
1016 /* XXX check this inside of IF_LOCK? */
1017 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
1018#ifdef IEEE80211_SUPPORT_SUPERG
1019 ieee80211_ff_age_all(ic, 100);
1020#endif
1021 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1022 ath_tx_kick(sc);
1023 }
1024#undef PA2DESC
1025
1026 /*
1027 * If we hit the maximum number of frames in this round,
1028 * reschedule for another immediate pass. This gives
1029 * the TX and TX completion routines time to run, which
1030 * will reduce latency.
1031 */
1032 if (npkts >= ATH_RX_MAX)
1033 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1034
1035 ATH_PCU_LOCK(sc);
1036 sc->sc_rxproc_cnt--;
1037 ATH_PCU_UNLOCK(sc);
1038}
1039
1040#undef ATH_RX_MAX
1041
1042/*
1043 * Only run the RX proc if it's not already running.
1044 * Since this may get run as part of the reset/flush path,
1045 * the task can't clash with an existing, running tasklet.
1046 */
1047static void
1048ath_legacy_rx_tasklet(void *arg, int npending)
1049{
1050 struct ath_softc *sc = arg;
1051
1052 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1053 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1054 ATH_PCU_LOCK(sc);
1055 if (sc->sc_inreset_cnt > 0) {
1056 device_printf(sc->sc_dev,
1057 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1058 ATH_PCU_UNLOCK(sc);
1059 return;
1060 }
1061 ATH_PCU_UNLOCK(sc);
1062
1063 ath_rx_proc(sc, 1);
1064}
1065
1066static void
1067ath_legacy_flushrecv(struct ath_softc *sc)
1068{
1069
1070 ath_rx_proc(sc, 0);
1071}
1072
1073/*
1074 * Disable the receive h/w in preparation for a reset.
1075 */
1076static void
1077ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1078{
1079#define PA2DESC(_sc, _pa) \
1080 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1081 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1082 struct ath_hal *ah = sc->sc_ah;
1083
1084 ath_hal_stoppcurecv(ah); /* disable PCU */
1085 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1086 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1087 /*
1088 * TODO: see if this particular DELAY() is required; it may be
1089 * masking some missing FIFO flush or DMA sync.
1090 */
1091#if 0
1092 if (dodelay)
1093#endif
1094 DELAY(3000); /* 3ms is long enough for 1 frame */
1095#ifdef ATH_DEBUG
1096 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1097 struct ath_buf *bf;
1098 u_int ix;
1099
1100 device_printf(sc->sc_dev,
1101 "%s: rx queue %p, link %p\n",
1102 __func__,
1103 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1104 sc->sc_rxlink);
1105 ix = 0;
1106 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1107 struct ath_desc *ds = bf->bf_desc;
1108 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1109 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1110 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1111 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1112 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1113 ix++;
1114 }
1115 }
1116#endif
1117 /*
1118 * Free both high/low RX pending, just in case.
1119 */
1120 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1121 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1122 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1123 }
1124 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1125 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1126 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1127 }
1128 sc->sc_rxlink = NULL; /* just in case */
1129#undef PA2DESC
1130}
1131
1132/*
1133 * Enable the receive h/w following a reset.
1134 */
1135static int
1136ath_legacy_startrecv(struct ath_softc *sc)
1137{
1138 struct ath_hal *ah = sc->sc_ah;
1139 struct ath_buf *bf;
1140
1141 sc->sc_rxlink = NULL;
1142 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1143 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1144 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1145 int error = ath_rxbuf_init(sc, bf);
1146 if (error != 0) {
1147 DPRINTF(sc, ATH_DEBUG_RECV,
1148 "%s: ath_rxbuf_init failed %d\n",
1149 __func__, error);
1150 return error;
1151 }
1152 }
1153
1154 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1155 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1156 ath_hal_rxena(ah); /* enable recv descriptors */
1157 ath_mode_init(sc); /* set filters, etc. */
1158 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1159 return 0;
1160}
1161
1162static int
1163ath_legacy_dma_rxsetup(struct ath_softc *sc)
1164{
1165 int error;
1166
1167 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1168 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1169 if (error != 0)
1170 return (error);
1171
1172 return (0);
1173}
1174
1175static int
1176ath_legacy_dma_rxteardown(struct ath_softc *sc)
1177{
1178
1179 if (sc->sc_rxdma.dd_desc_len != 0)
1180 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1181 return (0);
1182}
1183
1184void
1185ath_recv_setup_legacy(struct ath_softc *sc)
1186{
1187
1188 /* Sensible legacy defaults */
1189 /*
1190 * XXX this should be changed to properly support the
1191 * exact RX descriptor size for each HAL.
1192 */
1193 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1194
1195 sc->sc_rx.recv_start = ath_legacy_startrecv;
1196 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1197 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1198 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1199 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1200
1201 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1202 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1203}
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