1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
|
31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_pci.c 238433 2012-07-14 02:22:17Z adrian $");
| 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_pci.c 238709 2012-07-23 02:49:25Z adrian $");
|
32
33/*
34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
35 */
36#include "opt_ath.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/module.h>
41#include <sys/kernel.h>
42#include <sys/lock.h>
43#include <sys/mutex.h>
44#include <sys/errno.h>
45
46#include <machine/bus.h>
47#include <machine/resource.h>
48#include <sys/bus.h>
49#include <sys/rman.h>
50
51#include <sys/socket.h>
52
53#include <net/if.h>
54#include <net/if_media.h>
55#include <net/if_arp.h>
56
57#include <net80211/ieee80211_var.h>
58
59#include <dev/ath/if_athvar.h>
60
61#include <dev/pci/pcivar.h>
62#include <dev/pci/pcireg.h>
63
64/* For EEPROM firmware */
65#ifdef ATH_EEPROM_FIRMWARE
66#include <sys/linker.h>
67#include <sys/firmware.h>
68#endif /* ATH_EEPROM_FIRMWARE */
69
70/*
71 * PCI glue.
72 */
73
74struct ath_pci_softc {
75 struct ath_softc sc_sc;
76 struct resource *sc_sr; /* memory resource */
77 struct resource *sc_irq; /* irq resource */
78 void *sc_ih; /* interrupt handler */
79};
80
81#define BS_BAR 0x10
82#define PCIR_RETRY_TIMEOUT 0x41
83#define PCIR_CFG_PMCSR 0x48
84
85#define DEFAULT_CACHESIZE 32
86
87static void
88ath_pci_setup(device_t dev)
89{
90 uint8_t cz;
91
92 /* XXX TODO: need to override the _system_ saved copies of this */
93
94 /*
95 * If the cache line size is 0, force it to a reasonable
96 * value.
97 */
98 cz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
99 if (cz == 0) {
100 pci_write_config(dev, PCIR_CACHELNSZ,
101 DEFAULT_CACHESIZE / 4, 1);
102 }
103
104 /* Override the system latency timer */
105 pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1);
106
107 /* If a PCI NIC, force wakeup */
108#ifdef ATH_PCI_WAKEUP_WAR
109 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */
110 if (1) {
111 uint16_t pmcsr;
112 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2);
113 pmcsr |= 3;
114 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
115 pmcsr &= ~3;
116 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
117 }
118#endif
119
120 /*
121 * Disable retry timeout to keep PCI Tx retries from
122 * interfering with C3 CPU state.
123 */
124 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1);
125}
126
127static int
128ath_pci_probe(device_t dev)
129{
130 const char* devname;
131
132 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
133 if (devname != NULL) {
134 device_set_desc(dev, devname);
135 return BUS_PROBE_DEFAULT;
136 }
137 return ENXIO;
138}
139
140static int
141ath_pci_attach(device_t dev)
142{
143 struct ath_pci_softc *psc = device_get_softc(dev);
144 struct ath_softc *sc = &psc->sc_sc;
145 int error = ENXIO;
146 int rid;
147#ifdef ATH_EEPROM_FIRMWARE
148 const struct firmware *fw = NULL;
149 const char *buf;
150#endif
151
152 sc->sc_dev = dev;
153
154 /*
155 * Enable bus mastering.
156 */
157 pci_enable_busmaster(dev);
158
159 /*
160 * Setup other PCI bus configuration parameters.
161 */
162 ath_pci_setup(dev);
163
164 /*
165 * Setup memory-mapping of PCI registers.
166 */
167 rid = BS_BAR;
168 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
169 RF_ACTIVE);
170 if (psc->sc_sr == NULL) {
171 device_printf(dev, "cannot map register space\n");
172 goto bad;
173 }
174 /* XXX uintptr_t is a bandaid for ia64; to be fixed */
175 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr);
176 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr);
177 /*
178 * Mark device invalid so any interrupts (shared or otherwise)
179 * that arrive before the HAL is setup are discarded.
180 */
181 sc->sc_invalid = 1;
182
183 /*
184 * Arrange interrupt line.
185 */
186 rid = 0;
187 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
188 RF_SHAREABLE|RF_ACTIVE);
189 if (psc->sc_irq == NULL) {
190 device_printf(dev, "could not map interrupt\n");
191 goto bad1;
192 }
193 if (bus_setup_intr(dev, psc->sc_irq,
194 INTR_TYPE_NET | INTR_MPSAFE,
195 NULL, ath_intr, sc, &psc->sc_ih)) {
196 device_printf(dev, "could not establish interrupt\n");
197 goto bad2;
198 }
199
200 /*
201 * Setup DMA descriptor area.
202 */
203 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
204 1, 0, /* alignment, bounds */
205 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
206 BUS_SPACE_MAXADDR, /* highaddr */
207 NULL, NULL, /* filter, filterarg */
208 0x3ffff, /* maxsize XXX */
209 ATH_MAX_SCATTER, /* nsegments */
210 0x3ffff, /* maxsegsize XXX */
211 BUS_DMA_ALLOCNOW, /* flags */
212 NULL, /* lockfunc */
213 NULL, /* lockarg */
214 &sc->sc_dmat)) {
215 device_printf(dev, "cannot allocate DMA tag\n");
216 goto bad3;
217 }
218
219#ifdef ATH_EEPROM_FIRMWARE
220 /*
221 * If there's an EEPROM firmware image, load that in.
222 */
223 if (resource_string_value(device_get_name(dev), device_get_unit(dev),
224 "eeprom_firmware", &buf) == 0) {
225 if (bootverbose)
226 device_printf(dev, "%s: looking up firmware @ '%s'\n",
227 __func__, buf);
228
229 fw = firmware_get(buf);
230 if (fw == NULL) {
231 device_printf(dev, "%s: couldn't find firmware\n",
232 __func__);
233 goto bad3;
234 }
235
236 device_printf(dev, "%s: EEPROM firmware @ %p\n",
237 __func__, fw->data);
238 sc->sc_eepromdata =
239 malloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO);
240 if (! sc->sc_eepromdata) {
241 device_printf(dev, "%s: can't malloc eepromdata\n",
242 __func__);
243 goto bad3;
244 }
245 memcpy(sc->sc_eepromdata, fw->data, fw->datasize);
246 firmware_put(fw, 0);
247 }
248#endif /* ATH_EEPROM_FIRMWARE */
249
250 ATH_LOCK_INIT(sc);
251 ATH_PCU_LOCK_INIT(sc);
252 ATH_RX_LOCK_INIT(sc);
| 32
33/*
34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
35 */
36#include "opt_ath.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/module.h>
41#include <sys/kernel.h>
42#include <sys/lock.h>
43#include <sys/mutex.h>
44#include <sys/errno.h>
45
46#include <machine/bus.h>
47#include <machine/resource.h>
48#include <sys/bus.h>
49#include <sys/rman.h>
50
51#include <sys/socket.h>
52
53#include <net/if.h>
54#include <net/if_media.h>
55#include <net/if_arp.h>
56
57#include <net80211/ieee80211_var.h>
58
59#include <dev/ath/if_athvar.h>
60
61#include <dev/pci/pcivar.h>
62#include <dev/pci/pcireg.h>
63
64/* For EEPROM firmware */
65#ifdef ATH_EEPROM_FIRMWARE
66#include <sys/linker.h>
67#include <sys/firmware.h>
68#endif /* ATH_EEPROM_FIRMWARE */
69
70/*
71 * PCI glue.
72 */
73
74struct ath_pci_softc {
75 struct ath_softc sc_sc;
76 struct resource *sc_sr; /* memory resource */
77 struct resource *sc_irq; /* irq resource */
78 void *sc_ih; /* interrupt handler */
79};
80
81#define BS_BAR 0x10
82#define PCIR_RETRY_TIMEOUT 0x41
83#define PCIR_CFG_PMCSR 0x48
84
85#define DEFAULT_CACHESIZE 32
86
87static void
88ath_pci_setup(device_t dev)
89{
90 uint8_t cz;
91
92 /* XXX TODO: need to override the _system_ saved copies of this */
93
94 /*
95 * If the cache line size is 0, force it to a reasonable
96 * value.
97 */
98 cz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
99 if (cz == 0) {
100 pci_write_config(dev, PCIR_CACHELNSZ,
101 DEFAULT_CACHESIZE / 4, 1);
102 }
103
104 /* Override the system latency timer */
105 pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1);
106
107 /* If a PCI NIC, force wakeup */
108#ifdef ATH_PCI_WAKEUP_WAR
109 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */
110 if (1) {
111 uint16_t pmcsr;
112 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2);
113 pmcsr |= 3;
114 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
115 pmcsr &= ~3;
116 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
117 }
118#endif
119
120 /*
121 * Disable retry timeout to keep PCI Tx retries from
122 * interfering with C3 CPU state.
123 */
124 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1);
125}
126
127static int
128ath_pci_probe(device_t dev)
129{
130 const char* devname;
131
132 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
133 if (devname != NULL) {
134 device_set_desc(dev, devname);
135 return BUS_PROBE_DEFAULT;
136 }
137 return ENXIO;
138}
139
140static int
141ath_pci_attach(device_t dev)
142{
143 struct ath_pci_softc *psc = device_get_softc(dev);
144 struct ath_softc *sc = &psc->sc_sc;
145 int error = ENXIO;
146 int rid;
147#ifdef ATH_EEPROM_FIRMWARE
148 const struct firmware *fw = NULL;
149 const char *buf;
150#endif
151
152 sc->sc_dev = dev;
153
154 /*
155 * Enable bus mastering.
156 */
157 pci_enable_busmaster(dev);
158
159 /*
160 * Setup other PCI bus configuration parameters.
161 */
162 ath_pci_setup(dev);
163
164 /*
165 * Setup memory-mapping of PCI registers.
166 */
167 rid = BS_BAR;
168 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
169 RF_ACTIVE);
170 if (psc->sc_sr == NULL) {
171 device_printf(dev, "cannot map register space\n");
172 goto bad;
173 }
174 /* XXX uintptr_t is a bandaid for ia64; to be fixed */
175 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr);
176 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr);
177 /*
178 * Mark device invalid so any interrupts (shared or otherwise)
179 * that arrive before the HAL is setup are discarded.
180 */
181 sc->sc_invalid = 1;
182
183 /*
184 * Arrange interrupt line.
185 */
186 rid = 0;
187 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
188 RF_SHAREABLE|RF_ACTIVE);
189 if (psc->sc_irq == NULL) {
190 device_printf(dev, "could not map interrupt\n");
191 goto bad1;
192 }
193 if (bus_setup_intr(dev, psc->sc_irq,
194 INTR_TYPE_NET | INTR_MPSAFE,
195 NULL, ath_intr, sc, &psc->sc_ih)) {
196 device_printf(dev, "could not establish interrupt\n");
197 goto bad2;
198 }
199
200 /*
201 * Setup DMA descriptor area.
202 */
203 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
204 1, 0, /* alignment, bounds */
205 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
206 BUS_SPACE_MAXADDR, /* highaddr */
207 NULL, NULL, /* filter, filterarg */
208 0x3ffff, /* maxsize XXX */
209 ATH_MAX_SCATTER, /* nsegments */
210 0x3ffff, /* maxsegsize XXX */
211 BUS_DMA_ALLOCNOW, /* flags */
212 NULL, /* lockfunc */
213 NULL, /* lockarg */
214 &sc->sc_dmat)) {
215 device_printf(dev, "cannot allocate DMA tag\n");
216 goto bad3;
217 }
218
219#ifdef ATH_EEPROM_FIRMWARE
220 /*
221 * If there's an EEPROM firmware image, load that in.
222 */
223 if (resource_string_value(device_get_name(dev), device_get_unit(dev),
224 "eeprom_firmware", &buf) == 0) {
225 if (bootverbose)
226 device_printf(dev, "%s: looking up firmware @ '%s'\n",
227 __func__, buf);
228
229 fw = firmware_get(buf);
230 if (fw == NULL) {
231 device_printf(dev, "%s: couldn't find firmware\n",
232 __func__);
233 goto bad3;
234 }
235
236 device_printf(dev, "%s: EEPROM firmware @ %p\n",
237 __func__, fw->data);
238 sc->sc_eepromdata =
239 malloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO);
240 if (! sc->sc_eepromdata) {
241 device_printf(dev, "%s: can't malloc eepromdata\n",
242 __func__);
243 goto bad3;
244 }
245 memcpy(sc->sc_eepromdata, fw->data, fw->datasize);
246 firmware_put(fw, 0);
247 }
248#endif /* ATH_EEPROM_FIRMWARE */
249
250 ATH_LOCK_INIT(sc);
251 ATH_PCU_LOCK_INIT(sc);
252 ATH_RX_LOCK_INIT(sc);
|
| 253 ATH_TXSTATUS_LOCK_INIT(sc);
|
253
254 error = ath_attach(pci_get_device(dev), sc);
255 if (error == 0) /* success */
256 return 0;
257
| 254
255 error = ath_attach(pci_get_device(dev), sc);
256 if (error == 0) /* success */
257 return 0;
258
|
| 259 ATH_TXSTATUS_LOCK_DESTROY(sc);
|
258 ATH_PCU_LOCK_DESTROY(sc);
259 ATH_RX_LOCK_DESTROY(sc);
260 ATH_LOCK_DESTROY(sc);
261 bus_dma_tag_destroy(sc->sc_dmat);
262bad3:
263 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
264bad2:
265 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
266bad1:
267 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
268bad:
269 return (error);
270}
271
272static int
273ath_pci_detach(device_t dev)
274{
275 struct ath_pci_softc *psc = device_get_softc(dev);
276 struct ath_softc *sc = &psc->sc_sc;
277
278 /* check if device was removed */
279 sc->sc_invalid = !bus_child_present(dev);
280
281 /*
282 * Do a config read to clear pre-existing pci error status.
283 */
284 (void) pci_read_config(dev, PCIR_COMMAND, 4);
285
286 ath_detach(sc);
287
288 bus_generic_detach(dev);
289 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
290 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
291
292 bus_dma_tag_destroy(sc->sc_dmat);
293 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
294
295 if (sc->sc_eepromdata)
296 free(sc->sc_eepromdata, M_TEMP);
297
| 260 ATH_PCU_LOCK_DESTROY(sc);
261 ATH_RX_LOCK_DESTROY(sc);
262 ATH_LOCK_DESTROY(sc);
263 bus_dma_tag_destroy(sc->sc_dmat);
264bad3:
265 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
266bad2:
267 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
268bad1:
269 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
270bad:
271 return (error);
272}
273
274static int
275ath_pci_detach(device_t dev)
276{
277 struct ath_pci_softc *psc = device_get_softc(dev);
278 struct ath_softc *sc = &psc->sc_sc;
279
280 /* check if device was removed */
281 sc->sc_invalid = !bus_child_present(dev);
282
283 /*
284 * Do a config read to clear pre-existing pci error status.
285 */
286 (void) pci_read_config(dev, PCIR_COMMAND, 4);
287
288 ath_detach(sc);
289
290 bus_generic_detach(dev);
291 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
292 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
293
294 bus_dma_tag_destroy(sc->sc_dmat);
295 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
296
297 if (sc->sc_eepromdata)
298 free(sc->sc_eepromdata, M_TEMP);
299
|
| 300 ATH_TXSTATUS_LOCK_DESTROY(sc);
|
298 ATH_PCU_LOCK_DESTROY(sc);
299 ATH_RX_LOCK_DESTROY(sc);
300 ATH_LOCK_DESTROY(sc);
301
302 return (0);
303}
304
305static int
306ath_pci_shutdown(device_t dev)
307{
308 struct ath_pci_softc *psc = device_get_softc(dev);
309
310 ath_shutdown(&psc->sc_sc);
311 return (0);
312}
313
314static int
315ath_pci_suspend(device_t dev)
316{
317 struct ath_pci_softc *psc = device_get_softc(dev);
318
319 ath_suspend(&psc->sc_sc);
320
321 return (0);
322}
323
324static int
325ath_pci_resume(device_t dev)
326{
327 struct ath_pci_softc *psc = device_get_softc(dev);
328
329 /*
330 * Suspend/resume resets the PCI configuration space.
331 */
332 ath_pci_setup(dev);
333
334 ath_resume(&psc->sc_sc);
335
336 return (0);
337}
338
339static device_method_t ath_pci_methods[] = {
340 /* Device interface */
341 DEVMETHOD(device_probe, ath_pci_probe),
342 DEVMETHOD(device_attach, ath_pci_attach),
343 DEVMETHOD(device_detach, ath_pci_detach),
344 DEVMETHOD(device_shutdown, ath_pci_shutdown),
345 DEVMETHOD(device_suspend, ath_pci_suspend),
346 DEVMETHOD(device_resume, ath_pci_resume),
347
348 { 0,0 }
349};
350static driver_t ath_pci_driver = {
351 "ath",
352 ath_pci_methods,
353 sizeof (struct ath_pci_softc)
354};
355static devclass_t ath_devclass;
356DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0);
357MODULE_VERSION(ath_pci, 1);
358MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */
359MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */
| 301 ATH_PCU_LOCK_DESTROY(sc);
302 ATH_RX_LOCK_DESTROY(sc);
303 ATH_LOCK_DESTROY(sc);
304
305 return (0);
306}
307
308static int
309ath_pci_shutdown(device_t dev)
310{
311 struct ath_pci_softc *psc = device_get_softc(dev);
312
313 ath_shutdown(&psc->sc_sc);
314 return (0);
315}
316
317static int
318ath_pci_suspend(device_t dev)
319{
320 struct ath_pci_softc *psc = device_get_softc(dev);
321
322 ath_suspend(&psc->sc_sc);
323
324 return (0);
325}
326
327static int
328ath_pci_resume(device_t dev)
329{
330 struct ath_pci_softc *psc = device_get_softc(dev);
331
332 /*
333 * Suspend/resume resets the PCI configuration space.
334 */
335 ath_pci_setup(dev);
336
337 ath_resume(&psc->sc_sc);
338
339 return (0);
340}
341
342static device_method_t ath_pci_methods[] = {
343 /* Device interface */
344 DEVMETHOD(device_probe, ath_pci_probe),
345 DEVMETHOD(device_attach, ath_pci_attach),
346 DEVMETHOD(device_detach, ath_pci_detach),
347 DEVMETHOD(device_shutdown, ath_pci_shutdown),
348 DEVMETHOD(device_suspend, ath_pci_suspend),
349 DEVMETHOD(device_resume, ath_pci_resume),
350
351 { 0,0 }
352};
353static driver_t ath_pci_driver = {
354 "ath",
355 ath_pci_methods,
356 sizeof (struct ath_pci_softc)
357};
358static devclass_t ath_devclass;
359DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0);
360MODULE_VERSION(ath_pci, 1);
361MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */
362MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */
|