1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
|
32
33/*
34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/module.h>
40#include <sys/kernel.h>
41#include <sys/lock.h>
42#include <sys/mutex.h>
43#include <sys/errno.h>
44
45#include <machine/bus.h>
46#include <machine/resource.h>
47#include <sys/bus.h>
48#include <sys/rman.h>
49
50#include <sys/socket.h>
51
52#include <net/if.h>
53#include <net/if_media.h>
54#include <net/if_arp.h>
55
56#include <net80211/ieee80211_var.h>
57
58#include <dev/ath/if_athvar.h>
59
60#include <dev/pci/pcivar.h>
61#include <dev/pci/pcireg.h>
62
63/*
64 * PCI glue.
65 */
66
67struct ath_pci_softc {
68 struct ath_softc sc_sc;
69 struct resource *sc_sr; /* memory resource */
70 struct resource *sc_irq; /* irq resource */
71 void *sc_ih; /* interrupt handler */
72};
73
74#define BS_BAR 0x10
75#define PCIR_RETRY_TIMEOUT 0x41
76
77static int
78ath_pci_probe(device_t dev)
79{
80 const char* devname;
81
82 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
83 if (devname != NULL) {
84 device_set_desc(dev, devname);
85 return BUS_PROBE_DEFAULT;
86 }
87 return ENXIO;
88}
89
90static int
91ath_pci_attach(device_t dev)
92{
93 struct ath_pci_softc *psc = device_get_softc(dev);
94 struct ath_softc *sc = &psc->sc_sc;
95 int error = ENXIO;
96 int rid;
97
98 sc->sc_dev = dev;
99
100 /*
101 * Enable bus mastering.
102 */
103 pci_enable_busmaster(dev);
104
105 /*
106 * Disable retry timeout to keep PCI Tx retries from
107 * interfering with C3 CPU state.
108 */
109 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1);
110
111 /*
112 * Setup memory-mapping of PCI registers.
113 */
114 rid = BS_BAR;
115 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
116 RF_ACTIVE);
117 if (psc->sc_sr == NULL) {
118 device_printf(dev, "cannot map register space\n");
119 goto bad;
120 }
121 /* XXX uintptr_t is a bandaid for ia64; to be fixed */
122 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr);
123 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr);
124 /*
125 * Mark device invalid so any interrupts (shared or otherwise)
126 * that arrive before the HAL is setup are discarded.
127 */
128 sc->sc_invalid = 1;
129
130 /*
131 * Arrange interrupt line.
132 */
133 rid = 0;
134 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
135 RF_SHAREABLE|RF_ACTIVE);
136 if (psc->sc_irq == NULL) {
137 device_printf(dev, "could not map interrupt\n");
138 goto bad1;
139 }
140 if (bus_setup_intr(dev, psc->sc_irq,
141 INTR_TYPE_NET | INTR_MPSAFE,
142 NULL, ath_intr, sc, &psc->sc_ih)) {
143 device_printf(dev, "could not establish interrupt\n");
144 goto bad2;
145 }
146
147 /*
148 * Setup DMA descriptor area.
149 */
150 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
151 1, 0, /* alignment, bounds */
152 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
153 BUS_SPACE_MAXADDR, /* highaddr */
154 NULL, NULL, /* filter, filterarg */
155 0x3ffff, /* maxsize XXX */
156 ATH_MAX_SCATTER, /* nsegments */
157 0x3ffff, /* maxsegsize XXX */
158 BUS_DMA_ALLOCNOW, /* flags */
159 NULL, /* lockfunc */
160 NULL, /* lockarg */
161 &sc->sc_dmat)) {
162 device_printf(dev, "cannot allocate DMA tag\n");
163 goto bad3;
164 }
165
166 ATH_LOCK_INIT(sc);
167
168 error = ath_attach(pci_get_device(dev), sc);
169 if (error == 0) /* success */
170 return 0;
171
172 ATH_LOCK_DESTROY(sc);
173 bus_dma_tag_destroy(sc->sc_dmat);
174bad3:
175 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
176bad2:
177 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
178bad1:
179 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
180bad:
181 return (error);
182}
183
184static int
185ath_pci_detach(device_t dev)
186{
187 struct ath_pci_softc *psc = device_get_softc(dev);
188 struct ath_softc *sc = &psc->sc_sc;
189
190 /* check if device was removed */
191 sc->sc_invalid = !bus_child_present(dev);
192
193 ath_detach(sc);
194
195 bus_generic_detach(dev);
196 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
197 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
198
199 bus_dma_tag_destroy(sc->sc_dmat);
200 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
201
202 ATH_LOCK_DESTROY(sc);
203
204 return (0);
205}
206
207static int
208ath_pci_shutdown(device_t dev)
209{
210 struct ath_pci_softc *psc = device_get_softc(dev);
211
212 ath_shutdown(&psc->sc_sc);
213 return (0);
214}
215
216static int
217ath_pci_suspend(device_t dev)
218{
219 struct ath_pci_softc *psc = device_get_softc(dev);
220
221 ath_suspend(&psc->sc_sc);
222
223 return (0);
224}
225
226static int
227ath_pci_resume(device_t dev)
228{
229 struct ath_pci_softc *psc = device_get_softc(dev);
230
231 ath_resume(&psc->sc_sc);
232
233 return (0);
234}
235
236static device_method_t ath_pci_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, ath_pci_probe),
239 DEVMETHOD(device_attach, ath_pci_attach),
240 DEVMETHOD(device_detach, ath_pci_detach),
241 DEVMETHOD(device_shutdown, ath_pci_shutdown),
242 DEVMETHOD(device_suspend, ath_pci_suspend),
243 DEVMETHOD(device_resume, ath_pci_resume),
244
245 { 0,0 }
246};
247static driver_t ath_pci_driver = {
248 "ath",
249 ath_pci_methods,
250 sizeof (struct ath_pci_softc)
251};
252static devclass_t ath_devclass;
| 32
33/*
34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/module.h>
40#include <sys/kernel.h>
41#include <sys/lock.h>
42#include <sys/mutex.h>
43#include <sys/errno.h>
44
45#include <machine/bus.h>
46#include <machine/resource.h>
47#include <sys/bus.h>
48#include <sys/rman.h>
49
50#include <sys/socket.h>
51
52#include <net/if.h>
53#include <net/if_media.h>
54#include <net/if_arp.h>
55
56#include <net80211/ieee80211_var.h>
57
58#include <dev/ath/if_athvar.h>
59
60#include <dev/pci/pcivar.h>
61#include <dev/pci/pcireg.h>
62
63/*
64 * PCI glue.
65 */
66
67struct ath_pci_softc {
68 struct ath_softc sc_sc;
69 struct resource *sc_sr; /* memory resource */
70 struct resource *sc_irq; /* irq resource */
71 void *sc_ih; /* interrupt handler */
72};
73
74#define BS_BAR 0x10
75#define PCIR_RETRY_TIMEOUT 0x41
76
77static int
78ath_pci_probe(device_t dev)
79{
80 const char* devname;
81
82 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
83 if (devname != NULL) {
84 device_set_desc(dev, devname);
85 return BUS_PROBE_DEFAULT;
86 }
87 return ENXIO;
88}
89
90static int
91ath_pci_attach(device_t dev)
92{
93 struct ath_pci_softc *psc = device_get_softc(dev);
94 struct ath_softc *sc = &psc->sc_sc;
95 int error = ENXIO;
96 int rid;
97
98 sc->sc_dev = dev;
99
100 /*
101 * Enable bus mastering.
102 */
103 pci_enable_busmaster(dev);
104
105 /*
106 * Disable retry timeout to keep PCI Tx retries from
107 * interfering with C3 CPU state.
108 */
109 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1);
110
111 /*
112 * Setup memory-mapping of PCI registers.
113 */
114 rid = BS_BAR;
115 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
116 RF_ACTIVE);
117 if (psc->sc_sr == NULL) {
118 device_printf(dev, "cannot map register space\n");
119 goto bad;
120 }
121 /* XXX uintptr_t is a bandaid for ia64; to be fixed */
122 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr);
123 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr);
124 /*
125 * Mark device invalid so any interrupts (shared or otherwise)
126 * that arrive before the HAL is setup are discarded.
127 */
128 sc->sc_invalid = 1;
129
130 /*
131 * Arrange interrupt line.
132 */
133 rid = 0;
134 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
135 RF_SHAREABLE|RF_ACTIVE);
136 if (psc->sc_irq == NULL) {
137 device_printf(dev, "could not map interrupt\n");
138 goto bad1;
139 }
140 if (bus_setup_intr(dev, psc->sc_irq,
141 INTR_TYPE_NET | INTR_MPSAFE,
142 NULL, ath_intr, sc, &psc->sc_ih)) {
143 device_printf(dev, "could not establish interrupt\n");
144 goto bad2;
145 }
146
147 /*
148 * Setup DMA descriptor area.
149 */
150 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
151 1, 0, /* alignment, bounds */
152 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
153 BUS_SPACE_MAXADDR, /* highaddr */
154 NULL, NULL, /* filter, filterarg */
155 0x3ffff, /* maxsize XXX */
156 ATH_MAX_SCATTER, /* nsegments */
157 0x3ffff, /* maxsegsize XXX */
158 BUS_DMA_ALLOCNOW, /* flags */
159 NULL, /* lockfunc */
160 NULL, /* lockarg */
161 &sc->sc_dmat)) {
162 device_printf(dev, "cannot allocate DMA tag\n");
163 goto bad3;
164 }
165
166 ATH_LOCK_INIT(sc);
167
168 error = ath_attach(pci_get_device(dev), sc);
169 if (error == 0) /* success */
170 return 0;
171
172 ATH_LOCK_DESTROY(sc);
173 bus_dma_tag_destroy(sc->sc_dmat);
174bad3:
175 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
176bad2:
177 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
178bad1:
179 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
180bad:
181 return (error);
182}
183
184static int
185ath_pci_detach(device_t dev)
186{
187 struct ath_pci_softc *psc = device_get_softc(dev);
188 struct ath_softc *sc = &psc->sc_sc;
189
190 /* check if device was removed */
191 sc->sc_invalid = !bus_child_present(dev);
192
193 ath_detach(sc);
194
195 bus_generic_detach(dev);
196 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
197 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
198
199 bus_dma_tag_destroy(sc->sc_dmat);
200 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
201
202 ATH_LOCK_DESTROY(sc);
203
204 return (0);
205}
206
207static int
208ath_pci_shutdown(device_t dev)
209{
210 struct ath_pci_softc *psc = device_get_softc(dev);
211
212 ath_shutdown(&psc->sc_sc);
213 return (0);
214}
215
216static int
217ath_pci_suspend(device_t dev)
218{
219 struct ath_pci_softc *psc = device_get_softc(dev);
220
221 ath_suspend(&psc->sc_sc);
222
223 return (0);
224}
225
226static int
227ath_pci_resume(device_t dev)
228{
229 struct ath_pci_softc *psc = device_get_softc(dev);
230
231 ath_resume(&psc->sc_sc);
232
233 return (0);
234}
235
236static device_method_t ath_pci_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, ath_pci_probe),
239 DEVMETHOD(device_attach, ath_pci_attach),
240 DEVMETHOD(device_detach, ath_pci_detach),
241 DEVMETHOD(device_shutdown, ath_pci_shutdown),
242 DEVMETHOD(device_suspend, ath_pci_suspend),
243 DEVMETHOD(device_resume, ath_pci_resume),
244
245 { 0,0 }
246};
247static driver_t ath_pci_driver = {
248 "ath",
249 ath_pci_methods,
250 sizeof (struct ath_pci_softc)
251};
252static devclass_t ath_devclass;
|