39
40/*
41 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
42 */
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/module.h>
47#include <sys/kernel.h>
48#include <sys/lock.h>
49#include <sys/mutex.h>
50#include <sys/errno.h>
51
52#include <machine/bus.h>
53#include <machine/resource.h>
54#include <sys/bus.h>
55#include <sys/rman.h>
56
57#include <sys/socket.h>
58
59#include <net/if.h>
60#include <net/if_media.h>
61#include <net/if_arp.h>
62
63#include <net80211/ieee80211_var.h>
64
65#include <dev/ath/if_athvar.h>
66#include <contrib/dev/ath/ah.h>
67
68#include <dev/pci/pcivar.h>
69#include <dev/pci/pcireg.h>
70
71/*
72 * PCI glue.
73 */
74
75struct ath_pci_softc {
76 struct ath_softc sc_sc;
77 struct resource *sc_sr; /* memory resource */
78 struct resource *sc_irq; /* irq resource */
79 void *sc_ih; /* interrupt handler */
80 u_int8_t sc_saved_intline;
81 u_int8_t sc_saved_cachelinesz;
82 u_int8_t sc_saved_lattimer;
83};
84
85#define BS_BAR 0x10
86
87static int
88ath_pci_probe(device_t dev)
89{
90 const char* devname;
91
92 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
93 if (devname != NULL) {
94 device_set_desc(dev, devname);
95 return 0;
96 }
97 return ENXIO;
98}
99
100static int
101ath_pci_attach(device_t dev)
102{
103 struct ath_pci_softc *psc = device_get_softc(dev);
104 struct ath_softc *sc = &psc->sc_sc;
105 u_int32_t cmd;
106 int error = ENXIO;
107 int rid;
108
109 bzero(psc, sizeof (*psc));
110 sc->sc_dev = dev;
111
112 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
113 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
114 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
115 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
116
117 if ((cmd & PCIM_CMD_MEMEN) == 0) {
118 device_printf(dev, "failed to enable memory mapping\n");
119 goto bad;
120 }
121
122 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
123 device_printf(dev, "failed to enable bus mastering\n");
124 goto bad;
125 }
126
127 /*
128 * Setup memory-mapping of PCI registers.
129 */
130 rid = BS_BAR;
131 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
132 RF_ACTIVE);
133 if (psc->sc_sr == NULL) {
134 device_printf(dev, "cannot map register space\n");
135 goto bad;
136 }
137 sc->sc_st = rman_get_bustag(psc->sc_sr);
138 sc->sc_sh = rman_get_bushandle(psc->sc_sr);
139 /*
140 * Mark device invalid so any interrupts (shared or otherwise)
141 * that arrive before the HAL is setup are discarded.
142 */
143 sc->sc_invalid = 1;
144
145 /*
146 * Arrange interrupt line.
147 */
148 rid = 0;
149 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
150 RF_SHAREABLE|RF_ACTIVE);
151 if (psc->sc_irq == NULL) {
152 device_printf(dev, "could not map interrupt\n");
153 goto bad1;
154 }
155 if (bus_setup_intr(dev, psc->sc_irq,
156 INTR_TYPE_NET | INTR_MPSAFE,
157 ath_intr, sc, &psc->sc_ih)) {
158 device_printf(dev, "could not establish interrupt\n");
159 goto bad2;
160 }
161
162 /*
163 * Setup DMA descriptor area.
164 */
165 if (bus_dma_tag_create(NULL, /* parent */
166 1, 0, /* alignment, bounds */
167 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
168 BUS_SPACE_MAXADDR, /* highaddr */
169 NULL, NULL, /* filter, filterarg */
170 0x3ffff, /* maxsize XXX */
171 ATH_MAX_SCATTER, /* nsegments */
172 BUS_SPACE_MAXADDR, /* maxsegsize */
173 BUS_DMA_ALLOCNOW, /* flags */
174 NULL, /* lockfunc */
175 NULL, /* lockarg */
176 &sc->sc_dmat)) {
177 device_printf(dev, "cannot allocate DMA tag\n");
178 goto bad3;
179 }
180
181 ATH_LOCK_INIT(sc);
182
183 error = ath_attach(pci_get_device(dev), sc);
184 if (error == 0)
185 return error;
186
187 ATH_LOCK_DESTROY(sc);
188 bus_dma_tag_destroy(sc->sc_dmat);
189bad3:
190 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
191bad2:
192 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
193bad1:
194 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
195bad:
196 return (error);
197}
198
199static int
200ath_pci_detach(device_t dev)
201{
202 struct ath_pci_softc *psc = device_get_softc(dev);
203 struct ath_softc *sc = &psc->sc_sc;
204
205 /* check if device was removed */
206 sc->sc_invalid = !bus_child_present(dev);
207
208 ath_detach(sc);
209
210 bus_generic_detach(dev);
211 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
212 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
213
214 bus_dma_tag_destroy(sc->sc_dmat);
215 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
216
217 ATH_LOCK_DESTROY(sc);
218
219 return (0);
220}
221
222static int
223ath_pci_shutdown(device_t dev)
224{
225 struct ath_pci_softc *psc = device_get_softc(dev);
226
227 ath_shutdown(&psc->sc_sc);
228 return (0);
229}
230
231static int
232ath_pci_suspend(device_t dev)
233{
234 struct ath_pci_softc *psc = device_get_softc(dev);
235
236 ath_suspend(&psc->sc_sc);
237
238 psc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
239 psc->sc_saved_cachelinesz= pci_read_config(dev, PCIR_CACHELNSZ, 1);
240 psc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
241
242 return (0);
243}
244
245static int
246ath_pci_resume(device_t dev)
247{
248 struct ath_pci_softc *psc = device_get_softc(dev);
249 u_int16_t cmd;
250
251 pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1);
252 pci_write_config(dev, PCIR_CACHELNSZ, psc->sc_saved_cachelinesz, 1);
253 pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1);
254
255 /* re-enable mem-map and busmastering */
256 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
257 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
258 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
259
260 ath_resume(&psc->sc_sc);
261
262 return (0);
263}
264
265static device_method_t ath_pci_methods[] = {
266 /* Device interface */
267 DEVMETHOD(device_probe, ath_pci_probe),
268 DEVMETHOD(device_attach, ath_pci_attach),
269 DEVMETHOD(device_detach, ath_pci_detach),
270 DEVMETHOD(device_shutdown, ath_pci_shutdown),
271 DEVMETHOD(device_suspend, ath_pci_suspend),
272 DEVMETHOD(device_resume, ath_pci_resume),
273
274 { 0,0 }
275};
276static driver_t ath_pci_driver = {
277 "ath",
278 ath_pci_methods,
279 sizeof (struct ath_pci_softc)
280};
281static devclass_t ath_devclass;
282DRIVER_MODULE(if_ath, pci, ath_pci_driver, ath_devclass, 0, 0);
283DRIVER_MODULE(if_ath, cardbus, ath_pci_driver, ath_devclass, 0, 0);
284MODULE_VERSION(if_ath, 1);
285MODULE_DEPEND(if_ath, ath_hal, 1, 1, 1); /* Atheros HAL */
286MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
287MODULE_DEPEND(if_ath, ath_rate, 1, 1, 1); /* rate control algorithm */
| 39
40/*
41 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
42 */
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/module.h>
47#include <sys/kernel.h>
48#include <sys/lock.h>
49#include <sys/mutex.h>
50#include <sys/errno.h>
51
52#include <machine/bus.h>
53#include <machine/resource.h>
54#include <sys/bus.h>
55#include <sys/rman.h>
56
57#include <sys/socket.h>
58
59#include <net/if.h>
60#include <net/if_media.h>
61#include <net/if_arp.h>
62
63#include <net80211/ieee80211_var.h>
64
65#include <dev/ath/if_athvar.h>
66#include <contrib/dev/ath/ah.h>
67
68#include <dev/pci/pcivar.h>
69#include <dev/pci/pcireg.h>
70
71/*
72 * PCI glue.
73 */
74
75struct ath_pci_softc {
76 struct ath_softc sc_sc;
77 struct resource *sc_sr; /* memory resource */
78 struct resource *sc_irq; /* irq resource */
79 void *sc_ih; /* interrupt handler */
80 u_int8_t sc_saved_intline;
81 u_int8_t sc_saved_cachelinesz;
82 u_int8_t sc_saved_lattimer;
83};
84
85#define BS_BAR 0x10
86
87static int
88ath_pci_probe(device_t dev)
89{
90 const char* devname;
91
92 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
93 if (devname != NULL) {
94 device_set_desc(dev, devname);
95 return 0;
96 }
97 return ENXIO;
98}
99
100static int
101ath_pci_attach(device_t dev)
102{
103 struct ath_pci_softc *psc = device_get_softc(dev);
104 struct ath_softc *sc = &psc->sc_sc;
105 u_int32_t cmd;
106 int error = ENXIO;
107 int rid;
108
109 bzero(psc, sizeof (*psc));
110 sc->sc_dev = dev;
111
112 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
113 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
114 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
115 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
116
117 if ((cmd & PCIM_CMD_MEMEN) == 0) {
118 device_printf(dev, "failed to enable memory mapping\n");
119 goto bad;
120 }
121
122 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
123 device_printf(dev, "failed to enable bus mastering\n");
124 goto bad;
125 }
126
127 /*
128 * Setup memory-mapping of PCI registers.
129 */
130 rid = BS_BAR;
131 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
132 RF_ACTIVE);
133 if (psc->sc_sr == NULL) {
134 device_printf(dev, "cannot map register space\n");
135 goto bad;
136 }
137 sc->sc_st = rman_get_bustag(psc->sc_sr);
138 sc->sc_sh = rman_get_bushandle(psc->sc_sr);
139 /*
140 * Mark device invalid so any interrupts (shared or otherwise)
141 * that arrive before the HAL is setup are discarded.
142 */
143 sc->sc_invalid = 1;
144
145 /*
146 * Arrange interrupt line.
147 */
148 rid = 0;
149 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
150 RF_SHAREABLE|RF_ACTIVE);
151 if (psc->sc_irq == NULL) {
152 device_printf(dev, "could not map interrupt\n");
153 goto bad1;
154 }
155 if (bus_setup_intr(dev, psc->sc_irq,
156 INTR_TYPE_NET | INTR_MPSAFE,
157 ath_intr, sc, &psc->sc_ih)) {
158 device_printf(dev, "could not establish interrupt\n");
159 goto bad2;
160 }
161
162 /*
163 * Setup DMA descriptor area.
164 */
165 if (bus_dma_tag_create(NULL, /* parent */
166 1, 0, /* alignment, bounds */
167 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
168 BUS_SPACE_MAXADDR, /* highaddr */
169 NULL, NULL, /* filter, filterarg */
170 0x3ffff, /* maxsize XXX */
171 ATH_MAX_SCATTER, /* nsegments */
172 BUS_SPACE_MAXADDR, /* maxsegsize */
173 BUS_DMA_ALLOCNOW, /* flags */
174 NULL, /* lockfunc */
175 NULL, /* lockarg */
176 &sc->sc_dmat)) {
177 device_printf(dev, "cannot allocate DMA tag\n");
178 goto bad3;
179 }
180
181 ATH_LOCK_INIT(sc);
182
183 error = ath_attach(pci_get_device(dev), sc);
184 if (error == 0)
185 return error;
186
187 ATH_LOCK_DESTROY(sc);
188 bus_dma_tag_destroy(sc->sc_dmat);
189bad3:
190 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
191bad2:
192 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
193bad1:
194 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
195bad:
196 return (error);
197}
198
199static int
200ath_pci_detach(device_t dev)
201{
202 struct ath_pci_softc *psc = device_get_softc(dev);
203 struct ath_softc *sc = &psc->sc_sc;
204
205 /* check if device was removed */
206 sc->sc_invalid = !bus_child_present(dev);
207
208 ath_detach(sc);
209
210 bus_generic_detach(dev);
211 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
212 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
213
214 bus_dma_tag_destroy(sc->sc_dmat);
215 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
216
217 ATH_LOCK_DESTROY(sc);
218
219 return (0);
220}
221
222static int
223ath_pci_shutdown(device_t dev)
224{
225 struct ath_pci_softc *psc = device_get_softc(dev);
226
227 ath_shutdown(&psc->sc_sc);
228 return (0);
229}
230
231static int
232ath_pci_suspend(device_t dev)
233{
234 struct ath_pci_softc *psc = device_get_softc(dev);
235
236 ath_suspend(&psc->sc_sc);
237
238 psc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
239 psc->sc_saved_cachelinesz= pci_read_config(dev, PCIR_CACHELNSZ, 1);
240 psc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
241
242 return (0);
243}
244
245static int
246ath_pci_resume(device_t dev)
247{
248 struct ath_pci_softc *psc = device_get_softc(dev);
249 u_int16_t cmd;
250
251 pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1);
252 pci_write_config(dev, PCIR_CACHELNSZ, psc->sc_saved_cachelinesz, 1);
253 pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1);
254
255 /* re-enable mem-map and busmastering */
256 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
257 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
258 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
259
260 ath_resume(&psc->sc_sc);
261
262 return (0);
263}
264
265static device_method_t ath_pci_methods[] = {
266 /* Device interface */
267 DEVMETHOD(device_probe, ath_pci_probe),
268 DEVMETHOD(device_attach, ath_pci_attach),
269 DEVMETHOD(device_detach, ath_pci_detach),
270 DEVMETHOD(device_shutdown, ath_pci_shutdown),
271 DEVMETHOD(device_suspend, ath_pci_suspend),
272 DEVMETHOD(device_resume, ath_pci_resume),
273
274 { 0,0 }
275};
276static driver_t ath_pci_driver = {
277 "ath",
278 ath_pci_methods,
279 sizeof (struct ath_pci_softc)
280};
281static devclass_t ath_devclass;
282DRIVER_MODULE(if_ath, pci, ath_pci_driver, ath_devclass, 0, 0);
283DRIVER_MODULE(if_ath, cardbus, ath_pci_driver, ath_devclass, 0, 0);
284MODULE_VERSION(if_ath, 1);
285MODULE_DEPEND(if_ath, ath_hal, 1, 1, 1); /* Atheros HAL */
286MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
287MODULE_DEPEND(if_ath, ath_rate, 1, 1, 1); /* rate control algorithm */
|