1/*-
2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
|
39
40/*
41 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
42 */
43
44#include "opt_inet.h"
45
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/mbuf.h>
49#include <sys/malloc.h>
50#include <sys/module.h>
51#include <sys/kernel.h>
52#include <sys/lock.h>
53#include <sys/mutex.h>
54#include <sys/socket.h>
55#include <sys/sockio.h>
56#include <sys/errno.h>
57
58#include <machine/bus.h>
59#include <machine/resource.h>
60#include <sys/bus.h>
61#include <sys/rman.h>
62
63#include <net/if.h>
64#include <net/if_dl.h>
65#include <net/if_media.h>
66#include <net/ethernet.h>
67#include <net/if_llc.h>
68#include <net/if_arp.h>
69
70#include <net80211/ieee80211.h>
71#include <net80211/ieee80211_crypto.h>
72#include <net80211/ieee80211_node.h>
73#include <net80211/ieee80211_proto.h>
74#include <net80211/ieee80211_var.h>
75
76#ifdef INET
77#include <netinet/in.h>
78#include <netinet/if_ether.h>
79#endif
80
81#include <dev/ath/if_athvar.h>
82#include <contrib/dev/ath/ah.h>
83
84#include <dev/pci/pcivar.h>
85#include <dev/pci/pcireg.h>
86
87/*
88 * PCI glue.
89 */
90
91struct ath_pci_softc {
92 struct ath_softc sc_sc;
93 struct resource *sc_sr; /* memory resource */
94 struct resource *sc_irq; /* irq resource */
95 void *sc_ih; /* intererupt handler */
96 u_int8_t sc_saved_intline;
97 u_int8_t sc_saved_cachelinesz;
98 u_int8_t sc_saved_lattimer;
99};
100
101#define BS_BAR 0x10
102
103static int
104ath_pci_probe(device_t dev)
105{
106 const char* devname;
107
108 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
109 if (devname) {
110 device_set_desc(dev, devname);
111 return 0;
112 }
113 return ENXIO;
114}
115
116static int
117ath_pci_attach(device_t dev)
118{
119 struct ath_pci_softc *psc = device_get_softc(dev);
120 struct ath_softc *sc = &psc->sc_sc;
121 u_int32_t cmd;
122 int error = ENXIO;
123 int rid;
124
125 bzero(psc, sizeof (*psc));
126 sc->sc_dev = dev;
127
128 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
129 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
130 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
131 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
132
133 if ((cmd & PCIM_CMD_MEMEN) == 0) {
134 device_printf(dev, "failed to enable memory mapping\n");
135 goto bad;
136 }
137
138 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
139 device_printf(dev, "failed to enable bus mastering\n");
140 goto bad;
141 }
142
143 /*
144 * Setup memory-mapping of PCI registers.
145 */
146 rid = BS_BAR;
147 psc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
148 0, ~0, 1, RF_ACTIVE);
149 if (psc->sc_sr == NULL) {
150 device_printf(dev, "cannot map register space\n");
151 goto bad;
152 }
153 sc->sc_st = rman_get_bustag(psc->sc_sr);
154 sc->sc_sh = rman_get_bushandle(psc->sc_sr);
155 /*
156 * Mark device invalid so any interrupts (shared or otherwise)
157 * that arrive before the HAL is setup are discarded.
158 */
159 sc->sc_invalid = 1;
160
161 /*
162 * Arrange interrupt line.
163 */
164 rid = 0;
165 psc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
166 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
167 if (psc->sc_irq == NULL) {
168 device_printf(dev, "could not map interrupt\n");
169 goto bad1;
170 }
171 if (bus_setup_intr(dev, psc->sc_irq,
172 INTR_TYPE_NET | INTR_MPSAFE,
173 ath_intr, sc, &psc->sc_ih)) {
174 device_printf(dev, "could not establish interrupt\n");
175 goto bad2;
176 }
177
178 /*
179 * Setup DMA descriptor area.
180 */
181 if (bus_dma_tag_create(NULL, /* parent */
182 1, 0, /* alignment, bounds */
183 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
184 BUS_SPACE_MAXADDR, /* highaddr */
185 NULL, NULL, /* filter, filterarg */
186 0x3ffff, /* maxsize XXX */
187 ATH_MAX_SCATTER, /* nsegments */
188 0xffff, /* maxsegsize XXX */
189 BUS_DMA_ALLOCNOW, /* flags */
190 NULL, /* lockfunc */
191 NULL, /* lockarg */
192 &sc->sc_dmat)) {
193 device_printf(dev, "cannot allocate DMA tag\n");
194 goto bad3;
195 }
196
197 ATH_LOCK_INIT(sc);
198
199 error = ath_attach(pci_get_device(dev), sc);
200 if (error == 0)
201 return error;
202
203 ATH_LOCK_DESTROY(sc);
204 bus_dma_tag_destroy(sc->sc_dmat);
205bad3:
206 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
207bad2:
208 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
209bad1:
210 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
211bad:
212 return (error);
213}
214
215static int
216ath_pci_detach(device_t dev)
217{
218 struct ath_pci_softc *psc = device_get_softc(dev);
219 struct ath_softc *sc = &psc->sc_sc;
220
221 /* check if device was removed */
222 sc->sc_invalid = !bus_child_present(dev);
223
224 ath_detach(sc);
225
226 bus_generic_detach(dev);
227 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
228 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
229
230 bus_dma_tag_destroy(sc->sc_dmat);
231 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
232
233 ATH_LOCK_DESTROY(sc);
234
235 return (0);
236}
237
238static int
239ath_pci_shutdown(device_t dev)
240{
241 struct ath_pci_softc *psc = device_get_softc(dev);
242
243 ath_shutdown(&psc->sc_sc);
244 return (0);
245}
246
247static int
248ath_pci_suspend(device_t dev)
249{
250 struct ath_pci_softc *psc = device_get_softc(dev);
251
252 ath_suspend(&psc->sc_sc);
253
254 psc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
255 psc->sc_saved_cachelinesz= pci_read_config(dev, PCIR_CACHELNSZ, 1);
256 psc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
257
258 return (0);
259}
260
261static int
262ath_pci_resume(device_t dev)
263{
264 struct ath_pci_softc *psc = device_get_softc(dev);
265 u_int16_t cmd;
266
267 pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1);
268 pci_write_config(dev, PCIR_CACHELNSZ, psc->sc_saved_cachelinesz, 1);
269 pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1);
270
271 /* re-enable mem-map and busmastering */
272 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
273 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
274 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
275
276 ath_resume(&psc->sc_sc);
277
278 return (0);
279}
280
281static device_method_t ath_pci_methods[] = {
282 /* Device interface */
283 DEVMETHOD(device_probe, ath_pci_probe),
284 DEVMETHOD(device_attach, ath_pci_attach),
285 DEVMETHOD(device_detach, ath_pci_detach),
286 DEVMETHOD(device_shutdown, ath_pci_shutdown),
287 DEVMETHOD(device_suspend, ath_pci_suspend),
288 DEVMETHOD(device_resume, ath_pci_resume),
289
290 { 0,0 }
291};
292static driver_t ath_pci_driver = {
293 "ath",
294 ath_pci_methods,
295 sizeof (struct ath_pci_softc)
296};
297static devclass_t ath_devclass;
298DRIVER_MODULE(if_ath, pci, ath_pci_driver, ath_devclass, 0, 0);
| 39
40/*
41 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
42 */
43
44#include "opt_inet.h"
45
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/mbuf.h>
49#include <sys/malloc.h>
50#include <sys/module.h>
51#include <sys/kernel.h>
52#include <sys/lock.h>
53#include <sys/mutex.h>
54#include <sys/socket.h>
55#include <sys/sockio.h>
56#include <sys/errno.h>
57
58#include <machine/bus.h>
59#include <machine/resource.h>
60#include <sys/bus.h>
61#include <sys/rman.h>
62
63#include <net/if.h>
64#include <net/if_dl.h>
65#include <net/if_media.h>
66#include <net/ethernet.h>
67#include <net/if_llc.h>
68#include <net/if_arp.h>
69
70#include <net80211/ieee80211.h>
71#include <net80211/ieee80211_crypto.h>
72#include <net80211/ieee80211_node.h>
73#include <net80211/ieee80211_proto.h>
74#include <net80211/ieee80211_var.h>
75
76#ifdef INET
77#include <netinet/in.h>
78#include <netinet/if_ether.h>
79#endif
80
81#include <dev/ath/if_athvar.h>
82#include <contrib/dev/ath/ah.h>
83
84#include <dev/pci/pcivar.h>
85#include <dev/pci/pcireg.h>
86
87/*
88 * PCI glue.
89 */
90
91struct ath_pci_softc {
92 struct ath_softc sc_sc;
93 struct resource *sc_sr; /* memory resource */
94 struct resource *sc_irq; /* irq resource */
95 void *sc_ih; /* intererupt handler */
96 u_int8_t sc_saved_intline;
97 u_int8_t sc_saved_cachelinesz;
98 u_int8_t sc_saved_lattimer;
99};
100
101#define BS_BAR 0x10
102
103static int
104ath_pci_probe(device_t dev)
105{
106 const char* devname;
107
108 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
109 if (devname) {
110 device_set_desc(dev, devname);
111 return 0;
112 }
113 return ENXIO;
114}
115
116static int
117ath_pci_attach(device_t dev)
118{
119 struct ath_pci_softc *psc = device_get_softc(dev);
120 struct ath_softc *sc = &psc->sc_sc;
121 u_int32_t cmd;
122 int error = ENXIO;
123 int rid;
124
125 bzero(psc, sizeof (*psc));
126 sc->sc_dev = dev;
127
128 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
129 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
130 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
131 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
132
133 if ((cmd & PCIM_CMD_MEMEN) == 0) {
134 device_printf(dev, "failed to enable memory mapping\n");
135 goto bad;
136 }
137
138 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
139 device_printf(dev, "failed to enable bus mastering\n");
140 goto bad;
141 }
142
143 /*
144 * Setup memory-mapping of PCI registers.
145 */
146 rid = BS_BAR;
147 psc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
148 0, ~0, 1, RF_ACTIVE);
149 if (psc->sc_sr == NULL) {
150 device_printf(dev, "cannot map register space\n");
151 goto bad;
152 }
153 sc->sc_st = rman_get_bustag(psc->sc_sr);
154 sc->sc_sh = rman_get_bushandle(psc->sc_sr);
155 /*
156 * Mark device invalid so any interrupts (shared or otherwise)
157 * that arrive before the HAL is setup are discarded.
158 */
159 sc->sc_invalid = 1;
160
161 /*
162 * Arrange interrupt line.
163 */
164 rid = 0;
165 psc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
166 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
167 if (psc->sc_irq == NULL) {
168 device_printf(dev, "could not map interrupt\n");
169 goto bad1;
170 }
171 if (bus_setup_intr(dev, psc->sc_irq,
172 INTR_TYPE_NET | INTR_MPSAFE,
173 ath_intr, sc, &psc->sc_ih)) {
174 device_printf(dev, "could not establish interrupt\n");
175 goto bad2;
176 }
177
178 /*
179 * Setup DMA descriptor area.
180 */
181 if (bus_dma_tag_create(NULL, /* parent */
182 1, 0, /* alignment, bounds */
183 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
184 BUS_SPACE_MAXADDR, /* highaddr */
185 NULL, NULL, /* filter, filterarg */
186 0x3ffff, /* maxsize XXX */
187 ATH_MAX_SCATTER, /* nsegments */
188 0xffff, /* maxsegsize XXX */
189 BUS_DMA_ALLOCNOW, /* flags */
190 NULL, /* lockfunc */
191 NULL, /* lockarg */
192 &sc->sc_dmat)) {
193 device_printf(dev, "cannot allocate DMA tag\n");
194 goto bad3;
195 }
196
197 ATH_LOCK_INIT(sc);
198
199 error = ath_attach(pci_get_device(dev), sc);
200 if (error == 0)
201 return error;
202
203 ATH_LOCK_DESTROY(sc);
204 bus_dma_tag_destroy(sc->sc_dmat);
205bad3:
206 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
207bad2:
208 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
209bad1:
210 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
211bad:
212 return (error);
213}
214
215static int
216ath_pci_detach(device_t dev)
217{
218 struct ath_pci_softc *psc = device_get_softc(dev);
219 struct ath_softc *sc = &psc->sc_sc;
220
221 /* check if device was removed */
222 sc->sc_invalid = !bus_child_present(dev);
223
224 ath_detach(sc);
225
226 bus_generic_detach(dev);
227 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
228 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
229
230 bus_dma_tag_destroy(sc->sc_dmat);
231 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
232
233 ATH_LOCK_DESTROY(sc);
234
235 return (0);
236}
237
238static int
239ath_pci_shutdown(device_t dev)
240{
241 struct ath_pci_softc *psc = device_get_softc(dev);
242
243 ath_shutdown(&psc->sc_sc);
244 return (0);
245}
246
247static int
248ath_pci_suspend(device_t dev)
249{
250 struct ath_pci_softc *psc = device_get_softc(dev);
251
252 ath_suspend(&psc->sc_sc);
253
254 psc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
255 psc->sc_saved_cachelinesz= pci_read_config(dev, PCIR_CACHELNSZ, 1);
256 psc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
257
258 return (0);
259}
260
261static int
262ath_pci_resume(device_t dev)
263{
264 struct ath_pci_softc *psc = device_get_softc(dev);
265 u_int16_t cmd;
266
267 pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1);
268 pci_write_config(dev, PCIR_CACHELNSZ, psc->sc_saved_cachelinesz, 1);
269 pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1);
270
271 /* re-enable mem-map and busmastering */
272 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
273 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
274 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
275
276 ath_resume(&psc->sc_sc);
277
278 return (0);
279}
280
281static device_method_t ath_pci_methods[] = {
282 /* Device interface */
283 DEVMETHOD(device_probe, ath_pci_probe),
284 DEVMETHOD(device_attach, ath_pci_attach),
285 DEVMETHOD(device_detach, ath_pci_detach),
286 DEVMETHOD(device_shutdown, ath_pci_shutdown),
287 DEVMETHOD(device_suspend, ath_pci_suspend),
288 DEVMETHOD(device_resume, ath_pci_resume),
289
290 { 0,0 }
291};
292static driver_t ath_pci_driver = {
293 "ath",
294 ath_pci_methods,
295 sizeof (struct ath_pci_softc)
296};
297static devclass_t ath_devclass;
298DRIVER_MODULE(if_ath, pci, ath_pci_driver, ath_devclass, 0, 0);
|