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if_ath.c (122866) if_ath.c (123044)
1/*-
2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 122866 2003-11-17 19:15:09Z sam $");
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 123044 2003-11-29 01:23:59Z sam $");
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46

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900 * The upper layer has already installed/removed
901 * the multicast address(es), just recalculate the
902 * multicast filter for the card.
903 */
904 if (ifp->if_flags & IFF_RUNNING)
905 ath_mode_init(sc);
906 break;
907 case SIOCGATHSTATS:
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46

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900 * The upper layer has already installed/removed
901 * the multicast address(es), just recalculate the
902 * multicast filter for the card.
903 */
904 if (ifp->if_flags & IFF_RUNNING)
905 ath_mode_init(sc);
906 break;
907 case SIOCGATHSTATS:
908 copyout(&sc->sc_stats, ifr->ifr_data, sizeof (sc->sc_stats));
908 error = copyout(&sc->sc_stats,
909 ifr->ifr_data, sizeof (sc->sc_stats));
909 break;
910 break;
911 case SIOCGATHDIAG: {
912 struct ath_diag *ad = (struct ath_diag *)data;
913 struct ath_hal *ah = sc->sc_ah;
914 void *data;
915 u_int size;
916
917 if (ath_hal_getdiagstate(ah, ad->ad_id, &data, &size)) {
918 if (size < ad->ad_size)
919 ad->ad_size = size;
920 if (data)
921 error = copyout(data, ad->ad_data, ad->ad_size);
922 } else
923 error = EINVAL;
924 break;
925 }
910 default:
911 error = ieee80211_ioctl(ifp, cmd, data);
912 if (error == ENETRESET) {
913 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
914 (IFF_RUNNING|IFF_UP))
915 ath_init(ifp); /* XXX lose error */
916 error = 0;
917 }

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1594 *sc->sc_rxlink = bf->bf_daddr;
1595 sc->sc_rxlink = &ds->ds_link;
1596 return 0;
1597}
1598
1599static void
1600ath_rx_proc(void *arg, int npending)
1601{
926 default:
927 error = ieee80211_ioctl(ifp, cmd, data);
928 if (error == ENETRESET) {
929 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
930 (IFF_RUNNING|IFF_UP))
931 ath_init(ifp); /* XXX lose error */
932 error = 0;
933 }

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1610 *sc->sc_rxlink = bf->bf_daddr;
1611 sc->sc_rxlink = &ds->ds_link;
1612 return 0;
1613}
1614
1615static void
1616ath_rx_proc(void *arg, int npending)
1617{
1618#define PA2DESC(_sc, _pa) \
1619 ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \
1620 ((_pa) - (_sc)->sc_desc_paddr)))
1602 struct ath_softc *sc = arg;
1603 struct ath_buf *bf;
1604 struct ieee80211com *ic = &sc->sc_ic;
1605 struct ifnet *ifp = &ic->ic_if;
1606 struct ath_hal *ah = sc->sc_ah;
1607 struct ath_desc *ds;
1608 struct mbuf *m;
1609 struct ieee80211_frame *wh, whbuf;

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1626 /* NB: never process the self-linked entry at the end */
1627 break;
1628 }
1629 m = bf->bf_m;
1630 if (m == NULL) { /* NB: shouldn't happen */
1631 if_printf(ifp, "ath_rx_proc: no mbuf!\n");
1632 continue;
1633 }
1621 struct ath_softc *sc = arg;
1622 struct ath_buf *bf;
1623 struct ieee80211com *ic = &sc->sc_ic;
1624 struct ifnet *ifp = &ic->ic_if;
1625 struct ath_hal *ah = sc->sc_ah;
1626 struct ath_desc *ds;
1627 struct mbuf *m;
1628 struct ieee80211_frame *wh, whbuf;

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1645 /* NB: never process the self-linked entry at the end */
1646 break;
1647 }
1648 m = bf->bf_m;
1649 if (m == NULL) { /* NB: shouldn't happen */
1650 if_printf(ifp, "ath_rx_proc: no mbuf!\n");
1651 continue;
1652 }
1634 status = ath_hal_rxprocdesc(ah, ds);
1653 /* XXX sync descriptor memory */
1654 /*
1655 * Must provide the virtual address of the current
1656 * descriptor, the physical address, and the virtual
1657 * address of the next descriptor in the h/w chain.
1658 * This allows the HAL to look ahead to see if the
1659 * hardware is done with a descriptor by checking the
1660 * done bit in the following descriptor and the address
1661 * of the current descriptor the DMA engine is working
1662 * on. All this is necessary because of our use of
1663 * a self-linked list to avoid rx overruns.
1664 */
1665 status = ath_hal_rxprocdesc(ah, ds,
1666 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
1635#ifdef AR_DEBUG
1636 if (ath_debug > 1)
1637 ath_printrxbuf(bf, status == HAL_OK);
1638#endif
1639 if (status == HAL_EINPROGRESS)
1640 break;
1641 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1642 if (ds->ds_rxstat.rs_status != 0) {

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1761 else
1762 ieee80211_free_node(ic, ni);
1763 rx_next:
1764 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1765 } while (ath_rxbuf_init(sc, bf) == 0);
1766
1767 ath_hal_rxmonitor(ah); /* rx signal state monitoring */
1768 ath_hal_rxena(ah); /* in case of RXEOL */
1667#ifdef AR_DEBUG
1668 if (ath_debug > 1)
1669 ath_printrxbuf(bf, status == HAL_OK);
1670#endif
1671 if (status == HAL_EINPROGRESS)
1672 break;
1673 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1674 if (ds->ds_rxstat.rs_status != 0) {

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1793 else
1794 ieee80211_free_node(ic, ni);
1795 rx_next:
1796 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1797 } while (ath_rxbuf_init(sc, bf) == 0);
1798
1799 ath_hal_rxmonitor(ah); /* rx signal state monitoring */
1800 ath_hal_rxena(ah); /* in case of RXEOL */
1801#undef PA2DESC
1769}
1770
1771/*
1772 * XXX Size of an ACK control frame in bytes.
1773 */
1774#define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4)
1775
1776static int

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2232}
2233
2234/*
2235 * Disable the receive h/w in preparation for a reset.
2236 */
2237static void
2238ath_stoprecv(struct ath_softc *sc)
2239{
1802}
1803
1804/*
1805 * XXX Size of an ACK control frame in bytes.
1806 */
1807#define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4)
1808
1809static int

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2265}
2266
2267/*
2268 * Disable the receive h/w in preparation for a reset.
2269 */
2270static void
2271ath_stoprecv(struct ath_softc *sc)
2272{
2273#define PA2DESC(_sc, _pa) \
2274 ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \
2275 ((_pa) - (_sc)->sc_desc_paddr)))
2240 struct ath_hal *ah = sc->sc_ah;
2241
2242 ath_hal_stoppcurecv(ah); /* disable PCU */
2243 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
2244 ath_hal_stopdmarecv(ah); /* disable DMA engine */
2245 DELAY(3000); /* long enough for 1 frame */
2246#ifdef AR_DEBUG
2247 if (ath_debug) {
2248 struct ath_buf *bf;
2249
2250 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n",
2251 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink));
2252 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
2276 struct ath_hal *ah = sc->sc_ah;
2277
2278 ath_hal_stoppcurecv(ah); /* disable PCU */
2279 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
2280 ath_hal_stopdmarecv(ah); /* disable DMA engine */
2281 DELAY(3000); /* long enough for 1 frame */
2282#ifdef AR_DEBUG
2283 if (ath_debug) {
2284 struct ath_buf *bf;
2285
2286 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n",
2287 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink));
2288 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
2253 if (ath_hal_rxprocdesc(ah, bf->bf_desc) == HAL_OK)
2289 struct ath_desc *ds = bf->bf_desc;
2290 if (ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
2291 PA2DESC(sc, ds->ds_link)) == HAL_OK)
2254 ath_printrxbuf(bf, 1);
2255 }
2256 }
2257#endif
2258 sc->sc_rxlink = NULL; /* just in case */
2292 ath_printrxbuf(bf, 1);
2293 }
2294 }
2295#endif
2296 sc->sc_rxlink = NULL; /* just in case */
2297#undef PA2DESC
2259}
2260
2261/*
2262 * Enable the receive h/w following a reset.
2263 */
2264static int
2265ath_startrecv(struct ath_softc *sc)
2266{

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2417static int
2418ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2419{
2420 struct ifnet *ifp = &ic->ic_if;
2421 struct ath_softc *sc = ifp->if_softc;
2422 struct ath_hal *ah = sc->sc_ah;
2423 struct ieee80211_node *ni;
2424 int i, error;
2298}
2299
2300/*
2301 * Enable the receive h/w following a reset.
2302 */
2303static int
2304ath_startrecv(struct ath_softc *sc)
2305{

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2456static int
2457ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2458{
2459 struct ifnet *ifp = &ic->ic_if;
2460 struct ath_softc *sc = ifp->if_softc;
2461 struct ath_hal *ah = sc->sc_ah;
2462 struct ieee80211_node *ni;
2463 int i, error;
2425 u_int8_t *bssid;
2464 const u_int8_t *bssid;
2426 u_int32_t rfilt;
2427 static const HAL_LED_STATE leds[] = {
2428 HAL_LED_INIT, /* IEEE80211_S_INIT */
2429 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
2430 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
2431 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
2432 HAL_LED_RUN, /* IEEE80211_S_RUN */
2433 };

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2775 struct ath_softc *sc;
2776
2777 ifp = ifunit("ath0"); /* XXX */
2778 if (!ifp)
2779 return EINVAL;
2780 sc = ifp->if_softc;
2781 if (strcmp(dmode, "hal") == 0)
2782 ath_hal_dumpstate(sc->sc_ah);
2465 u_int32_t rfilt;
2466 static const HAL_LED_STATE leds[] = {
2467 HAL_LED_INIT, /* IEEE80211_S_INIT */
2468 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
2469 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
2470 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
2471 HAL_LED_RUN, /* IEEE80211_S_RUN */
2472 };

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2814 struct ath_softc *sc;
2815
2816 ifp = ifunit("ath0"); /* XXX */
2817 if (!ifp)
2818 return EINVAL;
2819 sc = ifp->if_softc;
2820 if (strcmp(dmode, "hal") == 0)
2821 ath_hal_dumpstate(sc->sc_ah);
2783 else if (strcmp(dmode, "eeprom") == 0)
2784 ath_hal_dumpeeprom(sc->sc_ah);
2785 else if (strcmp(dmode, "rfgain") == 0)
2786 ath_hal_dumprfgain(sc->sc_ah);
2787 else if (strcmp(dmode, "ani") == 0)
2788 ath_hal_dumpani(sc->sc_ah);
2789 else
2790 return EINVAL;
2791 }
2792 return error;
2793}
2794SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW,
2795 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state");
2796

--- 32 unchanged lines hidden --- 		2822 else
2823 return EINVAL;
2824 }
2825 return error;
2826}
2827SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW,
2828 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state");
2829

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