1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37#include <sys/cdefs.h>
|
38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 155491 2006-02-09 21:48:51Z sam $");
| 38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 155492 2006-02-09 22:03:26Z sam $");
|
39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46
47#include "opt_inet.h"
48
49#include <sys/param.h>
50#include <sys/systm.h>
51#include <sys/sysctl.h>
52#include <sys/mbuf.h>
53#include <sys/malloc.h>
54#include <sys/lock.h>
55#include <sys/mutex.h>
56#include <sys/kernel.h>
57#include <sys/socket.h>
58#include <sys/sockio.h>
59#include <sys/errno.h>
60#include <sys/callout.h>
61#include <sys/bus.h>
62#include <sys/endian.h>
63#include <sys/kthread.h>
64#include <sys/taskqueue.h>
65
66#include <machine/bus.h>
67
68#include <net/if.h>
69#include <net/if_dl.h>
70#include <net/if_media.h>
71#include <net/if_types.h>
72#include <net/if_arp.h>
73#include <net/ethernet.h>
74#include <net/if_llc.h>
75
76#include <net80211/ieee80211_var.h>
77
78#include <net/bpf.h>
79
80#ifdef INET
81#include <netinet/in.h>
82#include <netinet/if_ether.h>
83#endif
84
85#define AR_DEBUG
86#include <dev/ath/if_athvar.h>
87#include <contrib/dev/ath/ah_desc.h>
88#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
89
90#ifdef ATH_TX99_DIAG
91#include <dev/ath/ath_tx99/ath_tx99.h>
92#endif
93
94/* unaligned little endian access */
95#define LE_READ_2(p) \
96 ((u_int16_t) \
97 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
98#define LE_READ_4(p) \
99 ((u_int32_t) \
100 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
101 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
102
103enum {
104 ATH_LED_TX,
105 ATH_LED_RX,
106 ATH_LED_POLL,
107};
108
109static void ath_init(void *);
110static void ath_stop_locked(struct ifnet *);
111static void ath_stop(struct ifnet *);
112static void ath_start(struct ifnet *);
113static int ath_reset(struct ifnet *);
114static int ath_media_change(struct ifnet *);
115static void ath_watchdog(struct ifnet *);
116static int ath_ioctl(struct ifnet *, u_long, caddr_t);
117static void ath_fatal_proc(void *, int);
118static void ath_rxorn_proc(void *, int);
119static void ath_bmiss_proc(void *, int);
120static int ath_key_alloc(struct ieee80211com *,
121 const struct ieee80211_key *,
122 ieee80211_keyix *, ieee80211_keyix *);
123static int ath_key_delete(struct ieee80211com *,
124 const struct ieee80211_key *);
125static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
126 const u_int8_t mac[IEEE80211_ADDR_LEN]);
127static void ath_key_update_begin(struct ieee80211com *);
128static void ath_key_update_end(struct ieee80211com *);
129static void ath_mode_init(struct ath_softc *);
130static void ath_setslottime(struct ath_softc *);
131static void ath_updateslot(struct ifnet *);
132static int ath_beaconq_setup(struct ath_hal *);
133static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
134static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
135static void ath_beacon_proc(void *, int);
136static void ath_bstuck_proc(void *, int);
137static void ath_beacon_free(struct ath_softc *);
138static void ath_beacon_config(struct ath_softc *);
139static void ath_descdma_cleanup(struct ath_softc *sc,
140 struct ath_descdma *, ath_bufhead *);
141static int ath_desc_alloc(struct ath_softc *);
142static void ath_desc_free(struct ath_softc *);
143static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
144static void ath_node_free(struct ieee80211_node *);
145static u_int8_t ath_node_getrssi(const struct ieee80211_node *);
146static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
147static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
148 struct ieee80211_node *ni,
149 int subtype, int rssi, u_int32_t rstamp);
150static void ath_setdefantenna(struct ath_softc *, u_int);
151static void ath_rx_proc(void *, int);
152static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
153static int ath_tx_setup(struct ath_softc *, int, int);
154static int ath_wme_update(struct ieee80211com *);
155static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
156static void ath_tx_cleanup(struct ath_softc *);
157static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
158 struct ath_buf *, struct mbuf *);
159static void ath_tx_proc_q0(void *, int);
160static void ath_tx_proc_q0123(void *, int);
161static void ath_tx_proc(void *, int);
162static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
163static void ath_draintxq(struct ath_softc *);
164static void ath_stoprecv(struct ath_softc *);
165static int ath_startrecv(struct ath_softc *);
166static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
167static void ath_next_scan(void *);
168static void ath_calibrate(void *);
169static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
170static void ath_setup_stationkey(struct ieee80211_node *);
171static void ath_newassoc(struct ieee80211_node *, int);
172static int ath_getchannels(struct ath_softc *, u_int cc,
173 HAL_BOOL outdoor, HAL_BOOL xchanmode);
174static void ath_led_event(struct ath_softc *, int);
175static void ath_update_txpow(struct ath_softc *);
176
177static int ath_rate_setup(struct ath_softc *, u_int mode);
178static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
179
180static void ath_sysctlattach(struct ath_softc *);
181static void ath_bpfattach(struct ath_softc *);
182static void ath_announce(struct ath_softc *);
183
184SYSCTL_DECL(_hw_ath);
185
186/* XXX validate sysctl values */
187static int ath_dwelltime = 200; /* 5 channels/second */
188SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
189 0, "channel dwell time (ms) for AP/station scanning");
190static int ath_calinterval = 30; /* calibrate every 30 secs */
191SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
192 0, "chip calibration interval (secs)");
193static int ath_outdoor = AH_TRUE; /* outdoor operation */
194SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
195 0, "outdoor operation");
196TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
197static int ath_xchanmode = AH_TRUE; /* extended channel use */
198SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
199 0, "extended channel mode");
200TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
201static int ath_countrycode = CTRY_DEFAULT; /* country code */
202SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
203 0, "country code");
204TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
205static int ath_regdomain = 0; /* regulatory domain */
206SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
207 0, "regulatory domain");
208
209static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
210SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf,
211 0, "rx buffers allocated");
212TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
213static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
214SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf,
215 0, "tx buffers allocated");
216TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
217
218#ifdef AR_DEBUG
219static int ath_debug = 0;
220SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
221 0, "control debugging printfs");
222TUNABLE_INT("hw.ath.debug", &ath_debug);
223enum {
224 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
225 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
226 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
227 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
228 ATH_DEBUG_RATE = 0x00000010, /* rate control */
229 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
230 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
231 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
232 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
233 ATH_DEBUG_INTR = 0x00001000, /* ISR */
234 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
235 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
236 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
237 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
238 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
239 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
240 ATH_DEBUG_NODE = 0x00080000, /* node management */
241 ATH_DEBUG_LED = 0x00100000, /* led management */
242 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
243 ATH_DEBUG_ANY = 0xffffffff
244};
245#define IFF_DUMPPKTS(sc, m) \
246 ((sc->sc_debug & (m)) || \
247 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
248#define DPRINTF(sc, m, fmt, ...) do { \
249 if (sc->sc_debug & (m)) \
250 printf(fmt, __VA_ARGS__); \
251} while (0)
252#define KEYPRINTF(sc, ix, hk, mac) do { \
253 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
254 ath_keyprint(__func__, ix, hk, mac); \
255} while (0)
256static void ath_printrxbuf(struct ath_buf *bf, int);
257static void ath_printtxbuf(struct ath_buf *bf, int);
258#else
259#define IFF_DUMPPKTS(sc, m) \
260 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
261#define DPRINTF(m, fmt, ...)
262#define KEYPRINTF(sc, k, ix, mac)
263#endif
264
265MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
266
267int
268ath_attach(u_int16_t devid, struct ath_softc *sc)
269{
270 struct ifnet *ifp;
271 struct ieee80211com *ic = &sc->sc_ic;
272 struct ath_hal *ah = NULL;
273 HAL_STATUS status;
274 int error = 0, i;
275
276 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
277
278 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
279 if (ifp == NULL) {
280 device_printf(sc->sc_dev, "can not if_alloc()\n");
281 error = ENOSPC;
282 goto bad;
283 }
284
285 /* set these up early for if_printf use */
286 if_initname(ifp, device_get_name(sc->sc_dev),
287 device_get_unit(sc->sc_dev));
288
289 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
290 if (ah == NULL) {
291 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
292 status);
293 error = ENXIO;
294 goto bad;
295 }
296 if (ah->ah_abi != HAL_ABI_VERSION) {
297 if_printf(ifp, "HAL ABI mismatch detected "
298 "(HAL:0x%x != driver:0x%x)\n",
299 ah->ah_abi, HAL_ABI_VERSION);
300 error = ENXIO;
301 goto bad;
302 }
303 sc->sc_ah = ah;
304 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
305
306 /*
307 * Check if the MAC has multi-rate retry support.
308 * We do this by trying to setup a fake extended
309 * descriptor. MAC's that don't have support will
310 * return false w/o doing anything. MAC's that do
311 * support it will return true w/o doing anything.
312 */
313 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
314
315 /*
316 * Check if the device has hardware counters for PHY
317 * errors. If so we need to enable the MIB interrupt
318 * so we can act on stat triggers.
319 */
320 if (ath_hal_hwphycounters(ah))
321 sc->sc_needmib = 1;
322
323 /*
324 * Get the hardware key cache size.
325 */
326 sc->sc_keymax = ath_hal_keycachesize(ah);
327 if (sc->sc_keymax > ATH_KEYMAX) {
328 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
329 ATH_KEYMAX, sc->sc_keymax);
330 sc->sc_keymax = ATH_KEYMAX;
331 }
332 /*
333 * Reset the key cache since some parts do not
334 * reset the contents on initial power up.
335 */
336 for (i = 0; i < sc->sc_keymax; i++)
337 ath_hal_keyreset(ah, i);
338 /*
339 * Mark key cache slots associated with global keys
340 * as in use. If we knew TKIP was not to be used we
341 * could leave the +32, +64, and +32+64 slots free.
342 * XXX only for splitmic.
343 */
344 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
345 setbit(sc->sc_keymap, i);
346 setbit(sc->sc_keymap, i+32);
347 setbit(sc->sc_keymap, i+64);
348 setbit(sc->sc_keymap, i+32+64);
349 }
350
351 /*
352 * Collect the channel list using the default country
353 * code and including outdoor channels. The 802.11 layer
354 * is resposible for filtering this list based on settings
355 * like the phy mode.
356 */
357 error = ath_getchannels(sc, ath_countrycode,
358 ath_outdoor, ath_xchanmode);
359 if (error != 0)
360 goto bad;
361
362 /*
363 * Setup rate tables for all potential media types.
364 */
365 ath_rate_setup(sc, IEEE80211_MODE_11A);
366 ath_rate_setup(sc, IEEE80211_MODE_11B);
367 ath_rate_setup(sc, IEEE80211_MODE_11G);
368 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
369 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
370 /* NB: setup here so ath_rate_update is happy */
371 ath_setcurmode(sc, IEEE80211_MODE_11A);
372
373 /*
374 * Allocate tx+rx descriptors and populate the lists.
375 */
376 error = ath_desc_alloc(sc);
377 if (error != 0) {
378 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
379 goto bad;
380 }
381 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0);
382 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE);
383
384 ATH_TXBUF_LOCK_INIT(sc);
385
386 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
387 taskqueue_thread_enqueue, &sc->sc_tq);
388 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
389 "%s taskq", ifp->if_xname);
390
391 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
392 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc);
393 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
394 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
395 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc);
396
397 /*
398 * Allocate hardware transmit queues: one queue for
399 * beacon frames and one data queue for each QoS
400 * priority. Note that the hal handles reseting
401 * these queues at the needed time.
402 *
403 * XXX PS-Poll
404 */
405 sc->sc_bhalq = ath_beaconq_setup(ah);
406 if (sc->sc_bhalq == (u_int) -1) {
407 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
408 error = EIO;
409 goto bad2;
410 }
411 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
412 if (sc->sc_cabq == NULL) {
413 if_printf(ifp, "unable to setup CAB xmit queue!\n");
414 error = EIO;
415 goto bad2;
416 }
417 /* NB: insure BK queue is the lowest priority h/w queue */
418 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
419 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
420 ieee80211_wme_acnames[WME_AC_BK]);
421 error = EIO;
422 goto bad2;
423 }
424 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
425 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
426 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
427 /*
428 * Not enough hardware tx queues to properly do WME;
429 * just punt and assign them all to the same h/w queue.
430 * We could do a better job of this if, for example,
431 * we allocate queues when we switch from station to
432 * AP mode.
433 */
434 if (sc->sc_ac2q[WME_AC_VI] != NULL)
435 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
436 if (sc->sc_ac2q[WME_AC_BE] != NULL)
437 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
438 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
439 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
440 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
441 }
442
443 /*
444 * Special case certain configurations. Note the
445 * CAB queue is handled by these specially so don't
446 * include them when checking the txq setup mask.
447 */
448 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
449 case 0x01:
450 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
451 break;
452 case 0x0f:
453 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
454 break;
455 default:
456 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
457 break;
458 }
459
460 /*
461 * Setup rate control. Some rate control modules
462 * call back to change the anntena state so expose
463 * the necessary entry points.
464 * XXX maybe belongs in struct ath_ratectrl?
465 */
466 sc->sc_setdefantenna = ath_setdefantenna;
467 sc->sc_rc = ath_rate_attach(sc);
468 if (sc->sc_rc == NULL) {
469 error = EIO;
470 goto bad2;
471 }
472
473 sc->sc_blinking = 0;
474 sc->sc_ledstate = 1;
475 sc->sc_ledon = 0; /* low true */
476 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
477 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
478 /*
479 * Auto-enable soft led processing for IBM cards and for
480 * 5211 minipci cards. Users can also manually enable/disable
481 * support with a sysctl.
482 */
483 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
484 if (sc->sc_softled) {
485 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
486 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
487 }
488
489 ifp->if_softc = sc;
490 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
491 ifp->if_start = ath_start;
492 ifp->if_watchdog = ath_watchdog;
493 ifp->if_ioctl = ath_ioctl;
494 ifp->if_init = ath_init;
495 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
496 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
497 IFQ_SET_READY(&ifp->if_snd);
498
499 ic->ic_ifp = ifp;
500 ic->ic_reset = ath_reset;
501 ic->ic_newassoc = ath_newassoc;
502 ic->ic_updateslot = ath_updateslot;
503 ic->ic_wme.wme_update = ath_wme_update;
504 /* XXX not right but it's not used anywhere important */
505 ic->ic_phytype = IEEE80211_T_OFDM;
506 ic->ic_opmode = IEEE80211_M_STA;
507 ic->ic_caps =
508 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
509 | IEEE80211_C_HOSTAP /* hostap mode */
510 | IEEE80211_C_MONITOR /* monitor mode */
511 | IEEE80211_C_AHDEMO /* adhoc demo mode */
512 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
513 | IEEE80211_C_SHSLOT /* short slot time supported */
514 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
515 ;
516 /*
517 * Query the hal to figure out h/w crypto support.
518 */
519 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
520 ic->ic_caps |= IEEE80211_C_WEP;
521 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
522 ic->ic_caps |= IEEE80211_C_AES;
523 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
524 ic->ic_caps |= IEEE80211_C_AES_CCM;
525 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
526 ic->ic_caps |= IEEE80211_C_CKIP;
527 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
528 ic->ic_caps |= IEEE80211_C_TKIP;
529 /*
530 * Check if h/w does the MIC and/or whether the
531 * separate key cache entries are required to
532 * handle both tx+rx MIC keys.
533 */
534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
535 ic->ic_caps |= IEEE80211_C_TKIPMIC;
536 if (ath_hal_tkipsplit(ah))
537 sc->sc_splitmic = 1;
538 }
539 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
540 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
541 /*
542 * TPC support can be done either with a global cap or
543 * per-packet support. The latter is not available on
544 * all parts. We're a bit pedantic here as all parts
545 * support a global cap.
546 */
547 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
548 ic->ic_caps |= IEEE80211_C_TXPMGT;
549
550 /*
551 * Mark WME capability only if we have sufficient
552 * hardware queues to do proper priority scheduling.
553 */
554 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
555 ic->ic_caps |= IEEE80211_C_WME;
556 /*
557 * Check for misc other capabilities.
558 */
559 if (ath_hal_hasbursting(ah))
560 ic->ic_caps |= IEEE80211_C_BURST;
561
562 /*
563 * Indicate we need the 802.11 header padded to a
564 * 32-bit boundary for 4-address and QoS frames.
565 */
566 ic->ic_flags |= IEEE80211_F_DATAPAD;
567
568 /*
569 * Query the hal about antenna support.
570 */
571 sc->sc_defant = ath_hal_getdefantenna(ah);
572
573 /*
574 * Not all chips have the VEOL support we want to
575 * use with IBSS beacons; check here for it.
576 */
577 sc->sc_hasveol = ath_hal_hasveol(ah);
578
579 /* get mac address from hardware */
580 ath_hal_getmac(ah, ic->ic_myaddr);
581
582 /* call MI attach routine. */
583 ieee80211_ifattach(ic);
584 sc->sc_opmode = ic->ic_opmode;
585 /* override default methods */
586 ic->ic_node_alloc = ath_node_alloc;
587 sc->sc_node_free = ic->ic_node_free;
588 ic->ic_node_free = ath_node_free;
589 ic->ic_node_getrssi = ath_node_getrssi;
590 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
591 ic->ic_recv_mgmt = ath_recv_mgmt;
592 sc->sc_newstate = ic->ic_newstate;
593 ic->ic_newstate = ath_newstate;
594 ic->ic_crypto.cs_max_keyix = sc->sc_keymax;
595 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
596 ic->ic_crypto.cs_key_delete = ath_key_delete;
597 ic->ic_crypto.cs_key_set = ath_key_set;
598 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
599 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
600 /* complete initialization */
601 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
602
603 ath_bpfattach(sc);
604 /*
605 * Setup dynamic sysctl's now that country code and
606 * regdomain are available from the hal.
607 */
608 ath_sysctlattach(sc);
609
610 if (bootverbose)
611 ieee80211_announce(ic);
612 ath_announce(sc);
613 return 0;
614bad2:
615 ath_tx_cleanup(sc);
616 ath_desc_free(sc);
617bad:
618 if (ah)
619 ath_hal_detach(ah);
620 if (ifp != NULL)
621 if_free(ifp);
622 sc->sc_invalid = 1;
623 return error;
624}
625
626int
627ath_detach(struct ath_softc *sc)
628{
629 struct ifnet *ifp = sc->sc_ifp;
630
631 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
632 __func__, ifp->if_flags);
633
634 ath_stop(ifp);
635 bpfdetach(ifp);
636 /*
637 * NB: the order of these is important:
638 * o call the 802.11 layer before detaching the hal to
639 * insure callbacks into the driver to delete global
640 * key cache entries can be handled
641 * o reclaim the tx queue data structures after calling
642 * the 802.11 layer as we'll get called back to reclaim
643 * node state and potentially want to use them
644 * o to cleanup the tx queues the hal is called, so detach
645 * it last
646 * Other than that, it's straightforward...
647 */
648 ieee80211_ifdetach(&sc->sc_ic);
649#ifdef ATH_TX99_DIAG
650 if (sc->sc_tx99 != NULL)
651 sc->sc_tx99->detach(sc->sc_tx99);
652#endif
653 taskqueue_free(sc->sc_tq);
654 ath_rate_detach(sc->sc_rc);
655 ath_desc_free(sc);
656 ath_tx_cleanup(sc);
657 ath_hal_detach(sc->sc_ah);
658 if_free(ifp);
659
660 return 0;
661}
662
663void
664ath_suspend(struct ath_softc *sc)
665{
666 struct ifnet *ifp = sc->sc_ifp;
667
668 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
669 __func__, ifp->if_flags);
670
671 ath_stop(ifp);
672}
673
674void
675ath_resume(struct ath_softc *sc)
676{
677 struct ifnet *ifp = sc->sc_ifp;
678
679 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
680 __func__, ifp->if_flags);
681
682 if (ifp->if_flags & IFF_UP) {
683 ath_init(sc);
684 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
685 ath_start(ifp);
686 }
687 if (sc->sc_softled) {
688 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
689 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
690 }
691}
692
693void
694ath_shutdown(struct ath_softc *sc)
695{
696 struct ifnet *ifp = sc->sc_ifp;
697
698 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
699 __func__, ifp->if_flags);
700
701 ath_stop(ifp);
702}
703
704/*
705 * Interrupt handler. Most of the actual processing is deferred.
706 */
707void
708ath_intr(void *arg)
709{
710 struct ath_softc *sc = arg;
711 struct ifnet *ifp = sc->sc_ifp;
712 struct ath_hal *ah = sc->sc_ah;
713 HAL_INT status;
714
715 if (sc->sc_invalid) {
716 /*
717 * The hardware is not ready/present, don't touch anything.
718 * Note this can happen early on if the IRQ is shared.
719 */
720 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
721 return;
722 }
723 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
724 return;
725 if (!((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags &
726 IFF_DRV_RUNNING))) {
727 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
728 __func__, ifp->if_flags);
729 ath_hal_getisr(ah, &status); /* clear ISR */
730 ath_hal_intrset(ah, 0); /* disable further intr's */
731 return;
732 }
733 /*
734 * Figure out the reason(s) for the interrupt. Note
735 * that the hal returns a pseudo-ISR that may include
736 * bits we haven't explicitly enabled so we mask the
737 * value to insure we only process bits we requested.
738 */
739 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
740 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
741 status &= sc->sc_imask; /* discard unasked for bits */
742 if (status & HAL_INT_FATAL) {
743 /*
744 * Fatal errors are unrecoverable. Typically
745 * these are caused by DMA errors. Unfortunately
746 * the exact reason is not (presently) returned
747 * by the hal.
748 */
749 sc->sc_stats.ast_hardware++;
750 ath_hal_intrset(ah, 0); /* disable intr's until reset */
751 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
752 } else if (status & HAL_INT_RXORN) {
753 sc->sc_stats.ast_rxorn++;
754 ath_hal_intrset(ah, 0); /* disable intr's until reset */
755 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask);
756 } else {
757 if (status & HAL_INT_SWBA) {
758 /*
759 * Software beacon alert--time to send a beacon.
760 * Handle beacon transmission directly; deferring
761 * this is too slow to meet timing constraints
762 * under load.
763 */
764 ath_beacon_proc(sc, 0);
765 }
766 if (status & HAL_INT_RXEOL) {
767 /*
768 * NB: the hardware should re-read the link when
769 * RXE bit is written, but it doesn't work at
770 * least on older hardware revs.
771 */
772 sc->sc_stats.ast_rxeol++;
773 sc->sc_rxlink = NULL;
774 }
775 if (status & HAL_INT_TXURN) {
776 sc->sc_stats.ast_txurn++;
777 /* bump tx trigger level */
778 ath_hal_updatetxtriglevel(ah, AH_TRUE);
779 }
780 if (status & HAL_INT_RX)
781 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
782 if (status & HAL_INT_TX)
783 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
784 if (status & HAL_INT_BMISS) {
785 sc->sc_stats.ast_bmiss++;
786 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
787 }
788 if (status & HAL_INT_MIB) {
789 sc->sc_stats.ast_mib++;
790 /*
791 * Disable interrupts until we service the MIB
792 * interrupt; otherwise it will continue to fire.
793 */
794 ath_hal_intrset(ah, 0);
795 /*
796 * Let the hal handle the event. We assume it will
797 * clear whatever condition caused the interrupt.
798 */
799 ath_hal_mibevent(ah, &sc->sc_halstats);
800 ath_hal_intrset(ah, sc->sc_imask);
801 }
802 }
803}
804
805static void
806ath_fatal_proc(void *arg, int pending)
807{
808 struct ath_softc *sc = arg;
809 struct ifnet *ifp = sc->sc_ifp;
810
811 if_printf(ifp, "hardware error; resetting\n");
812 ath_reset(ifp);
813}
814
815static void
816ath_rxorn_proc(void *arg, int pending)
817{
818 struct ath_softc *sc = arg;
819 struct ifnet *ifp = sc->sc_ifp;
820
821 if_printf(ifp, "rx FIFO overrun; resetting\n");
822 ath_reset(ifp);
823}
824
825static void
826ath_bmiss_proc(void *arg, int pending)
827{
828 struct ath_softc *sc = arg;
829 struct ieee80211com *ic = &sc->sc_ic;
830
831 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
832 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
833 ("unexpect operating mode %u", ic->ic_opmode));
834 if (ic->ic_state == IEEE80211_S_RUN) {
| 39
40/*
41 * Driver for the Atheros Wireless LAN controller.
42 *
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
45 */
46
47#include "opt_inet.h"
48
49#include <sys/param.h>
50#include <sys/systm.h>
51#include <sys/sysctl.h>
52#include <sys/mbuf.h>
53#include <sys/malloc.h>
54#include <sys/lock.h>
55#include <sys/mutex.h>
56#include <sys/kernel.h>
57#include <sys/socket.h>
58#include <sys/sockio.h>
59#include <sys/errno.h>
60#include <sys/callout.h>
61#include <sys/bus.h>
62#include <sys/endian.h>
63#include <sys/kthread.h>
64#include <sys/taskqueue.h>
65
66#include <machine/bus.h>
67
68#include <net/if.h>
69#include <net/if_dl.h>
70#include <net/if_media.h>
71#include <net/if_types.h>
72#include <net/if_arp.h>
73#include <net/ethernet.h>
74#include <net/if_llc.h>
75
76#include <net80211/ieee80211_var.h>
77
78#include <net/bpf.h>
79
80#ifdef INET
81#include <netinet/in.h>
82#include <netinet/if_ether.h>
83#endif
84
85#define AR_DEBUG
86#include <dev/ath/if_athvar.h>
87#include <contrib/dev/ath/ah_desc.h>
88#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
89
90#ifdef ATH_TX99_DIAG
91#include <dev/ath/ath_tx99/ath_tx99.h>
92#endif
93
94/* unaligned little endian access */
95#define LE_READ_2(p) \
96 ((u_int16_t) \
97 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
98#define LE_READ_4(p) \
99 ((u_int32_t) \
100 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
101 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
102
103enum {
104 ATH_LED_TX,
105 ATH_LED_RX,
106 ATH_LED_POLL,
107};
108
109static void ath_init(void *);
110static void ath_stop_locked(struct ifnet *);
111static void ath_stop(struct ifnet *);
112static void ath_start(struct ifnet *);
113static int ath_reset(struct ifnet *);
114static int ath_media_change(struct ifnet *);
115static void ath_watchdog(struct ifnet *);
116static int ath_ioctl(struct ifnet *, u_long, caddr_t);
117static void ath_fatal_proc(void *, int);
118static void ath_rxorn_proc(void *, int);
119static void ath_bmiss_proc(void *, int);
120static int ath_key_alloc(struct ieee80211com *,
121 const struct ieee80211_key *,
122 ieee80211_keyix *, ieee80211_keyix *);
123static int ath_key_delete(struct ieee80211com *,
124 const struct ieee80211_key *);
125static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
126 const u_int8_t mac[IEEE80211_ADDR_LEN]);
127static void ath_key_update_begin(struct ieee80211com *);
128static void ath_key_update_end(struct ieee80211com *);
129static void ath_mode_init(struct ath_softc *);
130static void ath_setslottime(struct ath_softc *);
131static void ath_updateslot(struct ifnet *);
132static int ath_beaconq_setup(struct ath_hal *);
133static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
134static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
135static void ath_beacon_proc(void *, int);
136static void ath_bstuck_proc(void *, int);
137static void ath_beacon_free(struct ath_softc *);
138static void ath_beacon_config(struct ath_softc *);
139static void ath_descdma_cleanup(struct ath_softc *sc,
140 struct ath_descdma *, ath_bufhead *);
141static int ath_desc_alloc(struct ath_softc *);
142static void ath_desc_free(struct ath_softc *);
143static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
144static void ath_node_free(struct ieee80211_node *);
145static u_int8_t ath_node_getrssi(const struct ieee80211_node *);
146static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
147static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
148 struct ieee80211_node *ni,
149 int subtype, int rssi, u_int32_t rstamp);
150static void ath_setdefantenna(struct ath_softc *, u_int);
151static void ath_rx_proc(void *, int);
152static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
153static int ath_tx_setup(struct ath_softc *, int, int);
154static int ath_wme_update(struct ieee80211com *);
155static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
156static void ath_tx_cleanup(struct ath_softc *);
157static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
158 struct ath_buf *, struct mbuf *);
159static void ath_tx_proc_q0(void *, int);
160static void ath_tx_proc_q0123(void *, int);
161static void ath_tx_proc(void *, int);
162static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
163static void ath_draintxq(struct ath_softc *);
164static void ath_stoprecv(struct ath_softc *);
165static int ath_startrecv(struct ath_softc *);
166static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
167static void ath_next_scan(void *);
168static void ath_calibrate(void *);
169static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
170static void ath_setup_stationkey(struct ieee80211_node *);
171static void ath_newassoc(struct ieee80211_node *, int);
172static int ath_getchannels(struct ath_softc *, u_int cc,
173 HAL_BOOL outdoor, HAL_BOOL xchanmode);
174static void ath_led_event(struct ath_softc *, int);
175static void ath_update_txpow(struct ath_softc *);
176
177static int ath_rate_setup(struct ath_softc *, u_int mode);
178static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
179
180static void ath_sysctlattach(struct ath_softc *);
181static void ath_bpfattach(struct ath_softc *);
182static void ath_announce(struct ath_softc *);
183
184SYSCTL_DECL(_hw_ath);
185
186/* XXX validate sysctl values */
187static int ath_dwelltime = 200; /* 5 channels/second */
188SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
189 0, "channel dwell time (ms) for AP/station scanning");
190static int ath_calinterval = 30; /* calibrate every 30 secs */
191SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
192 0, "chip calibration interval (secs)");
193static int ath_outdoor = AH_TRUE; /* outdoor operation */
194SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
195 0, "outdoor operation");
196TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
197static int ath_xchanmode = AH_TRUE; /* extended channel use */
198SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
199 0, "extended channel mode");
200TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
201static int ath_countrycode = CTRY_DEFAULT; /* country code */
202SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
203 0, "country code");
204TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
205static int ath_regdomain = 0; /* regulatory domain */
206SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
207 0, "regulatory domain");
208
209static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
210SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf,
211 0, "rx buffers allocated");
212TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
213static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
214SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf,
215 0, "tx buffers allocated");
216TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
217
218#ifdef AR_DEBUG
219static int ath_debug = 0;
220SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
221 0, "control debugging printfs");
222TUNABLE_INT("hw.ath.debug", &ath_debug);
223enum {
224 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
225 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
226 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
227 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
228 ATH_DEBUG_RATE = 0x00000010, /* rate control */
229 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
230 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
231 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
232 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
233 ATH_DEBUG_INTR = 0x00001000, /* ISR */
234 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
235 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
236 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
237 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
238 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
239 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
240 ATH_DEBUG_NODE = 0x00080000, /* node management */
241 ATH_DEBUG_LED = 0x00100000, /* led management */
242 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
243 ATH_DEBUG_ANY = 0xffffffff
244};
245#define IFF_DUMPPKTS(sc, m) \
246 ((sc->sc_debug & (m)) || \
247 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
248#define DPRINTF(sc, m, fmt, ...) do { \
249 if (sc->sc_debug & (m)) \
250 printf(fmt, __VA_ARGS__); \
251} while (0)
252#define KEYPRINTF(sc, ix, hk, mac) do { \
253 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
254 ath_keyprint(__func__, ix, hk, mac); \
255} while (0)
256static void ath_printrxbuf(struct ath_buf *bf, int);
257static void ath_printtxbuf(struct ath_buf *bf, int);
258#else
259#define IFF_DUMPPKTS(sc, m) \
260 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
261#define DPRINTF(m, fmt, ...)
262#define KEYPRINTF(sc, k, ix, mac)
263#endif
264
265MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
266
267int
268ath_attach(u_int16_t devid, struct ath_softc *sc)
269{
270 struct ifnet *ifp;
271 struct ieee80211com *ic = &sc->sc_ic;
272 struct ath_hal *ah = NULL;
273 HAL_STATUS status;
274 int error = 0, i;
275
276 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
277
278 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
279 if (ifp == NULL) {
280 device_printf(sc->sc_dev, "can not if_alloc()\n");
281 error = ENOSPC;
282 goto bad;
283 }
284
285 /* set these up early for if_printf use */
286 if_initname(ifp, device_get_name(sc->sc_dev),
287 device_get_unit(sc->sc_dev));
288
289 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
290 if (ah == NULL) {
291 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
292 status);
293 error = ENXIO;
294 goto bad;
295 }
296 if (ah->ah_abi != HAL_ABI_VERSION) {
297 if_printf(ifp, "HAL ABI mismatch detected "
298 "(HAL:0x%x != driver:0x%x)\n",
299 ah->ah_abi, HAL_ABI_VERSION);
300 error = ENXIO;
301 goto bad;
302 }
303 sc->sc_ah = ah;
304 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
305
306 /*
307 * Check if the MAC has multi-rate retry support.
308 * We do this by trying to setup a fake extended
309 * descriptor. MAC's that don't have support will
310 * return false w/o doing anything. MAC's that do
311 * support it will return true w/o doing anything.
312 */
313 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
314
315 /*
316 * Check if the device has hardware counters for PHY
317 * errors. If so we need to enable the MIB interrupt
318 * so we can act on stat triggers.
319 */
320 if (ath_hal_hwphycounters(ah))
321 sc->sc_needmib = 1;
322
323 /*
324 * Get the hardware key cache size.
325 */
326 sc->sc_keymax = ath_hal_keycachesize(ah);
327 if (sc->sc_keymax > ATH_KEYMAX) {
328 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
329 ATH_KEYMAX, sc->sc_keymax);
330 sc->sc_keymax = ATH_KEYMAX;
331 }
332 /*
333 * Reset the key cache since some parts do not
334 * reset the contents on initial power up.
335 */
336 for (i = 0; i < sc->sc_keymax; i++)
337 ath_hal_keyreset(ah, i);
338 /*
339 * Mark key cache slots associated with global keys
340 * as in use. If we knew TKIP was not to be used we
341 * could leave the +32, +64, and +32+64 slots free.
342 * XXX only for splitmic.
343 */
344 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
345 setbit(sc->sc_keymap, i);
346 setbit(sc->sc_keymap, i+32);
347 setbit(sc->sc_keymap, i+64);
348 setbit(sc->sc_keymap, i+32+64);
349 }
350
351 /*
352 * Collect the channel list using the default country
353 * code and including outdoor channels. The 802.11 layer
354 * is resposible for filtering this list based on settings
355 * like the phy mode.
356 */
357 error = ath_getchannels(sc, ath_countrycode,
358 ath_outdoor, ath_xchanmode);
359 if (error != 0)
360 goto bad;
361
362 /*
363 * Setup rate tables for all potential media types.
364 */
365 ath_rate_setup(sc, IEEE80211_MODE_11A);
366 ath_rate_setup(sc, IEEE80211_MODE_11B);
367 ath_rate_setup(sc, IEEE80211_MODE_11G);
368 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
369 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
370 /* NB: setup here so ath_rate_update is happy */
371 ath_setcurmode(sc, IEEE80211_MODE_11A);
372
373 /*
374 * Allocate tx+rx descriptors and populate the lists.
375 */
376 error = ath_desc_alloc(sc);
377 if (error != 0) {
378 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
379 goto bad;
380 }
381 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0);
382 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE);
383
384 ATH_TXBUF_LOCK_INIT(sc);
385
386 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
387 taskqueue_thread_enqueue, &sc->sc_tq);
388 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
389 "%s taskq", ifp->if_xname);
390
391 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
392 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc);
393 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
394 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
395 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc);
396
397 /*
398 * Allocate hardware transmit queues: one queue for
399 * beacon frames and one data queue for each QoS
400 * priority. Note that the hal handles reseting
401 * these queues at the needed time.
402 *
403 * XXX PS-Poll
404 */
405 sc->sc_bhalq = ath_beaconq_setup(ah);
406 if (sc->sc_bhalq == (u_int) -1) {
407 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
408 error = EIO;
409 goto bad2;
410 }
411 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
412 if (sc->sc_cabq == NULL) {
413 if_printf(ifp, "unable to setup CAB xmit queue!\n");
414 error = EIO;
415 goto bad2;
416 }
417 /* NB: insure BK queue is the lowest priority h/w queue */
418 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
419 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
420 ieee80211_wme_acnames[WME_AC_BK]);
421 error = EIO;
422 goto bad2;
423 }
424 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
425 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
426 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
427 /*
428 * Not enough hardware tx queues to properly do WME;
429 * just punt and assign them all to the same h/w queue.
430 * We could do a better job of this if, for example,
431 * we allocate queues when we switch from station to
432 * AP mode.
433 */
434 if (sc->sc_ac2q[WME_AC_VI] != NULL)
435 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
436 if (sc->sc_ac2q[WME_AC_BE] != NULL)
437 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
438 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
439 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
440 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
441 }
442
443 /*
444 * Special case certain configurations. Note the
445 * CAB queue is handled by these specially so don't
446 * include them when checking the txq setup mask.
447 */
448 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
449 case 0x01:
450 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
451 break;
452 case 0x0f:
453 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
454 break;
455 default:
456 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
457 break;
458 }
459
460 /*
461 * Setup rate control. Some rate control modules
462 * call back to change the anntena state so expose
463 * the necessary entry points.
464 * XXX maybe belongs in struct ath_ratectrl?
465 */
466 sc->sc_setdefantenna = ath_setdefantenna;
467 sc->sc_rc = ath_rate_attach(sc);
468 if (sc->sc_rc == NULL) {
469 error = EIO;
470 goto bad2;
471 }
472
473 sc->sc_blinking = 0;
474 sc->sc_ledstate = 1;
475 sc->sc_ledon = 0; /* low true */
476 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
477 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
478 /*
479 * Auto-enable soft led processing for IBM cards and for
480 * 5211 minipci cards. Users can also manually enable/disable
481 * support with a sysctl.
482 */
483 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
484 if (sc->sc_softled) {
485 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
486 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
487 }
488
489 ifp->if_softc = sc;
490 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
491 ifp->if_start = ath_start;
492 ifp->if_watchdog = ath_watchdog;
493 ifp->if_ioctl = ath_ioctl;
494 ifp->if_init = ath_init;
495 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
496 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
497 IFQ_SET_READY(&ifp->if_snd);
498
499 ic->ic_ifp = ifp;
500 ic->ic_reset = ath_reset;
501 ic->ic_newassoc = ath_newassoc;
502 ic->ic_updateslot = ath_updateslot;
503 ic->ic_wme.wme_update = ath_wme_update;
504 /* XXX not right but it's not used anywhere important */
505 ic->ic_phytype = IEEE80211_T_OFDM;
506 ic->ic_opmode = IEEE80211_M_STA;
507 ic->ic_caps =
508 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
509 | IEEE80211_C_HOSTAP /* hostap mode */
510 | IEEE80211_C_MONITOR /* monitor mode */
511 | IEEE80211_C_AHDEMO /* adhoc demo mode */
512 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
513 | IEEE80211_C_SHSLOT /* short slot time supported */
514 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
515 ;
516 /*
517 * Query the hal to figure out h/w crypto support.
518 */
519 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
520 ic->ic_caps |= IEEE80211_C_WEP;
521 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
522 ic->ic_caps |= IEEE80211_C_AES;
523 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
524 ic->ic_caps |= IEEE80211_C_AES_CCM;
525 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
526 ic->ic_caps |= IEEE80211_C_CKIP;
527 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
528 ic->ic_caps |= IEEE80211_C_TKIP;
529 /*
530 * Check if h/w does the MIC and/or whether the
531 * separate key cache entries are required to
532 * handle both tx+rx MIC keys.
533 */
534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
535 ic->ic_caps |= IEEE80211_C_TKIPMIC;
536 if (ath_hal_tkipsplit(ah))
537 sc->sc_splitmic = 1;
538 }
539 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
540 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
541 /*
542 * TPC support can be done either with a global cap or
543 * per-packet support. The latter is not available on
544 * all parts. We're a bit pedantic here as all parts
545 * support a global cap.
546 */
547 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
548 ic->ic_caps |= IEEE80211_C_TXPMGT;
549
550 /*
551 * Mark WME capability only if we have sufficient
552 * hardware queues to do proper priority scheduling.
553 */
554 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
555 ic->ic_caps |= IEEE80211_C_WME;
556 /*
557 * Check for misc other capabilities.
558 */
559 if (ath_hal_hasbursting(ah))
560 ic->ic_caps |= IEEE80211_C_BURST;
561
562 /*
563 * Indicate we need the 802.11 header padded to a
564 * 32-bit boundary for 4-address and QoS frames.
565 */
566 ic->ic_flags |= IEEE80211_F_DATAPAD;
567
568 /*
569 * Query the hal about antenna support.
570 */
571 sc->sc_defant = ath_hal_getdefantenna(ah);
572
573 /*
574 * Not all chips have the VEOL support we want to
575 * use with IBSS beacons; check here for it.
576 */
577 sc->sc_hasveol = ath_hal_hasveol(ah);
578
579 /* get mac address from hardware */
580 ath_hal_getmac(ah, ic->ic_myaddr);
581
582 /* call MI attach routine. */
583 ieee80211_ifattach(ic);
584 sc->sc_opmode = ic->ic_opmode;
585 /* override default methods */
586 ic->ic_node_alloc = ath_node_alloc;
587 sc->sc_node_free = ic->ic_node_free;
588 ic->ic_node_free = ath_node_free;
589 ic->ic_node_getrssi = ath_node_getrssi;
590 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
591 ic->ic_recv_mgmt = ath_recv_mgmt;
592 sc->sc_newstate = ic->ic_newstate;
593 ic->ic_newstate = ath_newstate;
594 ic->ic_crypto.cs_max_keyix = sc->sc_keymax;
595 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
596 ic->ic_crypto.cs_key_delete = ath_key_delete;
597 ic->ic_crypto.cs_key_set = ath_key_set;
598 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
599 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
600 /* complete initialization */
601 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
602
603 ath_bpfattach(sc);
604 /*
605 * Setup dynamic sysctl's now that country code and
606 * regdomain are available from the hal.
607 */
608 ath_sysctlattach(sc);
609
610 if (bootverbose)
611 ieee80211_announce(ic);
612 ath_announce(sc);
613 return 0;
614bad2:
615 ath_tx_cleanup(sc);
616 ath_desc_free(sc);
617bad:
618 if (ah)
619 ath_hal_detach(ah);
620 if (ifp != NULL)
621 if_free(ifp);
622 sc->sc_invalid = 1;
623 return error;
624}
625
626int
627ath_detach(struct ath_softc *sc)
628{
629 struct ifnet *ifp = sc->sc_ifp;
630
631 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
632 __func__, ifp->if_flags);
633
634 ath_stop(ifp);
635 bpfdetach(ifp);
636 /*
637 * NB: the order of these is important:
638 * o call the 802.11 layer before detaching the hal to
639 * insure callbacks into the driver to delete global
640 * key cache entries can be handled
641 * o reclaim the tx queue data structures after calling
642 * the 802.11 layer as we'll get called back to reclaim
643 * node state and potentially want to use them
644 * o to cleanup the tx queues the hal is called, so detach
645 * it last
646 * Other than that, it's straightforward...
647 */
648 ieee80211_ifdetach(&sc->sc_ic);
649#ifdef ATH_TX99_DIAG
650 if (sc->sc_tx99 != NULL)
651 sc->sc_tx99->detach(sc->sc_tx99);
652#endif
653 taskqueue_free(sc->sc_tq);
654 ath_rate_detach(sc->sc_rc);
655 ath_desc_free(sc);
656 ath_tx_cleanup(sc);
657 ath_hal_detach(sc->sc_ah);
658 if_free(ifp);
659
660 return 0;
661}
662
663void
664ath_suspend(struct ath_softc *sc)
665{
666 struct ifnet *ifp = sc->sc_ifp;
667
668 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
669 __func__, ifp->if_flags);
670
671 ath_stop(ifp);
672}
673
674void
675ath_resume(struct ath_softc *sc)
676{
677 struct ifnet *ifp = sc->sc_ifp;
678
679 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
680 __func__, ifp->if_flags);
681
682 if (ifp->if_flags & IFF_UP) {
683 ath_init(sc);
684 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
685 ath_start(ifp);
686 }
687 if (sc->sc_softled) {
688 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
689 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
690 }
691}
692
693void
694ath_shutdown(struct ath_softc *sc)
695{
696 struct ifnet *ifp = sc->sc_ifp;
697
698 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
699 __func__, ifp->if_flags);
700
701 ath_stop(ifp);
702}
703
704/*
705 * Interrupt handler. Most of the actual processing is deferred.
706 */
707void
708ath_intr(void *arg)
709{
710 struct ath_softc *sc = arg;
711 struct ifnet *ifp = sc->sc_ifp;
712 struct ath_hal *ah = sc->sc_ah;
713 HAL_INT status;
714
715 if (sc->sc_invalid) {
716 /*
717 * The hardware is not ready/present, don't touch anything.
718 * Note this can happen early on if the IRQ is shared.
719 */
720 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
721 return;
722 }
723 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
724 return;
725 if (!((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags &
726 IFF_DRV_RUNNING))) {
727 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
728 __func__, ifp->if_flags);
729 ath_hal_getisr(ah, &status); /* clear ISR */
730 ath_hal_intrset(ah, 0); /* disable further intr's */
731 return;
732 }
733 /*
734 * Figure out the reason(s) for the interrupt. Note
735 * that the hal returns a pseudo-ISR that may include
736 * bits we haven't explicitly enabled so we mask the
737 * value to insure we only process bits we requested.
738 */
739 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
740 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
741 status &= sc->sc_imask; /* discard unasked for bits */
742 if (status & HAL_INT_FATAL) {
743 /*
744 * Fatal errors are unrecoverable. Typically
745 * these are caused by DMA errors. Unfortunately
746 * the exact reason is not (presently) returned
747 * by the hal.
748 */
749 sc->sc_stats.ast_hardware++;
750 ath_hal_intrset(ah, 0); /* disable intr's until reset */
751 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
752 } else if (status & HAL_INT_RXORN) {
753 sc->sc_stats.ast_rxorn++;
754 ath_hal_intrset(ah, 0); /* disable intr's until reset */
755 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask);
756 } else {
757 if (status & HAL_INT_SWBA) {
758 /*
759 * Software beacon alert--time to send a beacon.
760 * Handle beacon transmission directly; deferring
761 * this is too slow to meet timing constraints
762 * under load.
763 */
764 ath_beacon_proc(sc, 0);
765 }
766 if (status & HAL_INT_RXEOL) {
767 /*
768 * NB: the hardware should re-read the link when
769 * RXE bit is written, but it doesn't work at
770 * least on older hardware revs.
771 */
772 sc->sc_stats.ast_rxeol++;
773 sc->sc_rxlink = NULL;
774 }
775 if (status & HAL_INT_TXURN) {
776 sc->sc_stats.ast_txurn++;
777 /* bump tx trigger level */
778 ath_hal_updatetxtriglevel(ah, AH_TRUE);
779 }
780 if (status & HAL_INT_RX)
781 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
782 if (status & HAL_INT_TX)
783 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
784 if (status & HAL_INT_BMISS) {
785 sc->sc_stats.ast_bmiss++;
786 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
787 }
788 if (status & HAL_INT_MIB) {
789 sc->sc_stats.ast_mib++;
790 /*
791 * Disable interrupts until we service the MIB
792 * interrupt; otherwise it will continue to fire.
793 */
794 ath_hal_intrset(ah, 0);
795 /*
796 * Let the hal handle the event. We assume it will
797 * clear whatever condition caused the interrupt.
798 */
799 ath_hal_mibevent(ah, &sc->sc_halstats);
800 ath_hal_intrset(ah, sc->sc_imask);
801 }
802 }
803}
804
805static void
806ath_fatal_proc(void *arg, int pending)
807{
808 struct ath_softc *sc = arg;
809 struct ifnet *ifp = sc->sc_ifp;
810
811 if_printf(ifp, "hardware error; resetting\n");
812 ath_reset(ifp);
813}
814
815static void
816ath_rxorn_proc(void *arg, int pending)
817{
818 struct ath_softc *sc = arg;
819 struct ifnet *ifp = sc->sc_ifp;
820
821 if_printf(ifp, "rx FIFO overrun; resetting\n");
822 ath_reset(ifp);
823}
824
825static void
826ath_bmiss_proc(void *arg, int pending)
827{
828 struct ath_softc *sc = arg;
829 struct ieee80211com *ic = &sc->sc_ic;
830
831 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
832 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
833 ("unexpect operating mode %u", ic->ic_opmode));
834 if (ic->ic_state == IEEE80211_S_RUN) {
|
| 835 u_int64_t lastrx = sc->sc_lastrx;
836 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
837 u_int bmisstimeout =
838 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024;
839
840 DPRINTF(sc, ATH_DEBUG_BEACON,
841 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
842 __func__, (unsigned long long) tsf,
843 (unsigned long long)(tsf - lastrx),
844 (unsigned long long) lastrx, bmisstimeout);
|
835 /*
| 845 /*
|
836 * Rather than go directly to scan state, try to
837 * reassociate first. If that fails then the state
838 * machine will drop us into scanning after timing
839 * out waiting for a probe response.
| 846 * Workaround phantom bmiss interrupts by sanity-checking
847 * the time of our last rx'd frame. If it is within the
848 * beacon miss interval then ignore the interrupt. If it's
849 * truly a bmiss we'll get another interrupt soon and that'll
850 * be dispatched up for processing.
|
840 */
| 851 */
|
841 NET_LOCK_GIANT();
842 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1);
843 NET_UNLOCK_GIANT();
| 852 if (tsf - lastrx > bmisstimeout) {
853 NET_LOCK_GIANT();
854 ieee80211_beacon_miss(ic);
855 NET_UNLOCK_GIANT();
856 } else
857 sc->sc_stats.ast_bmiss_phantom++;
|
844 }
845}
846
847static u_int
848ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
849{
850#define N(a) (sizeof(a) / sizeof(a[0]))
851 static const u_int modeflags[] = {
852 0, /* IEEE80211_MODE_AUTO */
853 CHANNEL_A, /* IEEE80211_MODE_11A */
854 CHANNEL_B, /* IEEE80211_MODE_11B */
855 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
856 0, /* IEEE80211_MODE_FH */
857 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */
858 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
859 };
860 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
861
862 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
863 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
864 return modeflags[mode];
865#undef N
866}
867
868static void
869ath_init(void *arg)
870{
871 struct ath_softc *sc = (struct ath_softc *) arg;
872 struct ieee80211com *ic = &sc->sc_ic;
873 struct ifnet *ifp = sc->sc_ifp;
874 struct ath_hal *ah = sc->sc_ah;
875 HAL_STATUS status;
876
877 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
878 __func__, ifp->if_flags);
879
880 ATH_LOCK(sc);
881 /*
882 * Stop anything previously setup. This is safe
883 * whether this is the first time through or not.
884 */
885 ath_stop_locked(ifp);
886
887 /*
888 * The basic interface to setting the hardware in a good
889 * state is ``reset''. On return the hardware is known to
890 * be powered up and with interrupts disabled. This must
891 * be followed by initialization of the appropriate bits
892 * and then setup of the interrupt mask.
893 */
894 sc->sc_curchan.channel = ic->ic_curchan->ic_freq;
895 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
896 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) {
897 if_printf(ifp, "unable to reset hardware; hal status %u\n",
898 status);
899 goto done;
900 }
901
902 /*
903 * This is needed only to setup initial state
904 * but it's best done after a reset.
905 */
906 ath_update_txpow(sc);
907 /*
908 * Likewise this is set during reset so update
909 * state cached in the driver.
910 */
911 sc->sc_diversity = ath_hal_getdiversity(ah);
912
913 /*
914 * Setup the hardware after reset: the key cache
915 * is filled as needed and the receive engine is
916 * set going. Frame transmit is handled entirely
917 * in the frame output path; there's nothing to do
918 * here except setup the interrupt mask.
919 */
920 if (ath_startrecv(sc) != 0) {
921 if_printf(ifp, "unable to start recv logic\n");
922 goto done;
923 }
924
925 /*
926 * Enable interrupts.
927 */
928 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
929 | HAL_INT_RXEOL | HAL_INT_RXORN
930 | HAL_INT_FATAL | HAL_INT_GLOBAL;
931 /*
932 * Enable MIB interrupts when there are hardware phy counters.
933 * Note we only do this (at the moment) for station mode.
934 */
935 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
936 sc->sc_imask |= HAL_INT_MIB;
937 ath_hal_intrset(ah, sc->sc_imask);
938
939 ifp->if_drv_flags |= IFF_DRV_RUNNING;
940 ic->ic_state = IEEE80211_S_INIT;
941
942 /*
943 * The hardware should be ready to go now so it's safe
944 * to kick the 802.11 state machine as it's likely to
945 * immediately call back to us to send mgmt frames.
946 */
947 ath_chan_change(sc, ic->ic_curchan);
948#ifdef ATH_TX99_DIAG
949 if (sc->sc_tx99 != NULL)
950 sc->sc_tx99->start(sc->sc_tx99);
951 else
952#endif
953 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
954 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
955 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
956 } else
957 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
958done:
959 ATH_UNLOCK(sc);
960}
961
962static void
963ath_stop_locked(struct ifnet *ifp)
964{
965 struct ath_softc *sc = ifp->if_softc;
966 struct ieee80211com *ic = &sc->sc_ic;
967 struct ath_hal *ah = sc->sc_ah;
968
969 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
970 __func__, sc->sc_invalid, ifp->if_flags);
971
972 ATH_LOCK_ASSERT(sc);
973 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
974 /*
975 * Shutdown the hardware and driver:
976 * reset 802.11 state machine
977 * turn off timers
978 * disable interrupts
979 * turn off the radio
980 * clear transmit machinery
981 * clear receive machinery
982 * drain and release tx queues
983 * reclaim beacon resources
984 * power down hardware
985 *
986 * Note that some of this work is not possible if the
987 * hardware is gone (invalid).
988 */
989#ifdef ATH_TX99_DIAG
990 if (sc->sc_tx99 != NULL)
991 sc->sc_tx99->stop(sc->sc_tx99);
992#endif
993 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
994 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
995 ifp->if_timer = 0;
996 if (!sc->sc_invalid) {
997 if (sc->sc_softled) {
998 callout_stop(&sc->sc_ledtimer);
999 ath_hal_gpioset(ah, sc->sc_ledpin,
1000 !sc->sc_ledon);
1001 sc->sc_blinking = 0;
1002 }
1003 ath_hal_intrset(ah, 0);
1004 }
1005 ath_draintxq(sc);
1006 if (!sc->sc_invalid) {
1007 ath_stoprecv(sc);
1008 ath_hal_phydisable(ah);
1009 } else
1010 sc->sc_rxlink = NULL;
1011 IFQ_DRV_PURGE(&ifp->if_snd);
1012 ath_beacon_free(sc);
1013 }
1014}
1015
1016static void
1017ath_stop(struct ifnet *ifp)
1018{
1019 struct ath_softc *sc = ifp->if_softc;
1020
1021 ATH_LOCK(sc);
1022 ath_stop_locked(ifp);
1023 if (!sc->sc_invalid) {
1024 /*
1025 * Set the chip in full sleep mode. Note that we are
1026 * careful to do this only when bringing the interface
1027 * completely to a stop. When the chip is in this state
1028 * it must be carefully woken up or references to
1029 * registers in the PCI clock domain may freeze the bus
1030 * (and system). This varies by chip and is mostly an
1031 * issue with newer parts that go to sleep more quickly.
1032 */
1033 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0);
1034 }
1035 ATH_UNLOCK(sc);
1036}
1037
1038/*
1039 * Reset the hardware w/o losing operational state. This is
1040 * basically a more efficient way of doing ath_stop, ath_init,
1041 * followed by state transitions to the current 802.11
1042 * operational state. Used to recover from various errors and
1043 * to reset or reload hardware state.
1044 */
1045static int
1046ath_reset(struct ifnet *ifp)
1047{
1048 struct ath_softc *sc = ifp->if_softc;
1049 struct ieee80211com *ic = &sc->sc_ic;
1050 struct ath_hal *ah = sc->sc_ah;
1051 struct ieee80211_channel *c;
1052 HAL_STATUS status;
1053
1054 /*
1055 * Convert to a HAL channel description with the flags
1056 * constrained to reflect the current operating mode.
1057 */
1058 c = ic->ic_curchan;
1059 sc->sc_curchan.channel = c->ic_freq;
1060 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1061
1062 ath_hal_intrset(ah, 0); /* disable interrupts */
1063 ath_draintxq(sc); /* stop xmit side */
1064 ath_stoprecv(sc); /* stop recv side */
1065 /* NB: indicate channel change so we do a full reset */
1066 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status))
1067 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1068 __func__, status);
1069 ath_update_txpow(sc); /* update tx power state */
1070 sc->sc_diversity = ath_hal_getdiversity(ah);
1071 if (ath_startrecv(sc) != 0) /* restart recv */
1072 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1073 /*
1074 * We may be doing a reset in response to an ioctl
1075 * that changes the channel so update any state that
1076 * might change as a result.
1077 */
1078 ath_chan_change(sc, c);
1079 if (ic->ic_state == IEEE80211_S_RUN)
1080 ath_beacon_config(sc); /* restart beacons */
1081 ath_hal_intrset(ah, sc->sc_imask);
1082
1083 ath_start(ifp); /* restart xmit */
1084 return 0;
1085}
1086
1087static void
1088ath_start(struct ifnet *ifp)
1089{
1090 struct ath_softc *sc = ifp->if_softc;
1091 struct ath_hal *ah = sc->sc_ah;
1092 struct ieee80211com *ic = &sc->sc_ic;
1093 struct ieee80211_node *ni;
1094 struct ath_buf *bf;
1095 struct mbuf *m;
1096 struct ieee80211_frame *wh;
1097 struct ether_header *eh;
1098
1099 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1100 return;
1101 for (;;) {
1102 /*
1103 * Grab a TX buffer and associated resources.
1104 */
1105 ATH_TXBUF_LOCK(sc);
1106 bf = STAILQ_FIRST(&sc->sc_txbuf);
1107 if (bf != NULL)
1108 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1109 ATH_TXBUF_UNLOCK(sc);
1110 if (bf == NULL) {
1111 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n",
1112 __func__);
1113 sc->sc_stats.ast_tx_qstop++;
1114 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1115 break;
1116 }
1117 /*
1118 * Poll the management queue for frames; they
1119 * have priority over normal data frames.
1120 */
1121 IF_DEQUEUE(&ic->ic_mgtq, m);
1122 if (m == NULL) {
1123 /*
1124 * No data frames go out unless we're associated.
1125 */
1126 if (ic->ic_state != IEEE80211_S_RUN) {
1127 DPRINTF(sc, ATH_DEBUG_ANY,
1128 "%s: ignore data packet, state %u\n",
1129 __func__, ic->ic_state);
1130 sc->sc_stats.ast_tx_discard++;
1131 ATH_TXBUF_LOCK(sc);
1132 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1133 ATH_TXBUF_UNLOCK(sc);
1134 break;
1135 }
1136 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1137 if (m == NULL) {
1138 ATH_TXBUF_LOCK(sc);
1139 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1140 ATH_TXBUF_UNLOCK(sc);
1141 break;
1142 }
1143 /*
1144 * Find the node for the destination so we can do
1145 * things like power save and fast frames aggregation.
1146 */
1147 if (m->m_len < sizeof(struct ether_header) &&
1148 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1149 ic->ic_stats.is_tx_nobuf++; /* XXX */
1150 ni = NULL;
1151 goto bad;
1152 }
1153 eh = mtod(m, struct ether_header *);
1154 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1155 if (ni == NULL) {
1156 /* NB: ieee80211_find_txnode does stat+msg */
1157 m_freem(m);
1158 goto bad;
1159 }
1160 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1161 (m->m_flags & M_PWR_SAV) == 0) {
1162 /*
1163 * Station in power save mode; pass the frame
1164 * to the 802.11 layer and continue. We'll get
1165 * the frame back when the time is right.
1166 */
1167 ieee80211_pwrsave(ic, ni, m);
1168 goto reclaim;
1169 }
1170 /* calculate priority so we can find the tx queue */
1171 if (ieee80211_classify(ic, m, ni)) {
1172 DPRINTF(sc, ATH_DEBUG_XMIT,
1173 "%s: discard, classification failure\n",
1174 __func__);
1175 m_freem(m);
1176 goto bad;
1177 }
1178 ifp->if_opackets++;
1179 BPF_MTAP(ifp, m);
1180 /*
1181 * Encapsulate the packet in prep for transmission.
1182 */
1183 m = ieee80211_encap(ic, m, ni);
1184 if (m == NULL) {
1185 DPRINTF(sc, ATH_DEBUG_ANY,
1186 "%s: encapsulation failure\n",
1187 __func__);
1188 sc->sc_stats.ast_tx_encap++;
1189 goto bad;
1190 }
1191 } else {
1192 /*
1193 * Hack! The referenced node pointer is in the
1194 * rcvif field of the packet header. This is
1195 * placed there by ieee80211_mgmt_output because
1196 * we need to hold the reference with the frame
1197 * and there's no other way (other than packet
1198 * tags which we consider too expensive to use)
1199 * to pass it along.
1200 */
1201 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1202 m->m_pkthdr.rcvif = NULL;
1203
1204 wh = mtod(m, struct ieee80211_frame *);
1205 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1206 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1207 /* fill time stamp */
1208 u_int64_t tsf;
1209 u_int32_t *tstamp;
1210
1211 tsf = ath_hal_gettsf64(ah);
1212 /* XXX: adjust 100us delay to xmit */
1213 tsf += 100;
1214 tstamp = (u_int32_t *)&wh[1];
1215 tstamp[0] = htole32(tsf & 0xffffffff);
1216 tstamp[1] = htole32(tsf >> 32);
1217 }
1218 sc->sc_stats.ast_tx_mgmt++;
1219 }
1220
1221 if (ath_tx_start(sc, ni, bf, m)) {
1222 bad:
1223 ifp->if_oerrors++;
1224 reclaim:
1225 ATH_TXBUF_LOCK(sc);
1226 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1227 ATH_TXBUF_UNLOCK(sc);
1228 if (ni != NULL)
1229 ieee80211_free_node(ni);
1230 continue;
1231 }
1232
1233 sc->sc_tx_timer = 5;
1234 ifp->if_timer = 1;
1235 }
1236}
1237
1238static int
1239ath_media_change(struct ifnet *ifp)
1240{
1241#define IS_UP(ifp) \
1242 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1243 int error;
1244
1245 error = ieee80211_media_change(ifp);
1246 if (error == ENETRESET) {
1247 struct ath_softc *sc = ifp->if_softc;
1248 struct ieee80211com *ic = &sc->sc_ic;
1249
1250 if (ic->ic_opmode == IEEE80211_M_AHDEMO) {
1251 /*
1252 * Adhoc demo mode is just ibss mode w/o beacons
1253 * (mostly). The hal knows nothing about it;
1254 * tell it we're operating in ibss mode.
1255 */
1256 sc->sc_opmode = HAL_M_IBSS;
1257 } else
1258 sc->sc_opmode = ic->ic_opmode;
1259 if (IS_UP(ifp))
1260 ath_init(ifp->if_softc); /* XXX lose error */
1261 error = 0;
1262 }
1263 return error;
1264#undef IS_UP
1265}
1266
1267#ifdef AR_DEBUG
1268static void
1269ath_keyprint(const char *tag, u_int ix,
1270 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1271{
1272 static const char *ciphers[] = {
1273 "WEP",
1274 "AES-OCB",
1275 "AES-CCM",
1276 "CKIP",
1277 "TKIP",
1278 "CLR",
1279 };
1280 int i, n;
1281
1282 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1283 for (i = 0, n = hk->kv_len; i < n; i++)
1284 printf("%02x", hk->kv_val[i]);
1285 printf(" mac %s", ether_sprintf(mac));
1286 if (hk->kv_type == HAL_CIPHER_TKIP) {
1287 printf(" mic ");
1288 for (i = 0; i < sizeof(hk->kv_mic); i++)
1289 printf("%02x", hk->kv_mic[i]);
1290 }
1291 printf("\n");
1292}
1293#endif
1294
1295/*
1296 * Set a TKIP key into the hardware. This handles the
1297 * potential distribution of key state to multiple key
1298 * cache slots for TKIP.
1299 */
1300static int
1301ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1302 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1303{
1304#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1305 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1306 struct ath_hal *ah = sc->sc_ah;
1307
1308 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1309 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1310 KASSERT(sc->sc_splitmic, ("key cache !split"));
1311 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1312 /*
1313 * TX key goes at first index, RX key at the rx index.
1314 * The hal handles the MIC keys at index+64.
1315 */
1316 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1317 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1318 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1319 return 0;
1320
1321 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1322 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1323 /* XXX delete tx key on failure? */
1324 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1325 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1326 /*
1327 * TX/RX key goes at first index.
1328 * The hal handles the MIC keys are index+64.
1329 */
1330 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1331 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1332 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1333 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1334 }
1335 return 0;
1336#undef IEEE80211_KEY_XR
1337}
1338
1339/*
1340 * Set a net80211 key into the hardware. This handles the
1341 * potential distribution of key state to multiple key
1342 * cache slots for TKIP with hardware MIC support.
1343 */
1344static int
1345ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1346 const u_int8_t mac0[IEEE80211_ADDR_LEN],
1347 struct ieee80211_node *bss)
1348{
1349#define N(a) (sizeof(a)/sizeof(a[0]))
1350 static const u_int8_t ciphermap[] = {
1351 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1352 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1353 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1354 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1355 (u_int8_t) -1, /* 4 is not allocated */
1356 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1357 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1358 };
1359 struct ath_hal *ah = sc->sc_ah;
1360 const struct ieee80211_cipher *cip = k->wk_cipher;
1361 u_int8_t gmac[IEEE80211_ADDR_LEN];
1362 const u_int8_t *mac;
1363 HAL_KEYVAL hk;
1364
1365 memset(&hk, 0, sizeof(hk));
1366 /*
1367 * Software crypto uses a "clear key" so non-crypto
1368 * state kept in the key cache are maintained and
1369 * so that rx frames have an entry to match.
1370 */
1371 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1372 KASSERT(cip->ic_cipher < N(ciphermap),
1373 ("invalid cipher type %u", cip->ic_cipher));
1374 hk.kv_type = ciphermap[cip->ic_cipher];
1375 hk.kv_len = k->wk_keylen;
1376 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1377 } else
1378 hk.kv_type = HAL_CIPHER_CLR;
1379
1380 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1381 /*
1382 * Group keys on hardware that supports multicast frame
1383 * key search use a mac that is the sender's address with
1384 * the high bit set instead of the app-specified address.
1385 */
1386 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1387 gmac[0] |= 0x80;
1388 mac = gmac;
1389 } else
1390 mac = mac0;
1391
1392 if (hk.kv_type == HAL_CIPHER_TKIP &&
1393 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1394 sc->sc_splitmic) {
1395 return ath_keyset_tkip(sc, k, &hk, mac);
1396 } else {
1397 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1398 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1399 }
1400#undef N
1401}
1402
1403/*
1404 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1405 * each key, one for decrypt/encrypt and the other for the MIC.
1406 */
1407static u_int16_t
1408key_alloc_2pair(struct ath_softc *sc,
1409 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1410{
1411#define N(a) (sizeof(a)/sizeof(a[0]))
1412 u_int i, keyix;
1413
1414 KASSERT(sc->sc_splitmic, ("key cache !split"));
1415 /* XXX could optimize */
1416 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1417 u_int8_t b = sc->sc_keymap[i];
1418 if (b != 0xff) {
1419 /*
1420 * One or more slots in this byte are free.
1421 */
1422 keyix = i*NBBY;
1423 while (b & 1) {
1424 again:
1425 keyix++;
1426 b >>= 1;
1427 }
1428 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1429 if (isset(sc->sc_keymap, keyix+32) ||
1430 isset(sc->sc_keymap, keyix+64) ||
1431 isset(sc->sc_keymap, keyix+32+64)) {
1432 /* full pair unavailable */
1433 /* XXX statistic */
1434 if (keyix == (i+1)*NBBY) {
1435 /* no slots were appropriate, advance */
1436 continue;
1437 }
1438 goto again;
1439 }
1440 setbit(sc->sc_keymap, keyix);
1441 setbit(sc->sc_keymap, keyix+64);
1442 setbit(sc->sc_keymap, keyix+32);
1443 setbit(sc->sc_keymap, keyix+32+64);
1444 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1445 "%s: key pair %u,%u %u,%u\n",
1446 __func__, keyix, keyix+64,
1447 keyix+32, keyix+32+64);
1448 *txkeyix = keyix;
1449 *rxkeyix = keyix+32;
1450 return 1;
1451 }
1452 }
1453 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1454 return 0;
1455#undef N
1456}
1457
1458/*
1459 * Allocate a single key cache slot.
1460 */
1461static int
1462key_alloc_single(struct ath_softc *sc,
1463 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1464{
1465#define N(a) (sizeof(a)/sizeof(a[0]))
1466 u_int i, keyix;
1467
1468 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1469 for (i = 0; i < N(sc->sc_keymap); i++) {
1470 u_int8_t b = sc->sc_keymap[i];
1471 if (b != 0xff) {
1472 /*
1473 * One or more slots are free.
1474 */
1475 keyix = i*NBBY;
1476 while (b & 1)
1477 keyix++, b >>= 1;
1478 setbit(sc->sc_keymap, keyix);
1479 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1480 __func__, keyix);
1481 *txkeyix = *rxkeyix = keyix;
1482 return 1;
1483 }
1484 }
1485 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1486 return 0;
1487#undef N
1488}
1489
1490/*
1491 * Allocate one or more key cache slots for a uniacst key. The
1492 * key itself is needed only to identify the cipher. For hardware
1493 * TKIP with split cipher+MIC keys we allocate two key cache slot
1494 * pairs so that we can setup separate TX and RX MIC keys. Note
1495 * that the MIC key for a TKIP key at slot i is assumed by the
1496 * hardware to be at slot i+64. This limits TKIP keys to the first
1497 * 64 entries.
1498 */
1499static int
1500ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
1501 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
1502{
1503 struct ath_softc *sc = ic->ic_ifp->if_softc;
1504
1505 /*
1506 * Group key allocation must be handled specially for
1507 * parts that do not support multicast key cache search
1508 * functionality. For those parts the key id must match
1509 * the h/w key index so lookups find the right key. On
1510 * parts w/ the key search facility we install the sender's
1511 * mac address (with the high bit set) and let the hardware
1512 * find the key w/o using the key id. This is preferred as
1513 * it permits us to support multiple users for adhoc and/or
1514 * multi-station operation.
1515 */
1516 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1517 if (!(&ic->ic_nw_keys[0] <= k &&
1518 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1519 /* should not happen */
1520 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1521 "%s: bogus group key\n", __func__);
1522 return 0;
1523 }
1524 /*
1525 * XXX we pre-allocate the global keys so
1526 * have no way to check if they've already been allocated.
1527 */
1528 *keyix = *rxkeyix = k - ic->ic_nw_keys;
1529 return 1;
1530 }
1531
1532 /*
1533 * We allocate two pair for TKIP when using the h/w to do
1534 * the MIC. For everything else, including software crypto,
1535 * we allocate a single entry. Note that s/w crypto requires
1536 * a pass-through slot on the 5211 and 5212. The 5210 does
1537 * not support pass-through cache entries and we map all
1538 * those requests to slot 0.
1539 */
1540 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1541 return key_alloc_single(sc, keyix, rxkeyix);
1542 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1543 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1544 return key_alloc_2pair(sc, keyix, rxkeyix);
1545 } else {
1546 return key_alloc_single(sc, keyix, rxkeyix);
1547 }
1548}
1549
1550/*
1551 * Delete an entry in the key cache allocated by ath_key_alloc.
1552 */
1553static int
1554ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1555{
1556 struct ath_softc *sc = ic->ic_ifp->if_softc;
1557 struct ath_hal *ah = sc->sc_ah;
1558 const struct ieee80211_cipher *cip = k->wk_cipher;
1559 u_int keyix = k->wk_keyix;
1560
1561 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1562
1563 ath_hal_keyreset(ah, keyix);
1564 /*
1565 * Handle split tx/rx keying required for TKIP with h/w MIC.
1566 */
1567 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1568 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
1569 ath_hal_keyreset(ah, keyix+32); /* RX key */
1570 if (keyix >= IEEE80211_WEP_NKID) {
1571 /*
1572 * Don't touch keymap entries for global keys so
1573 * they are never considered for dynamic allocation.
1574 */
1575 clrbit(sc->sc_keymap, keyix);
1576 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1577 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1578 sc->sc_splitmic) {
1579 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1580 clrbit(sc->sc_keymap, keyix+32); /* RX key */
1581 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */
1582 }
1583 }
1584 return 1;
1585}
1586
1587/*
1588 * Set the key cache contents for the specified key. Key cache
1589 * slot(s) must already have been allocated by ath_key_alloc.
1590 */
1591static int
1592ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1593 const u_int8_t mac[IEEE80211_ADDR_LEN])
1594{
1595 struct ath_softc *sc = ic->ic_ifp->if_softc;
1596
1597 return ath_keyset(sc, k, mac, ic->ic_bss);
1598}
1599
1600/*
1601 * Block/unblock tx+rx processing while a key change is done.
1602 * We assume the caller serializes key management operations
1603 * so we only need to worry about synchronization with other
1604 * uses that originate in the driver.
1605 */
1606static void
1607ath_key_update_begin(struct ieee80211com *ic)
1608{
1609 struct ifnet *ifp = ic->ic_ifp;
1610 struct ath_softc *sc = ifp->if_softc;
1611
1612 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1613#if 0
1614 tasklet_disable(&sc->sc_rxtq);
1615#endif
1616 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1617}
1618
1619static void
1620ath_key_update_end(struct ieee80211com *ic)
1621{
1622 struct ifnet *ifp = ic->ic_ifp;
1623 struct ath_softc *sc = ifp->if_softc;
1624
1625 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1626 IF_UNLOCK(&ifp->if_snd);
1627#if 0
1628 tasklet_enable(&sc->sc_rxtq);
1629#endif
1630}
1631
1632/*
1633 * Calculate the receive filter according to the
1634 * operating mode and state:
1635 *
1636 * o always accept unicast, broadcast, and multicast traffic
1637 * o maintain current state of phy error reception (the hal
1638 * may enable phy error frames for noise immunity work)
1639 * o probe request frames are accepted only when operating in
1640 * hostap, adhoc, or monitor modes
1641 * o enable promiscuous mode according to the interface state
1642 * o accept beacons:
1643 * - when operating in adhoc mode so the 802.11 layer creates
1644 * node table entries for peers,
1645 * - when operating in station mode for collecting rssi data when
1646 * the station is otherwise quiet, or
1647 * - when scanning
1648 */
1649static u_int32_t
1650ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1651{
1652 struct ieee80211com *ic = &sc->sc_ic;
1653 struct ath_hal *ah = sc->sc_ah;
1654 struct ifnet *ifp = sc->sc_ifp;
1655 u_int32_t rfilt;
1656
1657 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR)
1658 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1659 if (ic->ic_opmode != IEEE80211_M_STA)
1660 rfilt |= HAL_RX_FILTER_PROBEREQ;
1661 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1662 (ifp->if_flags & IFF_PROMISC))
1663 rfilt |= HAL_RX_FILTER_PROM;
1664 if (ic->ic_opmode == IEEE80211_M_STA ||
1665 ic->ic_opmode == IEEE80211_M_IBSS ||
1666 state == IEEE80211_S_SCAN)
1667 rfilt |= HAL_RX_FILTER_BEACON;
1668 return rfilt;
1669}
1670
1671static void
1672ath_mode_init(struct ath_softc *sc)
1673{
1674 struct ieee80211com *ic = &sc->sc_ic;
1675 struct ath_hal *ah = sc->sc_ah;
1676 struct ifnet *ifp = sc->sc_ifp;
1677 u_int32_t rfilt, mfilt[2], val;
1678 u_int8_t pos;
1679 struct ifmultiaddr *ifma;
1680
1681 /* configure rx filter */
1682 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1683 ath_hal_setrxfilter(ah, rfilt);
1684
1685 /* configure operational mode */
1686 ath_hal_setopmode(ah);
1687
1688 /*
1689 * Handle any link-level address change. Note that we only
1690 * need to force ic_myaddr; any other addresses are handled
1691 * as a byproduct of the ifnet code marking the interface
1692 * down then up.
1693 *
1694 * XXX should get from lladdr instead of arpcom but that's more work
1695 */
1696 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1697 ath_hal_setmac(ah, ic->ic_myaddr);
1698
1699 /* calculate and install multicast filter */
1700 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1701 mfilt[0] = mfilt[1] = 0;
1702 IF_ADDR_LOCK(ifp);
1703 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1704 caddr_t dl;
1705
1706 /* calculate XOR of eight 6bit values */
1707 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1708 val = LE_READ_4(dl + 0);
1709 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1710 val = LE_READ_4(dl + 3);
1711 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1712 pos &= 0x3f;
1713 mfilt[pos / 32] |= (1 << (pos % 32));
1714 }
1715 IF_ADDR_UNLOCK(ifp);
1716 } else {
1717 mfilt[0] = mfilt[1] = ~0;
1718 }
1719 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1720 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1721 __func__, rfilt, mfilt[0], mfilt[1]);
1722}
1723
1724/*
1725 * Set the slot time based on the current setting.
1726 */
1727static void
1728ath_setslottime(struct ath_softc *sc)
1729{
1730 struct ieee80211com *ic = &sc->sc_ic;
1731 struct ath_hal *ah = sc->sc_ah;
1732
1733 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1734 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1735 else
1736 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1737 sc->sc_updateslot = OK;
1738}
1739
1740/*
1741 * Callback from the 802.11 layer to update the
1742 * slot time based on the current setting.
1743 */
1744static void
1745ath_updateslot(struct ifnet *ifp)
1746{
1747 struct ath_softc *sc = ifp->if_softc;
1748 struct ieee80211com *ic = &sc->sc_ic;
1749
1750 /*
1751 * When not coordinating the BSS, change the hardware
1752 * immediately. For other operation we defer the change
1753 * until beacon updates have propagated to the stations.
1754 */
1755 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1756 sc->sc_updateslot = UPDATE;
1757 else
1758 ath_setslottime(sc);
1759}
1760
1761/*
1762 * Setup a h/w transmit queue for beacons.
1763 */
1764static int
1765ath_beaconq_setup(struct ath_hal *ah)
1766{
1767 HAL_TXQ_INFO qi;
1768
1769 memset(&qi, 0, sizeof(qi));
1770 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1771 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1772 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1773 /* NB: for dynamic turbo, don't enable any other interrupts */
1774 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1775 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1776}
1777
1778/*
1779 * Setup the transmit queue parameters for the beacon queue.
1780 */
1781static int
1782ath_beaconq_config(struct ath_softc *sc)
1783{
1784#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1785 struct ieee80211com *ic = &sc->sc_ic;
1786 struct ath_hal *ah = sc->sc_ah;
1787 HAL_TXQ_INFO qi;
1788
1789 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1790 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1791 /*
1792 * Always burst out beacon and CAB traffic.
1793 */
1794 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1795 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1796 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1797 } else {
1798 struct wmeParams *wmep =
1799 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1800 /*
1801 * Adhoc mode; important thing is to use 2x cwmin.
1802 */
1803 qi.tqi_aifs = wmep->wmep_aifsn;
1804 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1805 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1806 }
1807
1808 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1809 device_printf(sc->sc_dev, "unable to update parameters for "
1810 "beacon hardware queue!\n");
1811 return 0;
1812 } else {
1813 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1814 return 1;
1815 }
1816#undef ATH_EXPONENT_TO_VALUE
1817}
1818
1819/*
1820 * Allocate and setup an initial beacon frame.
1821 */
1822static int
1823ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1824{
1825 struct ieee80211com *ic = ni->ni_ic;
1826 struct ath_buf *bf;
1827 struct mbuf *m;
1828 int error;
1829
1830 bf = STAILQ_FIRST(&sc->sc_bbuf);
1831 if (bf == NULL) {
1832 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
1833 sc->sc_stats.ast_be_nombuf++; /* XXX */
1834 return ENOMEM; /* XXX */
1835 }
1836 /*
1837 * NB: the beacon data buffer must be 32-bit aligned;
1838 * we assume the mbuf routines will return us something
1839 * with this alignment (perhaps should assert).
1840 */
1841 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
1842 if (m == NULL) {
1843 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
1844 __func__);
1845 sc->sc_stats.ast_be_nombuf++;
1846 return ENOMEM;
1847 }
1848 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1849 bf->bf_segs, &bf->bf_nseg,
1850 BUS_DMA_NOWAIT);
1851 if (error == 0) {
1852 bf->bf_m = m;
1853 bf->bf_node = ieee80211_ref_node(ni);
1854 } else {
1855 m_freem(m);
1856 }
1857 return error;
1858}
1859
1860/*
1861 * Setup the beacon frame for transmit.
1862 */
1863static void
1864ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
1865{
1866#define USE_SHPREAMBLE(_ic) \
1867 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
1868 == IEEE80211_F_SHPREAMBLE)
1869 struct ieee80211_node *ni = bf->bf_node;
1870 struct ieee80211com *ic = ni->ni_ic;
1871 struct mbuf *m = bf->bf_m;
1872 struct ath_hal *ah = sc->sc_ah;
1873 struct ath_desc *ds;
1874 int flags, antenna;
1875 const HAL_RATE_TABLE *rt;
1876 u_int8_t rix, rate;
1877
1878 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
1879 __func__, m, m->m_len);
1880
1881 /* setup descriptors */
1882 ds = bf->bf_desc;
1883
1884 flags = HAL_TXDESC_NOACK;
1885 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
1886 ds->ds_link = bf->bf_daddr; /* self-linked */
1887 flags |= HAL_TXDESC_VEOL;
1888 /*
1889 * Let hardware handle antenna switching.
1890 */
1891 antenna = sc->sc_txantenna;
1892 } else {
1893 ds->ds_link = 0;
1894 /*
1895 * Switch antenna every 4 beacons.
1896 * XXX assumes two antenna
1897 */
1898 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
1899 }
1900
1901 KASSERT(bf->bf_nseg == 1,
1902 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
1903 ds->ds_data = bf->bf_segs[0].ds_addr;
1904 /*
1905 * Calculate rate code.
1906 * XXX everything at min xmit rate
1907 */
1908 rix = sc->sc_minrateix;
1909 rt = sc->sc_currates;
1910 rate = rt->info[rix].rateCode;
1911 if (USE_SHPREAMBLE(ic))
1912 rate |= rt->info[rix].shortPreamble;
1913 ath_hal_setuptxdesc(ah, ds
1914 , m->m_len + IEEE80211_CRC_LEN /* frame length */
1915 , sizeof(struct ieee80211_frame)/* header length */
1916 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
1917 , ni->ni_txpower /* txpower XXX */
1918 , rate, 1 /* series 0 rate/tries */
1919 , HAL_TXKEYIX_INVALID /* no encryption */
1920 , antenna /* antenna mode */
1921 , flags /* no ack, veol for beacons */
1922 , 0 /* rts/cts rate */
1923 , 0 /* rts/cts duration */
1924 );
1925 /* NB: beacon's BufLen must be a multiple of 4 bytes */
1926 ath_hal_filltxdesc(ah, ds
1927 , roundup(m->m_len, 4) /* buffer length */
1928 , AH_TRUE /* first segment */
1929 , AH_TRUE /* last segment */
1930 , ds /* first descriptor */
1931 );
1932#undef USE_SHPREAMBLE
1933}
1934
1935/*
1936 * Transmit a beacon frame at SWBA. Dynamic updates to the
1937 * frame contents are done as needed and the slot time is
1938 * also adjusted based on current state.
1939 */
1940static void
1941ath_beacon_proc(void *arg, int pending)
1942{
1943 struct ath_softc *sc = arg;
1944 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
1945 struct ieee80211_node *ni = bf->bf_node;
1946 struct ieee80211com *ic = ni->ni_ic;
1947 struct ath_hal *ah = sc->sc_ah;
1948 struct mbuf *m;
1949 int ncabq, error, otherant;
1950
1951 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
1952 __func__, pending);
1953
1954 if (ic->ic_opmode == IEEE80211_M_STA ||
1955 ic->ic_opmode == IEEE80211_M_MONITOR ||
1956 bf == NULL || bf->bf_m == NULL) {
1957 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
1958 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
1959 return;
1960 }
1961 /*
1962 * Check if the previous beacon has gone out. If
1963 * not don't don't try to post another, skip this
1964 * period and wait for the next. Missed beacons
1965 * indicate a problem and should not occur. If we
1966 * miss too many consecutive beacons reset the device.
1967 */
1968 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
1969 sc->sc_bmisscount++;
1970 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
1971 "%s: missed %u consecutive beacons\n",
1972 __func__, sc->sc_bmisscount);
1973 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
1974 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
1975 return;
1976 }
1977 if (sc->sc_bmisscount != 0) {
1978 DPRINTF(sc, ATH_DEBUG_BEACON,
1979 "%s: resume beacon xmit after %u misses\n",
1980 __func__, sc->sc_bmisscount);
1981 sc->sc_bmisscount = 0;
1982 }
1983
1984 /*
1985 * Update dynamic beacon contents. If this returns
1986 * non-zero then we need to remap the memory because
1987 * the beacon frame changed size (probably because
1988 * of the TIM bitmap).
1989 */
1990 m = bf->bf_m;
1991 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum);
1992 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) {
1993 /* XXX too conservative? */
1994 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1995 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1996 bf->bf_segs, &bf->bf_nseg,
1997 BUS_DMA_NOWAIT);
1998 if (error != 0) {
1999 if_printf(ic->ic_ifp,
2000 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
2001 __func__, error);
2002 return;
2003 }
2004 }
2005
2006 /*
2007 * Handle slot time change when a non-ERP station joins/leaves
2008 * an 11g network. The 802.11 layer notifies us via callback,
2009 * we mark updateslot, then wait one beacon before effecting
2010 * the change. This gives associated stations at least one
2011 * beacon interval to note the state change.
2012 */
2013 /* XXX locking */
2014 if (sc->sc_updateslot == UPDATE)
2015 sc->sc_updateslot = COMMIT; /* commit next beacon */
2016 else if (sc->sc_updateslot == COMMIT)
2017 ath_setslottime(sc); /* commit change to h/w */
2018
2019 /*
2020 * Check recent per-antenna transmit statistics and flip
2021 * the default antenna if noticeably more frames went out
2022 * on the non-default antenna.
2023 * XXX assumes 2 anntenae
2024 */
2025 otherant = sc->sc_defant & 1 ? 2 : 1;
2026 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2027 ath_setdefantenna(sc, otherant);
2028 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2029
2030 /*
2031 * Construct tx descriptor.
2032 */
2033 ath_beacon_setup(sc, bf);
2034
2035 /*
2036 * Stop any current dma and put the new frame on the queue.
2037 * This should never fail since we check above that no frames
2038 * are still pending on the queue.
2039 */
2040 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2041 DPRINTF(sc, ATH_DEBUG_ANY,
2042 "%s: beacon queue %u did not stop?\n",
2043 __func__, sc->sc_bhalq);
2044 }
2045 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2046
2047 /*
2048 * Enable the CAB queue before the beacon queue to
2049 * insure cab frames are triggered by this beacon.
2050 */
2051 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */
2052 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum);
2053 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2054 ath_hal_txstart(ah, sc->sc_bhalq);
2055 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2056 "%s: TXDP[%u] = %p (%p)\n", __func__,
2057 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2058
2059 sc->sc_stats.ast_be_xmit++;
2060}
2061
2062/*
2063 * Reset the hardware after detecting beacons have stopped.
2064 */
2065static void
2066ath_bstuck_proc(void *arg, int pending)
2067{
2068 struct ath_softc *sc = arg;
2069 struct ifnet *ifp = sc->sc_ifp;
2070
2071 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2072 sc->sc_bmisscount);
2073 ath_reset(ifp);
2074}
2075
2076/*
2077 * Reclaim beacon resources.
2078 */
2079static void
2080ath_beacon_free(struct ath_softc *sc)
2081{
2082 struct ath_buf *bf;
2083
2084 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2085 if (bf->bf_m != NULL) {
2086 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2087 m_freem(bf->bf_m);
2088 bf->bf_m = NULL;
2089 }
2090 if (bf->bf_node != NULL) {
2091 ieee80211_free_node(bf->bf_node);
2092 bf->bf_node = NULL;
2093 }
2094 }
2095}
2096
2097/*
2098 * Configure the beacon and sleep timers.
2099 *
2100 * When operating as an AP this resets the TSF and sets
2101 * up the hardware to notify us when we need to issue beacons.
2102 *
2103 * When operating in station mode this sets up the beacon
2104 * timers according to the timestamp of the last received
2105 * beacon and the current TSF, configures PCF and DTIM
2106 * handling, programs the sleep registers so the hardware
2107 * will wakeup in time to receive beacons, and configures
2108 * the beacon miss handling so we'll receive a BMISS
2109 * interrupt when we stop seeing beacons from the AP
2110 * we've associated with.
2111 */
2112static void
2113ath_beacon_config(struct ath_softc *sc)
2114{
2115#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10))
2116 struct ath_hal *ah = sc->sc_ah;
2117 struct ieee80211com *ic = &sc->sc_ic;
2118 struct ieee80211_node *ni = ic->ic_bss;
2119 u_int32_t nexttbtt, intval;
2120
2121 /* extract tstamp from last beacon and convert to TU */
2122 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2123 LE_READ_4(ni->ni_tstamp.data));
2124 /* NB: the beacon interval is kept internally in TU's */
2125 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2126 if (nexttbtt == 0) /* e.g. for ap mode */
2127 nexttbtt = intval;
2128 else if (intval) /* NB: can be 0 for monitor mode */
2129 nexttbtt = roundup(nexttbtt, intval);
2130 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2131 __func__, nexttbtt, intval, ni->ni_intval);
2132 if (ic->ic_opmode == IEEE80211_M_STA) {
2133 HAL_BEACON_STATE bs;
2134 u_int64_t tsf;
2135 u_int32_t tsftu;
2136 int dtimperiod, dtimcount;
2137 int cfpperiod, cfpcount;
2138
2139 /*
2140 * Setup dtim and cfp parameters according to
2141 * last beacon we received (which may be none).
2142 */
2143 dtimperiod = ni->ni_dtim_period;
2144 if (dtimperiod <= 0) /* NB: 0 if not known */
2145 dtimperiod = 1;
2146 dtimcount = ni->ni_dtim_count;
2147 if (dtimcount >= dtimperiod) /* NB: sanity check */
2148 dtimcount = 0; /* XXX? */
2149 cfpperiod = 1; /* NB: no PCF support yet */
2150 cfpcount = 0;
2151#define FUDGE 2
2152 /*
2153 * Pull nexttbtt forward to reflect the current
2154 * TSF and calculate dtim+cfp state for the result.
2155 */
2156 tsf = ath_hal_gettsf64(ah);
2157 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE;
2158 do {
2159 nexttbtt += intval;
2160 if (--dtimcount < 0) {
2161 dtimcount = dtimperiod - 1;
2162 if (--cfpcount < 0)
2163 cfpcount = cfpperiod - 1;
2164 }
2165 } while (nexttbtt < tsftu);
2166#undef FUDGE
2167 memset(&bs, 0, sizeof(bs));
2168 bs.bs_intval = intval;
2169 bs.bs_nexttbtt = nexttbtt;
2170 bs.bs_dtimperiod = dtimperiod*intval;
2171 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2172 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2173 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2174 bs.bs_cfpmaxduration = 0;
2175#if 0
2176 /*
2177 * The 802.11 layer records the offset to the DTIM
2178 * bitmap while receiving beacons; use it here to
2179 * enable h/w detection of our AID being marked in
2180 * the bitmap vector (to indicate frames for us are
2181 * pending at the AP).
2182 * XXX do DTIM handling in s/w to WAR old h/w bugs
2183 * XXX enable based on h/w rev for newer chips
2184 */
2185 bs.bs_timoffset = ni->ni_timoff;
2186#endif
2187 /*
2188 * Calculate the number of consecutive beacons to miss
2189 * before taking a BMISS interrupt. The configuration
2190 * is specified in ms, so we need to convert that to
2191 * TU's and then calculate based on the beacon interval.
2192 * Note that we clamp the result to at most 10 beacons.
2193 */
2194 bs.bs_bmissthreshold = ic->ic_bmissthreshold;
2195 if (bs.bs_bmissthreshold > 10)
2196 bs.bs_bmissthreshold = 10;
2197 else if (bs.bs_bmissthreshold <= 0)
2198 bs.bs_bmissthreshold = 1;
2199
2200 /*
2201 * Calculate sleep duration. The configuration is
2202 * given in ms. We insure a multiple of the beacon
2203 * period is used. Also, if the sleep duration is
2204 * greater than the DTIM period then it makes senses
2205 * to make it a multiple of that.
2206 *
2207 * XXX fixed at 100ms
2208 */
2209 bs.bs_sleepduration =
2210 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2211 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2212 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2213
2214 DPRINTF(sc, ATH_DEBUG_BEACON,
2215 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2216 , __func__
2217 , tsf, tsftu
2218 , bs.bs_intval
2219 , bs.bs_nexttbtt
2220 , bs.bs_dtimperiod
2221 , bs.bs_nextdtim
2222 , bs.bs_bmissthreshold
2223 , bs.bs_sleepduration
2224 , bs.bs_cfpperiod
2225 , bs.bs_cfpmaxduration
2226 , bs.bs_cfpnext
2227 , bs.bs_timoffset
2228 );
2229 ath_hal_intrset(ah, 0);
2230 ath_hal_beacontimers(ah, &bs);
2231 sc->sc_imask |= HAL_INT_BMISS;
2232 ath_hal_intrset(ah, sc->sc_imask);
2233 } else {
2234 ath_hal_intrset(ah, 0);
2235 if (nexttbtt == intval)
2236 intval |= HAL_BEACON_RESET_TSF;
2237 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2238 /*
2239 * In IBSS mode enable the beacon timers but only
2240 * enable SWBA interrupts if we need to manually
2241 * prepare beacon frames. Otherwise we use a
2242 * self-linked tx descriptor and let the hardware
2243 * deal with things.
2244 */
2245 intval |= HAL_BEACON_ENA;
2246 if (!sc->sc_hasveol)
2247 sc->sc_imask |= HAL_INT_SWBA;
2248 ath_beaconq_config(sc);
2249 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2250 /*
2251 * In AP mode we enable the beacon timers and
2252 * SWBA interrupts to prepare beacon frames.
2253 */
2254 intval |= HAL_BEACON_ENA;
2255 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2256 ath_beaconq_config(sc);
2257 }
2258 ath_hal_beaconinit(ah, nexttbtt, intval);
2259 sc->sc_bmisscount = 0;
2260 ath_hal_intrset(ah, sc->sc_imask);
2261 /*
2262 * When using a self-linked beacon descriptor in
2263 * ibss mode load it once here.
2264 */
2265 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2266 ath_beacon_proc(sc, 0);
2267 }
2268#undef TSF_TO_TU
2269}
2270
2271static void
2272ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2273{
2274 bus_addr_t *paddr = (bus_addr_t*) arg;
2275 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2276 *paddr = segs->ds_addr;
2277}
2278
2279static int
2280ath_descdma_setup(struct ath_softc *sc,
2281 struct ath_descdma *dd, ath_bufhead *head,
2282 const char *name, int nbuf, int ndesc)
2283{
2284#define DS2PHYS(_dd, _ds) \
2285 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2286 struct ifnet *ifp = sc->sc_ifp;
2287 struct ath_desc *ds;
2288 struct ath_buf *bf;
2289 int i, bsize, error;
2290
2291 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2292 __func__, name, nbuf, ndesc);
2293
2294 dd->dd_name = name;
2295 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2296
2297 /*
2298 * Setup DMA descriptor area.
2299 */
2300 error = bus_dma_tag_create(NULL, /* parent */
2301 PAGE_SIZE, 0, /* alignment, bounds */
2302 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2303 BUS_SPACE_MAXADDR, /* highaddr */
2304 NULL, NULL, /* filter, filterarg */
2305 dd->dd_desc_len, /* maxsize */
2306 1, /* nsegments */
2307 BUS_SPACE_MAXADDR, /* maxsegsize */
2308 BUS_DMA_ALLOCNOW, /* flags */
2309 NULL, /* lockfunc */
2310 NULL, /* lockarg */
2311 &dd->dd_dmat);
2312 if (error != 0) {
2313 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2314 return error;
2315 }
2316
2317 /* allocate descriptors */
2318 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
2319 if (error != 0) {
2320 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2321 "error %u\n", dd->dd_name, error);
2322 goto fail0;
2323 }
2324
2325 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
2326 BUS_DMA_NOWAIT, &dd->dd_dmamap);
2327 if (error != 0) {
2328 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2329 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2330 goto fail1;
2331 }
2332
2333 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2334 dd->dd_desc, dd->dd_desc_len,
2335 ath_load_cb, &dd->dd_desc_paddr,
2336 BUS_DMA_NOWAIT);
2337 if (error != 0) {
2338 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2339 dd->dd_name, error);
2340 goto fail2;
2341 }
2342
2343 ds = dd->dd_desc;
2344 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2345 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2346 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2347
2348 /* allocate rx buffers */
2349 bsize = sizeof(struct ath_buf) * nbuf;
2350 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2351 if (bf == NULL) {
2352 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2353 dd->dd_name, bsize);
2354 goto fail3;
2355 }
2356 dd->dd_bufptr = bf;
2357
2358 STAILQ_INIT(head);
2359 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2360 bf->bf_desc = ds;
2361 bf->bf_daddr = DS2PHYS(dd, ds);
2362 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
2363 &bf->bf_dmamap);
2364 if (error != 0) {
2365 if_printf(ifp, "unable to create dmamap for %s "
2366 "buffer %u, error %u\n", dd->dd_name, i, error);
2367 ath_descdma_cleanup(sc, dd, head);
2368 return error;
2369 }
2370 STAILQ_INSERT_TAIL(head, bf, bf_list);
2371 }
2372 return 0;
2373fail3:
2374 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2375fail2:
2376 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2377fail1:
2378 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2379fail0:
2380 bus_dma_tag_destroy(dd->dd_dmat);
2381 memset(dd, 0, sizeof(*dd));
2382 return error;
2383#undef DS2PHYS
2384}
2385
2386static void
2387ath_descdma_cleanup(struct ath_softc *sc,
2388 struct ath_descdma *dd, ath_bufhead *head)
2389{
2390 struct ath_buf *bf;
2391 struct ieee80211_node *ni;
2392
2393 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2394 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2395 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2396 bus_dma_tag_destroy(dd->dd_dmat);
2397
2398 STAILQ_FOREACH(bf, head, bf_list) {
2399 if (bf->bf_m) {
2400 m_freem(bf->bf_m);
2401 bf->bf_m = NULL;
2402 }
2403 if (bf->bf_dmamap != NULL) {
2404 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2405 bf->bf_dmamap = NULL;
2406 }
2407 ni = bf->bf_node;
2408 bf->bf_node = NULL;
2409 if (ni != NULL) {
2410 /*
2411 * Reclaim node reference.
2412 */
2413 ieee80211_free_node(ni);
2414 }
2415 }
2416
2417 STAILQ_INIT(head);
2418 free(dd->dd_bufptr, M_ATHDEV);
2419 memset(dd, 0, sizeof(*dd));
2420}
2421
2422static int
2423ath_desc_alloc(struct ath_softc *sc)
2424{
2425 int error;
2426
2427 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2428 "rx", ath_rxbuf, 1);
2429 if (error != 0)
2430 return error;
2431
2432 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2433 "tx", ath_txbuf, ATH_TXDESC);
2434 if (error != 0) {
2435 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2436 return error;
2437 }
2438
2439 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2440 "beacon", 1, 1);
2441 if (error != 0) {
2442 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2443 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2444 return error;
2445 }
2446 return 0;
2447}
2448
2449static void
2450ath_desc_free(struct ath_softc *sc)
2451{
2452
2453 if (sc->sc_bdma.dd_desc_len != 0)
2454 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2455 if (sc->sc_txdma.dd_desc_len != 0)
2456 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2457 if (sc->sc_rxdma.dd_desc_len != 0)
2458 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2459}
2460
2461static struct ieee80211_node *
2462ath_node_alloc(struct ieee80211_node_table *nt)
2463{
2464 struct ieee80211com *ic = nt->nt_ic;
2465 struct ath_softc *sc = ic->ic_ifp->if_softc;
2466 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2467 struct ath_node *an;
2468
2469 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2470 if (an == NULL) {
2471 /* XXX stat+msg */
2472 return NULL;
2473 }
2474 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2475 ath_rate_node_init(sc, an);
2476
2477 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2478 return &an->an_node;
2479}
2480
2481static void
2482ath_node_free(struct ieee80211_node *ni)
2483{
2484 struct ieee80211com *ic = ni->ni_ic;
2485 struct ath_softc *sc = ic->ic_ifp->if_softc;
2486
2487 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2488
2489 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2490 sc->sc_node_free(ni);
2491}
2492
2493static u_int8_t
2494ath_node_getrssi(const struct ieee80211_node *ni)
2495{
2496#define HAL_EP_RND(x, mul) \
2497 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2498 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2499 int32_t rssi;
2500
2501 /*
2502 * When only one frame is received there will be no state in
2503 * avgrssi so fallback on the value recorded by the 802.11 layer.
2504 */
2505 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2506 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2507 else
2508 rssi = ni->ni_rssi;
2509 /* NB: theoretically we shouldn't need this, but be paranoid */
2510 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2511#undef HAL_EP_RND
2512}
2513
2514static int
2515ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2516{
2517 struct ath_hal *ah = sc->sc_ah;
2518 int error;
2519 struct mbuf *m;
2520 struct ath_desc *ds;
2521
2522 m = bf->bf_m;
2523 if (m == NULL) {
2524 /*
2525 * NB: by assigning a page to the rx dma buffer we
2526 * implicitly satisfy the Atheros requirement that
2527 * this buffer be cache-line-aligned and sized to be
2528 * multiple of the cache line size. Not doing this
2529 * causes weird stuff to happen (for the 5210 at least).
2530 */
2531 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2532 if (m == NULL) {
2533 DPRINTF(sc, ATH_DEBUG_ANY,
2534 "%s: no mbuf/cluster\n", __func__);
2535 sc->sc_stats.ast_rx_nombuf++;
2536 return ENOMEM;
2537 }
2538 bf->bf_m = m;
2539 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2540
2541 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
2542 bf->bf_dmamap, m,
2543 bf->bf_segs, &bf->bf_nseg,
2544 BUS_DMA_NOWAIT);
2545 if (error != 0) {
2546 DPRINTF(sc, ATH_DEBUG_ANY,
2547 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
2548 __func__, error);
2549 sc->sc_stats.ast_rx_busdma++;
2550 return error;
2551 }
2552 KASSERT(bf->bf_nseg == 1,
2553 ("multi-segment packet; nseg %u", bf->bf_nseg));
2554 }
2555 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2556
2557 /*
2558 * Setup descriptors. For receive we always terminate
2559 * the descriptor list with a self-linked entry so we'll
2560 * not get overrun under high load (as can happen with a
2561 * 5212 when ANI processing enables PHY error frames).
2562 *
2563 * To insure the last descriptor is self-linked we create
2564 * each descriptor as self-linked and add it to the end. As
2565 * each additional descriptor is added the previous self-linked
2566 * entry is ``fixed'' naturally. This should be safe even
2567 * if DMA is happening. When processing RX interrupts we
2568 * never remove/process the last, self-linked, entry on the
2569 * descriptor list. This insures the hardware always has
2570 * someplace to write a new frame.
2571 */
2572 ds = bf->bf_desc;
2573 ds->ds_link = bf->bf_daddr; /* link to self */
2574 ds->ds_data = bf->bf_segs[0].ds_addr;
2575 ath_hal_setuprxdesc(ah, ds
2576 , m->m_len /* buffer size */
2577 , 0
2578 );
2579
2580 if (sc->sc_rxlink != NULL)
2581 *sc->sc_rxlink = bf->bf_daddr;
2582 sc->sc_rxlink = &ds->ds_link;
2583 return 0;
2584}
2585
2586/*
2587 * Extend 15-bit time stamp from rx descriptor to
2588 * a full 64-bit TSF using the specified TSF.
2589 */
2590static __inline u_int64_t
2591ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
2592{
2593 if ((tsf & 0x7fff) < rstamp)
2594 tsf -= 0x8000;
2595 return ((tsf &~ 0x7fff) | rstamp);
2596}
2597
2598/*
2599 * Intercept management frames to collect beacon rssi data
2600 * and to do ibss merges.
2601 */
2602static void
2603ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2604 struct ieee80211_node *ni,
2605 int subtype, int rssi, u_int32_t rstamp)
2606{
2607 struct ath_softc *sc = ic->ic_ifp->if_softc;
2608
2609 /*
2610 * Call up first so subsequent work can use information
2611 * potentially stored in the node (e.g. for ibss merge).
2612 */
2613 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2614 switch (subtype) {
2615 case IEEE80211_FC0_SUBTYPE_BEACON:
2616 /* update rssi statistics for use by the hal */
2617 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
2618 /* fall thru... */
2619 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2620 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2621 ic->ic_state == IEEE80211_S_RUN) {
2622 u_int64_t tsf = ath_extend_tsf(rstamp,
2623 ath_hal_gettsf64(sc->sc_ah));
2624 /*
2625 * Handle ibss merge as needed; check the tsf on the
2626 * frame before attempting the merge. The 802.11 spec
2627 * says the station should change it's bssid to match
2628 * the oldest station with the same ssid, where oldest
2629 * is determined by the tsf. Note that hardware
2630 * reconfiguration happens through callback to
2631 * ath_newstate as the state machine will go from
2632 * RUN -> RUN when this happens.
2633 */
2634 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2635 DPRINTF(sc, ATH_DEBUG_STATE,
2636 "ibss merge, rstamp %u tsf %ju "
2637 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2638 (uintmax_t)ni->ni_tstamp.tsf);
2639 (void) ieee80211_ibss_merge(ni);
2640 }
2641 }
2642 break;
2643 }
2644}
2645
2646/*
2647 * Set the default antenna.
2648 */
2649static void
2650ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2651{
2652 struct ath_hal *ah = sc->sc_ah;
2653
2654 /* XXX block beacon interrupts */
2655 ath_hal_setdefantenna(ah, antenna);
2656 if (sc->sc_defant != antenna)
2657 sc->sc_stats.ast_ant_defswitch++;
2658 sc->sc_defant = antenna;
2659 sc->sc_rxotherant = 0;
2660}
2661
2662static int
2663ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2664 const struct ath_desc *ds, u_int64_t tsf, int16_t nf)
2665{
2666 u_int8_t rix;
2667
2668 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2669
2670 /*
2671 * Discard anything shorter than an ack or cts.
2672 */
2673 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2674 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2675 __func__, m->m_pkthdr.len);
2676 sc->sc_stats.ast_rx_tooshort++;
2677 return 0;
2678 }
2679 sc->sc_rx_th.wr_tsf = htole64(
2680 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf));
2681 rix = ds->ds_rxstat.rs_rate;
2682 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2683 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2684 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2685 /* XXX propagate other error flags from descriptor */
2686 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2687 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf;
2688 sc->sc_rx_th.wr_antnoise = nf;
2689 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2690
2691 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m);
2692
2693 return 1;
2694}
2695
2696static void
2697ath_rx_proc(void *arg, int npending)
2698{
2699#define PA2DESC(_sc, _pa) \
2700 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2701 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2702 struct ath_softc *sc = arg;
2703 struct ath_buf *bf;
2704 struct ieee80211com *ic = &sc->sc_ic;
2705 struct ifnet *ifp = sc->sc_ifp;
2706 struct ath_hal *ah = sc->sc_ah;
2707 struct ath_desc *ds;
2708 struct mbuf *m;
2709 struct ieee80211_node *ni;
2710 struct ath_node *an;
| 858 }
859}
860
861static u_int
862ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
863{
864#define N(a) (sizeof(a) / sizeof(a[0]))
865 static const u_int modeflags[] = {
866 0, /* IEEE80211_MODE_AUTO */
867 CHANNEL_A, /* IEEE80211_MODE_11A */
868 CHANNEL_B, /* IEEE80211_MODE_11B */
869 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
870 0, /* IEEE80211_MODE_FH */
871 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */
872 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
873 };
874 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
875
876 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
877 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
878 return modeflags[mode];
879#undef N
880}
881
882static void
883ath_init(void *arg)
884{
885 struct ath_softc *sc = (struct ath_softc *) arg;
886 struct ieee80211com *ic = &sc->sc_ic;
887 struct ifnet *ifp = sc->sc_ifp;
888 struct ath_hal *ah = sc->sc_ah;
889 HAL_STATUS status;
890
891 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
892 __func__, ifp->if_flags);
893
894 ATH_LOCK(sc);
895 /*
896 * Stop anything previously setup. This is safe
897 * whether this is the first time through or not.
898 */
899 ath_stop_locked(ifp);
900
901 /*
902 * The basic interface to setting the hardware in a good
903 * state is ``reset''. On return the hardware is known to
904 * be powered up and with interrupts disabled. This must
905 * be followed by initialization of the appropriate bits
906 * and then setup of the interrupt mask.
907 */
908 sc->sc_curchan.channel = ic->ic_curchan->ic_freq;
909 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
910 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) {
911 if_printf(ifp, "unable to reset hardware; hal status %u\n",
912 status);
913 goto done;
914 }
915
916 /*
917 * This is needed only to setup initial state
918 * but it's best done after a reset.
919 */
920 ath_update_txpow(sc);
921 /*
922 * Likewise this is set during reset so update
923 * state cached in the driver.
924 */
925 sc->sc_diversity = ath_hal_getdiversity(ah);
926
927 /*
928 * Setup the hardware after reset: the key cache
929 * is filled as needed and the receive engine is
930 * set going. Frame transmit is handled entirely
931 * in the frame output path; there's nothing to do
932 * here except setup the interrupt mask.
933 */
934 if (ath_startrecv(sc) != 0) {
935 if_printf(ifp, "unable to start recv logic\n");
936 goto done;
937 }
938
939 /*
940 * Enable interrupts.
941 */
942 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
943 | HAL_INT_RXEOL | HAL_INT_RXORN
944 | HAL_INT_FATAL | HAL_INT_GLOBAL;
945 /*
946 * Enable MIB interrupts when there are hardware phy counters.
947 * Note we only do this (at the moment) for station mode.
948 */
949 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
950 sc->sc_imask |= HAL_INT_MIB;
951 ath_hal_intrset(ah, sc->sc_imask);
952
953 ifp->if_drv_flags |= IFF_DRV_RUNNING;
954 ic->ic_state = IEEE80211_S_INIT;
955
956 /*
957 * The hardware should be ready to go now so it's safe
958 * to kick the 802.11 state machine as it's likely to
959 * immediately call back to us to send mgmt frames.
960 */
961 ath_chan_change(sc, ic->ic_curchan);
962#ifdef ATH_TX99_DIAG
963 if (sc->sc_tx99 != NULL)
964 sc->sc_tx99->start(sc->sc_tx99);
965 else
966#endif
967 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
968 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
969 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
970 } else
971 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
972done:
973 ATH_UNLOCK(sc);
974}
975
976static void
977ath_stop_locked(struct ifnet *ifp)
978{
979 struct ath_softc *sc = ifp->if_softc;
980 struct ieee80211com *ic = &sc->sc_ic;
981 struct ath_hal *ah = sc->sc_ah;
982
983 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
984 __func__, sc->sc_invalid, ifp->if_flags);
985
986 ATH_LOCK_ASSERT(sc);
987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
988 /*
989 * Shutdown the hardware and driver:
990 * reset 802.11 state machine
991 * turn off timers
992 * disable interrupts
993 * turn off the radio
994 * clear transmit machinery
995 * clear receive machinery
996 * drain and release tx queues
997 * reclaim beacon resources
998 * power down hardware
999 *
1000 * Note that some of this work is not possible if the
1001 * hardware is gone (invalid).
1002 */
1003#ifdef ATH_TX99_DIAG
1004 if (sc->sc_tx99 != NULL)
1005 sc->sc_tx99->stop(sc->sc_tx99);
1006#endif
1007 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1008 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1009 ifp->if_timer = 0;
1010 if (!sc->sc_invalid) {
1011 if (sc->sc_softled) {
1012 callout_stop(&sc->sc_ledtimer);
1013 ath_hal_gpioset(ah, sc->sc_ledpin,
1014 !sc->sc_ledon);
1015 sc->sc_blinking = 0;
1016 }
1017 ath_hal_intrset(ah, 0);
1018 }
1019 ath_draintxq(sc);
1020 if (!sc->sc_invalid) {
1021 ath_stoprecv(sc);
1022 ath_hal_phydisable(ah);
1023 } else
1024 sc->sc_rxlink = NULL;
1025 IFQ_DRV_PURGE(&ifp->if_snd);
1026 ath_beacon_free(sc);
1027 }
1028}
1029
1030static void
1031ath_stop(struct ifnet *ifp)
1032{
1033 struct ath_softc *sc = ifp->if_softc;
1034
1035 ATH_LOCK(sc);
1036 ath_stop_locked(ifp);
1037 if (!sc->sc_invalid) {
1038 /*
1039 * Set the chip in full sleep mode. Note that we are
1040 * careful to do this only when bringing the interface
1041 * completely to a stop. When the chip is in this state
1042 * it must be carefully woken up or references to
1043 * registers in the PCI clock domain may freeze the bus
1044 * (and system). This varies by chip and is mostly an
1045 * issue with newer parts that go to sleep more quickly.
1046 */
1047 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0);
1048 }
1049 ATH_UNLOCK(sc);
1050}
1051
1052/*
1053 * Reset the hardware w/o losing operational state. This is
1054 * basically a more efficient way of doing ath_stop, ath_init,
1055 * followed by state transitions to the current 802.11
1056 * operational state. Used to recover from various errors and
1057 * to reset or reload hardware state.
1058 */
1059static int
1060ath_reset(struct ifnet *ifp)
1061{
1062 struct ath_softc *sc = ifp->if_softc;
1063 struct ieee80211com *ic = &sc->sc_ic;
1064 struct ath_hal *ah = sc->sc_ah;
1065 struct ieee80211_channel *c;
1066 HAL_STATUS status;
1067
1068 /*
1069 * Convert to a HAL channel description with the flags
1070 * constrained to reflect the current operating mode.
1071 */
1072 c = ic->ic_curchan;
1073 sc->sc_curchan.channel = c->ic_freq;
1074 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1075
1076 ath_hal_intrset(ah, 0); /* disable interrupts */
1077 ath_draintxq(sc); /* stop xmit side */
1078 ath_stoprecv(sc); /* stop recv side */
1079 /* NB: indicate channel change so we do a full reset */
1080 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status))
1081 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1082 __func__, status);
1083 ath_update_txpow(sc); /* update tx power state */
1084 sc->sc_diversity = ath_hal_getdiversity(ah);
1085 if (ath_startrecv(sc) != 0) /* restart recv */
1086 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1087 /*
1088 * We may be doing a reset in response to an ioctl
1089 * that changes the channel so update any state that
1090 * might change as a result.
1091 */
1092 ath_chan_change(sc, c);
1093 if (ic->ic_state == IEEE80211_S_RUN)
1094 ath_beacon_config(sc); /* restart beacons */
1095 ath_hal_intrset(ah, sc->sc_imask);
1096
1097 ath_start(ifp); /* restart xmit */
1098 return 0;
1099}
1100
1101static void
1102ath_start(struct ifnet *ifp)
1103{
1104 struct ath_softc *sc = ifp->if_softc;
1105 struct ath_hal *ah = sc->sc_ah;
1106 struct ieee80211com *ic = &sc->sc_ic;
1107 struct ieee80211_node *ni;
1108 struct ath_buf *bf;
1109 struct mbuf *m;
1110 struct ieee80211_frame *wh;
1111 struct ether_header *eh;
1112
1113 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1114 return;
1115 for (;;) {
1116 /*
1117 * Grab a TX buffer and associated resources.
1118 */
1119 ATH_TXBUF_LOCK(sc);
1120 bf = STAILQ_FIRST(&sc->sc_txbuf);
1121 if (bf != NULL)
1122 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1123 ATH_TXBUF_UNLOCK(sc);
1124 if (bf == NULL) {
1125 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n",
1126 __func__);
1127 sc->sc_stats.ast_tx_qstop++;
1128 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1129 break;
1130 }
1131 /*
1132 * Poll the management queue for frames; they
1133 * have priority over normal data frames.
1134 */
1135 IF_DEQUEUE(&ic->ic_mgtq, m);
1136 if (m == NULL) {
1137 /*
1138 * No data frames go out unless we're associated.
1139 */
1140 if (ic->ic_state != IEEE80211_S_RUN) {
1141 DPRINTF(sc, ATH_DEBUG_ANY,
1142 "%s: ignore data packet, state %u\n",
1143 __func__, ic->ic_state);
1144 sc->sc_stats.ast_tx_discard++;
1145 ATH_TXBUF_LOCK(sc);
1146 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1147 ATH_TXBUF_UNLOCK(sc);
1148 break;
1149 }
1150 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1151 if (m == NULL) {
1152 ATH_TXBUF_LOCK(sc);
1153 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1154 ATH_TXBUF_UNLOCK(sc);
1155 break;
1156 }
1157 /*
1158 * Find the node for the destination so we can do
1159 * things like power save and fast frames aggregation.
1160 */
1161 if (m->m_len < sizeof(struct ether_header) &&
1162 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1163 ic->ic_stats.is_tx_nobuf++; /* XXX */
1164 ni = NULL;
1165 goto bad;
1166 }
1167 eh = mtod(m, struct ether_header *);
1168 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1169 if (ni == NULL) {
1170 /* NB: ieee80211_find_txnode does stat+msg */
1171 m_freem(m);
1172 goto bad;
1173 }
1174 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1175 (m->m_flags & M_PWR_SAV) == 0) {
1176 /*
1177 * Station in power save mode; pass the frame
1178 * to the 802.11 layer and continue. We'll get
1179 * the frame back when the time is right.
1180 */
1181 ieee80211_pwrsave(ic, ni, m);
1182 goto reclaim;
1183 }
1184 /* calculate priority so we can find the tx queue */
1185 if (ieee80211_classify(ic, m, ni)) {
1186 DPRINTF(sc, ATH_DEBUG_XMIT,
1187 "%s: discard, classification failure\n",
1188 __func__);
1189 m_freem(m);
1190 goto bad;
1191 }
1192 ifp->if_opackets++;
1193 BPF_MTAP(ifp, m);
1194 /*
1195 * Encapsulate the packet in prep for transmission.
1196 */
1197 m = ieee80211_encap(ic, m, ni);
1198 if (m == NULL) {
1199 DPRINTF(sc, ATH_DEBUG_ANY,
1200 "%s: encapsulation failure\n",
1201 __func__);
1202 sc->sc_stats.ast_tx_encap++;
1203 goto bad;
1204 }
1205 } else {
1206 /*
1207 * Hack! The referenced node pointer is in the
1208 * rcvif field of the packet header. This is
1209 * placed there by ieee80211_mgmt_output because
1210 * we need to hold the reference with the frame
1211 * and there's no other way (other than packet
1212 * tags which we consider too expensive to use)
1213 * to pass it along.
1214 */
1215 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1216 m->m_pkthdr.rcvif = NULL;
1217
1218 wh = mtod(m, struct ieee80211_frame *);
1219 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1220 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1221 /* fill time stamp */
1222 u_int64_t tsf;
1223 u_int32_t *tstamp;
1224
1225 tsf = ath_hal_gettsf64(ah);
1226 /* XXX: adjust 100us delay to xmit */
1227 tsf += 100;
1228 tstamp = (u_int32_t *)&wh[1];
1229 tstamp[0] = htole32(tsf & 0xffffffff);
1230 tstamp[1] = htole32(tsf >> 32);
1231 }
1232 sc->sc_stats.ast_tx_mgmt++;
1233 }
1234
1235 if (ath_tx_start(sc, ni, bf, m)) {
1236 bad:
1237 ifp->if_oerrors++;
1238 reclaim:
1239 ATH_TXBUF_LOCK(sc);
1240 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1241 ATH_TXBUF_UNLOCK(sc);
1242 if (ni != NULL)
1243 ieee80211_free_node(ni);
1244 continue;
1245 }
1246
1247 sc->sc_tx_timer = 5;
1248 ifp->if_timer = 1;
1249 }
1250}
1251
1252static int
1253ath_media_change(struct ifnet *ifp)
1254{
1255#define IS_UP(ifp) \
1256 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1257 int error;
1258
1259 error = ieee80211_media_change(ifp);
1260 if (error == ENETRESET) {
1261 struct ath_softc *sc = ifp->if_softc;
1262 struct ieee80211com *ic = &sc->sc_ic;
1263
1264 if (ic->ic_opmode == IEEE80211_M_AHDEMO) {
1265 /*
1266 * Adhoc demo mode is just ibss mode w/o beacons
1267 * (mostly). The hal knows nothing about it;
1268 * tell it we're operating in ibss mode.
1269 */
1270 sc->sc_opmode = HAL_M_IBSS;
1271 } else
1272 sc->sc_opmode = ic->ic_opmode;
1273 if (IS_UP(ifp))
1274 ath_init(ifp->if_softc); /* XXX lose error */
1275 error = 0;
1276 }
1277 return error;
1278#undef IS_UP
1279}
1280
1281#ifdef AR_DEBUG
1282static void
1283ath_keyprint(const char *tag, u_int ix,
1284 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1285{
1286 static const char *ciphers[] = {
1287 "WEP",
1288 "AES-OCB",
1289 "AES-CCM",
1290 "CKIP",
1291 "TKIP",
1292 "CLR",
1293 };
1294 int i, n;
1295
1296 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1297 for (i = 0, n = hk->kv_len; i < n; i++)
1298 printf("%02x", hk->kv_val[i]);
1299 printf(" mac %s", ether_sprintf(mac));
1300 if (hk->kv_type == HAL_CIPHER_TKIP) {
1301 printf(" mic ");
1302 for (i = 0; i < sizeof(hk->kv_mic); i++)
1303 printf("%02x", hk->kv_mic[i]);
1304 }
1305 printf("\n");
1306}
1307#endif
1308
1309/*
1310 * Set a TKIP key into the hardware. This handles the
1311 * potential distribution of key state to multiple key
1312 * cache slots for TKIP.
1313 */
1314static int
1315ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1316 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1317{
1318#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1319 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1320 struct ath_hal *ah = sc->sc_ah;
1321
1322 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1323 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1324 KASSERT(sc->sc_splitmic, ("key cache !split"));
1325 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1326 /*
1327 * TX key goes at first index, RX key at the rx index.
1328 * The hal handles the MIC keys at index+64.
1329 */
1330 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1331 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1332 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1333 return 0;
1334
1335 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1336 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1337 /* XXX delete tx key on failure? */
1338 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1339 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1340 /*
1341 * TX/RX key goes at first index.
1342 * The hal handles the MIC keys are index+64.
1343 */
1344 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1345 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1346 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1347 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1348 }
1349 return 0;
1350#undef IEEE80211_KEY_XR
1351}
1352
1353/*
1354 * Set a net80211 key into the hardware. This handles the
1355 * potential distribution of key state to multiple key
1356 * cache slots for TKIP with hardware MIC support.
1357 */
1358static int
1359ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1360 const u_int8_t mac0[IEEE80211_ADDR_LEN],
1361 struct ieee80211_node *bss)
1362{
1363#define N(a) (sizeof(a)/sizeof(a[0]))
1364 static const u_int8_t ciphermap[] = {
1365 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1366 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1367 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1368 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1369 (u_int8_t) -1, /* 4 is not allocated */
1370 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1371 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1372 };
1373 struct ath_hal *ah = sc->sc_ah;
1374 const struct ieee80211_cipher *cip = k->wk_cipher;
1375 u_int8_t gmac[IEEE80211_ADDR_LEN];
1376 const u_int8_t *mac;
1377 HAL_KEYVAL hk;
1378
1379 memset(&hk, 0, sizeof(hk));
1380 /*
1381 * Software crypto uses a "clear key" so non-crypto
1382 * state kept in the key cache are maintained and
1383 * so that rx frames have an entry to match.
1384 */
1385 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1386 KASSERT(cip->ic_cipher < N(ciphermap),
1387 ("invalid cipher type %u", cip->ic_cipher));
1388 hk.kv_type = ciphermap[cip->ic_cipher];
1389 hk.kv_len = k->wk_keylen;
1390 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1391 } else
1392 hk.kv_type = HAL_CIPHER_CLR;
1393
1394 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1395 /*
1396 * Group keys on hardware that supports multicast frame
1397 * key search use a mac that is the sender's address with
1398 * the high bit set instead of the app-specified address.
1399 */
1400 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1401 gmac[0] |= 0x80;
1402 mac = gmac;
1403 } else
1404 mac = mac0;
1405
1406 if (hk.kv_type == HAL_CIPHER_TKIP &&
1407 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1408 sc->sc_splitmic) {
1409 return ath_keyset_tkip(sc, k, &hk, mac);
1410 } else {
1411 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1412 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1413 }
1414#undef N
1415}
1416
1417/*
1418 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1419 * each key, one for decrypt/encrypt and the other for the MIC.
1420 */
1421static u_int16_t
1422key_alloc_2pair(struct ath_softc *sc,
1423 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1424{
1425#define N(a) (sizeof(a)/sizeof(a[0]))
1426 u_int i, keyix;
1427
1428 KASSERT(sc->sc_splitmic, ("key cache !split"));
1429 /* XXX could optimize */
1430 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1431 u_int8_t b = sc->sc_keymap[i];
1432 if (b != 0xff) {
1433 /*
1434 * One or more slots in this byte are free.
1435 */
1436 keyix = i*NBBY;
1437 while (b & 1) {
1438 again:
1439 keyix++;
1440 b >>= 1;
1441 }
1442 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1443 if (isset(sc->sc_keymap, keyix+32) ||
1444 isset(sc->sc_keymap, keyix+64) ||
1445 isset(sc->sc_keymap, keyix+32+64)) {
1446 /* full pair unavailable */
1447 /* XXX statistic */
1448 if (keyix == (i+1)*NBBY) {
1449 /* no slots were appropriate, advance */
1450 continue;
1451 }
1452 goto again;
1453 }
1454 setbit(sc->sc_keymap, keyix);
1455 setbit(sc->sc_keymap, keyix+64);
1456 setbit(sc->sc_keymap, keyix+32);
1457 setbit(sc->sc_keymap, keyix+32+64);
1458 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1459 "%s: key pair %u,%u %u,%u\n",
1460 __func__, keyix, keyix+64,
1461 keyix+32, keyix+32+64);
1462 *txkeyix = keyix;
1463 *rxkeyix = keyix+32;
1464 return 1;
1465 }
1466 }
1467 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1468 return 0;
1469#undef N
1470}
1471
1472/*
1473 * Allocate a single key cache slot.
1474 */
1475static int
1476key_alloc_single(struct ath_softc *sc,
1477 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1478{
1479#define N(a) (sizeof(a)/sizeof(a[0]))
1480 u_int i, keyix;
1481
1482 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1483 for (i = 0; i < N(sc->sc_keymap); i++) {
1484 u_int8_t b = sc->sc_keymap[i];
1485 if (b != 0xff) {
1486 /*
1487 * One or more slots are free.
1488 */
1489 keyix = i*NBBY;
1490 while (b & 1)
1491 keyix++, b >>= 1;
1492 setbit(sc->sc_keymap, keyix);
1493 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1494 __func__, keyix);
1495 *txkeyix = *rxkeyix = keyix;
1496 return 1;
1497 }
1498 }
1499 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1500 return 0;
1501#undef N
1502}
1503
1504/*
1505 * Allocate one or more key cache slots for a uniacst key. The
1506 * key itself is needed only to identify the cipher. For hardware
1507 * TKIP with split cipher+MIC keys we allocate two key cache slot
1508 * pairs so that we can setup separate TX and RX MIC keys. Note
1509 * that the MIC key for a TKIP key at slot i is assumed by the
1510 * hardware to be at slot i+64. This limits TKIP keys to the first
1511 * 64 entries.
1512 */
1513static int
1514ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
1515 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
1516{
1517 struct ath_softc *sc = ic->ic_ifp->if_softc;
1518
1519 /*
1520 * Group key allocation must be handled specially for
1521 * parts that do not support multicast key cache search
1522 * functionality. For those parts the key id must match
1523 * the h/w key index so lookups find the right key. On
1524 * parts w/ the key search facility we install the sender's
1525 * mac address (with the high bit set) and let the hardware
1526 * find the key w/o using the key id. This is preferred as
1527 * it permits us to support multiple users for adhoc and/or
1528 * multi-station operation.
1529 */
1530 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1531 if (!(&ic->ic_nw_keys[0] <= k &&
1532 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1533 /* should not happen */
1534 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1535 "%s: bogus group key\n", __func__);
1536 return 0;
1537 }
1538 /*
1539 * XXX we pre-allocate the global keys so
1540 * have no way to check if they've already been allocated.
1541 */
1542 *keyix = *rxkeyix = k - ic->ic_nw_keys;
1543 return 1;
1544 }
1545
1546 /*
1547 * We allocate two pair for TKIP when using the h/w to do
1548 * the MIC. For everything else, including software crypto,
1549 * we allocate a single entry. Note that s/w crypto requires
1550 * a pass-through slot on the 5211 and 5212. The 5210 does
1551 * not support pass-through cache entries and we map all
1552 * those requests to slot 0.
1553 */
1554 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1555 return key_alloc_single(sc, keyix, rxkeyix);
1556 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1557 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1558 return key_alloc_2pair(sc, keyix, rxkeyix);
1559 } else {
1560 return key_alloc_single(sc, keyix, rxkeyix);
1561 }
1562}
1563
1564/*
1565 * Delete an entry in the key cache allocated by ath_key_alloc.
1566 */
1567static int
1568ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1569{
1570 struct ath_softc *sc = ic->ic_ifp->if_softc;
1571 struct ath_hal *ah = sc->sc_ah;
1572 const struct ieee80211_cipher *cip = k->wk_cipher;
1573 u_int keyix = k->wk_keyix;
1574
1575 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1576
1577 ath_hal_keyreset(ah, keyix);
1578 /*
1579 * Handle split tx/rx keying required for TKIP with h/w MIC.
1580 */
1581 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1582 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
1583 ath_hal_keyreset(ah, keyix+32); /* RX key */
1584 if (keyix >= IEEE80211_WEP_NKID) {
1585 /*
1586 * Don't touch keymap entries for global keys so
1587 * they are never considered for dynamic allocation.
1588 */
1589 clrbit(sc->sc_keymap, keyix);
1590 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1591 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1592 sc->sc_splitmic) {
1593 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1594 clrbit(sc->sc_keymap, keyix+32); /* RX key */
1595 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */
1596 }
1597 }
1598 return 1;
1599}
1600
1601/*
1602 * Set the key cache contents for the specified key. Key cache
1603 * slot(s) must already have been allocated by ath_key_alloc.
1604 */
1605static int
1606ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1607 const u_int8_t mac[IEEE80211_ADDR_LEN])
1608{
1609 struct ath_softc *sc = ic->ic_ifp->if_softc;
1610
1611 return ath_keyset(sc, k, mac, ic->ic_bss);
1612}
1613
1614/*
1615 * Block/unblock tx+rx processing while a key change is done.
1616 * We assume the caller serializes key management operations
1617 * so we only need to worry about synchronization with other
1618 * uses that originate in the driver.
1619 */
1620static void
1621ath_key_update_begin(struct ieee80211com *ic)
1622{
1623 struct ifnet *ifp = ic->ic_ifp;
1624 struct ath_softc *sc = ifp->if_softc;
1625
1626 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1627#if 0
1628 tasklet_disable(&sc->sc_rxtq);
1629#endif
1630 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1631}
1632
1633static void
1634ath_key_update_end(struct ieee80211com *ic)
1635{
1636 struct ifnet *ifp = ic->ic_ifp;
1637 struct ath_softc *sc = ifp->if_softc;
1638
1639 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1640 IF_UNLOCK(&ifp->if_snd);
1641#if 0
1642 tasklet_enable(&sc->sc_rxtq);
1643#endif
1644}
1645
1646/*
1647 * Calculate the receive filter according to the
1648 * operating mode and state:
1649 *
1650 * o always accept unicast, broadcast, and multicast traffic
1651 * o maintain current state of phy error reception (the hal
1652 * may enable phy error frames for noise immunity work)
1653 * o probe request frames are accepted only when operating in
1654 * hostap, adhoc, or monitor modes
1655 * o enable promiscuous mode according to the interface state
1656 * o accept beacons:
1657 * - when operating in adhoc mode so the 802.11 layer creates
1658 * node table entries for peers,
1659 * - when operating in station mode for collecting rssi data when
1660 * the station is otherwise quiet, or
1661 * - when scanning
1662 */
1663static u_int32_t
1664ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1665{
1666 struct ieee80211com *ic = &sc->sc_ic;
1667 struct ath_hal *ah = sc->sc_ah;
1668 struct ifnet *ifp = sc->sc_ifp;
1669 u_int32_t rfilt;
1670
1671 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR)
1672 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1673 if (ic->ic_opmode != IEEE80211_M_STA)
1674 rfilt |= HAL_RX_FILTER_PROBEREQ;
1675 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1676 (ifp->if_flags & IFF_PROMISC))
1677 rfilt |= HAL_RX_FILTER_PROM;
1678 if (ic->ic_opmode == IEEE80211_M_STA ||
1679 ic->ic_opmode == IEEE80211_M_IBSS ||
1680 state == IEEE80211_S_SCAN)
1681 rfilt |= HAL_RX_FILTER_BEACON;
1682 return rfilt;
1683}
1684
1685static void
1686ath_mode_init(struct ath_softc *sc)
1687{
1688 struct ieee80211com *ic = &sc->sc_ic;
1689 struct ath_hal *ah = sc->sc_ah;
1690 struct ifnet *ifp = sc->sc_ifp;
1691 u_int32_t rfilt, mfilt[2], val;
1692 u_int8_t pos;
1693 struct ifmultiaddr *ifma;
1694
1695 /* configure rx filter */
1696 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1697 ath_hal_setrxfilter(ah, rfilt);
1698
1699 /* configure operational mode */
1700 ath_hal_setopmode(ah);
1701
1702 /*
1703 * Handle any link-level address change. Note that we only
1704 * need to force ic_myaddr; any other addresses are handled
1705 * as a byproduct of the ifnet code marking the interface
1706 * down then up.
1707 *
1708 * XXX should get from lladdr instead of arpcom but that's more work
1709 */
1710 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1711 ath_hal_setmac(ah, ic->ic_myaddr);
1712
1713 /* calculate and install multicast filter */
1714 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1715 mfilt[0] = mfilt[1] = 0;
1716 IF_ADDR_LOCK(ifp);
1717 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1718 caddr_t dl;
1719
1720 /* calculate XOR of eight 6bit values */
1721 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1722 val = LE_READ_4(dl + 0);
1723 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1724 val = LE_READ_4(dl + 3);
1725 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1726 pos &= 0x3f;
1727 mfilt[pos / 32] |= (1 << (pos % 32));
1728 }
1729 IF_ADDR_UNLOCK(ifp);
1730 } else {
1731 mfilt[0] = mfilt[1] = ~0;
1732 }
1733 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1734 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1735 __func__, rfilt, mfilt[0], mfilt[1]);
1736}
1737
1738/*
1739 * Set the slot time based on the current setting.
1740 */
1741static void
1742ath_setslottime(struct ath_softc *sc)
1743{
1744 struct ieee80211com *ic = &sc->sc_ic;
1745 struct ath_hal *ah = sc->sc_ah;
1746
1747 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1748 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1749 else
1750 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1751 sc->sc_updateslot = OK;
1752}
1753
1754/*
1755 * Callback from the 802.11 layer to update the
1756 * slot time based on the current setting.
1757 */
1758static void
1759ath_updateslot(struct ifnet *ifp)
1760{
1761 struct ath_softc *sc = ifp->if_softc;
1762 struct ieee80211com *ic = &sc->sc_ic;
1763
1764 /*
1765 * When not coordinating the BSS, change the hardware
1766 * immediately. For other operation we defer the change
1767 * until beacon updates have propagated to the stations.
1768 */
1769 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1770 sc->sc_updateslot = UPDATE;
1771 else
1772 ath_setslottime(sc);
1773}
1774
1775/*
1776 * Setup a h/w transmit queue for beacons.
1777 */
1778static int
1779ath_beaconq_setup(struct ath_hal *ah)
1780{
1781 HAL_TXQ_INFO qi;
1782
1783 memset(&qi, 0, sizeof(qi));
1784 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1785 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1786 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1787 /* NB: for dynamic turbo, don't enable any other interrupts */
1788 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1789 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1790}
1791
1792/*
1793 * Setup the transmit queue parameters for the beacon queue.
1794 */
1795static int
1796ath_beaconq_config(struct ath_softc *sc)
1797{
1798#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1799 struct ieee80211com *ic = &sc->sc_ic;
1800 struct ath_hal *ah = sc->sc_ah;
1801 HAL_TXQ_INFO qi;
1802
1803 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1804 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1805 /*
1806 * Always burst out beacon and CAB traffic.
1807 */
1808 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1809 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1810 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1811 } else {
1812 struct wmeParams *wmep =
1813 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1814 /*
1815 * Adhoc mode; important thing is to use 2x cwmin.
1816 */
1817 qi.tqi_aifs = wmep->wmep_aifsn;
1818 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1819 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1820 }
1821
1822 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1823 device_printf(sc->sc_dev, "unable to update parameters for "
1824 "beacon hardware queue!\n");
1825 return 0;
1826 } else {
1827 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1828 return 1;
1829 }
1830#undef ATH_EXPONENT_TO_VALUE
1831}
1832
1833/*
1834 * Allocate and setup an initial beacon frame.
1835 */
1836static int
1837ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1838{
1839 struct ieee80211com *ic = ni->ni_ic;
1840 struct ath_buf *bf;
1841 struct mbuf *m;
1842 int error;
1843
1844 bf = STAILQ_FIRST(&sc->sc_bbuf);
1845 if (bf == NULL) {
1846 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
1847 sc->sc_stats.ast_be_nombuf++; /* XXX */
1848 return ENOMEM; /* XXX */
1849 }
1850 /*
1851 * NB: the beacon data buffer must be 32-bit aligned;
1852 * we assume the mbuf routines will return us something
1853 * with this alignment (perhaps should assert).
1854 */
1855 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
1856 if (m == NULL) {
1857 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
1858 __func__);
1859 sc->sc_stats.ast_be_nombuf++;
1860 return ENOMEM;
1861 }
1862 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1863 bf->bf_segs, &bf->bf_nseg,
1864 BUS_DMA_NOWAIT);
1865 if (error == 0) {
1866 bf->bf_m = m;
1867 bf->bf_node = ieee80211_ref_node(ni);
1868 } else {
1869 m_freem(m);
1870 }
1871 return error;
1872}
1873
1874/*
1875 * Setup the beacon frame for transmit.
1876 */
1877static void
1878ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
1879{
1880#define USE_SHPREAMBLE(_ic) \
1881 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
1882 == IEEE80211_F_SHPREAMBLE)
1883 struct ieee80211_node *ni = bf->bf_node;
1884 struct ieee80211com *ic = ni->ni_ic;
1885 struct mbuf *m = bf->bf_m;
1886 struct ath_hal *ah = sc->sc_ah;
1887 struct ath_desc *ds;
1888 int flags, antenna;
1889 const HAL_RATE_TABLE *rt;
1890 u_int8_t rix, rate;
1891
1892 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
1893 __func__, m, m->m_len);
1894
1895 /* setup descriptors */
1896 ds = bf->bf_desc;
1897
1898 flags = HAL_TXDESC_NOACK;
1899 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
1900 ds->ds_link = bf->bf_daddr; /* self-linked */
1901 flags |= HAL_TXDESC_VEOL;
1902 /*
1903 * Let hardware handle antenna switching.
1904 */
1905 antenna = sc->sc_txantenna;
1906 } else {
1907 ds->ds_link = 0;
1908 /*
1909 * Switch antenna every 4 beacons.
1910 * XXX assumes two antenna
1911 */
1912 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
1913 }
1914
1915 KASSERT(bf->bf_nseg == 1,
1916 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
1917 ds->ds_data = bf->bf_segs[0].ds_addr;
1918 /*
1919 * Calculate rate code.
1920 * XXX everything at min xmit rate
1921 */
1922 rix = sc->sc_minrateix;
1923 rt = sc->sc_currates;
1924 rate = rt->info[rix].rateCode;
1925 if (USE_SHPREAMBLE(ic))
1926 rate |= rt->info[rix].shortPreamble;
1927 ath_hal_setuptxdesc(ah, ds
1928 , m->m_len + IEEE80211_CRC_LEN /* frame length */
1929 , sizeof(struct ieee80211_frame)/* header length */
1930 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
1931 , ni->ni_txpower /* txpower XXX */
1932 , rate, 1 /* series 0 rate/tries */
1933 , HAL_TXKEYIX_INVALID /* no encryption */
1934 , antenna /* antenna mode */
1935 , flags /* no ack, veol for beacons */
1936 , 0 /* rts/cts rate */
1937 , 0 /* rts/cts duration */
1938 );
1939 /* NB: beacon's BufLen must be a multiple of 4 bytes */
1940 ath_hal_filltxdesc(ah, ds
1941 , roundup(m->m_len, 4) /* buffer length */
1942 , AH_TRUE /* first segment */
1943 , AH_TRUE /* last segment */
1944 , ds /* first descriptor */
1945 );
1946#undef USE_SHPREAMBLE
1947}
1948
1949/*
1950 * Transmit a beacon frame at SWBA. Dynamic updates to the
1951 * frame contents are done as needed and the slot time is
1952 * also adjusted based on current state.
1953 */
1954static void
1955ath_beacon_proc(void *arg, int pending)
1956{
1957 struct ath_softc *sc = arg;
1958 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
1959 struct ieee80211_node *ni = bf->bf_node;
1960 struct ieee80211com *ic = ni->ni_ic;
1961 struct ath_hal *ah = sc->sc_ah;
1962 struct mbuf *m;
1963 int ncabq, error, otherant;
1964
1965 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
1966 __func__, pending);
1967
1968 if (ic->ic_opmode == IEEE80211_M_STA ||
1969 ic->ic_opmode == IEEE80211_M_MONITOR ||
1970 bf == NULL || bf->bf_m == NULL) {
1971 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
1972 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
1973 return;
1974 }
1975 /*
1976 * Check if the previous beacon has gone out. If
1977 * not don't don't try to post another, skip this
1978 * period and wait for the next. Missed beacons
1979 * indicate a problem and should not occur. If we
1980 * miss too many consecutive beacons reset the device.
1981 */
1982 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
1983 sc->sc_bmisscount++;
1984 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
1985 "%s: missed %u consecutive beacons\n",
1986 __func__, sc->sc_bmisscount);
1987 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
1988 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
1989 return;
1990 }
1991 if (sc->sc_bmisscount != 0) {
1992 DPRINTF(sc, ATH_DEBUG_BEACON,
1993 "%s: resume beacon xmit after %u misses\n",
1994 __func__, sc->sc_bmisscount);
1995 sc->sc_bmisscount = 0;
1996 }
1997
1998 /*
1999 * Update dynamic beacon contents. If this returns
2000 * non-zero then we need to remap the memory because
2001 * the beacon frame changed size (probably because
2002 * of the TIM bitmap).
2003 */
2004 m = bf->bf_m;
2005 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum);
2006 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) {
2007 /* XXX too conservative? */
2008 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2009 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2010 bf->bf_segs, &bf->bf_nseg,
2011 BUS_DMA_NOWAIT);
2012 if (error != 0) {
2013 if_printf(ic->ic_ifp,
2014 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
2015 __func__, error);
2016 return;
2017 }
2018 }
2019
2020 /*
2021 * Handle slot time change when a non-ERP station joins/leaves
2022 * an 11g network. The 802.11 layer notifies us via callback,
2023 * we mark updateslot, then wait one beacon before effecting
2024 * the change. This gives associated stations at least one
2025 * beacon interval to note the state change.
2026 */
2027 /* XXX locking */
2028 if (sc->sc_updateslot == UPDATE)
2029 sc->sc_updateslot = COMMIT; /* commit next beacon */
2030 else if (sc->sc_updateslot == COMMIT)
2031 ath_setslottime(sc); /* commit change to h/w */
2032
2033 /*
2034 * Check recent per-antenna transmit statistics and flip
2035 * the default antenna if noticeably more frames went out
2036 * on the non-default antenna.
2037 * XXX assumes 2 anntenae
2038 */
2039 otherant = sc->sc_defant & 1 ? 2 : 1;
2040 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2041 ath_setdefantenna(sc, otherant);
2042 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2043
2044 /*
2045 * Construct tx descriptor.
2046 */
2047 ath_beacon_setup(sc, bf);
2048
2049 /*
2050 * Stop any current dma and put the new frame on the queue.
2051 * This should never fail since we check above that no frames
2052 * are still pending on the queue.
2053 */
2054 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2055 DPRINTF(sc, ATH_DEBUG_ANY,
2056 "%s: beacon queue %u did not stop?\n",
2057 __func__, sc->sc_bhalq);
2058 }
2059 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2060
2061 /*
2062 * Enable the CAB queue before the beacon queue to
2063 * insure cab frames are triggered by this beacon.
2064 */
2065 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */
2066 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum);
2067 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2068 ath_hal_txstart(ah, sc->sc_bhalq);
2069 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2070 "%s: TXDP[%u] = %p (%p)\n", __func__,
2071 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2072
2073 sc->sc_stats.ast_be_xmit++;
2074}
2075
2076/*
2077 * Reset the hardware after detecting beacons have stopped.
2078 */
2079static void
2080ath_bstuck_proc(void *arg, int pending)
2081{
2082 struct ath_softc *sc = arg;
2083 struct ifnet *ifp = sc->sc_ifp;
2084
2085 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2086 sc->sc_bmisscount);
2087 ath_reset(ifp);
2088}
2089
2090/*
2091 * Reclaim beacon resources.
2092 */
2093static void
2094ath_beacon_free(struct ath_softc *sc)
2095{
2096 struct ath_buf *bf;
2097
2098 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2099 if (bf->bf_m != NULL) {
2100 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2101 m_freem(bf->bf_m);
2102 bf->bf_m = NULL;
2103 }
2104 if (bf->bf_node != NULL) {
2105 ieee80211_free_node(bf->bf_node);
2106 bf->bf_node = NULL;
2107 }
2108 }
2109}
2110
2111/*
2112 * Configure the beacon and sleep timers.
2113 *
2114 * When operating as an AP this resets the TSF and sets
2115 * up the hardware to notify us when we need to issue beacons.
2116 *
2117 * When operating in station mode this sets up the beacon
2118 * timers according to the timestamp of the last received
2119 * beacon and the current TSF, configures PCF and DTIM
2120 * handling, programs the sleep registers so the hardware
2121 * will wakeup in time to receive beacons, and configures
2122 * the beacon miss handling so we'll receive a BMISS
2123 * interrupt when we stop seeing beacons from the AP
2124 * we've associated with.
2125 */
2126static void
2127ath_beacon_config(struct ath_softc *sc)
2128{
2129#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10))
2130 struct ath_hal *ah = sc->sc_ah;
2131 struct ieee80211com *ic = &sc->sc_ic;
2132 struct ieee80211_node *ni = ic->ic_bss;
2133 u_int32_t nexttbtt, intval;
2134
2135 /* extract tstamp from last beacon and convert to TU */
2136 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2137 LE_READ_4(ni->ni_tstamp.data));
2138 /* NB: the beacon interval is kept internally in TU's */
2139 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2140 if (nexttbtt == 0) /* e.g. for ap mode */
2141 nexttbtt = intval;
2142 else if (intval) /* NB: can be 0 for monitor mode */
2143 nexttbtt = roundup(nexttbtt, intval);
2144 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2145 __func__, nexttbtt, intval, ni->ni_intval);
2146 if (ic->ic_opmode == IEEE80211_M_STA) {
2147 HAL_BEACON_STATE bs;
2148 u_int64_t tsf;
2149 u_int32_t tsftu;
2150 int dtimperiod, dtimcount;
2151 int cfpperiod, cfpcount;
2152
2153 /*
2154 * Setup dtim and cfp parameters according to
2155 * last beacon we received (which may be none).
2156 */
2157 dtimperiod = ni->ni_dtim_period;
2158 if (dtimperiod <= 0) /* NB: 0 if not known */
2159 dtimperiod = 1;
2160 dtimcount = ni->ni_dtim_count;
2161 if (dtimcount >= dtimperiod) /* NB: sanity check */
2162 dtimcount = 0; /* XXX? */
2163 cfpperiod = 1; /* NB: no PCF support yet */
2164 cfpcount = 0;
2165#define FUDGE 2
2166 /*
2167 * Pull nexttbtt forward to reflect the current
2168 * TSF and calculate dtim+cfp state for the result.
2169 */
2170 tsf = ath_hal_gettsf64(ah);
2171 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE;
2172 do {
2173 nexttbtt += intval;
2174 if (--dtimcount < 0) {
2175 dtimcount = dtimperiod - 1;
2176 if (--cfpcount < 0)
2177 cfpcount = cfpperiod - 1;
2178 }
2179 } while (nexttbtt < tsftu);
2180#undef FUDGE
2181 memset(&bs, 0, sizeof(bs));
2182 bs.bs_intval = intval;
2183 bs.bs_nexttbtt = nexttbtt;
2184 bs.bs_dtimperiod = dtimperiod*intval;
2185 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2186 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2187 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2188 bs.bs_cfpmaxduration = 0;
2189#if 0
2190 /*
2191 * The 802.11 layer records the offset to the DTIM
2192 * bitmap while receiving beacons; use it here to
2193 * enable h/w detection of our AID being marked in
2194 * the bitmap vector (to indicate frames for us are
2195 * pending at the AP).
2196 * XXX do DTIM handling in s/w to WAR old h/w bugs
2197 * XXX enable based on h/w rev for newer chips
2198 */
2199 bs.bs_timoffset = ni->ni_timoff;
2200#endif
2201 /*
2202 * Calculate the number of consecutive beacons to miss
2203 * before taking a BMISS interrupt. The configuration
2204 * is specified in ms, so we need to convert that to
2205 * TU's and then calculate based on the beacon interval.
2206 * Note that we clamp the result to at most 10 beacons.
2207 */
2208 bs.bs_bmissthreshold = ic->ic_bmissthreshold;
2209 if (bs.bs_bmissthreshold > 10)
2210 bs.bs_bmissthreshold = 10;
2211 else if (bs.bs_bmissthreshold <= 0)
2212 bs.bs_bmissthreshold = 1;
2213
2214 /*
2215 * Calculate sleep duration. The configuration is
2216 * given in ms. We insure a multiple of the beacon
2217 * period is used. Also, if the sleep duration is
2218 * greater than the DTIM period then it makes senses
2219 * to make it a multiple of that.
2220 *
2221 * XXX fixed at 100ms
2222 */
2223 bs.bs_sleepduration =
2224 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2225 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2226 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2227
2228 DPRINTF(sc, ATH_DEBUG_BEACON,
2229 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2230 , __func__
2231 , tsf, tsftu
2232 , bs.bs_intval
2233 , bs.bs_nexttbtt
2234 , bs.bs_dtimperiod
2235 , bs.bs_nextdtim
2236 , bs.bs_bmissthreshold
2237 , bs.bs_sleepduration
2238 , bs.bs_cfpperiod
2239 , bs.bs_cfpmaxduration
2240 , bs.bs_cfpnext
2241 , bs.bs_timoffset
2242 );
2243 ath_hal_intrset(ah, 0);
2244 ath_hal_beacontimers(ah, &bs);
2245 sc->sc_imask |= HAL_INT_BMISS;
2246 ath_hal_intrset(ah, sc->sc_imask);
2247 } else {
2248 ath_hal_intrset(ah, 0);
2249 if (nexttbtt == intval)
2250 intval |= HAL_BEACON_RESET_TSF;
2251 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2252 /*
2253 * In IBSS mode enable the beacon timers but only
2254 * enable SWBA interrupts if we need to manually
2255 * prepare beacon frames. Otherwise we use a
2256 * self-linked tx descriptor and let the hardware
2257 * deal with things.
2258 */
2259 intval |= HAL_BEACON_ENA;
2260 if (!sc->sc_hasveol)
2261 sc->sc_imask |= HAL_INT_SWBA;
2262 ath_beaconq_config(sc);
2263 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2264 /*
2265 * In AP mode we enable the beacon timers and
2266 * SWBA interrupts to prepare beacon frames.
2267 */
2268 intval |= HAL_BEACON_ENA;
2269 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2270 ath_beaconq_config(sc);
2271 }
2272 ath_hal_beaconinit(ah, nexttbtt, intval);
2273 sc->sc_bmisscount = 0;
2274 ath_hal_intrset(ah, sc->sc_imask);
2275 /*
2276 * When using a self-linked beacon descriptor in
2277 * ibss mode load it once here.
2278 */
2279 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2280 ath_beacon_proc(sc, 0);
2281 }
2282#undef TSF_TO_TU
2283}
2284
2285static void
2286ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2287{
2288 bus_addr_t *paddr = (bus_addr_t*) arg;
2289 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2290 *paddr = segs->ds_addr;
2291}
2292
2293static int
2294ath_descdma_setup(struct ath_softc *sc,
2295 struct ath_descdma *dd, ath_bufhead *head,
2296 const char *name, int nbuf, int ndesc)
2297{
2298#define DS2PHYS(_dd, _ds) \
2299 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2300 struct ifnet *ifp = sc->sc_ifp;
2301 struct ath_desc *ds;
2302 struct ath_buf *bf;
2303 int i, bsize, error;
2304
2305 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2306 __func__, name, nbuf, ndesc);
2307
2308 dd->dd_name = name;
2309 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2310
2311 /*
2312 * Setup DMA descriptor area.
2313 */
2314 error = bus_dma_tag_create(NULL, /* parent */
2315 PAGE_SIZE, 0, /* alignment, bounds */
2316 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2317 BUS_SPACE_MAXADDR, /* highaddr */
2318 NULL, NULL, /* filter, filterarg */
2319 dd->dd_desc_len, /* maxsize */
2320 1, /* nsegments */
2321 BUS_SPACE_MAXADDR, /* maxsegsize */
2322 BUS_DMA_ALLOCNOW, /* flags */
2323 NULL, /* lockfunc */
2324 NULL, /* lockarg */
2325 &dd->dd_dmat);
2326 if (error != 0) {
2327 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2328 return error;
2329 }
2330
2331 /* allocate descriptors */
2332 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
2333 if (error != 0) {
2334 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2335 "error %u\n", dd->dd_name, error);
2336 goto fail0;
2337 }
2338
2339 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
2340 BUS_DMA_NOWAIT, &dd->dd_dmamap);
2341 if (error != 0) {
2342 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2343 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2344 goto fail1;
2345 }
2346
2347 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2348 dd->dd_desc, dd->dd_desc_len,
2349 ath_load_cb, &dd->dd_desc_paddr,
2350 BUS_DMA_NOWAIT);
2351 if (error != 0) {
2352 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2353 dd->dd_name, error);
2354 goto fail2;
2355 }
2356
2357 ds = dd->dd_desc;
2358 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2359 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2360 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2361
2362 /* allocate rx buffers */
2363 bsize = sizeof(struct ath_buf) * nbuf;
2364 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2365 if (bf == NULL) {
2366 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2367 dd->dd_name, bsize);
2368 goto fail3;
2369 }
2370 dd->dd_bufptr = bf;
2371
2372 STAILQ_INIT(head);
2373 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2374 bf->bf_desc = ds;
2375 bf->bf_daddr = DS2PHYS(dd, ds);
2376 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
2377 &bf->bf_dmamap);
2378 if (error != 0) {
2379 if_printf(ifp, "unable to create dmamap for %s "
2380 "buffer %u, error %u\n", dd->dd_name, i, error);
2381 ath_descdma_cleanup(sc, dd, head);
2382 return error;
2383 }
2384 STAILQ_INSERT_TAIL(head, bf, bf_list);
2385 }
2386 return 0;
2387fail3:
2388 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2389fail2:
2390 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2391fail1:
2392 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2393fail0:
2394 bus_dma_tag_destroy(dd->dd_dmat);
2395 memset(dd, 0, sizeof(*dd));
2396 return error;
2397#undef DS2PHYS
2398}
2399
2400static void
2401ath_descdma_cleanup(struct ath_softc *sc,
2402 struct ath_descdma *dd, ath_bufhead *head)
2403{
2404 struct ath_buf *bf;
2405 struct ieee80211_node *ni;
2406
2407 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2408 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2409 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2410 bus_dma_tag_destroy(dd->dd_dmat);
2411
2412 STAILQ_FOREACH(bf, head, bf_list) {
2413 if (bf->bf_m) {
2414 m_freem(bf->bf_m);
2415 bf->bf_m = NULL;
2416 }
2417 if (bf->bf_dmamap != NULL) {
2418 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2419 bf->bf_dmamap = NULL;
2420 }
2421 ni = bf->bf_node;
2422 bf->bf_node = NULL;
2423 if (ni != NULL) {
2424 /*
2425 * Reclaim node reference.
2426 */
2427 ieee80211_free_node(ni);
2428 }
2429 }
2430
2431 STAILQ_INIT(head);
2432 free(dd->dd_bufptr, M_ATHDEV);
2433 memset(dd, 0, sizeof(*dd));
2434}
2435
2436static int
2437ath_desc_alloc(struct ath_softc *sc)
2438{
2439 int error;
2440
2441 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2442 "rx", ath_rxbuf, 1);
2443 if (error != 0)
2444 return error;
2445
2446 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2447 "tx", ath_txbuf, ATH_TXDESC);
2448 if (error != 0) {
2449 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2450 return error;
2451 }
2452
2453 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2454 "beacon", 1, 1);
2455 if (error != 0) {
2456 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2457 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2458 return error;
2459 }
2460 return 0;
2461}
2462
2463static void
2464ath_desc_free(struct ath_softc *sc)
2465{
2466
2467 if (sc->sc_bdma.dd_desc_len != 0)
2468 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2469 if (sc->sc_txdma.dd_desc_len != 0)
2470 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2471 if (sc->sc_rxdma.dd_desc_len != 0)
2472 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2473}
2474
2475static struct ieee80211_node *
2476ath_node_alloc(struct ieee80211_node_table *nt)
2477{
2478 struct ieee80211com *ic = nt->nt_ic;
2479 struct ath_softc *sc = ic->ic_ifp->if_softc;
2480 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2481 struct ath_node *an;
2482
2483 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2484 if (an == NULL) {
2485 /* XXX stat+msg */
2486 return NULL;
2487 }
2488 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2489 ath_rate_node_init(sc, an);
2490
2491 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2492 return &an->an_node;
2493}
2494
2495static void
2496ath_node_free(struct ieee80211_node *ni)
2497{
2498 struct ieee80211com *ic = ni->ni_ic;
2499 struct ath_softc *sc = ic->ic_ifp->if_softc;
2500
2501 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2502
2503 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2504 sc->sc_node_free(ni);
2505}
2506
2507static u_int8_t
2508ath_node_getrssi(const struct ieee80211_node *ni)
2509{
2510#define HAL_EP_RND(x, mul) \
2511 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2512 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2513 int32_t rssi;
2514
2515 /*
2516 * When only one frame is received there will be no state in
2517 * avgrssi so fallback on the value recorded by the 802.11 layer.
2518 */
2519 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2520 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2521 else
2522 rssi = ni->ni_rssi;
2523 /* NB: theoretically we shouldn't need this, but be paranoid */
2524 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2525#undef HAL_EP_RND
2526}
2527
2528static int
2529ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2530{
2531 struct ath_hal *ah = sc->sc_ah;
2532 int error;
2533 struct mbuf *m;
2534 struct ath_desc *ds;
2535
2536 m = bf->bf_m;
2537 if (m == NULL) {
2538 /*
2539 * NB: by assigning a page to the rx dma buffer we
2540 * implicitly satisfy the Atheros requirement that
2541 * this buffer be cache-line-aligned and sized to be
2542 * multiple of the cache line size. Not doing this
2543 * causes weird stuff to happen (for the 5210 at least).
2544 */
2545 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2546 if (m == NULL) {
2547 DPRINTF(sc, ATH_DEBUG_ANY,
2548 "%s: no mbuf/cluster\n", __func__);
2549 sc->sc_stats.ast_rx_nombuf++;
2550 return ENOMEM;
2551 }
2552 bf->bf_m = m;
2553 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2554
2555 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
2556 bf->bf_dmamap, m,
2557 bf->bf_segs, &bf->bf_nseg,
2558 BUS_DMA_NOWAIT);
2559 if (error != 0) {
2560 DPRINTF(sc, ATH_DEBUG_ANY,
2561 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
2562 __func__, error);
2563 sc->sc_stats.ast_rx_busdma++;
2564 return error;
2565 }
2566 KASSERT(bf->bf_nseg == 1,
2567 ("multi-segment packet; nseg %u", bf->bf_nseg));
2568 }
2569 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2570
2571 /*
2572 * Setup descriptors. For receive we always terminate
2573 * the descriptor list with a self-linked entry so we'll
2574 * not get overrun under high load (as can happen with a
2575 * 5212 when ANI processing enables PHY error frames).
2576 *
2577 * To insure the last descriptor is self-linked we create
2578 * each descriptor as self-linked and add it to the end. As
2579 * each additional descriptor is added the previous self-linked
2580 * entry is ``fixed'' naturally. This should be safe even
2581 * if DMA is happening. When processing RX interrupts we
2582 * never remove/process the last, self-linked, entry on the
2583 * descriptor list. This insures the hardware always has
2584 * someplace to write a new frame.
2585 */
2586 ds = bf->bf_desc;
2587 ds->ds_link = bf->bf_daddr; /* link to self */
2588 ds->ds_data = bf->bf_segs[0].ds_addr;
2589 ath_hal_setuprxdesc(ah, ds
2590 , m->m_len /* buffer size */
2591 , 0
2592 );
2593
2594 if (sc->sc_rxlink != NULL)
2595 *sc->sc_rxlink = bf->bf_daddr;
2596 sc->sc_rxlink = &ds->ds_link;
2597 return 0;
2598}
2599
2600/*
2601 * Extend 15-bit time stamp from rx descriptor to
2602 * a full 64-bit TSF using the specified TSF.
2603 */
2604static __inline u_int64_t
2605ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
2606{
2607 if ((tsf & 0x7fff) < rstamp)
2608 tsf -= 0x8000;
2609 return ((tsf &~ 0x7fff) | rstamp);
2610}
2611
2612/*
2613 * Intercept management frames to collect beacon rssi data
2614 * and to do ibss merges.
2615 */
2616static void
2617ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2618 struct ieee80211_node *ni,
2619 int subtype, int rssi, u_int32_t rstamp)
2620{
2621 struct ath_softc *sc = ic->ic_ifp->if_softc;
2622
2623 /*
2624 * Call up first so subsequent work can use information
2625 * potentially stored in the node (e.g. for ibss merge).
2626 */
2627 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2628 switch (subtype) {
2629 case IEEE80211_FC0_SUBTYPE_BEACON:
2630 /* update rssi statistics for use by the hal */
2631 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
2632 /* fall thru... */
2633 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2634 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2635 ic->ic_state == IEEE80211_S_RUN) {
2636 u_int64_t tsf = ath_extend_tsf(rstamp,
2637 ath_hal_gettsf64(sc->sc_ah));
2638 /*
2639 * Handle ibss merge as needed; check the tsf on the
2640 * frame before attempting the merge. The 802.11 spec
2641 * says the station should change it's bssid to match
2642 * the oldest station with the same ssid, where oldest
2643 * is determined by the tsf. Note that hardware
2644 * reconfiguration happens through callback to
2645 * ath_newstate as the state machine will go from
2646 * RUN -> RUN when this happens.
2647 */
2648 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2649 DPRINTF(sc, ATH_DEBUG_STATE,
2650 "ibss merge, rstamp %u tsf %ju "
2651 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2652 (uintmax_t)ni->ni_tstamp.tsf);
2653 (void) ieee80211_ibss_merge(ni);
2654 }
2655 }
2656 break;
2657 }
2658}
2659
2660/*
2661 * Set the default antenna.
2662 */
2663static void
2664ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2665{
2666 struct ath_hal *ah = sc->sc_ah;
2667
2668 /* XXX block beacon interrupts */
2669 ath_hal_setdefantenna(ah, antenna);
2670 if (sc->sc_defant != antenna)
2671 sc->sc_stats.ast_ant_defswitch++;
2672 sc->sc_defant = antenna;
2673 sc->sc_rxotherant = 0;
2674}
2675
2676static int
2677ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2678 const struct ath_desc *ds, u_int64_t tsf, int16_t nf)
2679{
2680 u_int8_t rix;
2681
2682 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2683
2684 /*
2685 * Discard anything shorter than an ack or cts.
2686 */
2687 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2688 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2689 __func__, m->m_pkthdr.len);
2690 sc->sc_stats.ast_rx_tooshort++;
2691 return 0;
2692 }
2693 sc->sc_rx_th.wr_tsf = htole64(
2694 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf));
2695 rix = ds->ds_rxstat.rs_rate;
2696 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2697 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2698 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2699 /* XXX propagate other error flags from descriptor */
2700 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2701 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf;
2702 sc->sc_rx_th.wr_antnoise = nf;
2703 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2704
2705 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m);
2706
2707 return 1;
2708}
2709
2710static void
2711ath_rx_proc(void *arg, int npending)
2712{
2713#define PA2DESC(_sc, _pa) \
2714 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2715 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2716 struct ath_softc *sc = arg;
2717 struct ath_buf *bf;
2718 struct ieee80211com *ic = &sc->sc_ic;
2719 struct ifnet *ifp = sc->sc_ifp;
2720 struct ath_hal *ah = sc->sc_ah;
2721 struct ath_desc *ds;
2722 struct mbuf *m;
2723 struct ieee80211_node *ni;
2724 struct ath_node *an;
|
2711 int len, type;
| 2725 int len, type, ngood;
|
2712 u_int phyerr;
2713 HAL_STATUS status;
2714 int16_t nf;
2715 u_int64_t tsf;
2716
2717 NET_LOCK_GIANT(); /* XXX */
2718
2719 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
| 2726 u_int phyerr;
2727 HAL_STATUS status;
2728 int16_t nf;
2729 u_int64_t tsf;
2730
2731 NET_LOCK_GIANT(); /* XXX */
2732
2733 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
|
| 2734 ngood = 0;
|
2720 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
2721 tsf = ath_hal_gettsf64(ah);
2722 do {
2723 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2724 if (bf == NULL) { /* NB: shouldn't happen */
2725 if_printf(ifp, "%s: no buffer!\n", __func__);
2726 break;
2727 }
2728 ds = bf->bf_desc;
2729 if (ds->ds_link == bf->bf_daddr) {
2730 /* NB: never process the self-linked entry at the end */
2731 break;
2732 }
2733 m = bf->bf_m;
2734 if (m == NULL) { /* NB: shouldn't happen */
2735 if_printf(ifp, "%s: no mbuf!\n", __func__);
2736 continue;
2737 }
2738 /* XXX sync descriptor memory */
2739 /*
2740 * Must provide the virtual address of the current
2741 * descriptor, the physical address, and the virtual
2742 * address of the next descriptor in the h/w chain.
2743 * This allows the HAL to look ahead to see if the
2744 * hardware is done with a descriptor by checking the
2745 * done bit in the following descriptor and the address
2746 * of the current descriptor the DMA engine is working
2747 * on. All this is necessary because of our use of
2748 * a self-linked list to avoid rx overruns.
2749 */
2750 status = ath_hal_rxprocdesc(ah, ds,
2751 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2752#ifdef AR_DEBUG
2753 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2754 ath_printrxbuf(bf, status == HAL_OK);
2755#endif
2756 if (status == HAL_EINPROGRESS)
2757 break;
2758 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2759 if (ds->ds_rxstat.rs_more) {
2760 /*
2761 * Frame spans multiple descriptors; this
2762 * cannot happen yet as we don't support
2763 * jumbograms. If not in monitor mode,
2764 * discard the frame.
2765 */
2766 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2767 sc->sc_stats.ast_rx_toobig++;
2768 goto rx_next;
2769 }
2770 /* fall thru for monitor mode handling... */
2771 } else if (ds->ds_rxstat.rs_status != 0) {
2772 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2773 sc->sc_stats.ast_rx_crcerr++;
2774 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2775 sc->sc_stats.ast_rx_fifoerr++;
2776 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2777 sc->sc_stats.ast_rx_phyerr++;
2778 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2779 sc->sc_stats.ast_rx_phy[phyerr]++;
2780 goto rx_next;
2781 }
2782 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2783 /*
2784 * Decrypt error. If the error occurred
2785 * because there was no hardware key, then
2786 * let the frame through so the upper layers
2787 * can process it. This is necessary for 5210
2788 * parts which have no way to setup a ``clear''
2789 * key cache entry.
2790 *
2791 * XXX do key cache faulting
2792 */
2793 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2794 goto rx_accept;
2795 sc->sc_stats.ast_rx_badcrypt++;
2796 }
2797 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2798 sc->sc_stats.ast_rx_badmic++;
2799 /*
2800 * Do minimal work required to hand off
2801 * the 802.11 header for notifcation.
2802 */
2803 /* XXX frag's and qos frames */
2804 len = ds->ds_rxstat.rs_datalen;
2805 if (len >= sizeof (struct ieee80211_frame)) {
2806 bus_dmamap_sync(sc->sc_dmat,
2807 bf->bf_dmamap,
2808 BUS_DMASYNC_POSTREAD);
2809 ieee80211_notify_michael_failure(ic,
2810 mtod(m, struct ieee80211_frame *),
2811 sc->sc_splitmic ?
2812 ds->ds_rxstat.rs_keyix-32 :
2813 ds->ds_rxstat.rs_keyix
2814 );
2815 }
2816 }
2817 ifp->if_ierrors++;
2818 /*
2819 * When a tap is present pass error frames
2820 * that have been requested. By default we
2821 * pass decrypt+mic errors but others may be
2822 * interesting (e.g. crc).
2823 */
2824 if (sc->sc_drvbpf != NULL &&
2825 (ds->ds_rxstat.rs_status & sc->sc_monpass)) {
2826 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2827 BUS_DMASYNC_POSTREAD);
2828 /* NB: bpf needs the mbuf length setup */
2829 len = ds->ds_rxstat.rs_datalen;
2830 m->m_pkthdr.len = m->m_len = len;
2831 (void) ath_rx_tap(sc, m, ds, tsf, nf);
2832 }
2833 /* XXX pass MIC errors up for s/w reclaculation */
2834 goto rx_next;
2835 }
2836rx_accept:
2837 /*
2838 * Sync and unmap the frame. At this point we're
2839 * committed to passing the mbuf somewhere so clear
2840 * bf_m; this means a new sk_buff must be allocated
2841 * when the rx descriptor is setup again to receive
2842 * another frame.
2843 */
2844 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2845 BUS_DMASYNC_POSTREAD);
2846 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2847 bf->bf_m = NULL;
2848
2849 m->m_pkthdr.rcvif = ifp;
2850 len = ds->ds_rxstat.rs_datalen;
2851 m->m_pkthdr.len = m->m_len = len;
2852
2853 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
2854
2855 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, ds, tsf, nf)) {
2856 m_freem(m); /* XXX reclaim */
2857 goto rx_next;
2858 }
2859
2860 /*
2861 * From this point on we assume the frame is at least
2862 * as large as ieee80211_frame_min; verify that.
2863 */
2864 if (len < IEEE80211_MIN_LEN) {
2865 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
2866 __func__, len);
2867 sc->sc_stats.ast_rx_tooshort++;
2868 m_freem(m);
2869 goto rx_next;
2870 }
2871
2872 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
2873 ieee80211_dump_pkt(mtod(m, caddr_t), len,
2874 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
2875 ds->ds_rxstat.rs_rssi);
2876 }
2877
2878 m_adj(m, -IEEE80211_CRC_LEN);
2879
2880 /*
2881 * Locate the node for sender, track state, and then
2882 * pass the (referenced) node up to the 802.11 layer
2883 * for its use.
2884 */
2885 ni = ieee80211_find_rxnode_withkey(ic,
2886 mtod(m, const struct ieee80211_frame_min *),
2887 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ?
2888 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix);
2889 /*
2890 * Track rx rssi and do any rx antenna management.
2891 */
2892 an = ATH_NODE(ni);
2893 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2894 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi);
2895 /*
2896 * Send frame up for processing.
2897 */
2898 type = ieee80211_input(ic, m, ni,
2899 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2900 ieee80211_free_node(ni);
2901 if (sc->sc_diversity) {
2902 /*
2903 * When using fast diversity, change the default rx
2904 * antenna if diversity chooses the other antenna 3
2905 * times in a row.
2906 */
2907 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
2908 if (++sc->sc_rxotherant >= 3)
2909 ath_setdefantenna(sc,
2910 ds->ds_rxstat.rs_antenna);
2911 } else
2912 sc->sc_rxotherant = 0;
2913 }
2914 if (sc->sc_softled) {
2915 /*
2916 * Blink for any data frame. Otherwise do a
2917 * heartbeat-style blink when idle. The latter
2918 * is mainly for station mode where we depend on
2919 * periodic beacon frames to trigger the poll event.
2920 */
2921 if (type == IEEE80211_FC0_TYPE_DATA) {
2922 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
2923 ath_led_event(sc, ATH_LED_RX);
2924 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
2925 ath_led_event(sc, ATH_LED_POLL);
2926 }
| 2735 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
2736 tsf = ath_hal_gettsf64(ah);
2737 do {
2738 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2739 if (bf == NULL) { /* NB: shouldn't happen */
2740 if_printf(ifp, "%s: no buffer!\n", __func__);
2741 break;
2742 }
2743 ds = bf->bf_desc;
2744 if (ds->ds_link == bf->bf_daddr) {
2745 /* NB: never process the self-linked entry at the end */
2746 break;
2747 }
2748 m = bf->bf_m;
2749 if (m == NULL) { /* NB: shouldn't happen */
2750 if_printf(ifp, "%s: no mbuf!\n", __func__);
2751 continue;
2752 }
2753 /* XXX sync descriptor memory */
2754 /*
2755 * Must provide the virtual address of the current
2756 * descriptor, the physical address, and the virtual
2757 * address of the next descriptor in the h/w chain.
2758 * This allows the HAL to look ahead to see if the
2759 * hardware is done with a descriptor by checking the
2760 * done bit in the following descriptor and the address
2761 * of the current descriptor the DMA engine is working
2762 * on. All this is necessary because of our use of
2763 * a self-linked list to avoid rx overruns.
2764 */
2765 status = ath_hal_rxprocdesc(ah, ds,
2766 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2767#ifdef AR_DEBUG
2768 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2769 ath_printrxbuf(bf, status == HAL_OK);
2770#endif
2771 if (status == HAL_EINPROGRESS)
2772 break;
2773 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2774 if (ds->ds_rxstat.rs_more) {
2775 /*
2776 * Frame spans multiple descriptors; this
2777 * cannot happen yet as we don't support
2778 * jumbograms. If not in monitor mode,
2779 * discard the frame.
2780 */
2781 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2782 sc->sc_stats.ast_rx_toobig++;
2783 goto rx_next;
2784 }
2785 /* fall thru for monitor mode handling... */
2786 } else if (ds->ds_rxstat.rs_status != 0) {
2787 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2788 sc->sc_stats.ast_rx_crcerr++;
2789 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2790 sc->sc_stats.ast_rx_fifoerr++;
2791 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2792 sc->sc_stats.ast_rx_phyerr++;
2793 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2794 sc->sc_stats.ast_rx_phy[phyerr]++;
2795 goto rx_next;
2796 }
2797 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2798 /*
2799 * Decrypt error. If the error occurred
2800 * because there was no hardware key, then
2801 * let the frame through so the upper layers
2802 * can process it. This is necessary for 5210
2803 * parts which have no way to setup a ``clear''
2804 * key cache entry.
2805 *
2806 * XXX do key cache faulting
2807 */
2808 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2809 goto rx_accept;
2810 sc->sc_stats.ast_rx_badcrypt++;
2811 }
2812 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2813 sc->sc_stats.ast_rx_badmic++;
2814 /*
2815 * Do minimal work required to hand off
2816 * the 802.11 header for notifcation.
2817 */
2818 /* XXX frag's and qos frames */
2819 len = ds->ds_rxstat.rs_datalen;
2820 if (len >= sizeof (struct ieee80211_frame)) {
2821 bus_dmamap_sync(sc->sc_dmat,
2822 bf->bf_dmamap,
2823 BUS_DMASYNC_POSTREAD);
2824 ieee80211_notify_michael_failure(ic,
2825 mtod(m, struct ieee80211_frame *),
2826 sc->sc_splitmic ?
2827 ds->ds_rxstat.rs_keyix-32 :
2828 ds->ds_rxstat.rs_keyix
2829 );
2830 }
2831 }
2832 ifp->if_ierrors++;
2833 /*
2834 * When a tap is present pass error frames
2835 * that have been requested. By default we
2836 * pass decrypt+mic errors but others may be
2837 * interesting (e.g. crc).
2838 */
2839 if (sc->sc_drvbpf != NULL &&
2840 (ds->ds_rxstat.rs_status & sc->sc_monpass)) {
2841 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2842 BUS_DMASYNC_POSTREAD);
2843 /* NB: bpf needs the mbuf length setup */
2844 len = ds->ds_rxstat.rs_datalen;
2845 m->m_pkthdr.len = m->m_len = len;
2846 (void) ath_rx_tap(sc, m, ds, tsf, nf);
2847 }
2848 /* XXX pass MIC errors up for s/w reclaculation */
2849 goto rx_next;
2850 }
2851rx_accept:
2852 /*
2853 * Sync and unmap the frame. At this point we're
2854 * committed to passing the mbuf somewhere so clear
2855 * bf_m; this means a new sk_buff must be allocated
2856 * when the rx descriptor is setup again to receive
2857 * another frame.
2858 */
2859 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2860 BUS_DMASYNC_POSTREAD);
2861 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2862 bf->bf_m = NULL;
2863
2864 m->m_pkthdr.rcvif = ifp;
2865 len = ds->ds_rxstat.rs_datalen;
2866 m->m_pkthdr.len = m->m_len = len;
2867
2868 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
2869
2870 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, ds, tsf, nf)) {
2871 m_freem(m); /* XXX reclaim */
2872 goto rx_next;
2873 }
2874
2875 /*
2876 * From this point on we assume the frame is at least
2877 * as large as ieee80211_frame_min; verify that.
2878 */
2879 if (len < IEEE80211_MIN_LEN) {
2880 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
2881 __func__, len);
2882 sc->sc_stats.ast_rx_tooshort++;
2883 m_freem(m);
2884 goto rx_next;
2885 }
2886
2887 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
2888 ieee80211_dump_pkt(mtod(m, caddr_t), len,
2889 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
2890 ds->ds_rxstat.rs_rssi);
2891 }
2892
2893 m_adj(m, -IEEE80211_CRC_LEN);
2894
2895 /*
2896 * Locate the node for sender, track state, and then
2897 * pass the (referenced) node up to the 802.11 layer
2898 * for its use.
2899 */
2900 ni = ieee80211_find_rxnode_withkey(ic,
2901 mtod(m, const struct ieee80211_frame_min *),
2902 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ?
2903 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix);
2904 /*
2905 * Track rx rssi and do any rx antenna management.
2906 */
2907 an = ATH_NODE(ni);
2908 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2909 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi);
2910 /*
2911 * Send frame up for processing.
2912 */
2913 type = ieee80211_input(ic, m, ni,
2914 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2915 ieee80211_free_node(ni);
2916 if (sc->sc_diversity) {
2917 /*
2918 * When using fast diversity, change the default rx
2919 * antenna if diversity chooses the other antenna 3
2920 * times in a row.
2921 */
2922 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
2923 if (++sc->sc_rxotherant >= 3)
2924 ath_setdefantenna(sc,
2925 ds->ds_rxstat.rs_antenna);
2926 } else
2927 sc->sc_rxotherant = 0;
2928 }
2929 if (sc->sc_softled) {
2930 /*
2931 * Blink for any data frame. Otherwise do a
2932 * heartbeat-style blink when idle. The latter
2933 * is mainly for station mode where we depend on
2934 * periodic beacon frames to trigger the poll event.
2935 */
2936 if (type == IEEE80211_FC0_TYPE_DATA) {
2937 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
2938 ath_led_event(sc, ATH_LED_RX);
2939 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
2940 ath_led_event(sc, ATH_LED_POLL);
2941 }
|
| 2942 /*
2943 * Arrange to update the last rx timestamp only for
2944 * frames from our ap when operating in station mode.
2945 * This assumes the rx key is always setup when associated.
2946 */
2947 if (ic->ic_opmode == IEEE80211_M_STA &&
2948 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID)
2949 ngood++;
|
2927rx_next:
2928 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
2929 } while (ath_rxbuf_init(sc, bf) == 0);
2930
2931 /* rx signal state monitoring */
2932 ath_hal_rxmonitor(ah, &sc->sc_halstats);
| 2950rx_next:
2951 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
2952 } while (ath_rxbuf_init(sc, bf) == 0);
2953
2954 /* rx signal state monitoring */
2955 ath_hal_rxmonitor(ah, &sc->sc_halstats);
|
| 2956 if (ngood)
2957 sc->sc_lastrx = tsf;
|
2933
2934 NET_UNLOCK_GIANT(); /* XXX */
2935#undef PA2DESC
2936}
2937
2938/*
2939 * Setup a h/w transmit queue.
2940 */
2941static struct ath_txq *
2942ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2943{
2944#define N(a) (sizeof(a)/sizeof(a[0]))
2945 struct ath_hal *ah = sc->sc_ah;
2946 HAL_TXQ_INFO qi;
2947 int qnum;
2948
2949 memset(&qi, 0, sizeof(qi));
2950 qi.tqi_subtype = subtype;
2951 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2952 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2953 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2954 /*
2955 * Enable interrupts only for EOL and DESC conditions.
2956 * We mark tx descriptors to receive a DESC interrupt
2957 * when a tx queue gets deep; otherwise waiting for the
2958 * EOL to reap descriptors. Note that this is done to
2959 * reduce interrupt load and this only defers reaping
2960 * descriptors, never transmitting frames. Aside from
2961 * reducing interrupts this also permits more concurrency.
2962 * The only potential downside is if the tx queue backs
2963 * up in which case the top half of the kernel may backup
2964 * due to a lack of tx descriptors.
2965 */
2966 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE;
2967 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
2968 if (qnum == -1) {
2969 /*
2970 * NB: don't print a message, this happens
2971 * normally on parts with too few tx queues
2972 */
2973 return NULL;
2974 }
2975 if (qnum >= N(sc->sc_txq)) {
2976 device_printf(sc->sc_dev,
2977 "hal qnum %u out of range, max %zu!\n",
2978 qnum, N(sc->sc_txq));
2979 ath_hal_releasetxqueue(ah, qnum);
2980 return NULL;
2981 }
2982 if (!ATH_TXQ_SETUP(sc, qnum)) {
2983 struct ath_txq *txq = &sc->sc_txq[qnum];
2984
2985 txq->axq_qnum = qnum;
2986 txq->axq_depth = 0;
2987 txq->axq_intrcnt = 0;
2988 txq->axq_link = NULL;
2989 STAILQ_INIT(&txq->axq_q);
2990 ATH_TXQ_LOCK_INIT(sc, txq);
2991 sc->sc_txqsetup |= 1<<qnum;
2992 }
2993 return &sc->sc_txq[qnum];
2994#undef N
2995}
2996
2997/*
2998 * Setup a hardware data transmit queue for the specified
2999 * access control. The hal may not support all requested
3000 * queues in which case it will return a reference to a
3001 * previously setup queue. We record the mapping from ac's
3002 * to h/w queues for use by ath_tx_start and also track
3003 * the set of h/w queues being used to optimize work in the
3004 * transmit interrupt handler and related routines.
3005 */
3006static int
3007ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3008{
3009#define N(a) (sizeof(a)/sizeof(a[0]))
3010 struct ath_txq *txq;
3011
3012 if (ac >= N(sc->sc_ac2q)) {
3013 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3014 ac, N(sc->sc_ac2q));
3015 return 0;
3016 }
3017 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3018 if (txq != NULL) {
3019 sc->sc_ac2q[ac] = txq;
3020 return 1;
3021 } else
3022 return 0;
3023#undef N
3024}
3025
3026/*
3027 * Update WME parameters for a transmit queue.
3028 */
3029static int
3030ath_txq_update(struct ath_softc *sc, int ac)
3031{
3032#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3033#define ATH_TXOP_TO_US(v) (v<<5)
3034 struct ieee80211com *ic = &sc->sc_ic;
3035 struct ath_txq *txq = sc->sc_ac2q[ac];
3036 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3037 struct ath_hal *ah = sc->sc_ah;
3038 HAL_TXQ_INFO qi;
3039
3040 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3041 qi.tqi_aifs = wmep->wmep_aifsn;
3042 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3043 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3044 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3045
3046 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3047 device_printf(sc->sc_dev, "unable to update hardware queue "
3048 "parameters for %s traffic!\n",
3049 ieee80211_wme_acnames[ac]);
3050 return 0;
3051 } else {
3052 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3053 return 1;
3054 }
3055#undef ATH_TXOP_TO_US
3056#undef ATH_EXPONENT_TO_VALUE
3057}
3058
3059/*
3060 * Callback from the 802.11 layer to update WME parameters.
3061 */
3062static int
3063ath_wme_update(struct ieee80211com *ic)
3064{
3065 struct ath_softc *sc = ic->ic_ifp->if_softc;
3066
3067 return !ath_txq_update(sc, WME_AC_BE) ||
3068 !ath_txq_update(sc, WME_AC_BK) ||
3069 !ath_txq_update(sc, WME_AC_VI) ||
3070 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3071}
3072
3073/*
3074 * Reclaim resources for a setup queue.
3075 */
3076static void
3077ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3078{
3079
3080 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3081 ATH_TXQ_LOCK_DESTROY(txq);
3082 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3083}
3084
3085/*
3086 * Reclaim all tx queue resources.
3087 */
3088static void
3089ath_tx_cleanup(struct ath_softc *sc)
3090{
3091 int i;
3092
3093 ATH_TXBUF_LOCK_DESTROY(sc);
3094 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3095 if (ATH_TXQ_SETUP(sc, i))
3096 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3097}
3098
3099/*
3100 * Defragment an mbuf chain, returning at most maxfrags separate
3101 * mbufs+clusters. If this is not possible NULL is returned and
3102 * the original mbuf chain is left in it's present (potentially
3103 * modified) state. We use two techniques: collapsing consecutive
3104 * mbufs and replacing consecutive mbufs by a cluster.
3105 */
3106static struct mbuf *
3107ath_defrag(struct mbuf *m0, int how, int maxfrags)
3108{
3109 struct mbuf *m, *n, *n2, **prev;
3110 u_int curfrags;
3111
3112 /*
3113 * Calculate the current number of frags.
3114 */
3115 curfrags = 0;
3116 for (m = m0; m != NULL; m = m->m_next)
3117 curfrags++;
3118 /*
3119 * First, try to collapse mbufs. Note that we always collapse
3120 * towards the front so we don't need to deal with moving the
3121 * pkthdr. This may be suboptimal if the first mbuf has much
3122 * less data than the following.
3123 */
3124 m = m0;
3125again:
3126 for (;;) {
3127 n = m->m_next;
3128 if (n == NULL)
3129 break;
3130 if ((m->m_flags & M_RDONLY) == 0 &&
3131 n->m_len < M_TRAILINGSPACE(m)) {
3132 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3133 n->m_len);
3134 m->m_len += n->m_len;
3135 m->m_next = n->m_next;
3136 m_free(n);
3137 if (--curfrags <= maxfrags)
3138 return m0;
3139 } else
3140 m = n;
3141 }
3142 KASSERT(maxfrags > 1,
3143 ("maxfrags %u, but normal collapse failed", maxfrags));
3144 /*
3145 * Collapse consecutive mbufs to a cluster.
3146 */
3147 prev = &m0->m_next; /* NB: not the first mbuf */
3148 while ((n = *prev) != NULL) {
3149 if ((n2 = n->m_next) != NULL &&
3150 n->m_len + n2->m_len < MCLBYTES) {
3151 m = m_getcl(how, MT_DATA, 0);
3152 if (m == NULL)
3153 goto bad;
3154 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3155 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3156 n2->m_len);
3157 m->m_len = n->m_len + n2->m_len;
3158 m->m_next = n2->m_next;
3159 *prev = m;
3160 m_free(n);
3161 m_free(n2);
3162 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3163 return m0;
3164 /*
3165 * Still not there, try the normal collapse
3166 * again before we allocate another cluster.
3167 */
3168 goto again;
3169 }
3170 prev = &n->m_next;
3171 }
3172 /*
3173 * No place where we can collapse to a cluster; punt.
3174 * This can occur if, for example, you request 2 frags
3175 * but the packet requires that both be clusters (we
3176 * never reallocate the first mbuf to avoid moving the
3177 * packet header).
3178 */
3179bad:
3180 return NULL;
3181}
3182
3183/*
3184 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
3185 */
3186static int
3187ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
3188{
3189 int i;
3190
3191 for (i = 0; i < rt->rateCount; i++)
3192 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
3193 return i;
3194 return 0; /* NB: lowest rate */
3195}
3196
3197static int
3198ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
3199 struct mbuf *m0)
3200{
3201 struct ieee80211com *ic = &sc->sc_ic;
3202 struct ath_hal *ah = sc->sc_ah;
3203 struct ifnet *ifp = sc->sc_ifp;
3204 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3205 int i, error, iswep, ismcast, ismrr;
3206 int keyix, hdrlen, pktlen, try0;
3207 u_int8_t rix, txrate, ctsrate;
3208 u_int8_t cix = 0xff; /* NB: silence compiler */
3209 struct ath_desc *ds, *ds0;
3210 struct ath_txq *txq;
3211 struct ieee80211_frame *wh;
3212 u_int subtype, flags, ctsduration;
3213 HAL_PKT_TYPE atype;
3214 const HAL_RATE_TABLE *rt;
3215 HAL_BOOL shortPreamble;
3216 struct ath_node *an;
3217 struct mbuf *m;
3218 u_int pri;
3219
3220 wh = mtod(m0, struct ieee80211_frame *);
3221 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3222 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3223 hdrlen = ieee80211_anyhdrsize(wh);
3224 /*
3225 * Packet length must not include any
3226 * pad bytes; deduct them here.
3227 */
3228 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3229
3230 if (iswep) {
3231 const struct ieee80211_cipher *cip;
3232 struct ieee80211_key *k;
3233
3234 /*
3235 * Construct the 802.11 header+trailer for an encrypted
3236 * frame. The only reason this can fail is because of an
3237 * unknown or unsupported cipher/key type.
3238 */
3239 k = ieee80211_crypto_encap(ic, ni, m0);
3240 if (k == NULL) {
3241 /*
3242 * This can happen when the key is yanked after the
3243 * frame was queued. Just discard the frame; the
3244 * 802.11 layer counts failures and provides
3245 * debugging/diagnostics.
3246 */
3247 m_freem(m0);
3248 return EIO;
3249 }
3250 /*
3251 * Adjust the packet + header lengths for the crypto
3252 * additions and calculate the h/w key index. When
3253 * a s/w mic is done the frame will have had any mic
3254 * added to it prior to entry so skb->len above will
3255 * account for it. Otherwise we need to add it to the
3256 * packet length.
3257 */
3258 cip = k->wk_cipher;
3259 hdrlen += cip->ic_header;
3260 pktlen += cip->ic_header + cip->ic_trailer;
3261 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3262 pktlen += cip->ic_miclen;
3263 keyix = k->wk_keyix;
3264
3265 /* packet header may have moved, reset our local pointer */
3266 wh = mtod(m0, struct ieee80211_frame *);
3267 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3268 /*
3269 * Use station key cache slot, if assigned.
3270 */
3271 keyix = ni->ni_ucastkey.wk_keyix;
3272 if (keyix == IEEE80211_KEYIX_NONE)
3273 keyix = HAL_TXKEYIX_INVALID;
3274 } else
3275 keyix = HAL_TXKEYIX_INVALID;
3276
3277 pktlen += IEEE80211_CRC_LEN;
3278
3279 /*
3280 * Load the DMA map so any coalescing is done. This
3281 * also calculates the number of descriptors we need.
3282 */
3283 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3284 bf->bf_segs, &bf->bf_nseg,
3285 BUS_DMA_NOWAIT);
3286 if (error == EFBIG) {
3287 /* XXX packet requires too many descriptors */
3288 bf->bf_nseg = ATH_TXDESC+1;
3289 } else if (error != 0) {
3290 sc->sc_stats.ast_tx_busdma++;
3291 m_freem(m0);
3292 return error;
3293 }
3294 /*
3295 * Discard null packets and check for packets that
3296 * require too many TX descriptors. We try to convert
3297 * the latter to a cluster.
3298 */
3299 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3300 sc->sc_stats.ast_tx_linear++;
3301 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC);
3302 if (m == NULL) {
3303 m_freem(m0);
3304 sc->sc_stats.ast_tx_nombuf++;
3305 return ENOMEM;
3306 }
3307 m0 = m;
3308 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3309 bf->bf_segs, &bf->bf_nseg,
3310 BUS_DMA_NOWAIT);
3311 if (error != 0) {
3312 sc->sc_stats.ast_tx_busdma++;
3313 m_freem(m0);
3314 return error;
3315 }
3316 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3317 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3318 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3319 sc->sc_stats.ast_tx_nodata++;
3320 m_freem(m0);
3321 return EIO;
3322 }
3323 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3324 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3325 bf->bf_m = m0;
3326 bf->bf_node = ni; /* NB: held reference */
3327
3328 /* setup descriptors */
3329 ds = bf->bf_desc;
3330 rt = sc->sc_currates;
3331 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3332
3333 /*
3334 * NB: the 802.11 layer marks whether or not we should
3335 * use short preamble based on the current mode and
3336 * negotiated parameters.
3337 */
3338 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3339 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3340 shortPreamble = AH_TRUE;
3341 sc->sc_stats.ast_tx_shortpre++;
3342 } else {
3343 shortPreamble = AH_FALSE;
3344 }
3345
3346 an = ATH_NODE(ni);
3347 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3348 ismrr = 0; /* default no multi-rate retry*/
3349 /*
3350 * Calculate Atheros packet type from IEEE80211 packet header,
3351 * setup for rate calculations, and select h/w transmit queue.
3352 */
3353 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3354 case IEEE80211_FC0_TYPE_MGT:
3355 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3356 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3357 atype = HAL_PKT_TYPE_BEACON;
3358 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3359 atype = HAL_PKT_TYPE_PROBE_RESP;
3360 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3361 atype = HAL_PKT_TYPE_ATIM;
3362 else
3363 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3364 rix = sc->sc_minrateix;
3365 txrate = rt->info[rix].rateCode;
3366 if (shortPreamble)
3367 txrate |= rt->info[rix].shortPreamble;
3368 try0 = ATH_TXMGTTRY;
3369 /* NB: force all management frames to highest queue */
3370 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3371 /* NB: force all management frames to highest queue */
3372 pri = WME_AC_VO;
3373 } else
3374 pri = WME_AC_BE;
3375 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3376 break;
3377 case IEEE80211_FC0_TYPE_CTL:
3378 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3379 rix = sc->sc_minrateix;
3380 txrate = rt->info[rix].rateCode;
3381 if (shortPreamble)
3382 txrate |= rt->info[rix].shortPreamble;
3383 try0 = ATH_TXMGTTRY;
3384 /* NB: force all ctl frames to highest queue */
3385 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3386 /* NB: force all ctl frames to highest queue */
3387 pri = WME_AC_VO;
3388 } else
3389 pri = WME_AC_BE;
3390 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3391 break;
3392 case IEEE80211_FC0_TYPE_DATA:
3393 atype = HAL_PKT_TYPE_NORMAL; /* default */
3394 /*
3395 * Data frames: multicast frames go out at a fixed rate,
3396 * otherwise consult the rate control module for the
3397 * rate to use.
3398 */
3399 if (ismcast) {
3400 /*
3401 * Check mcast rate setting in case it's changed.
3402 * XXX move out of fastpath
3403 */
3404 if (ic->ic_mcast_rate != sc->sc_mcastrate) {
3405 sc->sc_mcastrix =
3406 ath_tx_findrix(rt, ic->ic_mcast_rate);
3407 sc->sc_mcastrate = ic->ic_mcast_rate;
3408 }
3409 rix = sc->sc_mcastrix;
3410 txrate = rt->info[rix].rateCode;
3411 if (shortPreamble)
3412 txrate |= rt->info[rix].shortPreamble;
3413 try0 = 1;
3414 } else {
3415 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3416 &rix, &try0, &txrate);
3417 sc->sc_txrate = txrate; /* for LED blinking */
3418 if (try0 != ATH_TXMAXTRY)
3419 ismrr = 1;
3420 }
3421 /*
3422 * Default all non-QoS traffic to the background queue.
3423 */
3424 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3425 pri = M_WME_GETAC(m0);
3426 if (cap->cap_wmeParams[pri].wmep_noackPolicy) {
3427 flags |= HAL_TXDESC_NOACK;
3428 sc->sc_stats.ast_tx_noack++;
3429 }
3430 } else
3431 pri = WME_AC_BE;
3432 break;
3433 default:
3434 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3435 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3436 /* XXX statistic */
3437 m_freem(m0);
3438 return EIO;
3439 }
3440 txq = sc->sc_ac2q[pri];
3441
3442 /*
3443 * When servicing one or more stations in power-save mode
3444 * multicast frames must be buffered until after the beacon.
3445 * We use the CAB queue for that.
3446 */
3447 if (ismcast && ic->ic_ps_sta) {
3448 txq = sc->sc_cabq;
3449 /* XXX? more bit in 802.11 frame header */
3450 }
3451
3452 /*
3453 * Calculate miscellaneous flags.
3454 */
3455 if (ismcast) {
3456 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3457 sc->sc_stats.ast_tx_noack++;
3458 } else if (pktlen > ic->ic_rtsthreshold) {
3459 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3460 cix = rt->info[rix].controlRate;
3461 sc->sc_stats.ast_tx_rts++;
3462 }
3463
3464 /*
3465 * If 802.11g protection is enabled, determine whether
3466 * to use RTS/CTS or just CTS. Note that this is only
3467 * done for OFDM unicast frames.
3468 */
3469 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3470 rt->info[rix].phy == IEEE80211_T_OFDM &&
3471 (flags & HAL_TXDESC_NOACK) == 0) {
3472 /* XXX fragments must use CCK rates w/ protection */
3473 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3474 flags |= HAL_TXDESC_RTSENA;
3475 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3476 flags |= HAL_TXDESC_CTSENA;
3477 cix = rt->info[sc->sc_protrix].controlRate;
3478 sc->sc_stats.ast_tx_protect++;
3479 }
3480
3481 /*
3482 * Calculate duration. This logically belongs in the 802.11
3483 * layer but it lacks sufficient information to calculate it.
3484 */
3485 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3486 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3487 u_int16_t dur;
3488 /*
3489 * XXX not right with fragmentation.
3490 */
3491 if (shortPreamble)
3492 dur = rt->info[rix].spAckDuration;
3493 else
3494 dur = rt->info[rix].lpAckDuration;
3495 *(u_int16_t *)wh->i_dur = htole16(dur);
3496 }
3497
3498 /*
3499 * Calculate RTS/CTS rate and duration if needed.
3500 */
3501 ctsduration = 0;
3502 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3503 /*
3504 * CTS transmit rate is derived from the transmit rate
3505 * by looking in the h/w rate table. We must also factor
3506 * in whether or not a short preamble is to be used.
3507 */
3508 /* NB: cix is set above where RTS/CTS is enabled */
3509 KASSERT(cix != 0xff, ("cix not setup"));
3510 ctsrate = rt->info[cix].rateCode;
3511 /*
3512 * Compute the transmit duration based on the frame
3513 * size and the size of an ACK frame. We call into the
3514 * HAL to do the computation since it depends on the
3515 * characteristics of the actual PHY being used.
3516 *
3517 * NB: CTS is assumed the same size as an ACK so we can
3518 * use the precalculated ACK durations.
3519 */
3520 if (shortPreamble) {
3521 ctsrate |= rt->info[cix].shortPreamble;
3522 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3523 ctsduration += rt->info[cix].spAckDuration;
3524 ctsduration += ath_hal_computetxtime(ah,
3525 rt, pktlen, rix, AH_TRUE);
3526 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3527 ctsduration += rt->info[rix].spAckDuration;
3528 } else {
3529 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3530 ctsduration += rt->info[cix].lpAckDuration;
3531 ctsduration += ath_hal_computetxtime(ah,
3532 rt, pktlen, rix, AH_FALSE);
3533 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3534 ctsduration += rt->info[rix].lpAckDuration;
3535 }
3536 /*
3537 * Must disable multi-rate retry when using RTS/CTS.
3538 */
3539 ismrr = 0;
3540 try0 = ATH_TXMGTTRY; /* XXX */
3541 } else
3542 ctsrate = 0;
3543
3544 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3545 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3546 sc->sc_hwmap[txrate].ieeerate, -1);
3547
3548 if (ic->ic_rawbpf)
3549 bpf_mtap(ic->ic_rawbpf, m0);
3550 if (sc->sc_drvbpf) {
3551 u_int64_t tsf = ath_hal_gettsf64(ah);
3552
3553 sc->sc_tx_th.wt_tsf = htole64(tsf);
3554 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3555 if (iswep)
3556 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3557 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3558 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3559 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3560
3561 bpf_mtap2(sc->sc_drvbpf,
3562 &sc->sc_tx_th, sc->sc_tx_th_len, m0);
3563 }
3564
3565 /*
3566 * Determine if a tx interrupt should be generated for
3567 * this descriptor. We take a tx interrupt to reap
3568 * descriptors when the h/w hits an EOL condition or
3569 * when the descriptor is specifically marked to generate
3570 * an interrupt. We periodically mark descriptors in this
3571 * way to insure timely replenishing of the supply needed
3572 * for sending frames. Defering interrupts reduces system
3573 * load and potentially allows more concurrent work to be
3574 * done but if done to aggressively can cause senders to
3575 * backup.
3576 *
3577 * NB: use >= to deal with sc_txintrperiod changing
3578 * dynamically through sysctl.
3579 */
3580 if (flags & HAL_TXDESC_INTREQ) {
3581 txq->axq_intrcnt = 0;
3582 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3583 flags |= HAL_TXDESC_INTREQ;
3584 txq->axq_intrcnt = 0;
3585 }
3586
3587 /*
3588 * Formulate first tx descriptor with tx controls.
3589 */
3590 /* XXX check return value? */
3591 ath_hal_setuptxdesc(ah, ds
3592 , pktlen /* packet length */
3593 , hdrlen /* header length */
3594 , atype /* Atheros packet type */
3595 , ni->ni_txpower /* txpower */
3596 , txrate, try0 /* series 0 rate/tries */
3597 , keyix /* key cache index */
3598 , sc->sc_txantenna /* antenna mode */
3599 , flags /* flags */
3600 , ctsrate /* rts/cts rate */
3601 , ctsduration /* rts/cts duration */
3602 );
3603 bf->bf_flags = flags;
3604 /*
3605 * Setup the multi-rate retry state only when we're
3606 * going to use it. This assumes ath_hal_setuptxdesc
3607 * initializes the descriptors (so we don't have to)
3608 * when the hardware supports multi-rate retry and
3609 * we don't use it.
3610 */
3611 if (ismrr)
3612 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3613
3614 /*
3615 * Fillin the remainder of the descriptor info.
3616 */
3617 ds0 = ds;
3618 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3619 ds->ds_data = bf->bf_segs[i].ds_addr;
3620 if (i == bf->bf_nseg - 1)
3621 ds->ds_link = 0;
3622 else
3623 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3624 ath_hal_filltxdesc(ah, ds
3625 , bf->bf_segs[i].ds_len /* segment length */
3626 , i == 0 /* first segment */
3627 , i == bf->bf_nseg - 1 /* last segment */
3628 , ds0 /* first descriptor */
3629 );
3630 DPRINTF(sc, ATH_DEBUG_XMIT,
3631 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3632 __func__, i, ds->ds_link, ds->ds_data,
3633 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3634 }
3635 /*
3636 * Insert the frame on the outbound list and
3637 * pass it on to the hardware.
3638 */
3639 ATH_TXQ_LOCK(txq);
3640 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3641 if (txq->axq_link == NULL) {
3642 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3643 DPRINTF(sc, ATH_DEBUG_XMIT,
3644 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3645 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3646 txq->axq_depth);
3647 } else {
3648 *txq->axq_link = bf->bf_daddr;
3649 DPRINTF(sc, ATH_DEBUG_XMIT,
3650 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3651 txq->axq_qnum, txq->axq_link,
3652 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3653 }
3654 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3655 /*
3656 * The CAB queue is started from the SWBA handler since
3657 * frames only go out on DTIM and to avoid possible races.
3658 */
3659 if (txq != sc->sc_cabq)
3660 ath_hal_txstart(ah, txq->axq_qnum);
3661 ATH_TXQ_UNLOCK(txq);
3662
3663 return 0;
3664}
3665
3666/*
3667 * Process completed xmit descriptors from the specified queue.
3668 */
| 2958
2959 NET_UNLOCK_GIANT(); /* XXX */
2960#undef PA2DESC
2961}
2962
2963/*
2964 * Setup a h/w transmit queue.
2965 */
2966static struct ath_txq *
2967ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2968{
2969#define N(a) (sizeof(a)/sizeof(a[0]))
2970 struct ath_hal *ah = sc->sc_ah;
2971 HAL_TXQ_INFO qi;
2972 int qnum;
2973
2974 memset(&qi, 0, sizeof(qi));
2975 qi.tqi_subtype = subtype;
2976 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2977 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2978 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2979 /*
2980 * Enable interrupts only for EOL and DESC conditions.
2981 * We mark tx descriptors to receive a DESC interrupt
2982 * when a tx queue gets deep; otherwise waiting for the
2983 * EOL to reap descriptors. Note that this is done to
2984 * reduce interrupt load and this only defers reaping
2985 * descriptors, never transmitting frames. Aside from
2986 * reducing interrupts this also permits more concurrency.
2987 * The only potential downside is if the tx queue backs
2988 * up in which case the top half of the kernel may backup
2989 * due to a lack of tx descriptors.
2990 */
2991 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE;
2992 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
2993 if (qnum == -1) {
2994 /*
2995 * NB: don't print a message, this happens
2996 * normally on parts with too few tx queues
2997 */
2998 return NULL;
2999 }
3000 if (qnum >= N(sc->sc_txq)) {
3001 device_printf(sc->sc_dev,
3002 "hal qnum %u out of range, max %zu!\n",
3003 qnum, N(sc->sc_txq));
3004 ath_hal_releasetxqueue(ah, qnum);
3005 return NULL;
3006 }
3007 if (!ATH_TXQ_SETUP(sc, qnum)) {
3008 struct ath_txq *txq = &sc->sc_txq[qnum];
3009
3010 txq->axq_qnum = qnum;
3011 txq->axq_depth = 0;
3012 txq->axq_intrcnt = 0;
3013 txq->axq_link = NULL;
3014 STAILQ_INIT(&txq->axq_q);
3015 ATH_TXQ_LOCK_INIT(sc, txq);
3016 sc->sc_txqsetup |= 1<<qnum;
3017 }
3018 return &sc->sc_txq[qnum];
3019#undef N
3020}
3021
3022/*
3023 * Setup a hardware data transmit queue for the specified
3024 * access control. The hal may not support all requested
3025 * queues in which case it will return a reference to a
3026 * previously setup queue. We record the mapping from ac's
3027 * to h/w queues for use by ath_tx_start and also track
3028 * the set of h/w queues being used to optimize work in the
3029 * transmit interrupt handler and related routines.
3030 */
3031static int
3032ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3033{
3034#define N(a) (sizeof(a)/sizeof(a[0]))
3035 struct ath_txq *txq;
3036
3037 if (ac >= N(sc->sc_ac2q)) {
3038 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3039 ac, N(sc->sc_ac2q));
3040 return 0;
3041 }
3042 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3043 if (txq != NULL) {
3044 sc->sc_ac2q[ac] = txq;
3045 return 1;
3046 } else
3047 return 0;
3048#undef N
3049}
3050
3051/*
3052 * Update WME parameters for a transmit queue.
3053 */
3054static int
3055ath_txq_update(struct ath_softc *sc, int ac)
3056{
3057#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3058#define ATH_TXOP_TO_US(v) (v<<5)
3059 struct ieee80211com *ic = &sc->sc_ic;
3060 struct ath_txq *txq = sc->sc_ac2q[ac];
3061 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3062 struct ath_hal *ah = sc->sc_ah;
3063 HAL_TXQ_INFO qi;
3064
3065 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3066 qi.tqi_aifs = wmep->wmep_aifsn;
3067 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3068 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3069 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3070
3071 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3072 device_printf(sc->sc_dev, "unable to update hardware queue "
3073 "parameters for %s traffic!\n",
3074 ieee80211_wme_acnames[ac]);
3075 return 0;
3076 } else {
3077 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3078 return 1;
3079 }
3080#undef ATH_TXOP_TO_US
3081#undef ATH_EXPONENT_TO_VALUE
3082}
3083
3084/*
3085 * Callback from the 802.11 layer to update WME parameters.
3086 */
3087static int
3088ath_wme_update(struct ieee80211com *ic)
3089{
3090 struct ath_softc *sc = ic->ic_ifp->if_softc;
3091
3092 return !ath_txq_update(sc, WME_AC_BE) ||
3093 !ath_txq_update(sc, WME_AC_BK) ||
3094 !ath_txq_update(sc, WME_AC_VI) ||
3095 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3096}
3097
3098/*
3099 * Reclaim resources for a setup queue.
3100 */
3101static void
3102ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3103{
3104
3105 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3106 ATH_TXQ_LOCK_DESTROY(txq);
3107 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3108}
3109
3110/*
3111 * Reclaim all tx queue resources.
3112 */
3113static void
3114ath_tx_cleanup(struct ath_softc *sc)
3115{
3116 int i;
3117
3118 ATH_TXBUF_LOCK_DESTROY(sc);
3119 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3120 if (ATH_TXQ_SETUP(sc, i))
3121 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3122}
3123
3124/*
3125 * Defragment an mbuf chain, returning at most maxfrags separate
3126 * mbufs+clusters. If this is not possible NULL is returned and
3127 * the original mbuf chain is left in it's present (potentially
3128 * modified) state. We use two techniques: collapsing consecutive
3129 * mbufs and replacing consecutive mbufs by a cluster.
3130 */
3131static struct mbuf *
3132ath_defrag(struct mbuf *m0, int how, int maxfrags)
3133{
3134 struct mbuf *m, *n, *n2, **prev;
3135 u_int curfrags;
3136
3137 /*
3138 * Calculate the current number of frags.
3139 */
3140 curfrags = 0;
3141 for (m = m0; m != NULL; m = m->m_next)
3142 curfrags++;
3143 /*
3144 * First, try to collapse mbufs. Note that we always collapse
3145 * towards the front so we don't need to deal with moving the
3146 * pkthdr. This may be suboptimal if the first mbuf has much
3147 * less data than the following.
3148 */
3149 m = m0;
3150again:
3151 for (;;) {
3152 n = m->m_next;
3153 if (n == NULL)
3154 break;
3155 if ((m->m_flags & M_RDONLY) == 0 &&
3156 n->m_len < M_TRAILINGSPACE(m)) {
3157 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3158 n->m_len);
3159 m->m_len += n->m_len;
3160 m->m_next = n->m_next;
3161 m_free(n);
3162 if (--curfrags <= maxfrags)
3163 return m0;
3164 } else
3165 m = n;
3166 }
3167 KASSERT(maxfrags > 1,
3168 ("maxfrags %u, but normal collapse failed", maxfrags));
3169 /*
3170 * Collapse consecutive mbufs to a cluster.
3171 */
3172 prev = &m0->m_next; /* NB: not the first mbuf */
3173 while ((n = *prev) != NULL) {
3174 if ((n2 = n->m_next) != NULL &&
3175 n->m_len + n2->m_len < MCLBYTES) {
3176 m = m_getcl(how, MT_DATA, 0);
3177 if (m == NULL)
3178 goto bad;
3179 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3180 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3181 n2->m_len);
3182 m->m_len = n->m_len + n2->m_len;
3183 m->m_next = n2->m_next;
3184 *prev = m;
3185 m_free(n);
3186 m_free(n2);
3187 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3188 return m0;
3189 /*
3190 * Still not there, try the normal collapse
3191 * again before we allocate another cluster.
3192 */
3193 goto again;
3194 }
3195 prev = &n->m_next;
3196 }
3197 /*
3198 * No place where we can collapse to a cluster; punt.
3199 * This can occur if, for example, you request 2 frags
3200 * but the packet requires that both be clusters (we
3201 * never reallocate the first mbuf to avoid moving the
3202 * packet header).
3203 */
3204bad:
3205 return NULL;
3206}
3207
3208/*
3209 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
3210 */
3211static int
3212ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
3213{
3214 int i;
3215
3216 for (i = 0; i < rt->rateCount; i++)
3217 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
3218 return i;
3219 return 0; /* NB: lowest rate */
3220}
3221
3222static int
3223ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
3224 struct mbuf *m0)
3225{
3226 struct ieee80211com *ic = &sc->sc_ic;
3227 struct ath_hal *ah = sc->sc_ah;
3228 struct ifnet *ifp = sc->sc_ifp;
3229 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3230 int i, error, iswep, ismcast, ismrr;
3231 int keyix, hdrlen, pktlen, try0;
3232 u_int8_t rix, txrate, ctsrate;
3233 u_int8_t cix = 0xff; /* NB: silence compiler */
3234 struct ath_desc *ds, *ds0;
3235 struct ath_txq *txq;
3236 struct ieee80211_frame *wh;
3237 u_int subtype, flags, ctsduration;
3238 HAL_PKT_TYPE atype;
3239 const HAL_RATE_TABLE *rt;
3240 HAL_BOOL shortPreamble;
3241 struct ath_node *an;
3242 struct mbuf *m;
3243 u_int pri;
3244
3245 wh = mtod(m0, struct ieee80211_frame *);
3246 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3247 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3248 hdrlen = ieee80211_anyhdrsize(wh);
3249 /*
3250 * Packet length must not include any
3251 * pad bytes; deduct them here.
3252 */
3253 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3254
3255 if (iswep) {
3256 const struct ieee80211_cipher *cip;
3257 struct ieee80211_key *k;
3258
3259 /*
3260 * Construct the 802.11 header+trailer for an encrypted
3261 * frame. The only reason this can fail is because of an
3262 * unknown or unsupported cipher/key type.
3263 */
3264 k = ieee80211_crypto_encap(ic, ni, m0);
3265 if (k == NULL) {
3266 /*
3267 * This can happen when the key is yanked after the
3268 * frame was queued. Just discard the frame; the
3269 * 802.11 layer counts failures and provides
3270 * debugging/diagnostics.
3271 */
3272 m_freem(m0);
3273 return EIO;
3274 }
3275 /*
3276 * Adjust the packet + header lengths for the crypto
3277 * additions and calculate the h/w key index. When
3278 * a s/w mic is done the frame will have had any mic
3279 * added to it prior to entry so skb->len above will
3280 * account for it. Otherwise we need to add it to the
3281 * packet length.
3282 */
3283 cip = k->wk_cipher;
3284 hdrlen += cip->ic_header;
3285 pktlen += cip->ic_header + cip->ic_trailer;
3286 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3287 pktlen += cip->ic_miclen;
3288 keyix = k->wk_keyix;
3289
3290 /* packet header may have moved, reset our local pointer */
3291 wh = mtod(m0, struct ieee80211_frame *);
3292 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3293 /*
3294 * Use station key cache slot, if assigned.
3295 */
3296 keyix = ni->ni_ucastkey.wk_keyix;
3297 if (keyix == IEEE80211_KEYIX_NONE)
3298 keyix = HAL_TXKEYIX_INVALID;
3299 } else
3300 keyix = HAL_TXKEYIX_INVALID;
3301
3302 pktlen += IEEE80211_CRC_LEN;
3303
3304 /*
3305 * Load the DMA map so any coalescing is done. This
3306 * also calculates the number of descriptors we need.
3307 */
3308 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3309 bf->bf_segs, &bf->bf_nseg,
3310 BUS_DMA_NOWAIT);
3311 if (error == EFBIG) {
3312 /* XXX packet requires too many descriptors */
3313 bf->bf_nseg = ATH_TXDESC+1;
3314 } else if (error != 0) {
3315 sc->sc_stats.ast_tx_busdma++;
3316 m_freem(m0);
3317 return error;
3318 }
3319 /*
3320 * Discard null packets and check for packets that
3321 * require too many TX descriptors. We try to convert
3322 * the latter to a cluster.
3323 */
3324 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3325 sc->sc_stats.ast_tx_linear++;
3326 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC);
3327 if (m == NULL) {
3328 m_freem(m0);
3329 sc->sc_stats.ast_tx_nombuf++;
3330 return ENOMEM;
3331 }
3332 m0 = m;
3333 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3334 bf->bf_segs, &bf->bf_nseg,
3335 BUS_DMA_NOWAIT);
3336 if (error != 0) {
3337 sc->sc_stats.ast_tx_busdma++;
3338 m_freem(m0);
3339 return error;
3340 }
3341 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3342 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3343 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3344 sc->sc_stats.ast_tx_nodata++;
3345 m_freem(m0);
3346 return EIO;
3347 }
3348 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3349 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3350 bf->bf_m = m0;
3351 bf->bf_node = ni; /* NB: held reference */
3352
3353 /* setup descriptors */
3354 ds = bf->bf_desc;
3355 rt = sc->sc_currates;
3356 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3357
3358 /*
3359 * NB: the 802.11 layer marks whether or not we should
3360 * use short preamble based on the current mode and
3361 * negotiated parameters.
3362 */
3363 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3364 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3365 shortPreamble = AH_TRUE;
3366 sc->sc_stats.ast_tx_shortpre++;
3367 } else {
3368 shortPreamble = AH_FALSE;
3369 }
3370
3371 an = ATH_NODE(ni);
3372 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3373 ismrr = 0; /* default no multi-rate retry*/
3374 /*
3375 * Calculate Atheros packet type from IEEE80211 packet header,
3376 * setup for rate calculations, and select h/w transmit queue.
3377 */
3378 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3379 case IEEE80211_FC0_TYPE_MGT:
3380 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3381 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3382 atype = HAL_PKT_TYPE_BEACON;
3383 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3384 atype = HAL_PKT_TYPE_PROBE_RESP;
3385 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3386 atype = HAL_PKT_TYPE_ATIM;
3387 else
3388 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3389 rix = sc->sc_minrateix;
3390 txrate = rt->info[rix].rateCode;
3391 if (shortPreamble)
3392 txrate |= rt->info[rix].shortPreamble;
3393 try0 = ATH_TXMGTTRY;
3394 /* NB: force all management frames to highest queue */
3395 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3396 /* NB: force all management frames to highest queue */
3397 pri = WME_AC_VO;
3398 } else
3399 pri = WME_AC_BE;
3400 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3401 break;
3402 case IEEE80211_FC0_TYPE_CTL:
3403 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3404 rix = sc->sc_minrateix;
3405 txrate = rt->info[rix].rateCode;
3406 if (shortPreamble)
3407 txrate |= rt->info[rix].shortPreamble;
3408 try0 = ATH_TXMGTTRY;
3409 /* NB: force all ctl frames to highest queue */
3410 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3411 /* NB: force all ctl frames to highest queue */
3412 pri = WME_AC_VO;
3413 } else
3414 pri = WME_AC_BE;
3415 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3416 break;
3417 case IEEE80211_FC0_TYPE_DATA:
3418 atype = HAL_PKT_TYPE_NORMAL; /* default */
3419 /*
3420 * Data frames: multicast frames go out at a fixed rate,
3421 * otherwise consult the rate control module for the
3422 * rate to use.
3423 */
3424 if (ismcast) {
3425 /*
3426 * Check mcast rate setting in case it's changed.
3427 * XXX move out of fastpath
3428 */
3429 if (ic->ic_mcast_rate != sc->sc_mcastrate) {
3430 sc->sc_mcastrix =
3431 ath_tx_findrix(rt, ic->ic_mcast_rate);
3432 sc->sc_mcastrate = ic->ic_mcast_rate;
3433 }
3434 rix = sc->sc_mcastrix;
3435 txrate = rt->info[rix].rateCode;
3436 if (shortPreamble)
3437 txrate |= rt->info[rix].shortPreamble;
3438 try0 = 1;
3439 } else {
3440 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3441 &rix, &try0, &txrate);
3442 sc->sc_txrate = txrate; /* for LED blinking */
3443 if (try0 != ATH_TXMAXTRY)
3444 ismrr = 1;
3445 }
3446 /*
3447 * Default all non-QoS traffic to the background queue.
3448 */
3449 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3450 pri = M_WME_GETAC(m0);
3451 if (cap->cap_wmeParams[pri].wmep_noackPolicy) {
3452 flags |= HAL_TXDESC_NOACK;
3453 sc->sc_stats.ast_tx_noack++;
3454 }
3455 } else
3456 pri = WME_AC_BE;
3457 break;
3458 default:
3459 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3460 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3461 /* XXX statistic */
3462 m_freem(m0);
3463 return EIO;
3464 }
3465 txq = sc->sc_ac2q[pri];
3466
3467 /*
3468 * When servicing one or more stations in power-save mode
3469 * multicast frames must be buffered until after the beacon.
3470 * We use the CAB queue for that.
3471 */
3472 if (ismcast && ic->ic_ps_sta) {
3473 txq = sc->sc_cabq;
3474 /* XXX? more bit in 802.11 frame header */
3475 }
3476
3477 /*
3478 * Calculate miscellaneous flags.
3479 */
3480 if (ismcast) {
3481 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3482 sc->sc_stats.ast_tx_noack++;
3483 } else if (pktlen > ic->ic_rtsthreshold) {
3484 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3485 cix = rt->info[rix].controlRate;
3486 sc->sc_stats.ast_tx_rts++;
3487 }
3488
3489 /*
3490 * If 802.11g protection is enabled, determine whether
3491 * to use RTS/CTS or just CTS. Note that this is only
3492 * done for OFDM unicast frames.
3493 */
3494 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3495 rt->info[rix].phy == IEEE80211_T_OFDM &&
3496 (flags & HAL_TXDESC_NOACK) == 0) {
3497 /* XXX fragments must use CCK rates w/ protection */
3498 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3499 flags |= HAL_TXDESC_RTSENA;
3500 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3501 flags |= HAL_TXDESC_CTSENA;
3502 cix = rt->info[sc->sc_protrix].controlRate;
3503 sc->sc_stats.ast_tx_protect++;
3504 }
3505
3506 /*
3507 * Calculate duration. This logically belongs in the 802.11
3508 * layer but it lacks sufficient information to calculate it.
3509 */
3510 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3511 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3512 u_int16_t dur;
3513 /*
3514 * XXX not right with fragmentation.
3515 */
3516 if (shortPreamble)
3517 dur = rt->info[rix].spAckDuration;
3518 else
3519 dur = rt->info[rix].lpAckDuration;
3520 *(u_int16_t *)wh->i_dur = htole16(dur);
3521 }
3522
3523 /*
3524 * Calculate RTS/CTS rate and duration if needed.
3525 */
3526 ctsduration = 0;
3527 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3528 /*
3529 * CTS transmit rate is derived from the transmit rate
3530 * by looking in the h/w rate table. We must also factor
3531 * in whether or not a short preamble is to be used.
3532 */
3533 /* NB: cix is set above where RTS/CTS is enabled */
3534 KASSERT(cix != 0xff, ("cix not setup"));
3535 ctsrate = rt->info[cix].rateCode;
3536 /*
3537 * Compute the transmit duration based on the frame
3538 * size and the size of an ACK frame. We call into the
3539 * HAL to do the computation since it depends on the
3540 * characteristics of the actual PHY being used.
3541 *
3542 * NB: CTS is assumed the same size as an ACK so we can
3543 * use the precalculated ACK durations.
3544 */
3545 if (shortPreamble) {
3546 ctsrate |= rt->info[cix].shortPreamble;
3547 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3548 ctsduration += rt->info[cix].spAckDuration;
3549 ctsduration += ath_hal_computetxtime(ah,
3550 rt, pktlen, rix, AH_TRUE);
3551 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3552 ctsduration += rt->info[rix].spAckDuration;
3553 } else {
3554 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3555 ctsduration += rt->info[cix].lpAckDuration;
3556 ctsduration += ath_hal_computetxtime(ah,
3557 rt, pktlen, rix, AH_FALSE);
3558 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3559 ctsduration += rt->info[rix].lpAckDuration;
3560 }
3561 /*
3562 * Must disable multi-rate retry when using RTS/CTS.
3563 */
3564 ismrr = 0;
3565 try0 = ATH_TXMGTTRY; /* XXX */
3566 } else
3567 ctsrate = 0;
3568
3569 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3570 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3571 sc->sc_hwmap[txrate].ieeerate, -1);
3572
3573 if (ic->ic_rawbpf)
3574 bpf_mtap(ic->ic_rawbpf, m0);
3575 if (sc->sc_drvbpf) {
3576 u_int64_t tsf = ath_hal_gettsf64(ah);
3577
3578 sc->sc_tx_th.wt_tsf = htole64(tsf);
3579 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3580 if (iswep)
3581 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3582 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3583 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3584 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3585
3586 bpf_mtap2(sc->sc_drvbpf,
3587 &sc->sc_tx_th, sc->sc_tx_th_len, m0);
3588 }
3589
3590 /*
3591 * Determine if a tx interrupt should be generated for
3592 * this descriptor. We take a tx interrupt to reap
3593 * descriptors when the h/w hits an EOL condition or
3594 * when the descriptor is specifically marked to generate
3595 * an interrupt. We periodically mark descriptors in this
3596 * way to insure timely replenishing of the supply needed
3597 * for sending frames. Defering interrupts reduces system
3598 * load and potentially allows more concurrent work to be
3599 * done but if done to aggressively can cause senders to
3600 * backup.
3601 *
3602 * NB: use >= to deal with sc_txintrperiod changing
3603 * dynamically through sysctl.
3604 */
3605 if (flags & HAL_TXDESC_INTREQ) {
3606 txq->axq_intrcnt = 0;
3607 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3608 flags |= HAL_TXDESC_INTREQ;
3609 txq->axq_intrcnt = 0;
3610 }
3611
3612 /*
3613 * Formulate first tx descriptor with tx controls.
3614 */
3615 /* XXX check return value? */
3616 ath_hal_setuptxdesc(ah, ds
3617 , pktlen /* packet length */
3618 , hdrlen /* header length */
3619 , atype /* Atheros packet type */
3620 , ni->ni_txpower /* txpower */
3621 , txrate, try0 /* series 0 rate/tries */
3622 , keyix /* key cache index */
3623 , sc->sc_txantenna /* antenna mode */
3624 , flags /* flags */
3625 , ctsrate /* rts/cts rate */
3626 , ctsduration /* rts/cts duration */
3627 );
3628 bf->bf_flags = flags;
3629 /*
3630 * Setup the multi-rate retry state only when we're
3631 * going to use it. This assumes ath_hal_setuptxdesc
3632 * initializes the descriptors (so we don't have to)
3633 * when the hardware supports multi-rate retry and
3634 * we don't use it.
3635 */
3636 if (ismrr)
3637 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3638
3639 /*
3640 * Fillin the remainder of the descriptor info.
3641 */
3642 ds0 = ds;
3643 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3644 ds->ds_data = bf->bf_segs[i].ds_addr;
3645 if (i == bf->bf_nseg - 1)
3646 ds->ds_link = 0;
3647 else
3648 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3649 ath_hal_filltxdesc(ah, ds
3650 , bf->bf_segs[i].ds_len /* segment length */
3651 , i == 0 /* first segment */
3652 , i == bf->bf_nseg - 1 /* last segment */
3653 , ds0 /* first descriptor */
3654 );
3655 DPRINTF(sc, ATH_DEBUG_XMIT,
3656 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3657 __func__, i, ds->ds_link, ds->ds_data,
3658 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3659 }
3660 /*
3661 * Insert the frame on the outbound list and
3662 * pass it on to the hardware.
3663 */
3664 ATH_TXQ_LOCK(txq);
3665 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3666 if (txq->axq_link == NULL) {
3667 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3668 DPRINTF(sc, ATH_DEBUG_XMIT,
3669 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3670 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3671 txq->axq_depth);
3672 } else {
3673 *txq->axq_link = bf->bf_daddr;
3674 DPRINTF(sc, ATH_DEBUG_XMIT,
3675 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3676 txq->axq_qnum, txq->axq_link,
3677 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3678 }
3679 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3680 /*
3681 * The CAB queue is started from the SWBA handler since
3682 * frames only go out on DTIM and to avoid possible races.
3683 */
3684 if (txq != sc->sc_cabq)
3685 ath_hal_txstart(ah, txq->axq_qnum);
3686 ATH_TXQ_UNLOCK(txq);
3687
3688 return 0;
3689}
3690
3691/*
3692 * Process completed xmit descriptors from the specified queue.
3693 */
|
3669static void
| 3694static int
|
3670ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3671{
3672 struct ath_hal *ah = sc->sc_ah;
3673 struct ieee80211com *ic = &sc->sc_ic;
3674 struct ath_buf *bf;
3675 struct ath_desc *ds, *ds0;
3676 struct ieee80211_node *ni;
3677 struct ath_node *an;
| 3695ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3696{
3697 struct ath_hal *ah = sc->sc_ah;
3698 struct ieee80211com *ic = &sc->sc_ic;
3699 struct ath_buf *bf;
3700 struct ath_desc *ds, *ds0;
3701 struct ieee80211_node *ni;
3702 struct ath_node *an;
|
3678 int sr, lr, pri;
| 3703 int sr, lr, pri, nacked;
|
3679 HAL_STATUS status;
3680
3681 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3682 __func__, txq->axq_qnum,
3683 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3684 txq->axq_link);
| 3704 HAL_STATUS status;
3705
3706 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3707 __func__, txq->axq_qnum,
3708 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3709 txq->axq_link);
|
| 3710 nacked = 0;
|
3685 for (;;) {
3686 ATH_TXQ_LOCK(txq);
3687 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3688 bf = STAILQ_FIRST(&txq->axq_q);
3689 if (bf == NULL) {
3690 txq->axq_link = NULL;
3691 ATH_TXQ_UNLOCK(txq);
3692 break;
3693 }
3694 ds0 = &bf->bf_desc[0];
3695 ds = &bf->bf_desc[bf->bf_nseg - 1];
3696 status = ath_hal_txprocdesc(ah, ds);
3697#ifdef AR_DEBUG
3698 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3699 ath_printtxbuf(bf, status == HAL_OK);
3700#endif
3701 if (status == HAL_EINPROGRESS) {
3702 ATH_TXQ_UNLOCK(txq);
3703 break;
3704 }
3705 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3706 ATH_TXQ_UNLOCK(txq);
3707
3708 ni = bf->bf_node;
3709 if (ni != NULL) {
3710 an = ATH_NODE(ni);
3711 if (ds->ds_txstat.ts_status == 0) {
3712 u_int8_t txant = ds->ds_txstat.ts_antenna;
3713 sc->sc_stats.ast_ant_tx[txant]++;
3714 sc->sc_ant_tx[txant]++;
3715 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3716 sc->sc_stats.ast_tx_altrate++;
3717 sc->sc_stats.ast_tx_rssi =
3718 ds->ds_txstat.ts_rssi;
3719 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3720 ds->ds_txstat.ts_rssi);
3721 pri = M_WME_GETAC(bf->bf_m);
3722 if (pri >= WME_AC_VO)
3723 ic->ic_wme.wme_hipri_traffic++;
3724 ni->ni_inact = ni->ni_inact_reload;
3725 } else {
3726 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3727 sc->sc_stats.ast_tx_xretries++;
3728 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3729 sc->sc_stats.ast_tx_fifoerr++;
3730 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3731 sc->sc_stats.ast_tx_filtered++;
3732 }
3733 sr = ds->ds_txstat.ts_shortretry;
3734 lr = ds->ds_txstat.ts_longretry;
3735 sc->sc_stats.ast_tx_shortretry += sr;
3736 sc->sc_stats.ast_tx_longretry += lr;
3737 /*
3738 * Hand the descriptor to the rate control algorithm.
3739 */
3740 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
| 3711 for (;;) {
3712 ATH_TXQ_LOCK(txq);
3713 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3714 bf = STAILQ_FIRST(&txq->axq_q);
3715 if (bf == NULL) {
3716 txq->axq_link = NULL;
3717 ATH_TXQ_UNLOCK(txq);
3718 break;
3719 }
3720 ds0 = &bf->bf_desc[0];
3721 ds = &bf->bf_desc[bf->bf_nseg - 1];
3722 status = ath_hal_txprocdesc(ah, ds);
3723#ifdef AR_DEBUG
3724 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3725 ath_printtxbuf(bf, status == HAL_OK);
3726#endif
3727 if (status == HAL_EINPROGRESS) {
3728 ATH_TXQ_UNLOCK(txq);
3729 break;
3730 }
3731 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3732 ATH_TXQ_UNLOCK(txq);
3733
3734 ni = bf->bf_node;
3735 if (ni != NULL) {
3736 an = ATH_NODE(ni);
3737 if (ds->ds_txstat.ts_status == 0) {
3738 u_int8_t txant = ds->ds_txstat.ts_antenna;
3739 sc->sc_stats.ast_ant_tx[txant]++;
3740 sc->sc_ant_tx[txant]++;
3741 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3742 sc->sc_stats.ast_tx_altrate++;
3743 sc->sc_stats.ast_tx_rssi =
3744 ds->ds_txstat.ts_rssi;
3745 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3746 ds->ds_txstat.ts_rssi);
3747 pri = M_WME_GETAC(bf->bf_m);
3748 if (pri >= WME_AC_VO)
3749 ic->ic_wme.wme_hipri_traffic++;
3750 ni->ni_inact = ni->ni_inact_reload;
3751 } else {
3752 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3753 sc->sc_stats.ast_tx_xretries++;
3754 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3755 sc->sc_stats.ast_tx_fifoerr++;
3756 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3757 sc->sc_stats.ast_tx_filtered++;
3758 }
3759 sr = ds->ds_txstat.ts_shortretry;
3760 lr = ds->ds_txstat.ts_longretry;
3761 sc->sc_stats.ast_tx_shortretry += sr;
3762 sc->sc_stats.ast_tx_longretry += lr;
3763 /*
3764 * Hand the descriptor to the rate control algorithm.
3765 */
3766 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
|
3741 (bf->bf_flags & HAL_TXDESC_NOACK) == 0)
| 3767 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3768 /*
3769 * If frame was ack'd update the last rx time
3770 * used to workaround phantom bmiss interrupts.
3771 */
3772 if (ds->ds_txstat.ts_status == 0)
3773 nacked++;
|
3742 ath_rate_tx_complete(sc, an, ds, ds0);
| 3774 ath_rate_tx_complete(sc, an, ds, ds0);
|
| 3775 }
|
3743 /*
3744 * Reclaim reference to node.
3745 *
3746 * NB: the node may be reclaimed here if, for example
3747 * this is a DEAUTH message that was sent and the
3748 * node was timed out due to inactivity.
3749 */
3750 ieee80211_free_node(ni);
3751 }
3752 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3753 BUS_DMASYNC_POSTWRITE);
3754 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3755 m_freem(bf->bf_m);
3756 bf->bf_m = NULL;
3757 bf->bf_node = NULL;
3758
3759 ATH_TXBUF_LOCK(sc);
3760 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3761 ATH_TXBUF_UNLOCK(sc);
3762 }
| 3776 /*
3777 * Reclaim reference to node.
3778 *
3779 * NB: the node may be reclaimed here if, for example
3780 * this is a DEAUTH message that was sent and the
3781 * node was timed out due to inactivity.
3782 */
3783 ieee80211_free_node(ni);
3784 }
3785 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3786 BUS_DMASYNC_POSTWRITE);
3787 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3788 m_freem(bf->bf_m);
3789 bf->bf_m = NULL;
3790 bf->bf_node = NULL;
3791
3792 ATH_TXBUF_LOCK(sc);
3793 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3794 ATH_TXBUF_UNLOCK(sc);
3795 }
|
| 3796 return nacked;
|
3763}
3764
| 3797}
3798
|
| 3799static __inline int
3800txqactive(struct ath_hal *ah, int qnum)
3801{
3802 /* XXX not yet */
3803 return 1;
3804}
3805
|
3765/*
3766 * Deferred processing of transmit interrupt; special-cased
3767 * for a single hardware transmit queue (e.g. 5210 and 5211).
3768 */
3769static void
3770ath_tx_proc_q0(void *arg, int npending)
3771{
3772 struct ath_softc *sc = arg;
3773 struct ifnet *ifp = sc->sc_ifp;
3774
| 3806/*
3807 * Deferred processing of transmit interrupt; special-cased
3808 * for a single hardware transmit queue (e.g. 5210 and 5211).
3809 */
3810static void
3811ath_tx_proc_q0(void *arg, int npending)
3812{
3813 struct ath_softc *sc = arg;
3814 struct ifnet *ifp = sc->sc_ifp;
3815
|
3775 ath_tx_processq(sc, &sc->sc_txq[0]);
| 3816 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
3817 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3818 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
3819 ath_tx_processq(sc, sc->sc_cabq);
|
3776 ath_tx_processq(sc, sc->sc_cabq);
3777 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3778 sc->sc_tx_timer = 0;
3779
3780 if (sc->sc_softled)
3781 ath_led_event(sc, ATH_LED_TX);
3782
3783 ath_start(ifp);
3784}
3785
3786/*
3787 * Deferred processing of transmit interrupt; special-cased
3788 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3789 */
3790static void
3791ath_tx_proc_q0123(void *arg, int npending)
3792{
3793 struct ath_softc *sc = arg;
3794 struct ifnet *ifp = sc->sc_ifp;
| 3820 ath_tx_processq(sc, sc->sc_cabq);
3821 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3822 sc->sc_tx_timer = 0;
3823
3824 if (sc->sc_softled)
3825 ath_led_event(sc, ATH_LED_TX);
3826
3827 ath_start(ifp);
3828}
3829
3830/*
3831 * Deferred processing of transmit interrupt; special-cased
3832 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3833 */
3834static void
3835ath_tx_proc_q0123(void *arg, int npending)
3836{
3837 struct ath_softc *sc = arg;
3838 struct ifnet *ifp = sc->sc_ifp;
|
| 3839 int nacked;
|
3795
3796 /*
3797 * Process each active queue.
3798 */
| 3840
3841 /*
3842 * Process each active queue.
3843 */
|
3799 ath_tx_processq(sc, &sc->sc_txq[0]);
3800 ath_tx_processq(sc, &sc->sc_txq[1]);
3801 ath_tx_processq(sc, &sc->sc_txq[2]);
3802 ath_tx_processq(sc, &sc->sc_txq[3]);
3803 ath_tx_processq(sc, sc->sc_cabq);
| 3844 nacked = 0;
3845 if (txqactive(sc->sc_ah, 0))
3846 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
3847 if (txqactive(sc->sc_ah, 1))
3848 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
3849 if (txqactive(sc->sc_ah, 2))
3850 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
3851 if (txqactive(sc->sc_ah, 3))
3852 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
3853 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
3854 ath_tx_processq(sc, sc->sc_cabq);
3855 if (nacked)
3856 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
|
3804
3805 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3806 sc->sc_tx_timer = 0;
3807
3808 if (sc->sc_softled)
3809 ath_led_event(sc, ATH_LED_TX);
3810
3811 ath_start(ifp);
3812}
3813
3814/*
3815 * Deferred processing of transmit interrupt.
3816 */
3817static void
3818ath_tx_proc(void *arg, int npending)
3819{
3820 struct ath_softc *sc = arg;
3821 struct ifnet *ifp = sc->sc_ifp;
| 3857
3858 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3859 sc->sc_tx_timer = 0;
3860
3861 if (sc->sc_softled)
3862 ath_led_event(sc, ATH_LED_TX);
3863
3864 ath_start(ifp);
3865}
3866
3867/*
3868 * Deferred processing of transmit interrupt.
3869 */
3870static void
3871ath_tx_proc(void *arg, int npending)
3872{
3873 struct ath_softc *sc = arg;
3874 struct ifnet *ifp = sc->sc_ifp;
|
3822 int i;
| 3875 int i, nacked;
|
3823
3824 /*
3825 * Process each active queue.
3826 */
| 3876
3877 /*
3878 * Process each active queue.
3879 */
|
3827 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */
| 3880 nacked = 0;
|
3828 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
| 3881 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
|
3829 if (ATH_TXQ_SETUP(sc, i))
3830 ath_tx_processq(sc, &sc->sc_txq[i]);
| 3882 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
3883 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
3884 if (nacked)
3885 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
|
3831
3832 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3833 sc->sc_tx_timer = 0;
3834
3835 if (sc->sc_softled)
3836 ath_led_event(sc, ATH_LED_TX);
3837
3838 ath_start(ifp);
3839}
3840
3841static void
3842ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
3843{
3844 struct ath_hal *ah = sc->sc_ah;
3845 struct ieee80211_node *ni;
3846 struct ath_buf *bf;
3847
3848 /*
3849 * NB: this assumes output has been stopped and
3850 * we do not need to block ath_tx_tasklet
3851 */
3852 for (;;) {
3853 ATH_TXQ_LOCK(txq);
3854 bf = STAILQ_FIRST(&txq->axq_q);
3855 if (bf == NULL) {
3856 txq->axq_link = NULL;
3857 ATH_TXQ_UNLOCK(txq);
3858 break;
3859 }
3860 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3861 ATH_TXQ_UNLOCK(txq);
3862#ifdef AR_DEBUG
3863 if (sc->sc_debug & ATH_DEBUG_RESET)
3864 ath_printtxbuf(bf,
3865 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
3866#endif /* AR_DEBUG */
3867 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3868 m_freem(bf->bf_m);
3869 bf->bf_m = NULL;
3870 ni = bf->bf_node;
3871 bf->bf_node = NULL;
3872 if (ni != NULL) {
3873 /*
3874 * Reclaim node reference.
3875 */
3876 ieee80211_free_node(ni);
3877 }
3878 ATH_TXBUF_LOCK(sc);
3879 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3880 ATH_TXBUF_UNLOCK(sc);
3881 }
3882}
3883
3884static void
3885ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
3886{
3887 struct ath_hal *ah = sc->sc_ah;
3888
3889 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
3890 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
3891 __func__, txq->axq_qnum,
3892 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
3893 txq->axq_link);
3894}
3895
3896/*
3897 * Drain the transmit queues and reclaim resources.
3898 */
3899static void
3900ath_draintxq(struct ath_softc *sc)
3901{
3902 struct ath_hal *ah = sc->sc_ah;
3903 struct ifnet *ifp = sc->sc_ifp;
3904 int i;
3905
3906 /* XXX return value */
3907 if (!sc->sc_invalid) {
3908 /* don't touch the hardware if marked invalid */
3909 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
3910 DPRINTF(sc, ATH_DEBUG_RESET,
3911 "%s: beacon queue %p\n", __func__,
3912 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
3913 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3914 if (ATH_TXQ_SETUP(sc, i))
3915 ath_tx_stopdma(sc, &sc->sc_txq[i]);
3916 }
3917 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3918 if (ATH_TXQ_SETUP(sc, i))
3919 ath_tx_draintxq(sc, &sc->sc_txq[i]);
3920 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3921 sc->sc_tx_timer = 0;
3922}
3923
3924/*
3925 * Disable the receive h/w in preparation for a reset.
3926 */
3927static void
3928ath_stoprecv(struct ath_softc *sc)
3929{
3930#define PA2DESC(_sc, _pa) \
3931 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3932 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3933 struct ath_hal *ah = sc->sc_ah;
3934
3935 ath_hal_stoppcurecv(ah); /* disable PCU */
3936 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
3937 ath_hal_stopdmarecv(ah); /* disable DMA engine */
3938 DELAY(3000); /* 3ms is long enough for 1 frame */
3939#ifdef AR_DEBUG
3940 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
3941 struct ath_buf *bf;
3942
3943 printf("%s: rx queue %p, link %p\n", __func__,
3944 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
3945 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
3946 struct ath_desc *ds = bf->bf_desc;
3947 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
3948 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
3949 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
3950 ath_printrxbuf(bf, status == HAL_OK);
3951 }
3952 }
3953#endif
3954 sc->sc_rxlink = NULL; /* just in case */
3955#undef PA2DESC
3956}
3957
3958/*
3959 * Enable the receive h/w following a reset.
3960 */
3961static int
3962ath_startrecv(struct ath_softc *sc)
3963{
3964 struct ath_hal *ah = sc->sc_ah;
3965 struct ath_buf *bf;
3966
3967 sc->sc_rxlink = NULL;
3968 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
3969 int error = ath_rxbuf_init(sc, bf);
3970 if (error != 0) {
3971 DPRINTF(sc, ATH_DEBUG_RECV,
3972 "%s: ath_rxbuf_init failed %d\n",
3973 __func__, error);
3974 return error;
3975 }
3976 }
3977
3978 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3979 ath_hal_putrxbuf(ah, bf->bf_daddr);
3980 ath_hal_rxena(ah); /* enable recv descriptors */
3981 ath_mode_init(sc); /* set filters, etc. */
3982 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
3983 return 0;
3984}
3985
3986/*
3987 * Update internal state after a channel change.
3988 */
3989static void
3990ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
3991{
3992 struct ieee80211com *ic = &sc->sc_ic;
3993 enum ieee80211_phymode mode;
3994 u_int16_t flags;
3995
3996 /*
3997 * Change channels and update the h/w rate map
3998 * if we're switching; e.g. 11a to 11b/g.
3999 */
4000 mode = ieee80211_chan2mode(ic, chan);
4001 if (mode != sc->sc_curmode)
4002 ath_setcurmode(sc, mode);
4003 /*
4004 * Update BPF state. NB: ethereal et. al. don't handle
4005 * merged flags well so pick a unique mode for their use.
4006 */
4007 if (IEEE80211_IS_CHAN_A(chan))
4008 flags = IEEE80211_CHAN_A;
4009 /* XXX 11g schizophrenia */
4010 else if (IEEE80211_IS_CHAN_G(chan) ||
4011 IEEE80211_IS_CHAN_PUREG(chan))
4012 flags = IEEE80211_CHAN_G;
4013 else
4014 flags = IEEE80211_CHAN_B;
4015 if (IEEE80211_IS_CHAN_T(chan))
4016 flags |= IEEE80211_CHAN_TURBO;
4017 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
4018 htole16(chan->ic_freq);
4019 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
4020 htole16(flags);
4021}
4022
4023/*
4024 * Set/change channels. If the channel is really being changed,
4025 * it's done by reseting the chip. To accomplish this we must
4026 * first cleanup any pending DMA, then restart stuff after a la
4027 * ath_init.
4028 */
4029static int
4030ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4031{
4032 struct ath_hal *ah = sc->sc_ah;
4033 struct ieee80211com *ic = &sc->sc_ic;
4034 HAL_CHANNEL hchan;
4035
4036 /*
4037 * Convert to a HAL channel description with
4038 * the flags constrained to reflect the current
4039 * operating mode.
4040 */
4041 hchan.channel = chan->ic_freq;
4042 hchan.channelFlags = ath_chan2flags(ic, chan);
4043
4044 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n",
4045 __func__,
4046 ath_hal_mhz2ieee(sc->sc_curchan.channel,
4047 sc->sc_curchan.channelFlags),
4048 sc->sc_curchan.channel,
4049 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel);
4050 if (hchan.channel != sc->sc_curchan.channel ||
4051 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4052 HAL_STATUS status;
4053
4054 /*
4055 * To switch channels clear any pending DMA operations;
4056 * wait long enough for the RX fifo to drain, reset the
4057 * hardware at the new frequency, and then re-enable
4058 * the relevant bits of the h/w.
4059 */
4060 ath_hal_intrset(ah, 0); /* disable interrupts */
4061 ath_draintxq(sc); /* clear pending tx frames */
4062 ath_stoprecv(sc); /* turn off frame recv */
4063 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) {
4064 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset "
4065 "channel %u (%u Mhz)\n",
4066 ieee80211_chan2ieee(ic, chan), chan->ic_freq);
4067 return EIO;
4068 }
4069 sc->sc_curchan = hchan;
4070 ath_update_txpow(sc); /* update tx power state */
4071 sc->sc_diversity = ath_hal_getdiversity(ah);
4072
4073 /*
4074 * Re-enable rx framework.
4075 */
4076 if (ath_startrecv(sc) != 0) {
4077 if_printf(ic->ic_ifp,
4078 "ath_chan_set: unable to restart recv logic\n");
4079 return EIO;
4080 }
4081
4082 /*
4083 * Change channels and update the h/w rate map
4084 * if we're switching; e.g. 11a to 11b/g.
4085 */
4086 ic->ic_ibss_chan = chan;
4087 ath_chan_change(sc, chan);
4088
4089 /*
4090 * Re-enable interrupts.
4091 */
4092 ath_hal_intrset(ah, sc->sc_imask);
4093 }
4094 return 0;
4095}
4096
4097static void
4098ath_next_scan(void *arg)
4099{
4100 struct ath_softc *sc = arg;
4101 struct ieee80211com *ic = &sc->sc_ic;
4102
4103 if (ic->ic_state == IEEE80211_S_SCAN)
4104 ieee80211_next_scan(ic);
4105}
4106
4107/*
4108 * Periodically recalibrate the PHY to account
4109 * for temperature/environment changes.
4110 */
4111static void
4112ath_calibrate(void *arg)
4113{
4114 struct ath_softc *sc = arg;
4115 struct ath_hal *ah = sc->sc_ah;
4116
4117 sc->sc_stats.ast_per_cal++;
4118
4119 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n",
4120 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
4121
4122 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4123 /*
4124 * Rfgain is out of bounds, reset the chip
4125 * to load new gain values.
4126 */
4127 sc->sc_stats.ast_per_rfgain++;
4128 ath_reset(sc->sc_ifp);
4129 }
4130 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) {
4131 DPRINTF(sc, ATH_DEBUG_ANY,
4132 "%s: calibration of channel %u failed\n",
4133 __func__, sc->sc_curchan.channel);
4134 sc->sc_stats.ast_per_calfail++;
4135 }
4136 /*
4137 * Calibrate noise floor data again in case of change.
4138 */
4139 ath_hal_process_noisefloor(ah);
4140 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc);
4141}
4142
4143static int
4144ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4145{
4146 struct ifnet *ifp = ic->ic_ifp;
4147 struct ath_softc *sc = ifp->if_softc;
4148 struct ath_hal *ah = sc->sc_ah;
4149 struct ieee80211_node *ni;
4150 int i, error;
4151 const u_int8_t *bssid;
4152 u_int32_t rfilt;
4153 static const HAL_LED_STATE leds[] = {
4154 HAL_LED_INIT, /* IEEE80211_S_INIT */
4155 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4156 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4157 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4158 HAL_LED_RUN, /* IEEE80211_S_RUN */
4159 };
4160
4161 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4162 ieee80211_state_name[ic->ic_state],
4163 ieee80211_state_name[nstate]);
4164
4165 callout_stop(&sc->sc_scan_ch);
4166 callout_stop(&sc->sc_cal_ch);
4167 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4168
4169 if (nstate == IEEE80211_S_INIT) {
4170 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4171 /*
4172 * NB: disable interrupts so we don't rx frames.
4173 */
4174 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4175 /*
4176 * Notify the rate control algorithm.
4177 */
4178 ath_rate_newstate(sc, nstate);
4179 goto done;
4180 }
4181 ni = ic->ic_bss;
4182 error = ath_chan_set(sc, ic->ic_curchan);
4183 if (error != 0)
4184 goto bad;
4185 rfilt = ath_calcrxfilter(sc, nstate);
4186 if (nstate == IEEE80211_S_SCAN)
4187 bssid = ifp->if_broadcastaddr;
4188 else
4189 bssid = ni->ni_bssid;
4190 ath_hal_setrxfilter(ah, rfilt);
4191 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n",
4192 __func__, rfilt, ether_sprintf(bssid));
4193
4194 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4195 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4196 else
4197 ath_hal_setassocid(ah, bssid, 0);
4198 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4199 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4200 if (ath_hal_keyisvalid(ah, i))
4201 ath_hal_keysetmac(ah, i, bssid);
4202 }
4203
4204 /*
4205 * Notify the rate control algorithm so rates
4206 * are setup should ath_beacon_alloc be called.
4207 */
4208 ath_rate_newstate(sc, nstate);
4209
4210 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4211 /* nothing to do */;
4212 } else if (nstate == IEEE80211_S_RUN) {
4213 DPRINTF(sc, ATH_DEBUG_STATE,
4214 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s "
4215 "capinfo=0x%04x chan=%d\n"
4216 , __func__
4217 , ic->ic_flags
4218 , ni->ni_intval
4219 , ether_sprintf(ni->ni_bssid)
4220 , ni->ni_capinfo
4221 , ieee80211_chan2ieee(ic, ic->ic_curchan));
4222
4223 switch (ic->ic_opmode) {
4224 case IEEE80211_M_HOSTAP:
4225 case IEEE80211_M_IBSS:
4226 /*
4227 * Allocate and setup the beacon frame.
4228 *
4229 * Stop any previous beacon DMA. This may be
4230 * necessary, for example, when an ibss merge
4231 * causes reconfiguration; there will be a state
4232 * transition from RUN->RUN that means we may
4233 * be called with beacon transmission active.
4234 */
4235 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4236 ath_beacon_free(sc);
4237 error = ath_beacon_alloc(sc, ni);
4238 if (error != 0)
4239 goto bad;
4240 /*
4241 * Configure the beacon and sleep timers.
4242 */
4243 ath_beacon_config(sc);
4244 break;
4245 case IEEE80211_M_STA:
4246 /*
4247 * Allocate a key cache slot to the station.
4248 */
4249 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4250 sc->sc_hasclrkey &&
4251 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4252 ath_setup_stationkey(ni);
4253 /*
4254 * Configure the beacon and sleep timers.
4255 */
4256 ath_beacon_config(sc);
4257 break;
4258 default:
4259 break;
4260 }
4261
4262 /*
4263 * Let the hal process statistics collected during a
4264 * scan so it can provide calibrated noise floor data.
4265 */
4266 ath_hal_process_noisefloor(ah);
4267 /*
4268 * Reset rssi stats; maybe not the best place...
4269 */
4270 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4271 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4272 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4273 } else {
4274 ath_hal_intrset(ah,
4275 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4276 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4277 }
4278done:
4279 /*
4280 * Invoke the parent method to complete the work.
4281 */
4282 error = sc->sc_newstate(ic, nstate, arg);
4283 /*
4284 * Finally, start any timers.
4285 */
4286 if (nstate == IEEE80211_S_RUN) {
4287 /* start periodic recalibration timer */
4288 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz,
4289 ath_calibrate, sc);
4290 } else if (nstate == IEEE80211_S_SCAN) {
4291 /* start ap/neighbor scan timer */
4292 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4293 ath_next_scan, sc);
4294 }
4295bad:
4296 return error;
4297}
4298
4299/*
4300 * Allocate a key cache slot to the station so we can
4301 * setup a mapping from key index to node. The key cache
4302 * slot is needed for managing antenna state and for
4303 * compression when stations do not use crypto. We do
4304 * it uniliaterally here; if crypto is employed this slot
4305 * will be reassigned.
4306 */
4307static void
4308ath_setup_stationkey(struct ieee80211_node *ni)
4309{
4310 struct ieee80211com *ic = ni->ni_ic;
4311 struct ath_softc *sc = ic->ic_ifp->if_softc;
4312 ieee80211_keyix keyix, rxkeyix;
4313
4314 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4315 /*
4316 * Key cache is full; we'll fall back to doing
4317 * the more expensive lookup in software. Note
4318 * this also means no h/w compression.
4319 */
4320 /* XXX msg+statistic */
4321 } else {
4322 /* XXX locking? */
4323 ni->ni_ucastkey.wk_keyix = keyix;
4324 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4325 /* NB: this will create a pass-thru key entry */
4326 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4327 }
4328}
4329
4330/*
4331 * Setup driver-specific state for a newly associated node.
4332 * Note that we're called also on a re-associate, the isnew
4333 * param tells us if this is the first time or not.
4334 */
4335static void
4336ath_newassoc(struct ieee80211_node *ni, int isnew)
4337{
4338 struct ieee80211com *ic = ni->ni_ic;
4339 struct ath_softc *sc = ic->ic_ifp->if_softc;
4340
4341 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4342 if (isnew &&
4343 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4344 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4345 ("new assoc with a unicast key already setup (keyix %u)",
4346 ni->ni_ucastkey.wk_keyix));
4347 ath_setup_stationkey(ni);
4348 }
4349}
4350
4351static int
4352ath_getchannels(struct ath_softc *sc, u_int cc,
4353 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4354{
4355 struct ieee80211com *ic = &sc->sc_ic;
4356 struct ifnet *ifp = sc->sc_ifp;
4357 struct ath_hal *ah = sc->sc_ah;
4358 HAL_CHANNEL *chans;
4359 int i, ix, nchan;
4360
4361 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL),
4362 M_TEMP, M_NOWAIT);
4363 if (chans == NULL) {
4364 if_printf(ifp, "unable to allocate channel table\n");
4365 return ENOMEM;
4366 }
4367 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4368 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4369 u_int32_t rd;
4370
4371 ath_hal_getregdomain(ah, &rd);
4372 if_printf(ifp, "unable to collect channel list from hal; "
4373 "regdomain likely %u country code %u\n", rd, cc);
4374 free(chans, M_TEMP);
4375 return EINVAL;
4376 }
4377
4378 /*
4379 * Convert HAL channels to ieee80211 ones and insert
4380 * them in the table according to their channel number.
4381 */
4382 for (i = 0; i < nchan; i++) {
4383 HAL_CHANNEL *c = &chans[i];
4384 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags);
4385 if (ix > IEEE80211_CHAN_MAX) {
4386 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n",
4387 ix, c->channel, c->channelFlags);
4388 continue;
4389 }
4390 /* NB: flags are known to be compatible */
4391 if (ic->ic_channels[ix].ic_freq == 0) {
4392 ic->ic_channels[ix].ic_freq = c->channel;
4393 ic->ic_channels[ix].ic_flags = c->channelFlags;
4394 } else {
4395 /* channels overlap; e.g. 11g and 11b */
4396 ic->ic_channels[ix].ic_flags |= c->channelFlags;
4397 }
4398 }
4399 free(chans, M_TEMP);
4400 return 0;
4401}
4402
4403static void
4404ath_led_done(void *arg)
4405{
4406 struct ath_softc *sc = arg;
4407
4408 sc->sc_blinking = 0;
4409}
4410
4411/*
4412 * Turn the LED off: flip the pin and then set a timer so no
4413 * update will happen for the specified duration.
4414 */
4415static void
4416ath_led_off(void *arg)
4417{
4418 struct ath_softc *sc = arg;
4419
4420 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4421 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4422}
4423
4424/*
4425 * Blink the LED according to the specified on/off times.
4426 */
4427static void
4428ath_led_blink(struct ath_softc *sc, int on, int off)
4429{
4430 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4431 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4432 sc->sc_blinking = 1;
4433 sc->sc_ledoff = off;
4434 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4435}
4436
4437static void
4438ath_led_event(struct ath_softc *sc, int event)
4439{
4440
4441 sc->sc_ledevent = ticks; /* time of last event */
4442 if (sc->sc_blinking) /* don't interrupt active blink */
4443 return;
4444 switch (event) {
4445 case ATH_LED_POLL:
4446 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4447 sc->sc_hwmap[0].ledoff);
4448 break;
4449 case ATH_LED_TX:
4450 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4451 sc->sc_hwmap[sc->sc_txrate].ledoff);
4452 break;
4453 case ATH_LED_RX:
4454 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4455 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4456 break;
4457 }
4458}
4459
4460static void
4461ath_update_txpow(struct ath_softc *sc)
4462{
4463 struct ieee80211com *ic = &sc->sc_ic;
4464 struct ath_hal *ah = sc->sc_ah;
4465 u_int32_t txpow;
4466
4467 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4468 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4469 /* read back in case value is clamped */
4470 ath_hal_gettxpowlimit(ah, &txpow);
4471 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4472 }
4473 /*
4474 * Fetch max tx power level for status requests.
4475 */
4476 ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4477 ic->ic_bss->ni_txpower = txpow;
4478}
4479
4480static void
4481rate_setup(struct ath_softc *sc,
4482 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs)
4483{
4484 int i, maxrates;
4485
4486 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4487 DPRINTF(sc, ATH_DEBUG_ANY,
4488 "%s: rate table too small (%u > %u)\n",
4489 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4490 maxrates = IEEE80211_RATE_MAXSIZE;
4491 } else
4492 maxrates = rt->rateCount;
4493 for (i = 0; i < maxrates; i++)
4494 rs->rs_rates[i] = rt->info[i].dot11Rate;
4495 rs->rs_nrates = maxrates;
4496}
4497
4498static int
4499ath_rate_setup(struct ath_softc *sc, u_int mode)
4500{
4501 struct ath_hal *ah = sc->sc_ah;
4502 struct ieee80211com *ic = &sc->sc_ic;
4503 const HAL_RATE_TABLE *rt;
4504
4505 switch (mode) {
4506 case IEEE80211_MODE_11A:
4507 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4508 break;
4509 case IEEE80211_MODE_11B:
4510 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4511 break;
4512 case IEEE80211_MODE_11G:
4513 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4514 break;
4515 case IEEE80211_MODE_TURBO_A:
4516 /* XXX until static/dynamic turbo is fixed */
4517 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4518 break;
4519 case IEEE80211_MODE_TURBO_G:
4520 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4521 break;
4522 default:
4523 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4524 __func__, mode);
4525 return 0;
4526 }
4527 sc->sc_rates[mode] = rt;
4528 if (rt != NULL) {
4529 rate_setup(sc, rt, &ic->ic_sup_rates[mode]);
4530 return 1;
4531 } else
4532 return 0;
4533}
4534
4535static void
4536ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4537{
4538#define N(a) (sizeof(a)/sizeof(a[0]))
4539 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4540 static const struct {
4541 u_int rate; /* tx/rx 802.11 rate */
4542 u_int16_t timeOn; /* LED on time (ms) */
4543 u_int16_t timeOff; /* LED off time (ms) */
4544 } blinkrates[] = {
4545 { 108, 40, 10 },
4546 { 96, 44, 11 },
4547 { 72, 50, 13 },
4548 { 48, 57, 14 },
4549 { 36, 67, 16 },
4550 { 24, 80, 20 },
4551 { 22, 100, 25 },
4552 { 18, 133, 34 },
4553 { 12, 160, 40 },
4554 { 10, 200, 50 },
4555 { 6, 240, 58 },
4556 { 4, 267, 66 },
4557 { 2, 400, 100 },
4558 { 0, 500, 130 },
4559 };
4560 const HAL_RATE_TABLE *rt;
4561 int i, j;
4562
4563 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4564 rt = sc->sc_rates[mode];
4565 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4566 for (i = 0; i < rt->rateCount; i++)
4567 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4568 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4569 for (i = 0; i < 32; i++) {
4570 u_int8_t ix = rt->rateCodeToIndex[i];
4571 if (ix == 0xff) {
4572 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
4573 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
4574 continue;
4575 }
4576 sc->sc_hwmap[i].ieeerate =
4577 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
4578 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
4579 if (rt->info[ix].shortPreamble ||
4580 rt->info[ix].phy == IEEE80211_T_OFDM)
4581 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
4582 /* NB: receive frames include FCS */
4583 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
4584 IEEE80211_RADIOTAP_F_FCS;
4585 /* setup blink rate table to avoid per-packet lookup */
4586 for (j = 0; j < N(blinkrates)-1; j++)
4587 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
4588 break;
4589 /* NB: this uses the last entry if the rate isn't found */
4590 /* XXX beware of overlow */
4591 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
4592 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
4593 }
4594 sc->sc_currates = rt;
4595 sc->sc_curmode = mode;
4596 /*
4597 * All protection frames are transmited at 2Mb/s for
4598 * 11g, otherwise at 1Mb/s.
4599 */
4600 if (mode == IEEE80211_MODE_11G)
4601 sc->sc_protrix = ath_tx_findrix(rt, 2*2);
4602 else
4603 sc->sc_protrix = ath_tx_findrix(rt, 2*1);
4604 /* rate index used to send management frames */
4605 sc->sc_minrateix = 0;
4606 /*
4607 * Setup multicast rate state.
4608 */
4609 /* XXX layering violation */
4610 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
4611 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
4612 /* NB: caller is responsible for reseting rate control state */
4613#undef N
4614}
4615
4616#ifdef AR_DEBUG
4617static void
4618ath_printrxbuf(struct ath_buf *bf, int done)
4619{
4620 struct ath_desc *ds;
4621 int i;
4622
4623 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4624 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n",
4625 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4626 ds->ds_link, ds->ds_data,
4627 ds->ds_ctl0, ds->ds_ctl1,
4628 ds->ds_hw[0], ds->ds_hw[1],
4629 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
4630 }
4631}
4632
4633static void
4634ath_printtxbuf(struct ath_buf *bf, int done)
4635{
4636 struct ath_desc *ds;
4637 int i;
4638
4639 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4640 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n",
4641 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4642 ds->ds_link, ds->ds_data,
4643 ds->ds_ctl0, ds->ds_ctl1,
4644 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
4645 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
4646 }
4647}
4648#endif /* AR_DEBUG */
4649
4650static void
4651ath_watchdog(struct ifnet *ifp)
4652{
4653 struct ath_softc *sc = ifp->if_softc;
4654 struct ieee80211com *ic = &sc->sc_ic;
4655
4656 ifp->if_timer = 0;
4657 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
4658 return;
4659 if (sc->sc_tx_timer) {
4660 if (--sc->sc_tx_timer == 0) {
4661 if_printf(ifp, "device timeout\n");
4662 ath_reset(ifp);
4663 ifp->if_oerrors++;
4664 sc->sc_stats.ast_watchdog++;
4665 } else
4666 ifp->if_timer = 1;
4667 }
4668 ieee80211_watchdog(ic);
4669}
4670
4671/*
4672 * Diagnostic interface to the HAL. This is used by various
4673 * tools to do things like retrieve register contents for
4674 * debugging. The mechanism is intentionally opaque so that
4675 * it can change frequently w/o concern for compatiblity.
4676 */
4677static int
4678ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
4679{
4680 struct ath_hal *ah = sc->sc_ah;
4681 u_int id = ad->ad_id & ATH_DIAG_ID;
4682 void *indata = NULL;
4683 void *outdata = NULL;
4684 u_int32_t insize = ad->ad_in_size;
4685 u_int32_t outsize = ad->ad_out_size;
4686 int error = 0;
4687
4688 if (ad->ad_id & ATH_DIAG_IN) {
4689 /*
4690 * Copy in data.
4691 */
4692 indata = malloc(insize, M_TEMP, M_NOWAIT);
4693 if (indata == NULL) {
4694 error = ENOMEM;
4695 goto bad;
4696 }
4697 error = copyin(ad->ad_in_data, indata, insize);
4698 if (error)
4699 goto bad;
4700 }
4701 if (ad->ad_id & ATH_DIAG_DYN) {
4702 /*
4703 * Allocate a buffer for the results (otherwise the HAL
4704 * returns a pointer to a buffer where we can read the
4705 * results). Note that we depend on the HAL leaving this
4706 * pointer for us to use below in reclaiming the buffer;
4707 * may want to be more defensive.
4708 */
4709 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
4710 if (outdata == NULL) {
4711 error = ENOMEM;
4712 goto bad;
4713 }
4714 }
4715 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
4716 if (outsize < ad->ad_out_size)
4717 ad->ad_out_size = outsize;
4718 if (outdata != NULL)
4719 error = copyout(outdata, ad->ad_out_data,
4720 ad->ad_out_size);
4721 } else {
4722 error = EINVAL;
4723 }
4724bad:
4725 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
4726 free(indata, M_TEMP);
4727 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
4728 free(outdata, M_TEMP);
4729 return error;
4730}
4731
4732static int
4733ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
4734{
4735#define IS_RUNNING(ifp) \
4736 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
4737 struct ath_softc *sc = ifp->if_softc;
4738 struct ieee80211com *ic = &sc->sc_ic;
4739 struct ifreq *ifr = (struct ifreq *)data;
4740 int error = 0;
4741
4742 ATH_LOCK(sc);
4743 switch (cmd) {
4744 case SIOCSIFFLAGS:
4745 if (IS_RUNNING(ifp)) {
4746 /*
4747 * To avoid rescanning another access point,
4748 * do not call ath_init() here. Instead,
4749 * only reflect promisc mode settings.
4750 */
4751 ath_mode_init(sc);
4752 } else if (ifp->if_flags & IFF_UP) {
4753 /*
4754 * Beware of being called during attach/detach
4755 * to reset promiscuous mode. In that case we
4756 * will still be marked UP but not RUNNING.
4757 * However trying to re-init the interface
4758 * is the wrong thing to do as we've already
4759 * torn down much of our state. There's
4760 * probably a better way to deal with this.
4761 */
4762 if (!sc->sc_invalid && ic->ic_bss != NULL)
4763 ath_init(sc); /* XXX lose error */
4764 } else
4765 ath_stop_locked(ifp);
4766 break;
4767 case SIOCADDMULTI:
4768 case SIOCDELMULTI:
4769 /*
4770 * The upper layer has already installed/removed
4771 * the multicast address(es), just recalculate the
4772 * multicast filter for the card.
4773 */
4774 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4775 ath_mode_init(sc);
4776 break;
4777 case SIOCGATHSTATS:
4778 /* NB: embed these numbers to get a consistent view */
4779 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
4780 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
4781 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
4782 ATH_UNLOCK(sc);
4783 /*
4784 * NB: Drop the softc lock in case of a page fault;
4785 * we'll accept any potential inconsisentcy in the
4786 * statistics. The alternative is to copy the data
4787 * to a local structure.
4788 */
4789 return copyout(&sc->sc_stats,
4790 ifr->ifr_data, sizeof (sc->sc_stats));
4791 case SIOCGATHDIAG:
4792 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
4793 break;
4794 default:
4795 error = ieee80211_ioctl(ic, cmd, data);
4796 if (error == ENETRESET) {
4797 if (IS_RUNNING(ifp) &&
4798 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
4799 ath_init(sc); /* XXX lose error */
4800 error = 0;
4801 }
4802 if (error == ERESTART)
4803 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
4804 break;
4805 }
4806 ATH_UNLOCK(sc);
4807 return error;
4808#undef IS_RUNNING
4809}
4810
4811static int
4812ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
4813{
4814 struct ath_softc *sc = arg1;
4815 u_int slottime = ath_hal_getslottime(sc->sc_ah);
4816 int error;
4817
4818 error = sysctl_handle_int(oidp, &slottime, 0, req);
4819 if (error || !req->newptr)
4820 return error;
4821 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
4822}
4823
4824static int
4825ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
4826{
4827 struct ath_softc *sc = arg1;
4828 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
4829 int error;
4830
4831 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
4832 if (error || !req->newptr)
4833 return error;
4834 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
4835}
4836
4837static int
4838ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
4839{
4840 struct ath_softc *sc = arg1;
4841 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
4842 int error;
4843
4844 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
4845 if (error || !req->newptr)
4846 return error;
4847 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
4848}
4849
4850static int
4851ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
4852{
4853 struct ath_softc *sc = arg1;
4854 int softled = sc->sc_softled;
4855 int error;
4856
4857 error = sysctl_handle_int(oidp, &softled, 0, req);
4858 if (error || !req->newptr)
4859 return error;
4860 softled = (softled != 0);
4861 if (softled != sc->sc_softled) {
4862 if (softled) {
4863 /* NB: handle any sc_ledpin change */
4864 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
4865 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
4866 !sc->sc_ledon);
4867 }
4868 sc->sc_softled = softled;
4869 }
4870 return 0;
4871}
4872
4873static int
4874ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
4875{
4876 struct ath_softc *sc = arg1;
4877 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
4878 int error;
4879
4880 error = sysctl_handle_int(oidp, &defantenna, 0, req);
4881 if (!error && req->newptr)
4882 ath_hal_setdefantenna(sc->sc_ah, defantenna);
4883 return error;
4884}
4885
4886static int
4887ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
4888{
4889 struct ath_softc *sc = arg1;
4890 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
4891 int error;
4892
4893 error = sysctl_handle_int(oidp, &diversity, 0, req);
4894 if (error || !req->newptr)
4895 return error;
4896 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
4897 return EINVAL;
4898 sc->sc_diversity = diversity;
4899 return 0;
4900}
4901
4902static int
4903ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
4904{
4905 struct ath_softc *sc = arg1;
4906 u_int32_t diag;
4907 int error;
4908
4909 if (!ath_hal_getdiag(sc->sc_ah, &diag))
4910 return EINVAL;
4911 error = sysctl_handle_int(oidp, &diag, 0, req);
4912 if (error || !req->newptr)
4913 return error;
4914 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
4915}
4916
4917static int
4918ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
4919{
4920 struct ath_softc *sc = arg1;
4921 struct ifnet *ifp = sc->sc_ifp;
4922 u_int32_t scale;
4923 int error;
4924
4925 ath_hal_gettpscale(sc->sc_ah, &scale);
4926 error = sysctl_handle_int(oidp, &scale, 0, req);
4927 if (error || !req->newptr)
4928 return error;
4929 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
4930}
4931
4932static int
4933ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
4934{
4935 struct ath_softc *sc = arg1;
4936 u_int tpc = ath_hal_gettpc(sc->sc_ah);
4937 int error;
4938
4939 error = sysctl_handle_int(oidp, &tpc, 0, req);
4940 if (error || !req->newptr)
4941 return error;
4942 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
4943}
4944
4945static int
4946ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS)
4947{
4948 struct ath_softc *sc = arg1;
4949 u_int32_t rd;
4950 int error;
4951
4952 if (!ath_hal_getregdomain(sc->sc_ah, &rd))
4953 return EINVAL;
4954 error = sysctl_handle_int(oidp, &rd, 0, req);
4955 if (error || !req->newptr)
4956 return error;
4957 return !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0;
4958}
4959
4960static void
4961ath_sysctlattach(struct ath_softc *sc)
4962{
4963 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
4964 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
4965 struct ath_hal *ah = sc->sc_ah;
4966
4967 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
4968 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4969 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
4970 "EEPROM country code");
4971 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4972 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4973 ath_sysctl_regdomain, "I", "EEPROM regdomain code");
4974 sc->sc_debug = ath_debug;
4975 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4976 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
4977 "control debugging printfs");
4978
4979 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4980 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4981 ath_sysctl_slottime, "I", "802.11 slot time (us)");
4982 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4983 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4984 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
4985 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4986 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4987 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
4988 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4989 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4990 ath_sysctl_softled, "I", "enable/disable software LED support");
4991 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4992 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
4993 "GPIO pin connected to LED");
4994 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4995 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
4996 "setting to turn LED on");
4997 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4998 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
4999 "idle time for inactivity LED (ticks)");
5000 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5001 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
5002 "tx antenna (0=auto)");
5003 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5004 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5005 ath_sysctl_rxantenna, "I", "default/rx antenna");
5006 if (ath_hal_hasdiversity(ah))
5007 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5008 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5009 ath_sysctl_diversity, "I", "antenna diversity");
5010 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
5011 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5012 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
5013 "tx descriptor batching");
5014 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5015 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5016 ath_sysctl_diag, "I", "h/w diagnostic control");
5017 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5018 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5019 ath_sysctl_tpscale, "I", "tx power scaling");
5020 if (ath_hal_hastpc(ah))
5021 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5022 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5023 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
5024 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
5025 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5026 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
5027 "mask of error frames to pass when monitoring");
5028}
5029
5030static void
5031ath_bpfattach(struct ath_softc *sc)
5032{
5033 struct ifnet *ifp = sc->sc_ifp;
5034
5035 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
5036 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
5037 &sc->sc_drvbpf);
5038 /*
5039 * Initialize constant fields.
5040 * XXX make header lengths a multiple of 32-bits so subsequent
5041 * headers are properly aligned; this is a kludge to keep
5042 * certain applications happy.
5043 *
5044 * NB: the channel is setup each time we transition to the
5045 * RUN state to avoid filling it in for each frame.
5046 */
5047 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t));
5048 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
5049 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
5050
5051 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t));
5052 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
5053 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
5054}
5055
5056/*
5057 * Announce various information on device/driver attach.
5058 */
5059static void
5060ath_announce(struct ath_softc *sc)
5061{
5062#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
5063 struct ifnet *ifp = sc->sc_ifp;
5064 struct ath_hal *ah = sc->sc_ah;
5065 u_int modes, cc;
5066
5067 if_printf(ifp, "mac %d.%d phy %d.%d",
5068 ah->ah_macVersion, ah->ah_macRev,
5069 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5070 /*
5071 * Print radio revision(s). We check the wireless modes
5072 * to avoid falsely printing revs for inoperable parts.
5073 * Dual-band radio revs are returned in the 5Ghz rev number.
5074 */
5075 ath_hal_getcountrycode(ah, &cc);
5076 modes = ath_hal_getwirelessmodes(ah, cc);
5077 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
5078 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
5079 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
5080 ah->ah_analog5GhzRev >> 4,
5081 ah->ah_analog5GhzRev & 0xf,
5082 ah->ah_analog2GhzRev >> 4,
5083 ah->ah_analog2GhzRev & 0xf);
5084 else
5085 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5086 ah->ah_analog5GhzRev & 0xf);
5087 } else
5088 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5089 ah->ah_analog5GhzRev & 0xf);
5090 printf("\n");
5091 if (bootverbose) {
5092 int i;
5093 for (i = 0; i <= WME_AC_VO; i++) {
5094 struct ath_txq *txq = sc->sc_ac2q[i];
5095 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5096 txq->axq_qnum, ieee80211_wme_acnames[i]);
5097 }
5098 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5099 sc->sc_cabq->axq_qnum);
5100 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5101 }
5102 if (ath_rxbuf != ATH_RXBUF)
5103 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5104 if (ath_txbuf != ATH_TXBUF)
5105 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5106#undef HAL_MODE_DUALBAND
5107}
| 3886
3887 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3888 sc->sc_tx_timer = 0;
3889
3890 if (sc->sc_softled)
3891 ath_led_event(sc, ATH_LED_TX);
3892
3893 ath_start(ifp);
3894}
3895
3896static void
3897ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
3898{
3899 struct ath_hal *ah = sc->sc_ah;
3900 struct ieee80211_node *ni;
3901 struct ath_buf *bf;
3902
3903 /*
3904 * NB: this assumes output has been stopped and
3905 * we do not need to block ath_tx_tasklet
3906 */
3907 for (;;) {
3908 ATH_TXQ_LOCK(txq);
3909 bf = STAILQ_FIRST(&txq->axq_q);
3910 if (bf == NULL) {
3911 txq->axq_link = NULL;
3912 ATH_TXQ_UNLOCK(txq);
3913 break;
3914 }
3915 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3916 ATH_TXQ_UNLOCK(txq);
3917#ifdef AR_DEBUG
3918 if (sc->sc_debug & ATH_DEBUG_RESET)
3919 ath_printtxbuf(bf,
3920 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
3921#endif /* AR_DEBUG */
3922 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3923 m_freem(bf->bf_m);
3924 bf->bf_m = NULL;
3925 ni = bf->bf_node;
3926 bf->bf_node = NULL;
3927 if (ni != NULL) {
3928 /*
3929 * Reclaim node reference.
3930 */
3931 ieee80211_free_node(ni);
3932 }
3933 ATH_TXBUF_LOCK(sc);
3934 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3935 ATH_TXBUF_UNLOCK(sc);
3936 }
3937}
3938
3939static void
3940ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
3941{
3942 struct ath_hal *ah = sc->sc_ah;
3943
3944 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
3945 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
3946 __func__, txq->axq_qnum,
3947 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
3948 txq->axq_link);
3949}
3950
3951/*
3952 * Drain the transmit queues and reclaim resources.
3953 */
3954static void
3955ath_draintxq(struct ath_softc *sc)
3956{
3957 struct ath_hal *ah = sc->sc_ah;
3958 struct ifnet *ifp = sc->sc_ifp;
3959 int i;
3960
3961 /* XXX return value */
3962 if (!sc->sc_invalid) {
3963 /* don't touch the hardware if marked invalid */
3964 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
3965 DPRINTF(sc, ATH_DEBUG_RESET,
3966 "%s: beacon queue %p\n", __func__,
3967 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
3968 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3969 if (ATH_TXQ_SETUP(sc, i))
3970 ath_tx_stopdma(sc, &sc->sc_txq[i]);
3971 }
3972 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3973 if (ATH_TXQ_SETUP(sc, i))
3974 ath_tx_draintxq(sc, &sc->sc_txq[i]);
3975 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3976 sc->sc_tx_timer = 0;
3977}
3978
3979/*
3980 * Disable the receive h/w in preparation for a reset.
3981 */
3982static void
3983ath_stoprecv(struct ath_softc *sc)
3984{
3985#define PA2DESC(_sc, _pa) \
3986 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3987 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3988 struct ath_hal *ah = sc->sc_ah;
3989
3990 ath_hal_stoppcurecv(ah); /* disable PCU */
3991 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
3992 ath_hal_stopdmarecv(ah); /* disable DMA engine */
3993 DELAY(3000); /* 3ms is long enough for 1 frame */
3994#ifdef AR_DEBUG
3995 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
3996 struct ath_buf *bf;
3997
3998 printf("%s: rx queue %p, link %p\n", __func__,
3999 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
4000 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4001 struct ath_desc *ds = bf->bf_desc;
4002 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
4003 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
4004 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
4005 ath_printrxbuf(bf, status == HAL_OK);
4006 }
4007 }
4008#endif
4009 sc->sc_rxlink = NULL; /* just in case */
4010#undef PA2DESC
4011}
4012
4013/*
4014 * Enable the receive h/w following a reset.
4015 */
4016static int
4017ath_startrecv(struct ath_softc *sc)
4018{
4019 struct ath_hal *ah = sc->sc_ah;
4020 struct ath_buf *bf;
4021
4022 sc->sc_rxlink = NULL;
4023 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4024 int error = ath_rxbuf_init(sc, bf);
4025 if (error != 0) {
4026 DPRINTF(sc, ATH_DEBUG_RECV,
4027 "%s: ath_rxbuf_init failed %d\n",
4028 __func__, error);
4029 return error;
4030 }
4031 }
4032
4033 bf = STAILQ_FIRST(&sc->sc_rxbuf);
4034 ath_hal_putrxbuf(ah, bf->bf_daddr);
4035 ath_hal_rxena(ah); /* enable recv descriptors */
4036 ath_mode_init(sc); /* set filters, etc. */
4037 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
4038 return 0;
4039}
4040
4041/*
4042 * Update internal state after a channel change.
4043 */
4044static void
4045ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4046{
4047 struct ieee80211com *ic = &sc->sc_ic;
4048 enum ieee80211_phymode mode;
4049 u_int16_t flags;
4050
4051 /*
4052 * Change channels and update the h/w rate map
4053 * if we're switching; e.g. 11a to 11b/g.
4054 */
4055 mode = ieee80211_chan2mode(ic, chan);
4056 if (mode != sc->sc_curmode)
4057 ath_setcurmode(sc, mode);
4058 /*
4059 * Update BPF state. NB: ethereal et. al. don't handle
4060 * merged flags well so pick a unique mode for their use.
4061 */
4062 if (IEEE80211_IS_CHAN_A(chan))
4063 flags = IEEE80211_CHAN_A;
4064 /* XXX 11g schizophrenia */
4065 else if (IEEE80211_IS_CHAN_G(chan) ||
4066 IEEE80211_IS_CHAN_PUREG(chan))
4067 flags = IEEE80211_CHAN_G;
4068 else
4069 flags = IEEE80211_CHAN_B;
4070 if (IEEE80211_IS_CHAN_T(chan))
4071 flags |= IEEE80211_CHAN_TURBO;
4072 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
4073 htole16(chan->ic_freq);
4074 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
4075 htole16(flags);
4076}
4077
4078/*
4079 * Set/change channels. If the channel is really being changed,
4080 * it's done by reseting the chip. To accomplish this we must
4081 * first cleanup any pending DMA, then restart stuff after a la
4082 * ath_init.
4083 */
4084static int
4085ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4086{
4087 struct ath_hal *ah = sc->sc_ah;
4088 struct ieee80211com *ic = &sc->sc_ic;
4089 HAL_CHANNEL hchan;
4090
4091 /*
4092 * Convert to a HAL channel description with
4093 * the flags constrained to reflect the current
4094 * operating mode.
4095 */
4096 hchan.channel = chan->ic_freq;
4097 hchan.channelFlags = ath_chan2flags(ic, chan);
4098
4099 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n",
4100 __func__,
4101 ath_hal_mhz2ieee(sc->sc_curchan.channel,
4102 sc->sc_curchan.channelFlags),
4103 sc->sc_curchan.channel,
4104 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel);
4105 if (hchan.channel != sc->sc_curchan.channel ||
4106 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4107 HAL_STATUS status;
4108
4109 /*
4110 * To switch channels clear any pending DMA operations;
4111 * wait long enough for the RX fifo to drain, reset the
4112 * hardware at the new frequency, and then re-enable
4113 * the relevant bits of the h/w.
4114 */
4115 ath_hal_intrset(ah, 0); /* disable interrupts */
4116 ath_draintxq(sc); /* clear pending tx frames */
4117 ath_stoprecv(sc); /* turn off frame recv */
4118 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) {
4119 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset "
4120 "channel %u (%u Mhz)\n",
4121 ieee80211_chan2ieee(ic, chan), chan->ic_freq);
4122 return EIO;
4123 }
4124 sc->sc_curchan = hchan;
4125 ath_update_txpow(sc); /* update tx power state */
4126 sc->sc_diversity = ath_hal_getdiversity(ah);
4127
4128 /*
4129 * Re-enable rx framework.
4130 */
4131 if (ath_startrecv(sc) != 0) {
4132 if_printf(ic->ic_ifp,
4133 "ath_chan_set: unable to restart recv logic\n");
4134 return EIO;
4135 }
4136
4137 /*
4138 * Change channels and update the h/w rate map
4139 * if we're switching; e.g. 11a to 11b/g.
4140 */
4141 ic->ic_ibss_chan = chan;
4142 ath_chan_change(sc, chan);
4143
4144 /*
4145 * Re-enable interrupts.
4146 */
4147 ath_hal_intrset(ah, sc->sc_imask);
4148 }
4149 return 0;
4150}
4151
4152static void
4153ath_next_scan(void *arg)
4154{
4155 struct ath_softc *sc = arg;
4156 struct ieee80211com *ic = &sc->sc_ic;
4157
4158 if (ic->ic_state == IEEE80211_S_SCAN)
4159 ieee80211_next_scan(ic);
4160}
4161
4162/*
4163 * Periodically recalibrate the PHY to account
4164 * for temperature/environment changes.
4165 */
4166static void
4167ath_calibrate(void *arg)
4168{
4169 struct ath_softc *sc = arg;
4170 struct ath_hal *ah = sc->sc_ah;
4171
4172 sc->sc_stats.ast_per_cal++;
4173
4174 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n",
4175 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
4176
4177 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4178 /*
4179 * Rfgain is out of bounds, reset the chip
4180 * to load new gain values.
4181 */
4182 sc->sc_stats.ast_per_rfgain++;
4183 ath_reset(sc->sc_ifp);
4184 }
4185 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) {
4186 DPRINTF(sc, ATH_DEBUG_ANY,
4187 "%s: calibration of channel %u failed\n",
4188 __func__, sc->sc_curchan.channel);
4189 sc->sc_stats.ast_per_calfail++;
4190 }
4191 /*
4192 * Calibrate noise floor data again in case of change.
4193 */
4194 ath_hal_process_noisefloor(ah);
4195 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc);
4196}
4197
4198static int
4199ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4200{
4201 struct ifnet *ifp = ic->ic_ifp;
4202 struct ath_softc *sc = ifp->if_softc;
4203 struct ath_hal *ah = sc->sc_ah;
4204 struct ieee80211_node *ni;
4205 int i, error;
4206 const u_int8_t *bssid;
4207 u_int32_t rfilt;
4208 static const HAL_LED_STATE leds[] = {
4209 HAL_LED_INIT, /* IEEE80211_S_INIT */
4210 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4211 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4212 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4213 HAL_LED_RUN, /* IEEE80211_S_RUN */
4214 };
4215
4216 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4217 ieee80211_state_name[ic->ic_state],
4218 ieee80211_state_name[nstate]);
4219
4220 callout_stop(&sc->sc_scan_ch);
4221 callout_stop(&sc->sc_cal_ch);
4222 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4223
4224 if (nstate == IEEE80211_S_INIT) {
4225 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4226 /*
4227 * NB: disable interrupts so we don't rx frames.
4228 */
4229 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4230 /*
4231 * Notify the rate control algorithm.
4232 */
4233 ath_rate_newstate(sc, nstate);
4234 goto done;
4235 }
4236 ni = ic->ic_bss;
4237 error = ath_chan_set(sc, ic->ic_curchan);
4238 if (error != 0)
4239 goto bad;
4240 rfilt = ath_calcrxfilter(sc, nstate);
4241 if (nstate == IEEE80211_S_SCAN)
4242 bssid = ifp->if_broadcastaddr;
4243 else
4244 bssid = ni->ni_bssid;
4245 ath_hal_setrxfilter(ah, rfilt);
4246 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n",
4247 __func__, rfilt, ether_sprintf(bssid));
4248
4249 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4250 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4251 else
4252 ath_hal_setassocid(ah, bssid, 0);
4253 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4254 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4255 if (ath_hal_keyisvalid(ah, i))
4256 ath_hal_keysetmac(ah, i, bssid);
4257 }
4258
4259 /*
4260 * Notify the rate control algorithm so rates
4261 * are setup should ath_beacon_alloc be called.
4262 */
4263 ath_rate_newstate(sc, nstate);
4264
4265 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4266 /* nothing to do */;
4267 } else if (nstate == IEEE80211_S_RUN) {
4268 DPRINTF(sc, ATH_DEBUG_STATE,
4269 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s "
4270 "capinfo=0x%04x chan=%d\n"
4271 , __func__
4272 , ic->ic_flags
4273 , ni->ni_intval
4274 , ether_sprintf(ni->ni_bssid)
4275 , ni->ni_capinfo
4276 , ieee80211_chan2ieee(ic, ic->ic_curchan));
4277
4278 switch (ic->ic_opmode) {
4279 case IEEE80211_M_HOSTAP:
4280 case IEEE80211_M_IBSS:
4281 /*
4282 * Allocate and setup the beacon frame.
4283 *
4284 * Stop any previous beacon DMA. This may be
4285 * necessary, for example, when an ibss merge
4286 * causes reconfiguration; there will be a state
4287 * transition from RUN->RUN that means we may
4288 * be called with beacon transmission active.
4289 */
4290 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4291 ath_beacon_free(sc);
4292 error = ath_beacon_alloc(sc, ni);
4293 if (error != 0)
4294 goto bad;
4295 /*
4296 * Configure the beacon and sleep timers.
4297 */
4298 ath_beacon_config(sc);
4299 break;
4300 case IEEE80211_M_STA:
4301 /*
4302 * Allocate a key cache slot to the station.
4303 */
4304 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4305 sc->sc_hasclrkey &&
4306 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4307 ath_setup_stationkey(ni);
4308 /*
4309 * Configure the beacon and sleep timers.
4310 */
4311 ath_beacon_config(sc);
4312 break;
4313 default:
4314 break;
4315 }
4316
4317 /*
4318 * Let the hal process statistics collected during a
4319 * scan so it can provide calibrated noise floor data.
4320 */
4321 ath_hal_process_noisefloor(ah);
4322 /*
4323 * Reset rssi stats; maybe not the best place...
4324 */
4325 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4326 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4327 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4328 } else {
4329 ath_hal_intrset(ah,
4330 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4331 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4332 }
4333done:
4334 /*
4335 * Invoke the parent method to complete the work.
4336 */
4337 error = sc->sc_newstate(ic, nstate, arg);
4338 /*
4339 * Finally, start any timers.
4340 */
4341 if (nstate == IEEE80211_S_RUN) {
4342 /* start periodic recalibration timer */
4343 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz,
4344 ath_calibrate, sc);
4345 } else if (nstate == IEEE80211_S_SCAN) {
4346 /* start ap/neighbor scan timer */
4347 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4348 ath_next_scan, sc);
4349 }
4350bad:
4351 return error;
4352}
4353
4354/*
4355 * Allocate a key cache slot to the station so we can
4356 * setup a mapping from key index to node. The key cache
4357 * slot is needed for managing antenna state and for
4358 * compression when stations do not use crypto. We do
4359 * it uniliaterally here; if crypto is employed this slot
4360 * will be reassigned.
4361 */
4362static void
4363ath_setup_stationkey(struct ieee80211_node *ni)
4364{
4365 struct ieee80211com *ic = ni->ni_ic;
4366 struct ath_softc *sc = ic->ic_ifp->if_softc;
4367 ieee80211_keyix keyix, rxkeyix;
4368
4369 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4370 /*
4371 * Key cache is full; we'll fall back to doing
4372 * the more expensive lookup in software. Note
4373 * this also means no h/w compression.
4374 */
4375 /* XXX msg+statistic */
4376 } else {
4377 /* XXX locking? */
4378 ni->ni_ucastkey.wk_keyix = keyix;
4379 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4380 /* NB: this will create a pass-thru key entry */
4381 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4382 }
4383}
4384
4385/*
4386 * Setup driver-specific state for a newly associated node.
4387 * Note that we're called also on a re-associate, the isnew
4388 * param tells us if this is the first time or not.
4389 */
4390static void
4391ath_newassoc(struct ieee80211_node *ni, int isnew)
4392{
4393 struct ieee80211com *ic = ni->ni_ic;
4394 struct ath_softc *sc = ic->ic_ifp->if_softc;
4395
4396 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4397 if (isnew &&
4398 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4399 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4400 ("new assoc with a unicast key already setup (keyix %u)",
4401 ni->ni_ucastkey.wk_keyix));
4402 ath_setup_stationkey(ni);
4403 }
4404}
4405
4406static int
4407ath_getchannels(struct ath_softc *sc, u_int cc,
4408 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4409{
4410 struct ieee80211com *ic = &sc->sc_ic;
4411 struct ifnet *ifp = sc->sc_ifp;
4412 struct ath_hal *ah = sc->sc_ah;
4413 HAL_CHANNEL *chans;
4414 int i, ix, nchan;
4415
4416 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL),
4417 M_TEMP, M_NOWAIT);
4418 if (chans == NULL) {
4419 if_printf(ifp, "unable to allocate channel table\n");
4420 return ENOMEM;
4421 }
4422 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4423 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4424 u_int32_t rd;
4425
4426 ath_hal_getregdomain(ah, &rd);
4427 if_printf(ifp, "unable to collect channel list from hal; "
4428 "regdomain likely %u country code %u\n", rd, cc);
4429 free(chans, M_TEMP);
4430 return EINVAL;
4431 }
4432
4433 /*
4434 * Convert HAL channels to ieee80211 ones and insert
4435 * them in the table according to their channel number.
4436 */
4437 for (i = 0; i < nchan; i++) {
4438 HAL_CHANNEL *c = &chans[i];
4439 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags);
4440 if (ix > IEEE80211_CHAN_MAX) {
4441 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n",
4442 ix, c->channel, c->channelFlags);
4443 continue;
4444 }
4445 /* NB: flags are known to be compatible */
4446 if (ic->ic_channels[ix].ic_freq == 0) {
4447 ic->ic_channels[ix].ic_freq = c->channel;
4448 ic->ic_channels[ix].ic_flags = c->channelFlags;
4449 } else {
4450 /* channels overlap; e.g. 11g and 11b */
4451 ic->ic_channels[ix].ic_flags |= c->channelFlags;
4452 }
4453 }
4454 free(chans, M_TEMP);
4455 return 0;
4456}
4457
4458static void
4459ath_led_done(void *arg)
4460{
4461 struct ath_softc *sc = arg;
4462
4463 sc->sc_blinking = 0;
4464}
4465
4466/*
4467 * Turn the LED off: flip the pin and then set a timer so no
4468 * update will happen for the specified duration.
4469 */
4470static void
4471ath_led_off(void *arg)
4472{
4473 struct ath_softc *sc = arg;
4474
4475 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4476 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4477}
4478
4479/*
4480 * Blink the LED according to the specified on/off times.
4481 */
4482static void
4483ath_led_blink(struct ath_softc *sc, int on, int off)
4484{
4485 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4486 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4487 sc->sc_blinking = 1;
4488 sc->sc_ledoff = off;
4489 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4490}
4491
4492static void
4493ath_led_event(struct ath_softc *sc, int event)
4494{
4495
4496 sc->sc_ledevent = ticks; /* time of last event */
4497 if (sc->sc_blinking) /* don't interrupt active blink */
4498 return;
4499 switch (event) {
4500 case ATH_LED_POLL:
4501 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4502 sc->sc_hwmap[0].ledoff);
4503 break;
4504 case ATH_LED_TX:
4505 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4506 sc->sc_hwmap[sc->sc_txrate].ledoff);
4507 break;
4508 case ATH_LED_RX:
4509 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4510 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4511 break;
4512 }
4513}
4514
4515static void
4516ath_update_txpow(struct ath_softc *sc)
4517{
4518 struct ieee80211com *ic = &sc->sc_ic;
4519 struct ath_hal *ah = sc->sc_ah;
4520 u_int32_t txpow;
4521
4522 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4523 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4524 /* read back in case value is clamped */
4525 ath_hal_gettxpowlimit(ah, &txpow);
4526 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4527 }
4528 /*
4529 * Fetch max tx power level for status requests.
4530 */
4531 ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4532 ic->ic_bss->ni_txpower = txpow;
4533}
4534
4535static void
4536rate_setup(struct ath_softc *sc,
4537 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs)
4538{
4539 int i, maxrates;
4540
4541 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4542 DPRINTF(sc, ATH_DEBUG_ANY,
4543 "%s: rate table too small (%u > %u)\n",
4544 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4545 maxrates = IEEE80211_RATE_MAXSIZE;
4546 } else
4547 maxrates = rt->rateCount;
4548 for (i = 0; i < maxrates; i++)
4549 rs->rs_rates[i] = rt->info[i].dot11Rate;
4550 rs->rs_nrates = maxrates;
4551}
4552
4553static int
4554ath_rate_setup(struct ath_softc *sc, u_int mode)
4555{
4556 struct ath_hal *ah = sc->sc_ah;
4557 struct ieee80211com *ic = &sc->sc_ic;
4558 const HAL_RATE_TABLE *rt;
4559
4560 switch (mode) {
4561 case IEEE80211_MODE_11A:
4562 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4563 break;
4564 case IEEE80211_MODE_11B:
4565 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4566 break;
4567 case IEEE80211_MODE_11G:
4568 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4569 break;
4570 case IEEE80211_MODE_TURBO_A:
4571 /* XXX until static/dynamic turbo is fixed */
4572 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4573 break;
4574 case IEEE80211_MODE_TURBO_G:
4575 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4576 break;
4577 default:
4578 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4579 __func__, mode);
4580 return 0;
4581 }
4582 sc->sc_rates[mode] = rt;
4583 if (rt != NULL) {
4584 rate_setup(sc, rt, &ic->ic_sup_rates[mode]);
4585 return 1;
4586 } else
4587 return 0;
4588}
4589
4590static void
4591ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4592{
4593#define N(a) (sizeof(a)/sizeof(a[0]))
4594 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4595 static const struct {
4596 u_int rate; /* tx/rx 802.11 rate */
4597 u_int16_t timeOn; /* LED on time (ms) */
4598 u_int16_t timeOff; /* LED off time (ms) */
4599 } blinkrates[] = {
4600 { 108, 40, 10 },
4601 { 96, 44, 11 },
4602 { 72, 50, 13 },
4603 { 48, 57, 14 },
4604 { 36, 67, 16 },
4605 { 24, 80, 20 },
4606 { 22, 100, 25 },
4607 { 18, 133, 34 },
4608 { 12, 160, 40 },
4609 { 10, 200, 50 },
4610 { 6, 240, 58 },
4611 { 4, 267, 66 },
4612 { 2, 400, 100 },
4613 { 0, 500, 130 },
4614 };
4615 const HAL_RATE_TABLE *rt;
4616 int i, j;
4617
4618 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4619 rt = sc->sc_rates[mode];
4620 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4621 for (i = 0; i < rt->rateCount; i++)
4622 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4623 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4624 for (i = 0; i < 32; i++) {
4625 u_int8_t ix = rt->rateCodeToIndex[i];
4626 if (ix == 0xff) {
4627 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
4628 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
4629 continue;
4630 }
4631 sc->sc_hwmap[i].ieeerate =
4632 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
4633 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
4634 if (rt->info[ix].shortPreamble ||
4635 rt->info[ix].phy == IEEE80211_T_OFDM)
4636 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
4637 /* NB: receive frames include FCS */
4638 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
4639 IEEE80211_RADIOTAP_F_FCS;
4640 /* setup blink rate table to avoid per-packet lookup */
4641 for (j = 0; j < N(blinkrates)-1; j++)
4642 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
4643 break;
4644 /* NB: this uses the last entry if the rate isn't found */
4645 /* XXX beware of overlow */
4646 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
4647 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
4648 }
4649 sc->sc_currates = rt;
4650 sc->sc_curmode = mode;
4651 /*
4652 * All protection frames are transmited at 2Mb/s for
4653 * 11g, otherwise at 1Mb/s.
4654 */
4655 if (mode == IEEE80211_MODE_11G)
4656 sc->sc_protrix = ath_tx_findrix(rt, 2*2);
4657 else
4658 sc->sc_protrix = ath_tx_findrix(rt, 2*1);
4659 /* rate index used to send management frames */
4660 sc->sc_minrateix = 0;
4661 /*
4662 * Setup multicast rate state.
4663 */
4664 /* XXX layering violation */
4665 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
4666 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
4667 /* NB: caller is responsible for reseting rate control state */
4668#undef N
4669}
4670
4671#ifdef AR_DEBUG
4672static void
4673ath_printrxbuf(struct ath_buf *bf, int done)
4674{
4675 struct ath_desc *ds;
4676 int i;
4677
4678 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4679 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n",
4680 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4681 ds->ds_link, ds->ds_data,
4682 ds->ds_ctl0, ds->ds_ctl1,
4683 ds->ds_hw[0], ds->ds_hw[1],
4684 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
4685 }
4686}
4687
4688static void
4689ath_printtxbuf(struct ath_buf *bf, int done)
4690{
4691 struct ath_desc *ds;
4692 int i;
4693
4694 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4695 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n",
4696 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4697 ds->ds_link, ds->ds_data,
4698 ds->ds_ctl0, ds->ds_ctl1,
4699 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
4700 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
4701 }
4702}
4703#endif /* AR_DEBUG */
4704
4705static void
4706ath_watchdog(struct ifnet *ifp)
4707{
4708 struct ath_softc *sc = ifp->if_softc;
4709 struct ieee80211com *ic = &sc->sc_ic;
4710
4711 ifp->if_timer = 0;
4712 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
4713 return;
4714 if (sc->sc_tx_timer) {
4715 if (--sc->sc_tx_timer == 0) {
4716 if_printf(ifp, "device timeout\n");
4717 ath_reset(ifp);
4718 ifp->if_oerrors++;
4719 sc->sc_stats.ast_watchdog++;
4720 } else
4721 ifp->if_timer = 1;
4722 }
4723 ieee80211_watchdog(ic);
4724}
4725
4726/*
4727 * Diagnostic interface to the HAL. This is used by various
4728 * tools to do things like retrieve register contents for
4729 * debugging. The mechanism is intentionally opaque so that
4730 * it can change frequently w/o concern for compatiblity.
4731 */
4732static int
4733ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
4734{
4735 struct ath_hal *ah = sc->sc_ah;
4736 u_int id = ad->ad_id & ATH_DIAG_ID;
4737 void *indata = NULL;
4738 void *outdata = NULL;
4739 u_int32_t insize = ad->ad_in_size;
4740 u_int32_t outsize = ad->ad_out_size;
4741 int error = 0;
4742
4743 if (ad->ad_id & ATH_DIAG_IN) {
4744 /*
4745 * Copy in data.
4746 */
4747 indata = malloc(insize, M_TEMP, M_NOWAIT);
4748 if (indata == NULL) {
4749 error = ENOMEM;
4750 goto bad;
4751 }
4752 error = copyin(ad->ad_in_data, indata, insize);
4753 if (error)
4754 goto bad;
4755 }
4756 if (ad->ad_id & ATH_DIAG_DYN) {
4757 /*
4758 * Allocate a buffer for the results (otherwise the HAL
4759 * returns a pointer to a buffer where we can read the
4760 * results). Note that we depend on the HAL leaving this
4761 * pointer for us to use below in reclaiming the buffer;
4762 * may want to be more defensive.
4763 */
4764 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
4765 if (outdata == NULL) {
4766 error = ENOMEM;
4767 goto bad;
4768 }
4769 }
4770 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
4771 if (outsize < ad->ad_out_size)
4772 ad->ad_out_size = outsize;
4773 if (outdata != NULL)
4774 error = copyout(outdata, ad->ad_out_data,
4775 ad->ad_out_size);
4776 } else {
4777 error = EINVAL;
4778 }
4779bad:
4780 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
4781 free(indata, M_TEMP);
4782 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
4783 free(outdata, M_TEMP);
4784 return error;
4785}
4786
4787static int
4788ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
4789{
4790#define IS_RUNNING(ifp) \
4791 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
4792 struct ath_softc *sc = ifp->if_softc;
4793 struct ieee80211com *ic = &sc->sc_ic;
4794 struct ifreq *ifr = (struct ifreq *)data;
4795 int error = 0;
4796
4797 ATH_LOCK(sc);
4798 switch (cmd) {
4799 case SIOCSIFFLAGS:
4800 if (IS_RUNNING(ifp)) {
4801 /*
4802 * To avoid rescanning another access point,
4803 * do not call ath_init() here. Instead,
4804 * only reflect promisc mode settings.
4805 */
4806 ath_mode_init(sc);
4807 } else if (ifp->if_flags & IFF_UP) {
4808 /*
4809 * Beware of being called during attach/detach
4810 * to reset promiscuous mode. In that case we
4811 * will still be marked UP but not RUNNING.
4812 * However trying to re-init the interface
4813 * is the wrong thing to do as we've already
4814 * torn down much of our state. There's
4815 * probably a better way to deal with this.
4816 */
4817 if (!sc->sc_invalid && ic->ic_bss != NULL)
4818 ath_init(sc); /* XXX lose error */
4819 } else
4820 ath_stop_locked(ifp);
4821 break;
4822 case SIOCADDMULTI:
4823 case SIOCDELMULTI:
4824 /*
4825 * The upper layer has already installed/removed
4826 * the multicast address(es), just recalculate the
4827 * multicast filter for the card.
4828 */
4829 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4830 ath_mode_init(sc);
4831 break;
4832 case SIOCGATHSTATS:
4833 /* NB: embed these numbers to get a consistent view */
4834 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
4835 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
4836 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
4837 ATH_UNLOCK(sc);
4838 /*
4839 * NB: Drop the softc lock in case of a page fault;
4840 * we'll accept any potential inconsisentcy in the
4841 * statistics. The alternative is to copy the data
4842 * to a local structure.
4843 */
4844 return copyout(&sc->sc_stats,
4845 ifr->ifr_data, sizeof (sc->sc_stats));
4846 case SIOCGATHDIAG:
4847 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
4848 break;
4849 default:
4850 error = ieee80211_ioctl(ic, cmd, data);
4851 if (error == ENETRESET) {
4852 if (IS_RUNNING(ifp) &&
4853 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
4854 ath_init(sc); /* XXX lose error */
4855 error = 0;
4856 }
4857 if (error == ERESTART)
4858 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
4859 break;
4860 }
4861 ATH_UNLOCK(sc);
4862 return error;
4863#undef IS_RUNNING
4864}
4865
4866static int
4867ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
4868{
4869 struct ath_softc *sc = arg1;
4870 u_int slottime = ath_hal_getslottime(sc->sc_ah);
4871 int error;
4872
4873 error = sysctl_handle_int(oidp, &slottime, 0, req);
4874 if (error || !req->newptr)
4875 return error;
4876 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
4877}
4878
4879static int
4880ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
4881{
4882 struct ath_softc *sc = arg1;
4883 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
4884 int error;
4885
4886 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
4887 if (error || !req->newptr)
4888 return error;
4889 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
4890}
4891
4892static int
4893ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
4894{
4895 struct ath_softc *sc = arg1;
4896 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
4897 int error;
4898
4899 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
4900 if (error || !req->newptr)
4901 return error;
4902 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
4903}
4904
4905static int
4906ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
4907{
4908 struct ath_softc *sc = arg1;
4909 int softled = sc->sc_softled;
4910 int error;
4911
4912 error = sysctl_handle_int(oidp, &softled, 0, req);
4913 if (error || !req->newptr)
4914 return error;
4915 softled = (softled != 0);
4916 if (softled != sc->sc_softled) {
4917 if (softled) {
4918 /* NB: handle any sc_ledpin change */
4919 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
4920 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
4921 !sc->sc_ledon);
4922 }
4923 sc->sc_softled = softled;
4924 }
4925 return 0;
4926}
4927
4928static int
4929ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
4930{
4931 struct ath_softc *sc = arg1;
4932 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
4933 int error;
4934
4935 error = sysctl_handle_int(oidp, &defantenna, 0, req);
4936 if (!error && req->newptr)
4937 ath_hal_setdefantenna(sc->sc_ah, defantenna);
4938 return error;
4939}
4940
4941static int
4942ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
4943{
4944 struct ath_softc *sc = arg1;
4945 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
4946 int error;
4947
4948 error = sysctl_handle_int(oidp, &diversity, 0, req);
4949 if (error || !req->newptr)
4950 return error;
4951 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
4952 return EINVAL;
4953 sc->sc_diversity = diversity;
4954 return 0;
4955}
4956
4957static int
4958ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
4959{
4960 struct ath_softc *sc = arg1;
4961 u_int32_t diag;
4962 int error;
4963
4964 if (!ath_hal_getdiag(sc->sc_ah, &diag))
4965 return EINVAL;
4966 error = sysctl_handle_int(oidp, &diag, 0, req);
4967 if (error || !req->newptr)
4968 return error;
4969 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
4970}
4971
4972static int
4973ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
4974{
4975 struct ath_softc *sc = arg1;
4976 struct ifnet *ifp = sc->sc_ifp;
4977 u_int32_t scale;
4978 int error;
4979
4980 ath_hal_gettpscale(sc->sc_ah, &scale);
4981 error = sysctl_handle_int(oidp, &scale, 0, req);
4982 if (error || !req->newptr)
4983 return error;
4984 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
4985}
4986
4987static int
4988ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
4989{
4990 struct ath_softc *sc = arg1;
4991 u_int tpc = ath_hal_gettpc(sc->sc_ah);
4992 int error;
4993
4994 error = sysctl_handle_int(oidp, &tpc, 0, req);
4995 if (error || !req->newptr)
4996 return error;
4997 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
4998}
4999
5000static int
5001ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS)
5002{
5003 struct ath_softc *sc = arg1;
5004 u_int32_t rd;
5005 int error;
5006
5007 if (!ath_hal_getregdomain(sc->sc_ah, &rd))
5008 return EINVAL;
5009 error = sysctl_handle_int(oidp, &rd, 0, req);
5010 if (error || !req->newptr)
5011 return error;
5012 return !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0;
5013}
5014
5015static void
5016ath_sysctlattach(struct ath_softc *sc)
5017{
5018 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
5019 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
5020 struct ath_hal *ah = sc->sc_ah;
5021
5022 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
5023 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5024 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
5025 "EEPROM country code");
5026 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5027 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5028 ath_sysctl_regdomain, "I", "EEPROM regdomain code");
5029 sc->sc_debug = ath_debug;
5030 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5031 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
5032 "control debugging printfs");
5033
5034 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5035 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5036 ath_sysctl_slottime, "I", "802.11 slot time (us)");
5037 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5038 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5039 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
5040 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5041 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5042 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
5043 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5044 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5045 ath_sysctl_softled, "I", "enable/disable software LED support");
5046 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5047 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
5048 "GPIO pin connected to LED");
5049 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5050 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
5051 "setting to turn LED on");
5052 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5053 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
5054 "idle time for inactivity LED (ticks)");
5055 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5056 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
5057 "tx antenna (0=auto)");
5058 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5059 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5060 ath_sysctl_rxantenna, "I", "default/rx antenna");
5061 if (ath_hal_hasdiversity(ah))
5062 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5063 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5064 ath_sysctl_diversity, "I", "antenna diversity");
5065 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
5066 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5067 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
5068 "tx descriptor batching");
5069 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5070 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5071 ath_sysctl_diag, "I", "h/w diagnostic control");
5072 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5073 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5074 ath_sysctl_tpscale, "I", "tx power scaling");
5075 if (ath_hal_hastpc(ah))
5076 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5077 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5078 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
5079 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
5080 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5081 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
5082 "mask of error frames to pass when monitoring");
5083}
5084
5085static void
5086ath_bpfattach(struct ath_softc *sc)
5087{
5088 struct ifnet *ifp = sc->sc_ifp;
5089
5090 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
5091 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
5092 &sc->sc_drvbpf);
5093 /*
5094 * Initialize constant fields.
5095 * XXX make header lengths a multiple of 32-bits so subsequent
5096 * headers are properly aligned; this is a kludge to keep
5097 * certain applications happy.
5098 *
5099 * NB: the channel is setup each time we transition to the
5100 * RUN state to avoid filling it in for each frame.
5101 */
5102 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t));
5103 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
5104 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
5105
5106 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t));
5107 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
5108 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
5109}
5110
5111/*
5112 * Announce various information on device/driver attach.
5113 */
5114static void
5115ath_announce(struct ath_softc *sc)
5116{
5117#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
5118 struct ifnet *ifp = sc->sc_ifp;
5119 struct ath_hal *ah = sc->sc_ah;
5120 u_int modes, cc;
5121
5122 if_printf(ifp, "mac %d.%d phy %d.%d",
5123 ah->ah_macVersion, ah->ah_macRev,
5124 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5125 /*
5126 * Print radio revision(s). We check the wireless modes
5127 * to avoid falsely printing revs for inoperable parts.
5128 * Dual-band radio revs are returned in the 5Ghz rev number.
5129 */
5130 ath_hal_getcountrycode(ah, &cc);
5131 modes = ath_hal_getwirelessmodes(ah, cc);
5132 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
5133 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
5134 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
5135 ah->ah_analog5GhzRev >> 4,
5136 ah->ah_analog5GhzRev & 0xf,
5137 ah->ah_analog2GhzRev >> 4,
5138 ah->ah_analog2GhzRev & 0xf);
5139 else
5140 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5141 ah->ah_analog5GhzRev & 0xf);
5142 } else
5143 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5144 ah->ah_analog5GhzRev & 0xf);
5145 printf("\n");
5146 if (bootverbose) {
5147 int i;
5148 for (i = 0; i <= WME_AC_VO; i++) {
5149 struct ath_txq *txq = sc->sc_ac2q[i];
5150 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5151 txq->axq_qnum, ieee80211_wme_acnames[i]);
5152 }
5153 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5154 sc->sc_cabq->axq_qnum);
5155 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5156 }
5157 if (ath_rxbuf != ATH_RXBUF)
5158 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5159 if (ath_txbuf != ATH_TXBUF)
5160 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5161#undef HAL_MODE_DUALBAND
5162}
|