1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 234089 2012-04-10 07:16:28Z adrian $");
32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42/*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49#include "opt_ah.h"
50#include "opt_wlan.h"
51
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/sysctl.h>
55#include <sys/mbuf.h>
56#include <sys/malloc.h>
57#include <sys/lock.h>
58#include <sys/mutex.h>
59#include <sys/kernel.h>
60#include <sys/socket.h>
61#include <sys/sockio.h>
62#include <sys/errno.h>
63#include <sys/callout.h>
64#include <sys/bus.h>
65#include <sys/endian.h>
66#include <sys/kthread.h>
67#include <sys/taskqueue.h>
68#include <sys/priv.h>
69#include <sys/module.h>
70#include <sys/ktr.h>
71#include <sys/smp.h> /* for mp_ncpus */
72
73#include <machine/bus.h>
74
75#include <net/if.h>
76#include <net/if_dl.h>
77#include <net/if_media.h>
78#include <net/if_types.h>
79#include <net/if_arp.h>
80#include <net/ethernet.h>
81#include <net/if_llc.h>
82
83#include <net80211/ieee80211_var.h>
84#include <net80211/ieee80211_regdomain.h>
85#ifdef IEEE80211_SUPPORT_SUPERG
86#include <net80211/ieee80211_superg.h>
87#endif
88#ifdef IEEE80211_SUPPORT_TDMA
89#include <net80211/ieee80211_tdma.h>
90#endif
91
92#include <net/bpf.h>
93
94#ifdef INET
95#include <netinet/in.h>
96#include <netinet/if_ether.h>
97#endif
98
99#include <dev/ath/if_athvar.h>
100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101#include <dev/ath/ath_hal/ah_diagcodes.h>
102
103#include <dev/ath/if_ath_debug.h>
104#include <dev/ath/if_ath_misc.h>
105#include <dev/ath/if_ath_tx.h>
106#include <dev/ath/if_ath_sysctl.h>
107#include <dev/ath/if_ath_led.h>
108#include <dev/ath/if_ath_keycache.h>
109#include <dev/ath/if_athdfs.h>
110
111#ifdef ATH_TX99_DIAG
112#include <dev/ath/ath_tx99/ath_tx99.h>
113#endif
114
115#define ATH_KTR_INTR KTR_SPARE4
116#define ATH_KTR_ERR KTR_SPARE3
117
118/*
119 * ATH_BCBUF determines the number of vap's that can transmit
120 * beacons and also (currently) the number of vap's that can
121 * have unique mac addresses/bssid. When staggering beacons
122 * 4 is probably a good max as otherwise the beacons become
123 * very closely spaced and there is limited time for cab q traffic
124 * to go out. You can burst beacons instead but that is not good
125 * for stations in power save and at some point you really want
126 * another radio (and channel).
127 *
128 * The limit on the number of mac addresses is tied to our use of
129 * the U/L bit and tracking addresses in a byte; it would be
130 * worthwhile to allow more for applications like proxy sta.
131 */
132CTASSERT(ATH_BCBUF <= 8);
133
134static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
135 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
136 const uint8_t [IEEE80211_ADDR_LEN],
137 const uint8_t [IEEE80211_ADDR_LEN]);
138static void ath_vap_delete(struct ieee80211vap *);
139static void ath_init(void *);
140static void ath_stop_locked(struct ifnet *);
141static void ath_stop(struct ifnet *);
142static void ath_start(struct ifnet *);
143static int ath_reset_vap(struct ieee80211vap *, u_long);
144static int ath_media_change(struct ifnet *);
145static void ath_watchdog(void *);
146static int ath_ioctl(struct ifnet *, u_long, caddr_t);
147static void ath_fatal_proc(void *, int);
148static void ath_bmiss_vap(struct ieee80211vap *);
149static void ath_bmiss_proc(void *, int);
150static void ath_key_update_begin(struct ieee80211vap *);
151static void ath_key_update_end(struct ieee80211vap *);
152static void ath_update_mcast(struct ifnet *);
153static void ath_update_promisc(struct ifnet *);
154static void ath_mode_init(struct ath_softc *);
155static void ath_setslottime(struct ath_softc *);
156static void ath_updateslot(struct ifnet *);
157static int ath_beaconq_setup(struct ath_hal *);
158static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
159static void ath_beacon_update(struct ieee80211vap *, int item);
160static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
161static void ath_beacon_proc(void *, int);
162static struct ath_buf *ath_beacon_generate(struct ath_softc *,
163 struct ieee80211vap *);
164static void ath_bstuck_proc(void *, int);
165static void ath_reset_proc(void *, int);
166static void ath_beacon_return(struct ath_softc *, struct ath_buf *);
167static void ath_beacon_free(struct ath_softc *);
168static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *);
169static void ath_descdma_cleanup(struct ath_softc *sc,
170 struct ath_descdma *, ath_bufhead *);
171static int ath_desc_alloc(struct ath_softc *);
172static void ath_desc_free(struct ath_softc *);
173static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
174 const uint8_t [IEEE80211_ADDR_LEN]);
175static void ath_node_cleanup(struct ieee80211_node *);
176static void ath_node_free(struct ieee80211_node *);
177static void ath_node_getsignal(const struct ieee80211_node *,
178 int8_t *, int8_t *);
179static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
180static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
181 int subtype, int rssi, int nf);
182static void ath_setdefantenna(struct ath_softc *, u_int);
183static void ath_rx_proc(struct ath_softc *sc, int);
184static void ath_rx_tasklet(void *, int);
185static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
186static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
187static int ath_tx_setup(struct ath_softc *, int, int);
188static int ath_wme_update(struct ieee80211com *);
189static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
190static void ath_tx_cleanup(struct ath_softc *);
191static void ath_tx_proc_q0(void *, int);
192static void ath_tx_proc_q0123(void *, int);
193static void ath_tx_proc(void *, int);
194static void ath_txq_sched_tasklet(void *, int);
195static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
196static void ath_draintxq(struct ath_softc *, ATH_RESET_TYPE reset_type);
197static void ath_stoprecv(struct ath_softc *, int);
198static int ath_startrecv(struct ath_softc *);
199static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
200static void ath_scan_start(struct ieee80211com *);
201static void ath_scan_end(struct ieee80211com *);
202static void ath_set_channel(struct ieee80211com *);
203#ifdef ATH_ENABLE_11N
204static void ath_update_chw(struct ieee80211com *);
205#endif /* ATH_ENABLE_11N */
206static void ath_calibrate(void *);
207static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
208static void ath_setup_stationkey(struct ieee80211_node *);
209static void ath_newassoc(struct ieee80211_node *, int);
210static int ath_setregdomain(struct ieee80211com *,
211 struct ieee80211_regdomain *, int,
212 struct ieee80211_channel []);
213static void ath_getradiocaps(struct ieee80211com *, int, int *,
214 struct ieee80211_channel []);
215static int ath_getchannels(struct ath_softc *);
216
217static int ath_rate_setup(struct ath_softc *, u_int mode);
218static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
219
220static void ath_announce(struct ath_softc *);
221
222static void ath_dfs_tasklet(void *, int);
223
224#ifdef IEEE80211_SUPPORT_TDMA
225static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
226 u_int32_t bintval);
227static void ath_tdma_bintvalsetup(struct ath_softc *sc,
228 const struct ieee80211_tdma_state *tdma);
229static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap);
230static void ath_tdma_update(struct ieee80211_node *ni,
231 const struct ieee80211_tdma_param *tdma, int);
232static void ath_tdma_beacon_send(struct ath_softc *sc,
233 struct ieee80211vap *vap);
234
235#define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */
236#define TDMA_LPF_LEN 6
237#define TDMA_DUMMY_MARKER 0x127
238#define TDMA_EP_MUL(x, mul) ((x) * (mul))
239#define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER))
240#define TDMA_LPF(x, y, len) \
241 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y))
242#define TDMA_SAMPLE(x, y) do { \
243 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \
244} while (0)
245#define TDMA_EP_RND(x,mul) \
246 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
247#define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER)
248#endif /* IEEE80211_SUPPORT_TDMA */
249
250SYSCTL_DECL(_hw_ath);
251
252/* XXX validate sysctl values */
253static int ath_longcalinterval = 30; /* long cals every 30 secs */
254SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
255 0, "long chip calibration interval (secs)");
256static int ath_shortcalinterval = 100; /* short cals every 100 ms */
257SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
258 0, "short chip calibration interval (msecs)");
259static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
260SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
261 0, "reset chip calibration results (secs)");
262static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
263SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
264 0, "ANI calibration (msecs)");
265
266static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
267SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
268 0, "rx buffers allocated");
269TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
270static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
271SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
272 0, "tx buffers allocated");
273TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
274
275static int ath_bstuck_threshold = 4; /* max missed beacons */
276SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
277 0, "max missed beacon xmits before chip reset");
278
279MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
280
281#define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
282#define HAL_MODE_HT40 \
283 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
284 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
285int
286ath_attach(u_int16_t devid, struct ath_softc *sc)
287{
288 struct ifnet *ifp;
289 struct ieee80211com *ic;
290 struct ath_hal *ah = NULL;
291 HAL_STATUS status;
292 int error = 0, i;
293 u_int wmodes;
294 uint8_t macaddr[IEEE80211_ADDR_LEN];
295 int rx_chainmask, tx_chainmask;
296
297 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
298
299 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
300 if (ifp == NULL) {
301 device_printf(sc->sc_dev, "can not if_alloc()\n");
302 error = ENOSPC;
303 goto bad;
304 }
305 ic = ifp->if_l2com;
306
307 /* set these up early for if_printf use */
308 if_initname(ifp, device_get_name(sc->sc_dev),
309 device_get_unit(sc->sc_dev));
310
311 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
312 sc->sc_eepromdata, &status);
313 if (ah == NULL) {
314 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
315 status);
316 error = ENXIO;
317 goto bad;
318 }
319 sc->sc_ah = ah;
320 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
321#ifdef ATH_DEBUG
322 sc->sc_debug = ath_debug;
323#endif
324
325 /*
326 * Check if the MAC has multi-rate retry support.
327 * We do this by trying to setup a fake extended
328 * descriptor. MAC's that don't have support will
329 * return false w/o doing anything. MAC's that do
330 * support it will return true w/o doing anything.
331 */
332 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
333
334 /*
335 * Check if the device has hardware counters for PHY
336 * errors. If so we need to enable the MIB interrupt
337 * so we can act on stat triggers.
338 */
339 if (ath_hal_hwphycounters(ah))
340 sc->sc_needmib = 1;
341
342 /*
343 * Get the hardware key cache size.
344 */
345 sc->sc_keymax = ath_hal_keycachesize(ah);
346 if (sc->sc_keymax > ATH_KEYMAX) {
347 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
348 ATH_KEYMAX, sc->sc_keymax);
349 sc->sc_keymax = ATH_KEYMAX;
350 }
351 /*
352 * Reset the key cache since some parts do not
353 * reset the contents on initial power up.
354 */
355 for (i = 0; i < sc->sc_keymax; i++)
356 ath_hal_keyreset(ah, i);
357
358 /*
359 * Collect the default channel list.
360 */
361 error = ath_getchannels(sc);
362 if (error != 0)
363 goto bad;
364
365 /*
366 * Setup rate tables for all potential media types.
367 */
368 ath_rate_setup(sc, IEEE80211_MODE_11A);
369 ath_rate_setup(sc, IEEE80211_MODE_11B);
370 ath_rate_setup(sc, IEEE80211_MODE_11G);
371 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
372 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
373 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
374 ath_rate_setup(sc, IEEE80211_MODE_11NA);
375 ath_rate_setup(sc, IEEE80211_MODE_11NG);
376 ath_rate_setup(sc, IEEE80211_MODE_HALF);
377 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
378
379 /* NB: setup here so ath_rate_update is happy */
380 ath_setcurmode(sc, IEEE80211_MODE_11A);
381
382 /*
383 * Allocate tx+rx descriptors and populate the lists.
384 */
385 error = ath_desc_alloc(sc);
386 if (error != 0) {
387 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
388 goto bad;
389 }
390 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
391 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
392
393 ATH_TXBUF_LOCK_INIT(sc);
394
395 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
396 taskqueue_thread_enqueue, &sc->sc_tq);
397 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
398 "%s taskq", ifp->if_xname);
399
400 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_tasklet, sc);
401 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
402 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
403 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
404 TASK_INIT(&sc->sc_txqtask,0, ath_txq_sched_tasklet, sc);
405
406 /*
407 * Allocate hardware transmit queues: one queue for
408 * beacon frames and one data queue for each QoS
409 * priority. Note that the hal handles resetting
410 * these queues at the needed time.
411 *
412 * XXX PS-Poll
413 */
414 sc->sc_bhalq = ath_beaconq_setup(ah);
415 if (sc->sc_bhalq == (u_int) -1) {
416 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
417 error = EIO;
418 goto bad2;
419 }
420 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
421 if (sc->sc_cabq == NULL) {
422 if_printf(ifp, "unable to setup CAB xmit queue!\n");
423 error = EIO;
424 goto bad2;
425 }
426 /* NB: insure BK queue is the lowest priority h/w queue */
427 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
428 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
429 ieee80211_wme_acnames[WME_AC_BK]);
430 error = EIO;
431 goto bad2;
432 }
433 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
434 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
435 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
436 /*
437 * Not enough hardware tx queues to properly do WME;
438 * just punt and assign them all to the same h/w queue.
439 * We could do a better job of this if, for example,
440 * we allocate queues when we switch from station to
441 * AP mode.
442 */
443 if (sc->sc_ac2q[WME_AC_VI] != NULL)
444 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
445 if (sc->sc_ac2q[WME_AC_BE] != NULL)
446 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
447 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
448 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
449 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
450 }
451
452 /*
453 * Special case certain configurations. Note the
454 * CAB queue is handled by these specially so don't
455 * include them when checking the txq setup mask.
456 */
457 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
458 case 0x01:
459 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
460 break;
461 case 0x0f:
462 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
463 break;
464 default:
465 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
466 break;
467 }
468
469 /*
470 * Setup rate control. Some rate control modules
471 * call back to change the anntena state so expose
472 * the necessary entry points.
473 * XXX maybe belongs in struct ath_ratectrl?
474 */
475 sc->sc_setdefantenna = ath_setdefantenna;
476 sc->sc_rc = ath_rate_attach(sc);
477 if (sc->sc_rc == NULL) {
478 error = EIO;
479 goto bad2;
480 }
481
482 /* Attach DFS module */
483 if (! ath_dfs_attach(sc)) {
484 device_printf(sc->sc_dev,
485 "%s: unable to attach DFS\n", __func__);
486 error = EIO;
487 goto bad2;
488 }
489
490 /* Start DFS processing tasklet */
491 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
492
493 /* Configure LED state */
494 sc->sc_blinking = 0;
495 sc->sc_ledstate = 1;
496 sc->sc_ledon = 0; /* low true */
497 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
498 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
499
500 /*
501 * Don't setup hardware-based blinking.
502 *
503 * Although some NICs may have this configured in the
504 * default reset register values, the user may wish
505 * to alter which pins have which function.
506 *
507 * The reference driver attaches the MAC network LED to GPIO1 and
508 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
509 * NIC has these reversed.
510 */
511 sc->sc_hardled = (1 == 0);
512 sc->sc_led_net_pin = -1;
513 sc->sc_led_pwr_pin = -1;
514 /*
515 * Auto-enable soft led processing for IBM cards and for
516 * 5211 minipci cards. Users can also manually enable/disable
517 * support with a sysctl.
518 */
519 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
520 ath_led_config(sc);
521 ath_hal_setledstate(ah, HAL_LED_INIT);
522
523 ifp->if_softc = sc;
524 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
525 ifp->if_start = ath_start;
526 ifp->if_ioctl = ath_ioctl;
527 ifp->if_init = ath_init;
528 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
529 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
530 IFQ_SET_READY(&ifp->if_snd);
531
532 ic->ic_ifp = ifp;
533 /* XXX not right but it's not used anywhere important */
534 ic->ic_phytype = IEEE80211_T_OFDM;
535 ic->ic_opmode = IEEE80211_M_STA;
536 ic->ic_caps =
537 IEEE80211_C_STA /* station mode */
538 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
539 | IEEE80211_C_HOSTAP /* hostap mode */
540 | IEEE80211_C_MONITOR /* monitor mode */
541 | IEEE80211_C_AHDEMO /* adhoc demo mode */
542 | IEEE80211_C_WDS /* 4-address traffic works */
543 | IEEE80211_C_MBSS /* mesh point link mode */
544 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
545 | IEEE80211_C_SHSLOT /* short slot time supported */
546 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
547 | IEEE80211_C_BGSCAN /* capable of bg scanning */
548 | IEEE80211_C_TXFRAG /* handle tx frags */
549#ifdef ATH_ENABLE_DFS
550 | IEEE80211_C_DFS /* Enable radar detection */
551#endif
552 ;
553 /*
554 * Query the hal to figure out h/w crypto support.
555 */
556 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
557 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
558 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
559 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
560 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
561 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
562 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
563 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
564 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
565 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
566 /*
567 * Check if h/w does the MIC and/or whether the
568 * separate key cache entries are required to
569 * handle both tx+rx MIC keys.
570 */
571 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
572 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
573 /*
574 * If the h/w supports storing tx+rx MIC keys
575 * in one cache slot automatically enable use.
576 */
577 if (ath_hal_hastkipsplit(ah) ||
578 !ath_hal_settkipsplit(ah, AH_FALSE))
579 sc->sc_splitmic = 1;
580 /*
581 * If the h/w can do TKIP MIC together with WME then
582 * we use it; otherwise we force the MIC to be done
583 * in software by the net80211 layer.
584 */
585 if (ath_hal_haswmetkipmic(ah))
586 sc->sc_wmetkipmic = 1;
587 }
588 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
589 /*
590 * Check for multicast key search support.
591 */
592 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
593 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
594 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
595 }
596 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
597 /*
598 * Mark key cache slots associated with global keys
599 * as in use. If we knew TKIP was not to be used we
600 * could leave the +32, +64, and +32+64 slots free.
601 */
602 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
603 setbit(sc->sc_keymap, i);
604 setbit(sc->sc_keymap, i+64);
605 if (sc->sc_splitmic) {
606 setbit(sc->sc_keymap, i+32);
607 setbit(sc->sc_keymap, i+32+64);
608 }
609 }
610 /*
611 * TPC support can be done either with a global cap or
612 * per-packet support. The latter is not available on
613 * all parts. We're a bit pedantic here as all parts
614 * support a global cap.
615 */
616 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
617 ic->ic_caps |= IEEE80211_C_TXPMGT;
618
619 /*
620 * Mark WME capability only if we have sufficient
621 * hardware queues to do proper priority scheduling.
622 */
623 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
624 ic->ic_caps |= IEEE80211_C_WME;
625 /*
626 * Check for misc other capabilities.
627 */
628 if (ath_hal_hasbursting(ah))
629 ic->ic_caps |= IEEE80211_C_BURST;
630 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
631 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
632 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
633 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
634 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah);
635 if (ath_hal_hasfastframes(ah))
636 ic->ic_caps |= IEEE80211_C_FF;
637 wmodes = ath_hal_getwirelessmodes(ah);
638 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
639 ic->ic_caps |= IEEE80211_C_TURBOP;
640#ifdef IEEE80211_SUPPORT_TDMA
641 if (ath_hal_macversion(ah) > 0x78) {
642 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
643 ic->ic_tdma_update = ath_tdma_update;
644 }
645#endif
646
647 /*
648 * TODO: enforce that at least this many frames are available
649 * in the txbuf list before allowing data frames (raw or
650 * otherwise) to be transmitted.
651 */
652 sc->sc_txq_data_minfree = 10;
653 /*
654 * Leave this as default to maintain legacy behaviour.
655 * Shortening the cabq/mcastq may end up causing some
656 * undesirable behaviour.
657 */
658 sc->sc_txq_mcastq_maxdepth = ath_txbuf;
659
660 /*
661 * Allow the TX and RX chainmasks to be overridden by
662 * environment variables and/or device.hints.
663 *
664 * This must be done early - before the hardware is
665 * calibrated or before the 802.11n stream calculation
666 * is done.
667 */
668 if (resource_int_value(device_get_name(sc->sc_dev),
669 device_get_unit(sc->sc_dev), "rx_chainmask",
670 &rx_chainmask) == 0) {
671 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
672 rx_chainmask);
673 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
674 }
675 if (resource_int_value(device_get_name(sc->sc_dev),
676 device_get_unit(sc->sc_dev), "tx_chainmask",
677 &tx_chainmask) == 0) {
678 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
679 tx_chainmask);
680 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
681 }
682
683 /*
684 * The if_ath 11n support is completely not ready for normal use.
685 * Enabling this option will likely break everything and everything.
686 * Don't think of doing that unless you know what you're doing.
687 */
688
689#ifdef ATH_ENABLE_11N
690 /*
691 * Query HT capabilities
692 */
693 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
694 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
695 int rxs, txs;
696
697 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
698 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
699 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
700 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
701 | IEEE80211_HTCAP_MAXAMSDU_3839
702 /* max A-MSDU length */
703 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
704 ;
705
706 /*
707 * Enable short-GI for HT20 only if the hardware
708 * advertises support.
709 * Notably, anything earlier than the AR9287 doesn't.
710 */
711 if ((ath_hal_getcapability(ah,
712 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
713 (wmodes & HAL_MODE_HT20)) {
714 device_printf(sc->sc_dev,
715 "[HT] enabling short-GI in 20MHz mode\n");
716 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
717 }
718
719 if (wmodes & HAL_MODE_HT40)
720 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
721 | IEEE80211_HTCAP_SHORTGI40;
722
723 /*
724 * TX/RX streams need to be taken into account when
725 * negotiating which MCS rates it'll receive and
726 * what MCS rates are available for TX.
727 */
728 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
729 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
730
731 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
732 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
733
734 ic->ic_txstream = txs;
735 ic->ic_rxstream = rxs;
736
737 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
738 &sc->sc_rts_aggr_limit);
739 if (sc->sc_rts_aggr_limit != (64 * 1024))
740 device_printf(sc->sc_dev,
741 "[HT] RTS aggregates limited to %d KiB\n",
742 sc->sc_rts_aggr_limit / 1024);
743
744 device_printf(sc->sc_dev,
745 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
746 }
747#endif
748
749 /*
750 * Check if the hardware requires PCI register serialisation.
751 * Some of the Owl based MACs require this.
752 */
753 if (mp_ncpus > 1 &&
754 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
755 0, NULL) == HAL_OK) {
756 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
757 device_printf(sc->sc_dev,
758 "Enabling register serialisation\n");
759 }
760
761 /*
762 * Indicate we need the 802.11 header padded to a
763 * 32-bit boundary for 4-address and QoS frames.
764 */
765 ic->ic_flags |= IEEE80211_F_DATAPAD;
766
767 /*
768 * Query the hal about antenna support.
769 */
770 sc->sc_defant = ath_hal_getdefantenna(ah);
771
772 /*
773 * Not all chips have the VEOL support we want to
774 * use with IBSS beacons; check here for it.
775 */
776 sc->sc_hasveol = ath_hal_hasveol(ah);
777
778 /* get mac address from hardware */
779 ath_hal_getmac(ah, macaddr);
780 if (sc->sc_hasbmask)
781 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
782
783 /* NB: used to size node table key mapping array */
784 ic->ic_max_keyix = sc->sc_keymax;
785 /* call MI attach routine. */
786 ieee80211_ifattach(ic, macaddr);
787 ic->ic_setregdomain = ath_setregdomain;
788 ic->ic_getradiocaps = ath_getradiocaps;
789 sc->sc_opmode = HAL_M_STA;
790
791 /* override default methods */
792 ic->ic_newassoc = ath_newassoc;
793 ic->ic_updateslot = ath_updateslot;
794 ic->ic_wme.wme_update = ath_wme_update;
795 ic->ic_vap_create = ath_vap_create;
796 ic->ic_vap_delete = ath_vap_delete;
797 ic->ic_raw_xmit = ath_raw_xmit;
798 ic->ic_update_mcast = ath_update_mcast;
799 ic->ic_update_promisc = ath_update_promisc;
800 ic->ic_node_alloc = ath_node_alloc;
801 sc->sc_node_free = ic->ic_node_free;
802 ic->ic_node_free = ath_node_free;
803 sc->sc_node_cleanup = ic->ic_node_cleanup;
804 ic->ic_node_cleanup = ath_node_cleanup;
805 ic->ic_node_getsignal = ath_node_getsignal;
806 ic->ic_scan_start = ath_scan_start;
807 ic->ic_scan_end = ath_scan_end;
808 ic->ic_set_channel = ath_set_channel;
809#ifdef ATH_ENABLE_11N
810 /* 802.11n specific - but just override anyway */
811 sc->sc_addba_request = ic->ic_addba_request;
812 sc->sc_addba_response = ic->ic_addba_response;
813 sc->sc_addba_stop = ic->ic_addba_stop;
814 sc->sc_bar_response = ic->ic_bar_response;
815 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
816
817 ic->ic_addba_request = ath_addba_request;
818 ic->ic_addba_response = ath_addba_response;
819 ic->ic_addba_response_timeout = ath_addba_response_timeout;
820 ic->ic_addba_stop = ath_addba_stop;
821 ic->ic_bar_response = ath_bar_response;
822
823 ic->ic_update_chw = ath_update_chw;
824#endif /* ATH_ENABLE_11N */
825
826 ieee80211_radiotap_attach(ic,
827 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
828 ATH_TX_RADIOTAP_PRESENT,
829 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
830 ATH_RX_RADIOTAP_PRESENT);
831
832 /*
833 * Setup dynamic sysctl's now that country code and
834 * regdomain are available from the hal.
835 */
836 ath_sysctlattach(sc);
837 ath_sysctl_stats_attach(sc);
838 ath_sysctl_hal_attach(sc);
839
840 if (bootverbose)
841 ieee80211_announce(ic);
842 ath_announce(sc);
843 return 0;
844bad2:
845 ath_tx_cleanup(sc);
846 ath_desc_free(sc);
847bad:
848 if (ah)
849 ath_hal_detach(ah);
850 if (ifp != NULL)
851 if_free(ifp);
852 sc->sc_invalid = 1;
853 return error;
854}
855
856int
857ath_detach(struct ath_softc *sc)
858{
859 struct ifnet *ifp = sc->sc_ifp;
860
861 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
862 __func__, ifp->if_flags);
863
864 /*
865 * NB: the order of these is important:
866 * o stop the chip so no more interrupts will fire
867 * o call the 802.11 layer before detaching the hal to
868 * insure callbacks into the driver to delete global
869 * key cache entries can be handled
870 * o free the taskqueue which drains any pending tasks
871 * o reclaim the tx queue data structures after calling
872 * the 802.11 layer as we'll get called back to reclaim
873 * node state and potentially want to use them
874 * o to cleanup the tx queues the hal is called, so detach
875 * it last
876 * Other than that, it's straightforward...
877 */
878 ath_stop(ifp);
879 ieee80211_ifdetach(ifp->if_l2com);
880 taskqueue_free(sc->sc_tq);
881#ifdef ATH_TX99_DIAG
882 if (sc->sc_tx99 != NULL)
883 sc->sc_tx99->detach(sc->sc_tx99);
884#endif
885 ath_rate_detach(sc->sc_rc);
886
887 ath_dfs_detach(sc);
888 ath_desc_free(sc);
889 ath_tx_cleanup(sc);
890 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
891 if_free(ifp);
892
893 return 0;
894}
895
896/*
897 * MAC address handling for multiple BSS on the same radio.
898 * The first vap uses the MAC address from the EEPROM. For
899 * subsequent vap's we set the U/L bit (bit 1) in the MAC
900 * address and use the next six bits as an index.
901 */
902static void
903assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
904{
905 int i;
906
907 if (clone && sc->sc_hasbmask) {
908 /* NB: we only do this if h/w supports multiple bssid */
909 for (i = 0; i < 8; i++)
910 if ((sc->sc_bssidmask & (1<<i)) == 0)
911 break;
912 if (i != 0)
913 mac[0] |= (i << 2)|0x2;
914 } else
915 i = 0;
916 sc->sc_bssidmask |= 1<<i;
917 sc->sc_hwbssidmask[0] &= ~mac[0];
918 if (i == 0)
919 sc->sc_nbssid0++;
920}
921
922static void
923reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
924{
925 int i = mac[0] >> 2;
926 uint8_t mask;
927
928 if (i != 0 || --sc->sc_nbssid0 == 0) {
929 sc->sc_bssidmask &= ~(1<<i);
930 /* recalculate bssid mask from remaining addresses */
931 mask = 0xff;
932 for (i = 1; i < 8; i++)
933 if (sc->sc_bssidmask & (1<<i))
934 mask &= ~((i<<2)|0x2);
935 sc->sc_hwbssidmask[0] |= mask;
936 }
937}
938
939/*
940 * Assign a beacon xmit slot. We try to space out
941 * assignments so when beacons are staggered the
942 * traffic coming out of the cab q has maximal time
943 * to go out before the next beacon is scheduled.
944 */
945static int
946assign_bslot(struct ath_softc *sc)
947{
948 u_int slot, free;
949
950 free = 0;
951 for (slot = 0; slot < ATH_BCBUF; slot++)
952 if (sc->sc_bslot[slot] == NULL) {
953 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
954 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
955 return slot;
956 free = slot;
957 /* NB: keep looking for a double slot */
958 }
959 return free;
960}
961
962static struct ieee80211vap *
963ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
964 enum ieee80211_opmode opmode, int flags,
965 const uint8_t bssid[IEEE80211_ADDR_LEN],
966 const uint8_t mac0[IEEE80211_ADDR_LEN])
967{
968 struct ath_softc *sc = ic->ic_ifp->if_softc;
969 struct ath_vap *avp;
970 struct ieee80211vap *vap;
971 uint8_t mac[IEEE80211_ADDR_LEN];
972 int needbeacon, error;
973 enum ieee80211_opmode ic_opmode;
974
975 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
976 M_80211_VAP, M_WAITOK | M_ZERO);
977 needbeacon = 0;
978 IEEE80211_ADDR_COPY(mac, mac0);
979
980 ATH_LOCK(sc);
981 ic_opmode = opmode; /* default to opmode of new vap */
982 switch (opmode) {
983 case IEEE80211_M_STA:
984 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
985 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
986 goto bad;
987 }
988 if (sc->sc_nvaps) {
989 /*
990 * With multiple vaps we must fall back
991 * to s/w beacon miss handling.
992 */
993 flags |= IEEE80211_CLONE_NOBEACONS;
994 }
995 if (flags & IEEE80211_CLONE_NOBEACONS) {
996 /*
997 * Station mode w/o beacons are implemented w/ AP mode.
998 */
999 ic_opmode = IEEE80211_M_HOSTAP;
1000 }
1001 break;
1002 case IEEE80211_M_IBSS:
1003 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1004 device_printf(sc->sc_dev,
1005 "only 1 ibss vap supported\n");
1006 goto bad;
1007 }
1008 needbeacon = 1;
1009 break;
1010 case IEEE80211_M_AHDEMO:
1011#ifdef IEEE80211_SUPPORT_TDMA
1012 if (flags & IEEE80211_CLONE_TDMA) {
1013 if (sc->sc_nvaps != 0) {
1014 device_printf(sc->sc_dev,
1015 "only 1 tdma vap supported\n");
1016 goto bad;
1017 }
1018 needbeacon = 1;
1019 flags |= IEEE80211_CLONE_NOBEACONS;
1020 }
1021 /* fall thru... */
1022#endif
1023 case IEEE80211_M_MONITOR:
1024 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1025 /*
1026 * Adopt existing mode. Adding a monitor or ahdemo
1027 * vap to an existing configuration is of dubious
1028 * value but should be ok.
1029 */
1030 /* XXX not right for monitor mode */
1031 ic_opmode = ic->ic_opmode;
1032 }
1033 break;
1034 case IEEE80211_M_HOSTAP:
1035 case IEEE80211_M_MBSS:
1036 needbeacon = 1;
1037 break;
1038 case IEEE80211_M_WDS:
1039 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1040 device_printf(sc->sc_dev,
1041 "wds not supported in sta mode\n");
1042 goto bad;
1043 }
1044 /*
1045 * Silently remove any request for a unique
1046 * bssid; WDS vap's always share the local
1047 * mac address.
1048 */
1049 flags &= ~IEEE80211_CLONE_BSSID;
1050 if (sc->sc_nvaps == 0)
1051 ic_opmode = IEEE80211_M_HOSTAP;
1052 else
1053 ic_opmode = ic->ic_opmode;
1054 break;
1055 default:
1056 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1057 goto bad;
1058 }
1059 /*
1060 * Check that a beacon buffer is available; the code below assumes it.
1061 */
1062 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1063 device_printf(sc->sc_dev, "no beacon buffer available\n");
1064 goto bad;
1065 }
1066
1067 /* STA, AHDEMO? */
1068 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1069 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1070 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1071 }
1072
1073 vap = &avp->av_vap;
1074 /* XXX can't hold mutex across if_alloc */
1075 ATH_UNLOCK(sc);
1076 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1077 bssid, mac);
1078 ATH_LOCK(sc);
1079 if (error != 0) {
1080 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1081 __func__, error);
1082 goto bad2;
1083 }
1084
1085 /* h/w crypto support */
1086 vap->iv_key_alloc = ath_key_alloc;
1087 vap->iv_key_delete = ath_key_delete;
1088 vap->iv_key_set = ath_key_set;
1089 vap->iv_key_update_begin = ath_key_update_begin;
1090 vap->iv_key_update_end = ath_key_update_end;
1091
1092 /* override various methods */
1093 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1094 vap->iv_recv_mgmt = ath_recv_mgmt;
1095 vap->iv_reset = ath_reset_vap;
1096 vap->iv_update_beacon = ath_beacon_update;
1097 avp->av_newstate = vap->iv_newstate;
1098 vap->iv_newstate = ath_newstate;
1099 avp->av_bmiss = vap->iv_bmiss;
1100 vap->iv_bmiss = ath_bmiss_vap;
1101
1102 /* Set default parameters */
1103
1104 /*
1105 * Anything earlier than some AR9300 series MACs don't
1106 * support a smaller MPDU density.
1107 */
1108 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1109 /*
1110 * All NICs can handle the maximum size, however
1111 * AR5416 based MACs can only TX aggregates w/ RTS
1112 * protection when the total aggregate size is <= 8k.
1113 * However, for now that's enforced by the TX path.
1114 */
1115 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1116
1117 avp->av_bslot = -1;
1118 if (needbeacon) {
1119 /*
1120 * Allocate beacon state and setup the q for buffered
1121 * multicast frames. We know a beacon buffer is
1122 * available because we checked above.
1123 */
1124 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1125 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1126 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1127 /*
1128 * Assign the vap to a beacon xmit slot. As above
1129 * this cannot fail to find a free one.
1130 */
1131 avp->av_bslot = assign_bslot(sc);
1132 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1133 ("beacon slot %u not empty", avp->av_bslot));
1134 sc->sc_bslot[avp->av_bslot] = vap;
1135 sc->sc_nbcnvaps++;
1136 }
1137 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1138 /*
1139 * Multple vaps are to transmit beacons and we
1140 * have h/w support for TSF adjusting; enable
1141 * use of staggered beacons.
1142 */
1143 sc->sc_stagbeacons = 1;
1144 }
1145 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1146 }
1147
1148 ic->ic_opmode = ic_opmode;
1149 if (opmode != IEEE80211_M_WDS) {
1150 sc->sc_nvaps++;
1151 if (opmode == IEEE80211_M_STA)
1152 sc->sc_nstavaps++;
1153 if (opmode == IEEE80211_M_MBSS)
1154 sc->sc_nmeshvaps++;
1155 }
1156 switch (ic_opmode) {
1157 case IEEE80211_M_IBSS:
1158 sc->sc_opmode = HAL_M_IBSS;
1159 break;
1160 case IEEE80211_M_STA:
1161 sc->sc_opmode = HAL_M_STA;
1162 break;
1163 case IEEE80211_M_AHDEMO:
1164#ifdef IEEE80211_SUPPORT_TDMA
1165 if (vap->iv_caps & IEEE80211_C_TDMA) {
1166 sc->sc_tdma = 1;
1167 /* NB: disable tsf adjust */
1168 sc->sc_stagbeacons = 0;
1169 }
1170 /*
1171 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1172 * just ap mode.
1173 */
1174 /* fall thru... */
1175#endif
1176 case IEEE80211_M_HOSTAP:
1177 case IEEE80211_M_MBSS:
1178 sc->sc_opmode = HAL_M_HOSTAP;
1179 break;
1180 case IEEE80211_M_MONITOR:
1181 sc->sc_opmode = HAL_M_MONITOR;
1182 break;
1183 default:
1184 /* XXX should not happen */
1185 break;
1186 }
1187 if (sc->sc_hastsfadd) {
1188 /*
1189 * Configure whether or not TSF adjust should be done.
1190 */
1191 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1192 }
1193 if (flags & IEEE80211_CLONE_NOBEACONS) {
1194 /*
1195 * Enable s/w beacon miss handling.
1196 */
1197 sc->sc_swbmiss = 1;
1198 }
1199 ATH_UNLOCK(sc);
1200
1201 /* complete setup */
1202 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1203 return vap;
1204bad2:
1205 reclaim_address(sc, mac);
1206 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1207bad:
1208 free(avp, M_80211_VAP);
1209 ATH_UNLOCK(sc);
1210 return NULL;
1211}
1212
1213static void
1214ath_vap_delete(struct ieee80211vap *vap)
1215{
1216 struct ieee80211com *ic = vap->iv_ic;
1217 struct ifnet *ifp = ic->ic_ifp;
1218 struct ath_softc *sc = ifp->if_softc;
1219 struct ath_hal *ah = sc->sc_ah;
1220 struct ath_vap *avp = ATH_VAP(vap);
1221
1222 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1223 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1224 /*
1225 * Quiesce the hardware while we remove the vap. In
1226 * particular we need to reclaim all references to
1227 * the vap state by any frames pending on the tx queues.
1228 */
1229 ath_hal_intrset(ah, 0); /* disable interrupts */
1230 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1231 /* XXX Do all frames from all vaps/nodes need draining here? */
1232 ath_stoprecv(sc, 1); /* stop recv side */
1233 }
1234
1235 ieee80211_vap_detach(vap);
1236
1237 /*
1238 * XXX Danger Will Robinson! Danger!
1239 *
1240 * Because ieee80211_vap_detach() can queue a frame (the station
1241 * diassociate message?) after we've drained the TXQ and
1242 * flushed the software TXQ, we will end up with a frame queued
1243 * to a node whose vap is about to be freed.
1244 *
1245 * To work around this, flush the hardware/software again.
1246 * This may be racy - the ath task may be running and the packet
1247 * may be being scheduled between sw->hw txq. Tsk.
1248 *
1249 * TODO: figure out why a new node gets allocated somewhere around
1250 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1251 * call!)
1252 */
1253
1254 ath_draintxq(sc, ATH_RESET_DEFAULT);
1255
1256 ATH_LOCK(sc);
1257 /*
1258 * Reclaim beacon state. Note this must be done before
1259 * the vap instance is reclaimed as we may have a reference
1260 * to it in the buffer for the beacon frame.
1261 */
1262 if (avp->av_bcbuf != NULL) {
1263 if (avp->av_bslot != -1) {
1264 sc->sc_bslot[avp->av_bslot] = NULL;
1265 sc->sc_nbcnvaps--;
1266 }
1267 ath_beacon_return(sc, avp->av_bcbuf);
1268 avp->av_bcbuf = NULL;
1269 if (sc->sc_nbcnvaps == 0) {
1270 sc->sc_stagbeacons = 0;
1271 if (sc->sc_hastsfadd)
1272 ath_hal_settsfadjust(sc->sc_ah, 0);
1273 }
1274 /*
1275 * Reclaim any pending mcast frames for the vap.
1276 */
1277 ath_tx_draintxq(sc, &avp->av_mcastq);
1278 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq);
1279 }
1280 /*
1281 * Update bookkeeping.
1282 */
1283 if (vap->iv_opmode == IEEE80211_M_STA) {
1284 sc->sc_nstavaps--;
1285 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1286 sc->sc_swbmiss = 0;
1287 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1288 vap->iv_opmode == IEEE80211_M_MBSS) {
1289 reclaim_address(sc, vap->iv_myaddr);
1290 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1291 if (vap->iv_opmode == IEEE80211_M_MBSS)
1292 sc->sc_nmeshvaps--;
1293 }
1294 if (vap->iv_opmode != IEEE80211_M_WDS)
1295 sc->sc_nvaps--;
1296#ifdef IEEE80211_SUPPORT_TDMA
1297 /* TDMA operation ceases when the last vap is destroyed */
1298 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1299 sc->sc_tdma = 0;
1300 sc->sc_swbmiss = 0;
1301 }
1302#endif
1303 free(avp, M_80211_VAP);
1304
1305 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1306 /*
1307 * Restart rx+tx machines if still running (RUNNING will
1308 * be reset if we just destroyed the last vap).
1309 */
1310 if (ath_startrecv(sc) != 0)
1311 if_printf(ifp, "%s: unable to restart recv logic\n",
1312 __func__);
1313 if (sc->sc_beacons) { /* restart beacons */
1314#ifdef IEEE80211_SUPPORT_TDMA
1315 if (sc->sc_tdma)
1316 ath_tdma_config(sc, NULL);
1317 else
1318#endif
1319 ath_beacon_config(sc, NULL);
1320 }
1321 ath_hal_intrset(ah, sc->sc_imask);
1322 }
1323 ATH_UNLOCK(sc);
1324}
1325
1326void
1327ath_suspend(struct ath_softc *sc)
1328{
1329 struct ifnet *ifp = sc->sc_ifp;
1330 struct ieee80211com *ic = ifp->if_l2com;
1331
1332 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1333 __func__, ifp->if_flags);
1334
1335 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1336 if (ic->ic_opmode == IEEE80211_M_STA)
1337 ath_stop(ifp);
1338 else
1339 ieee80211_suspend_all(ic);
1340 /*
1341 * NB: don't worry about putting the chip in low power
1342 * mode; pci will power off our socket on suspend and
1343 * CardBus detaches the device.
1344 */
1345}
1346
1347/*
1348 * Reset the key cache since some parts do not reset the
1349 * contents on resume. First we clear all entries, then
1350 * re-load keys that the 802.11 layer assumes are setup
1351 * in h/w.
1352 */
1353static void
1354ath_reset_keycache(struct ath_softc *sc)
1355{
1356 struct ifnet *ifp = sc->sc_ifp;
1357 struct ieee80211com *ic = ifp->if_l2com;
1358 struct ath_hal *ah = sc->sc_ah;
1359 int i;
1360
1361 for (i = 0; i < sc->sc_keymax; i++)
1362 ath_hal_keyreset(ah, i);
1363 ieee80211_crypto_reload_keys(ic);
1364}
1365
1366void
1367ath_resume(struct ath_softc *sc)
1368{
1369 struct ifnet *ifp = sc->sc_ifp;
1370 struct ieee80211com *ic = ifp->if_l2com;
1371 struct ath_hal *ah = sc->sc_ah;
1372 HAL_STATUS status;
1373
1374 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1375 __func__, ifp->if_flags);
1376
1377 /*
1378 * Must reset the chip before we reload the
1379 * keycache as we were powered down on suspend.
1380 */
1381 ath_hal_reset(ah, sc->sc_opmode,
1382 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1383 AH_FALSE, &status);
1384 ath_reset_keycache(sc);
1385
1386 /* Let DFS at it in case it's a DFS channel */
1387 ath_dfs_radar_enable(sc, ic->ic_curchan);
1388
1389 /* Restore the LED configuration */
1390 ath_led_config(sc);
1391 ath_hal_setledstate(ah, HAL_LED_INIT);
1392
1393 if (sc->sc_resume_up) {
1394 if (ic->ic_opmode == IEEE80211_M_STA) {
1395 ath_init(sc);
1396 ath_hal_setledstate(ah, HAL_LED_RUN);
1397 /*
1398 * Program the beacon registers using the last rx'd
1399 * beacon frame and enable sync on the next beacon
1400 * we see. This should handle the case where we
1401 * wakeup and find the same AP and also the case where
1402 * we wakeup and need to roam. For the latter we
1403 * should get bmiss events that trigger a roam.
1404 */
1405 ath_beacon_config(sc, NULL);
1406 sc->sc_syncbeacon = 1;
1407 } else
1408 ieee80211_resume_all(ic);
1409 }
1410
1411 /* XXX beacons ? */
1412}
1413
1414void
1415ath_shutdown(struct ath_softc *sc)
1416{
1417 struct ifnet *ifp = sc->sc_ifp;
1418
1419 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1420 __func__, ifp->if_flags);
1421
1422 ath_stop(ifp);
1423 /* NB: no point powering down chip as we're about to reboot */
1424}
1425
1426/*
1427 * Interrupt handler. Most of the actual processing is deferred.
1428 */
1429void
1430ath_intr(void *arg)
1431{
1432 struct ath_softc *sc = arg;
1433 struct ifnet *ifp = sc->sc_ifp;
1434 struct ath_hal *ah = sc->sc_ah;
1435 HAL_INT status = 0;
1436 uint32_t txqs;
1437
1438 /*
1439 * If we're inside a reset path, just print a warning and
1440 * clear the ISR. The reset routine will finish it for us.
1441 */
1442 ATH_PCU_LOCK(sc);
1443 if (sc->sc_inreset_cnt) {
1444 HAL_INT status;
1445 ath_hal_getisr(ah, &status); /* clear ISR */
1446 ath_hal_intrset(ah, 0); /* disable further intr's */
1447 DPRINTF(sc, ATH_DEBUG_ANY,
1448 "%s: in reset, ignoring: status=0x%x\n",
1449 __func__, status);
1450 ATH_PCU_UNLOCK(sc);
1451 return;
1452 }
1453
1454 if (sc->sc_invalid) {
1455 /*
1456 * The hardware is not ready/present, don't touch anything.
1457 * Note this can happen early on if the IRQ is shared.
1458 */
1459 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1460 ATH_PCU_UNLOCK(sc);
1461 return;
1462 }
1463 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
1464 ATH_PCU_UNLOCK(sc);
1465 return;
1466 }
1467
1468 if ((ifp->if_flags & IFF_UP) == 0 ||
1469 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1470 HAL_INT status;
1471
1472 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1473 __func__, ifp->if_flags);
1474 ath_hal_getisr(ah, &status); /* clear ISR */
1475 ath_hal_intrset(ah, 0); /* disable further intr's */
1476 ATH_PCU_UNLOCK(sc);
1477 return;
1478 }
1479
1480 /*
1481 * Figure out the reason(s) for the interrupt. Note
1482 * that the hal returns a pseudo-ISR that may include
1483 * bits we haven't explicitly enabled so we mask the
1484 * value to insure we only process bits we requested.
1485 */
1486 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1487 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1488 CTR1(ATH_KTR_INTR, "ath_intr: mask=0x%.8x", status);
1489#ifdef ATH_KTR_INTR_DEBUG
1490 CTR5(ATH_KTR_INTR,
1491 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
1492 ah->ah_intrstate[0],
1493 ah->ah_intrstate[1],
1494 ah->ah_intrstate[2],
1495 ah->ah_intrstate[3],
1496 ah->ah_intrstate[6]);
1497#endif
1498 status &= sc->sc_imask; /* discard unasked for bits */
1499
1500 /* Short-circuit un-handled interrupts */
1501 if (status == 0x0) {
1502 ATH_PCU_UNLOCK(sc);
1503 return;
1504 }
1505
1506 /*
1507 * Take a note that we're inside the interrupt handler, so
1508 * the reset routines know to wait.
1509 */
1510 sc->sc_intr_cnt++;
1511 ATH_PCU_UNLOCK(sc);
1512
1513 /*
1514 * Handle the interrupt. We won't run concurrent with the reset
1515 * or channel change routines as they'll wait for sc_intr_cnt
1516 * to be 0 before continuing.
1517 */
1518 if (status & HAL_INT_FATAL) {
1519 sc->sc_stats.ast_hardware++;
1520 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1521 ath_fatal_proc(sc, 0);
1522 } else {
1523 if (status & HAL_INT_SWBA) {
1524 /*
1525 * Software beacon alert--time to send a beacon.
1526 * Handle beacon transmission directly; deferring
1527 * this is too slow to meet timing constraints
1528 * under load.
1529 */
1530#ifdef IEEE80211_SUPPORT_TDMA
1531 if (sc->sc_tdma) {
1532 if (sc->sc_tdmaswba == 0) {
1533 struct ieee80211com *ic = ifp->if_l2com;
1534 struct ieee80211vap *vap =
1535 TAILQ_FIRST(&ic->ic_vaps);
1536 ath_tdma_beacon_send(sc, vap);
1537 sc->sc_tdmaswba =
1538 vap->iv_tdma->tdma_bintval;
1539 } else
1540 sc->sc_tdmaswba--;
1541 } else
1542#endif
1543 {
1544 ath_beacon_proc(sc, 0);
1545#ifdef IEEE80211_SUPPORT_SUPERG
1546 /*
1547 * Schedule the rx taskq in case there's no
1548 * traffic so any frames held on the staging
1549 * queue are aged and potentially flushed.
1550 */
1551 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1552#endif
1553 }
1554 }
1555 if (status & HAL_INT_RXEOL) {
1556 int imask;
1557 CTR0(ATH_KTR_ERR, "ath_intr: RXEOL");
1558 ATH_PCU_LOCK(sc);
1559 /*
1560 * NB: the hardware should re-read the link when
1561 * RXE bit is written, but it doesn't work at
1562 * least on older hardware revs.
1563 */
1564 sc->sc_stats.ast_rxeol++;
1565 /*
1566 * Disable RXEOL/RXORN - prevent an interrupt
1567 * storm until the PCU logic can be reset.
1568 * In case the interface is reset some other
1569 * way before "sc_kickpcu" is called, don't
1570 * modify sc_imask - that way if it is reset
1571 * by a call to ath_reset() somehow, the
1572 * interrupt mask will be correctly reprogrammed.
1573 */
1574 imask = sc->sc_imask;
1575 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
1576 ath_hal_intrset(ah, imask);
1577 /*
1578 * Only blank sc_rxlink if we've not yet kicked
1579 * the PCU.
1580 *
1581 * This isn't entirely correct - the correct solution
1582 * would be to have a PCU lock and engage that for
1583 * the duration of the PCU fiddling; which would include
1584 * running the RX process. Otherwise we could end up
1585 * messing up the RX descriptor chain and making the
1586 * RX desc list much shorter.
1587 */
1588 if (! sc->sc_kickpcu)
1589 sc->sc_rxlink = NULL;
1590 sc->sc_kickpcu = 1;
1591 /*
1592 * Enqueue an RX proc, to handled whatever
1593 * is in the RX queue.
1594 * This will then kick the PCU.
1595 */
1596 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1597 ATH_PCU_UNLOCK(sc);
1598 }
1599 if (status & HAL_INT_TXURN) {
1600 sc->sc_stats.ast_txurn++;
1601 /* bump tx trigger level */
1602 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1603 }
1604 if (status & HAL_INT_RX) {
1605 sc->sc_stats.ast_rx_intr++;
1606 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1607 }
1608 if (status & HAL_INT_TX) {
1609 sc->sc_stats.ast_tx_intr++;
1610 /*
1611 * Grab all the currently set bits in the HAL txq bitmap
1612 * and blank them. This is the only place we should be
1613 * doing this.
1614 */
1615 ATH_PCU_LOCK(sc);
1616 txqs = 0xffffffff;
1617 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
1618 sc->sc_txq_active |= txqs;
1619 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1620 ATH_PCU_UNLOCK(sc);
1621 }
1622 if (status & HAL_INT_BMISS) {
1623 sc->sc_stats.ast_bmiss++;
1624 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1625 }
1626 if (status & HAL_INT_GTT)
1627 sc->sc_stats.ast_tx_timeout++;
1628 if (status & HAL_INT_CST)
1629 sc->sc_stats.ast_tx_cst++;
1630 if (status & HAL_INT_MIB) {
1631 sc->sc_stats.ast_mib++;
1632 ATH_PCU_LOCK(sc);
1633 /*
1634 * Disable interrupts until we service the MIB
1635 * interrupt; otherwise it will continue to fire.
1636 */
1637 ath_hal_intrset(ah, 0);
1638 /*
1639 * Let the hal handle the event. We assume it will
1640 * clear whatever condition caused the interrupt.
1641 */
1642 ath_hal_mibevent(ah, &sc->sc_halstats);
1643 /*
1644 * Don't reset the interrupt if we've just
1645 * kicked the PCU, or we may get a nested
1646 * RXEOL before the rxproc has had a chance
1647 * to run.
1648 */
1649 if (sc->sc_kickpcu == 0)
1650 ath_hal_intrset(ah, sc->sc_imask);
1651 ATH_PCU_UNLOCK(sc);
1652 }
1653 if (status & HAL_INT_RXORN) {
1654 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1655 CTR0(ATH_KTR_ERR, "ath_intr: RXORN");
1656 sc->sc_stats.ast_rxorn++;
1657 }
1658 }
1659 ATH_PCU_LOCK(sc);
1660 sc->sc_intr_cnt--;
1661 ATH_PCU_UNLOCK(sc);
1662}
1663
1664static void
1665ath_fatal_proc(void *arg, int pending)
1666{
1667 struct ath_softc *sc = arg;
1668 struct ifnet *ifp = sc->sc_ifp;
1669 u_int32_t *state;
1670 u_int32_t len;
1671 void *sp;
1672
1673 if_printf(ifp, "hardware error; resetting\n");
1674 /*
1675 * Fatal errors are unrecoverable. Typically these
1676 * are caused by DMA errors. Collect h/w state from
1677 * the hal so we can diagnose what's going on.
1678 */
1679 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1680 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1681 state = sp;
1682 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1683 state[0], state[1] , state[2], state[3],
1684 state[4], state[5]);
1685 }
1686 ath_reset(ifp, ATH_RESET_NOLOSS);
1687}
1688
1689static void
1690ath_bmiss_vap(struct ieee80211vap *vap)
1691{
1692 /*
1693 * Workaround phantom bmiss interrupts by sanity-checking
1694 * the time of our last rx'd frame. If it is within the
1695 * beacon miss interval then ignore the interrupt. If it's
1696 * truly a bmiss we'll get another interrupt soon and that'll
1697 * be dispatched up for processing. Note this applies only
1698 * for h/w beacon miss events.
1699 */
1700 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1701 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1702 struct ath_softc *sc = ifp->if_softc;
1703 u_int64_t lastrx = sc->sc_lastrx;
1704 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1705 /* XXX should take a locked ref to iv_bss */
1706 u_int bmisstimeout =
1707 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1708
1709 DPRINTF(sc, ATH_DEBUG_BEACON,
1710 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1711 __func__, (unsigned long long) tsf,
1712 (unsigned long long)(tsf - lastrx),
1713 (unsigned long long) lastrx, bmisstimeout);
1714
1715 if (tsf - lastrx <= bmisstimeout) {
1716 sc->sc_stats.ast_bmiss_phantom++;
1717 return;
1718 }
1719 }
1720 ATH_VAP(vap)->av_bmiss(vap);
1721}
1722
1723static int
1724ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1725{
1726 uint32_t rsize;
1727 void *sp;
1728
1729 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
1730 return 0;
1731 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1732 *hangs = *(uint32_t *)sp;
1733 return 1;
1734}
1735
1736static void
1737ath_bmiss_proc(void *arg, int pending)
1738{
1739 struct ath_softc *sc = arg;
1740 struct ifnet *ifp = sc->sc_ifp;
1741 uint32_t hangs;
1742
1743 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1744
1745 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1746 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
1747 ath_reset(ifp, ATH_RESET_NOLOSS);
1748 } else
1749 ieee80211_beacon_miss(ifp->if_l2com);
1750}
1751
1752/*
1753 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1754 * calcs together with WME. If necessary disable the crypto
1755 * hardware and mark the 802.11 state so keys will be setup
1756 * with the MIC work done in software.
1757 */
1758static void
1759ath_settkipmic(struct ath_softc *sc)
1760{
1761 struct ifnet *ifp = sc->sc_ifp;
1762 struct ieee80211com *ic = ifp->if_l2com;
1763
1764 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1765 if (ic->ic_flags & IEEE80211_F_WME) {
1766 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1767 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1768 } else {
1769 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1770 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1771 }
1772 }
1773}
1774
1775static void
1776ath_init(void *arg)
1777{
1778 struct ath_softc *sc = (struct ath_softc *) arg;
1779 struct ifnet *ifp = sc->sc_ifp;
1780 struct ieee80211com *ic = ifp->if_l2com;
1781 struct ath_hal *ah = sc->sc_ah;
1782 HAL_STATUS status;
1783
1784 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1785 __func__, ifp->if_flags);
1786
1787 ATH_LOCK(sc);
1788 /*
1789 * Stop anything previously setup. This is safe
1790 * whether this is the first time through or not.
1791 */
1792 ath_stop_locked(ifp);
1793
1794 /*
1795 * The basic interface to setting the hardware in a good
1796 * state is ``reset''. On return the hardware is known to
1797 * be powered up and with interrupts disabled. This must
1798 * be followed by initialization of the appropriate bits
1799 * and then setup of the interrupt mask.
1800 */
1801 ath_settkipmic(sc);
1802 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
1803 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1804 status);
1805 ATH_UNLOCK(sc);
1806 return;
1807 }
1808 ath_chan_change(sc, ic->ic_curchan);
1809
1810 /* Let DFS at it in case it's a DFS channel */
1811 ath_dfs_radar_enable(sc, ic->ic_curchan);
1812
1813 /*
1814 * Likewise this is set during reset so update
1815 * state cached in the driver.
1816 */
1817 sc->sc_diversity = ath_hal_getdiversity(ah);
1818 sc->sc_lastlongcal = 0;
1819 sc->sc_resetcal = 1;
1820 sc->sc_lastcalreset = 0;
1821 sc->sc_lastani = 0;
1822 sc->sc_lastshortcal = 0;
1823 sc->sc_doresetcal = AH_FALSE;
1824 /*
1825 * Beacon timers were cleared here; give ath_newstate()
1826 * a hint that the beacon timers should be poked when
1827 * things transition to the RUN state.
1828 */
1829 sc->sc_beacons = 0;
1830
1831 /*
1832 * Initial aggregation settings.
1833 */
1834 sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH;
1835 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
1836 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
1837
1838 /*
1839 * Setup the hardware after reset: the key cache
1840 * is filled as needed and the receive engine is
1841 * set going. Frame transmit is handled entirely
1842 * in the frame output path; there's nothing to do
1843 * here except setup the interrupt mask.
1844 */
1845 if (ath_startrecv(sc) != 0) {
1846 if_printf(ifp, "unable to start recv logic\n");
1847 ATH_UNLOCK(sc);
1848 return;
1849 }
1850
1851 /*
1852 * Enable interrupts.
1853 */
1854 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1855 | HAL_INT_RXEOL | HAL_INT_RXORN
1856 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1857 /*
1858 * Enable MIB interrupts when there are hardware phy counters.
1859 * Note we only do this (at the moment) for station mode.
1860 */
1861 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1862 sc->sc_imask |= HAL_INT_MIB;
1863
1864 /* Enable global TX timeout and carrier sense timeout if available */
1865 if (ath_hal_gtxto_supported(ah))
1866 sc->sc_imask |= HAL_INT_GTT;
1867
1868 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
1869 __func__, sc->sc_imask);
1870
1871 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1872 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
1873 ath_hal_intrset(ah, sc->sc_imask);
1874
1875 ATH_UNLOCK(sc);
1876
1877#ifdef ATH_TX99_DIAG
1878 if (sc->sc_tx99 != NULL)
1879 sc->sc_tx99->start(sc->sc_tx99);
1880 else
1881#endif
1882 ieee80211_start_all(ic); /* start all vap's */
1883}
1884
1885static void
1886ath_stop_locked(struct ifnet *ifp)
1887{
1888 struct ath_softc *sc = ifp->if_softc;
1889 struct ath_hal *ah = sc->sc_ah;
1890
1891 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1892 __func__, sc->sc_invalid, ifp->if_flags);
1893
1894 ATH_LOCK_ASSERT(sc);
1895 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1896 /*
1897 * Shutdown the hardware and driver:
1898 * reset 802.11 state machine
1899 * turn off timers
1900 * disable interrupts
1901 * turn off the radio
1902 * clear transmit machinery
1903 * clear receive machinery
1904 * drain and release tx queues
1905 * reclaim beacon resources
1906 * power down hardware
1907 *
1908 * Note that some of this work is not possible if the
1909 * hardware is gone (invalid).
1910 */
1911#ifdef ATH_TX99_DIAG
1912 if (sc->sc_tx99 != NULL)
1913 sc->sc_tx99->stop(sc->sc_tx99);
1914#endif
1915 callout_stop(&sc->sc_wd_ch);
1916 sc->sc_wd_timer = 0;
1917 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1918 if (!sc->sc_invalid) {
1919 if (sc->sc_softled) {
1920 callout_stop(&sc->sc_ledtimer);
1921 ath_hal_gpioset(ah, sc->sc_ledpin,
1922 !sc->sc_ledon);
1923 sc->sc_blinking = 0;
1924 }
1925 ath_hal_intrset(ah, 0);
1926 }
1927 ath_draintxq(sc, ATH_RESET_DEFAULT);
1928 if (!sc->sc_invalid) {
1929 ath_stoprecv(sc, 1);
1930 ath_hal_phydisable(ah);
1931 } else
1932 sc->sc_rxlink = NULL;
1933 ath_beacon_free(sc); /* XXX not needed */
1934 }
1935}
1936
1937#define MAX_TXRX_ITERATIONS 1000
1938static void
1939ath_txrx_stop_locked(struct ath_softc *sc)
1940{
1941 int i = MAX_TXRX_ITERATIONS;
1942
1943 ATH_UNLOCK_ASSERT(sc);
1944 ATH_PCU_LOCK_ASSERT(sc);
1945
1946 /*
1947 * Sleep until all the pending operations have completed.
1948 *
1949 * The caller must ensure that reset has been incremented
1950 * or the pending operations may continue being queued.
1951 */
1952 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
1953 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
1954 if (i <= 0)
1955 break;
1956 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1);
1957 i--;
1958 }
1959
1960 if (i <= 0)
1961 device_printf(sc->sc_dev,
1962 "%s: didn't finish after %d iterations\n",
1963 __func__, MAX_TXRX_ITERATIONS);
1964}
1965#undef MAX_TXRX_ITERATIONS
1966
1967#if 0
1968static void
1969ath_txrx_stop(struct ath_softc *sc)
1970{
1971 ATH_UNLOCK_ASSERT(sc);
1972 ATH_PCU_UNLOCK_ASSERT(sc);
1973
1974 ATH_PCU_LOCK(sc);
1975 ath_txrx_stop_locked(sc);
1976 ATH_PCU_UNLOCK(sc);
1977}
1978#endif
1979
1980static void
1981ath_txrx_start(struct ath_softc *sc)
1982{
1983
1984 taskqueue_unblock(sc->sc_tq);
1985}
1986
1987/*
1988 * Grab the reset lock, and wait around until noone else
1989 * is trying to do anything with it.
1990 *
1991 * This is totally horrible but we can't hold this lock for
1992 * long enough to do TX/RX or we end up with net80211/ip stack
1993 * LORs and eventual deadlock.
1994 *
1995 * "dowait" signals whether to spin, waiting for the reset
1996 * lock count to reach 0. This should (for now) only be used
1997 * during the reset path, as the rest of the code may not
1998 * be locking-reentrant enough to behave correctly.
1999 *
2000 * Another, cleaner way should be found to serialise all of
2001 * these operations.
2002 */
2003#define MAX_RESET_ITERATIONS 10
2004static int
2005ath_reset_grablock(struct ath_softc *sc, int dowait)
2006{
2007 int w = 0;
2008 int i = MAX_RESET_ITERATIONS;
2009
2010 ATH_PCU_LOCK_ASSERT(sc);
2011 do {
2012 if (sc->sc_inreset_cnt == 0) {
2013 w = 1;
2014 break;
2015 }
2016 if (dowait == 0) {
2017 w = 0;
2018 break;
2019 }
2020 ATH_PCU_UNLOCK(sc);
2021 pause("ath_reset_grablock", 1);
2022 i--;
2023 ATH_PCU_LOCK(sc);
2024 } while (i > 0);
2025
2026 /*
2027 * We always increment the refcounter, regardless
2028 * of whether we succeeded to get it in an exclusive
2029 * way.
2030 */
2031 sc->sc_inreset_cnt++;
2032
2033 if (i <= 0)
2034 device_printf(sc->sc_dev,
2035 "%s: didn't finish after %d iterations\n",
2036 __func__, MAX_RESET_ITERATIONS);
2037
2038 if (w == 0)
2039 device_printf(sc->sc_dev,
2040 "%s: warning, recursive reset path!\n",
2041 __func__);
2042
2043 return w;
2044}
2045#undef MAX_RESET_ITERATIONS
2046
2047/*
2048 * XXX TODO: write ath_reset_releaselock
2049 */
2050
2051static void
2052ath_stop(struct ifnet *ifp)
2053{
2054 struct ath_softc *sc = ifp->if_softc;
2055
2056 ATH_LOCK(sc);
2057 ath_stop_locked(ifp);
2058 ATH_UNLOCK(sc);
2059}
2060
2061/*
2062 * Reset the hardware w/o losing operational state. This is
2063 * basically a more efficient way of doing ath_stop, ath_init,
2064 * followed by state transitions to the current 802.11
2065 * operational state. Used to recover from various errors and
2066 * to reset or reload hardware state.
2067 */
2068int
2069ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2070{
2071 struct ath_softc *sc = ifp->if_softc;
2072 struct ieee80211com *ic = ifp->if_l2com;
2073 struct ath_hal *ah = sc->sc_ah;
2074 HAL_STATUS status;
2075 int i;
2076
2077 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2078
2079 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2080 ATH_PCU_UNLOCK_ASSERT(sc);
2081 ATH_UNLOCK_ASSERT(sc);
2082
2083 /* Try to (stop any further TX/RX from occuring */
2084 taskqueue_block(sc->sc_tq);
2085
2086 ATH_PCU_LOCK(sc);
2087 ath_hal_intrset(ah, 0); /* disable interrupts */
2088 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */
2089 if (ath_reset_grablock(sc, 1) == 0) {
2090 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2091 __func__);
2092 }
2093 ATH_PCU_UNLOCK(sc);
2094
2095 /*
2096 * Should now wait for pending TX/RX to complete
2097 * and block future ones from occuring. This needs to be
2098 * done before the TX queue is drained.
2099 */
2100 ath_draintxq(sc, reset_type); /* stop xmit side */
2101
2102 /*
2103 * Regardless of whether we're doing a no-loss flush or
2104 * not, stop the PCU and handle what's in the RX queue.
2105 * That way frames aren't dropped which shouldn't be.
2106 */
2107 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2108 ath_rx_proc(sc, 0);
2109
2110 ath_settkipmic(sc); /* configure TKIP MIC handling */
2111 /* NB: indicate channel change so we do a full reset */
2112 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2113 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2114 __func__, status);
2115 sc->sc_diversity = ath_hal_getdiversity(ah);
2116
2117 /* Let DFS at it in case it's a DFS channel */
2118 ath_dfs_radar_enable(sc, ic->ic_curchan);
2119
2120 if (ath_startrecv(sc) != 0) /* restart recv */
2121 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2122 /*
2123 * We may be doing a reset in response to an ioctl
2124 * that changes the channel so update any state that
2125 * might change as a result.
2126 */
2127 ath_chan_change(sc, ic->ic_curchan);
2128 if (sc->sc_beacons) { /* restart beacons */
2129#ifdef IEEE80211_SUPPORT_TDMA
2130 if (sc->sc_tdma)
2131 ath_tdma_config(sc, NULL);
2132 else
2133#endif
2134 ath_beacon_config(sc, NULL);
2135 }
2136
2137 /*
2138 * Release the reset lock and re-enable interrupts here.
2139 * If an interrupt was being processed in ath_intr(),
2140 * it would disable interrupts at this point. So we have
2141 * to atomically enable interrupts and decrement the
2142 * reset counter - this way ath_intr() doesn't end up
2143 * disabling interrupts without a corresponding enable
2144 * in the rest or channel change path.
2145 */
2146 ATH_PCU_LOCK(sc);
2147 sc->sc_inreset_cnt--;
2148 /* XXX only do this if sc_inreset_cnt == 0? */
2149 ath_hal_intrset(ah, sc->sc_imask);
2150 ATH_PCU_UNLOCK(sc);
2151
2152 /*
2153 * TX and RX can be started here. If it were started with
2154 * sc_inreset_cnt > 0, the TX and RX path would abort.
2155 * Thus if this is a nested call through the reset or
2156 * channel change code, TX completion will occur but
2157 * RX completion and ath_start / ath_tx_start will not
2158 * run.
2159 */
2160
2161 /* Restart TX/RX as needed */
2162 ath_txrx_start(sc);
2163
2164 /* XXX Restart TX completion and pending TX */
2165 if (reset_type == ATH_RESET_NOLOSS) {
2166 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2167 if (ATH_TXQ_SETUP(sc, i)) {
2168 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2169 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2170 ath_txq_sched(sc, &sc->sc_txq[i]);
2171 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2172 }
2173 }
2174 }
2175
2176 /*
2177 * This may have been set during an ath_start() call which
2178 * set this once it detected a concurrent TX was going on.
2179 * So, clear it.
2180 */
2181 IF_LOCK(&ifp->if_snd);
2182 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2183 IF_UNLOCK(&ifp->if_snd);
2184
2185 /* Handle any frames in the TX queue */
2186 /*
2187 * XXX should this be done by the caller, rather than
2188 * ath_reset() ?
2189 */
2190 ath_start(ifp); /* restart xmit */
2191 return 0;
2192}
2193
2194static int
2195ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
2196{
2197 struct ieee80211com *ic = vap->iv_ic;
2198 struct ifnet *ifp = ic->ic_ifp;
2199 struct ath_softc *sc = ifp->if_softc;
2200 struct ath_hal *ah = sc->sc_ah;
2201
2202 switch (cmd) {
2203 case IEEE80211_IOC_TXPOWER:
2204 /*
2205 * If per-packet TPC is enabled, then we have nothing
2206 * to do; otherwise we need to force the global limit.
2207 * All this can happen directly; no need to reset.
2208 */
2209 if (!ath_hal_gettpc(ah))
2210 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
2211 return 0;
2212 }
2213 /* XXX? Full or NOLOSS? */
2214 return ath_reset(ifp, ATH_RESET_FULL);
2215}
2216
2217struct ath_buf *
2218_ath_getbuf_locked(struct ath_softc *sc)
2219{
2220 struct ath_buf *bf;
2221
2222 ATH_TXBUF_LOCK_ASSERT(sc);
2223
2224 bf = TAILQ_FIRST(&sc->sc_txbuf);
2225 if (bf == NULL) {
2226 sc->sc_stats.ast_tx_getnobuf++;
2227 } else {
2228 if (bf->bf_flags & ATH_BUF_BUSY) {
2229 sc->sc_stats.ast_tx_getbusybuf++;
2230 bf = NULL;
2231 }
2232 }
2233
2234 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0)
2235 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
2236 else
2237 bf = NULL;
2238
2239 if (bf == NULL) {
2240 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
2241 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
2242 "out of xmit buffers" : "xmit buffer busy");
2243 return NULL;
2244 }
2245
2246 /* Valid bf here; clear some basic fields */
2247 bf->bf_next = NULL; /* XXX just to be sure */
2248 bf->bf_last = NULL; /* XXX again, just to be sure */
2249 bf->bf_comp = NULL; /* XXX again, just to be sure */
2250 bzero(&bf->bf_state, sizeof(bf->bf_state));
2251
2252 return bf;
2253}
2254
2255/*
2256 * When retrying a software frame, buffers marked ATH_BUF_BUSY
2257 * can't be thrown back on the queue as they could still be
2258 * in use by the hardware.
2259 *
2260 * This duplicates the buffer, or returns NULL.
2261 *
2262 * The descriptor is also copied but the link pointers and
2263 * the DMA segments aren't copied; this frame should thus
2264 * be again passed through the descriptor setup/chain routines
2265 * so the link is correct.
2266 *
2267 * The caller must free the buffer using ath_freebuf().
2268 *
2269 * XXX TODO: this call shouldn't fail as it'll cause packet loss
2270 * XXX in the TX pathway when retries are needed.
2271 * XXX Figure out how to keep some buffers free, or factor the
2272 * XXX number of busy buffers into the xmit path (ath_start())
2273 * XXX so we don't over-commit.
2274 */
2275struct ath_buf *
2276ath_buf_clone(struct ath_softc *sc, const struct ath_buf *bf)
2277{
2278 struct ath_buf *tbf;
2279
2280 tbf = ath_getbuf(sc);
2281 if (tbf == NULL)
2282 return NULL; /* XXX failure? Why? */
2283
2284 /* Copy basics */
2285 tbf->bf_next = NULL;
2286 tbf->bf_nseg = bf->bf_nseg;
2287 tbf->bf_flags = bf->bf_flags & ~ATH_BUF_BUSY;
2288 tbf->bf_status = bf->bf_status;
2289 tbf->bf_m = bf->bf_m;
2290 tbf->bf_node = bf->bf_node;
2291 /* will be setup by the chain/setup function */
2292 tbf->bf_lastds = NULL;
2293 /* for now, last == self */
2294 tbf->bf_last = tbf;
2295 tbf->bf_comp = bf->bf_comp;
2296
2297 /* NOTE: DMA segments will be setup by the setup/chain functions */
2298
2299 /* The caller has to re-init the descriptor + links */
2300
2301 /* Copy state */
2302 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
2303
2304 return tbf;
2305}
2306
2307struct ath_buf *
2308ath_getbuf(struct ath_softc *sc)
2309{
2310 struct ath_buf *bf;
2311
2312 ATH_TXBUF_LOCK(sc);
2313 bf = _ath_getbuf_locked(sc);
2314 ATH_TXBUF_UNLOCK(sc);
2315 if (bf == NULL) {
2316 struct ifnet *ifp = sc->sc_ifp;
2317
2318 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
2319 sc->sc_stats.ast_tx_qstop++;
2320 IF_LOCK(&ifp->if_snd);
2321 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2322 IF_UNLOCK(&ifp->if_snd);
2323 }
2324 return bf;
2325}
2326
2327static void
2328ath_start(struct ifnet *ifp)
2329{
2330 struct ath_softc *sc = ifp->if_softc;
2331 struct ieee80211_node *ni;
2332 struct ath_buf *bf;
2333 struct mbuf *m, *next;
2334 ath_bufhead frags;
2335
2336 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
2337 return;
2338
2339 /* XXX is it ok to hold the ATH_LOCK here? */
2340 ATH_PCU_LOCK(sc);
2341 if (sc->sc_inreset_cnt > 0) {
2342 device_printf(sc->sc_dev,
2343 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2344 ATH_PCU_UNLOCK(sc);
2345 IF_LOCK(&ifp->if_snd);
2346 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2347 IF_UNLOCK(&ifp->if_snd);
2348 return;
2349 }
2350 sc->sc_txstart_cnt++;
2351 ATH_PCU_UNLOCK(sc);
2352
2353 for (;;) {
2354 /*
2355 * Grab a TX buffer and associated resources.
2356 */
2357 bf = ath_getbuf(sc);
2358 if (bf == NULL)
2359 break;
2360
2361 IFQ_DEQUEUE(&ifp->if_snd, m);
2362 if (m == NULL) {
2363 ATH_TXBUF_LOCK(sc);
2364 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
2365 ATH_TXBUF_UNLOCK(sc);
2366 break;
2367 }
2368 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
2369 /*
2370 * Check for fragmentation. If this frame
2371 * has been broken up verify we have enough
2372 * buffers to send all the fragments so all
2373 * go out or none...
2374 */
2375 TAILQ_INIT(&frags);
2376 if ((m->m_flags & M_FRAG) &&
2377 !ath_txfrag_setup(sc, &frags, m, ni)) {
2378 DPRINTF(sc, ATH_DEBUG_XMIT,
2379 "%s: out of txfrag buffers\n", __func__);
2380 sc->sc_stats.ast_tx_nofrag++;
2381 ifp->if_oerrors++;
2382 ath_freetx(m);
2383 goto bad;
2384 }
2385 ifp->if_opackets++;
2386 nextfrag:
2387 /*
2388 * Pass the frame to the h/w for transmission.
2389 * Fragmented frames have each frag chained together
2390 * with m_nextpkt. We know there are sufficient ath_buf's
2391 * to send all the frags because of work done by
2392 * ath_txfrag_setup. We leave m_nextpkt set while
2393 * calling ath_tx_start so it can use it to extend the
2394 * the tx duration to cover the subsequent frag and
2395 * so it can reclaim all the mbufs in case of an error;
2396 * ath_tx_start clears m_nextpkt once it commits to
2397 * handing the frame to the hardware.
2398 */
2399 next = m->m_nextpkt;
2400 if (ath_tx_start(sc, ni, bf, m)) {
2401 bad:
2402 ifp->if_oerrors++;
2403 reclaim:
2404 bf->bf_m = NULL;
2405 bf->bf_node = NULL;
2406 ATH_TXBUF_LOCK(sc);
2407 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
2408 ath_txfrag_cleanup(sc, &frags, ni);
2409 ATH_TXBUF_UNLOCK(sc);
2410 if (ni != NULL)
2411 ieee80211_free_node(ni);
2412 continue;
2413 }
2414 if (next != NULL) {
2415 /*
2416 * Beware of state changing between frags.
2417 * XXX check sta power-save state?
2418 */
2419 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
2420 DPRINTF(sc, ATH_DEBUG_XMIT,
2421 "%s: flush fragmented packet, state %s\n",
2422 __func__,
2423 ieee80211_state_name[ni->ni_vap->iv_state]);
2424 ath_freetx(next);
2425 goto reclaim;
2426 }
2427 m = next;
2428 bf = TAILQ_FIRST(&frags);
2429 KASSERT(bf != NULL, ("no buf for txfrag"));
2430 TAILQ_REMOVE(&frags, bf, bf_list);
2431 goto nextfrag;
2432 }
2433
2434 sc->sc_wd_timer = 5;
2435 }
2436
2437 ATH_PCU_LOCK(sc);
2438 sc->sc_txstart_cnt--;
2439 ATH_PCU_UNLOCK(sc);
2440}
2441
2442static int
2443ath_media_change(struct ifnet *ifp)
2444{
2445 int error = ieee80211_media_change(ifp);
2446 /* NB: only the fixed rate can change and that doesn't need a reset */
2447 return (error == ENETRESET ? 0 : error);
2448}
2449
2450/*
2451 * Block/unblock tx+rx processing while a key change is done.
2452 * We assume the caller serializes key management operations
2453 * so we only need to worry about synchronization with other
2454 * uses that originate in the driver.
2455 */
2456static void
2457ath_key_update_begin(struct ieee80211vap *vap)
2458{
2459 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2460 struct ath_softc *sc = ifp->if_softc;
2461
2462 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2463 taskqueue_block(sc->sc_tq);
2464 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2465}
2466
2467static void
2468ath_key_update_end(struct ieee80211vap *vap)
2469{
2470 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2471 struct ath_softc *sc = ifp->if_softc;
2472
2473 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2474 IF_UNLOCK(&ifp->if_snd);
2475 taskqueue_unblock(sc->sc_tq);
2476}
2477
2478/*
2479 * Calculate the receive filter according to the
2480 * operating mode and state:
2481 *
2482 * o always accept unicast, broadcast, and multicast traffic
2483 * o accept PHY error frames when hardware doesn't have MIB support
2484 * to count and we need them for ANI (sta mode only until recently)
2485 * and we are not scanning (ANI is disabled)
2486 * NB: older hal's add rx filter bits out of sight and we need to
2487 * blindly preserve them
2488 * o probe request frames are accepted only when operating in
2489 * hostap, adhoc, mesh, or monitor modes
2490 * o enable promiscuous mode
2491 * - when in monitor mode
2492 * - if interface marked PROMISC (assumes bridge setting is filtered)
2493 * o accept beacons:
2494 * - when operating in station mode for collecting rssi data when
2495 * the station is otherwise quiet, or
2496 * - when operating in adhoc mode so the 802.11 layer creates
2497 * node table entries for peers,
2498 * - when scanning
2499 * - when doing s/w beacon miss (e.g. for ap+sta)
2500 * - when operating in ap mode in 11g to detect overlapping bss that
2501 * require protection
2502 * - when operating in mesh mode to detect neighbors
2503 * o accept control frames:
2504 * - when in monitor mode
2505 * XXX HT protection for 11n
2506 */
2507static u_int32_t
2508ath_calcrxfilter(struct ath_softc *sc)
2509{
2510 struct ifnet *ifp = sc->sc_ifp;
2511 struct ieee80211com *ic = ifp->if_l2com;
2512 u_int32_t rfilt;
2513
2514 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
2515 if (!sc->sc_needmib && !sc->sc_scanning)
2516 rfilt |= HAL_RX_FILTER_PHYERR;
2517 if (ic->ic_opmode != IEEE80211_M_STA)
2518 rfilt |= HAL_RX_FILTER_PROBEREQ;
2519 /* XXX ic->ic_monvaps != 0? */
2520 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
2521 rfilt |= HAL_RX_FILTER_PROM;
2522 if (ic->ic_opmode == IEEE80211_M_STA ||
2523 ic->ic_opmode == IEEE80211_M_IBSS ||
2524 sc->sc_swbmiss || sc->sc_scanning)
2525 rfilt |= HAL_RX_FILTER_BEACON;
2526 /*
2527 * NB: We don't recalculate the rx filter when
2528 * ic_protmode changes; otherwise we could do
2529 * this only when ic_protmode != NONE.
2530 */
2531 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
2532 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
2533 rfilt |= HAL_RX_FILTER_BEACON;
2534
2535 /*
2536 * Enable hardware PS-POLL RX only for hostap mode;
2537 * STA mode sends PS-POLL frames but never
2538 * receives them.
2539 */
2540 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
2541 0, NULL) == HAL_OK &&
2542 ic->ic_opmode == IEEE80211_M_HOSTAP)
2543 rfilt |= HAL_RX_FILTER_PSPOLL;
2544
2545 if (sc->sc_nmeshvaps) {
2546 rfilt |= HAL_RX_FILTER_BEACON;
2547 if (sc->sc_hasbmatch)
2548 rfilt |= HAL_RX_FILTER_BSSID;
2549 else
2550 rfilt |= HAL_RX_FILTER_PROM;
2551 }
2552 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2553 rfilt |= HAL_RX_FILTER_CONTROL;
2554
2555 /*
2556 * Enable RX of compressed BAR frames only when doing
2557 * 802.11n. Required for A-MPDU.
2558 */
2559 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
2560 rfilt |= HAL_RX_FILTER_COMPBAR;
2561
2562 /*
2563 * Enable radar PHY errors if requested by the
2564 * DFS module.
2565 */
2566 if (sc->sc_dodfs)
2567 rfilt |= HAL_RX_FILTER_PHYRADAR;
2568
2569 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
2570 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
2571 return rfilt;
2572}
2573
2574static void
2575ath_update_promisc(struct ifnet *ifp)
2576{
2577 struct ath_softc *sc = ifp->if_softc;
2578 u_int32_t rfilt;
2579
2580 /* configure rx filter */
2581 rfilt = ath_calcrxfilter(sc);
2582 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2583
2584 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2585}
2586
2587static void
2588ath_update_mcast(struct ifnet *ifp)
2589{
2590 struct ath_softc *sc = ifp->if_softc;
2591 u_int32_t mfilt[2];
2592
2593 /* calculate and install multicast filter */
2594 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2595 struct ifmultiaddr *ifma;
2596 /*
2597 * Merge multicast addresses to form the hardware filter.
2598 */
2599 mfilt[0] = mfilt[1] = 0;
2600 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2601 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2602 caddr_t dl;
2603 u_int32_t val;
2604 u_int8_t pos;
2605
2606 /* calculate XOR of eight 6bit values */
2607 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2608 val = LE_READ_4(dl + 0);
2609 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2610 val = LE_READ_4(dl + 3);
2611 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2612 pos &= 0x3f;
2613 mfilt[pos / 32] |= (1 << (pos % 32));
2614 }
2615 if_maddr_runlock(ifp);
2616 } else
2617 mfilt[0] = mfilt[1] = ~0;
2618 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2619 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2620 __func__, mfilt[0], mfilt[1]);
2621}
2622
2623static void
2624ath_mode_init(struct ath_softc *sc)
2625{
2626 struct ifnet *ifp = sc->sc_ifp;
2627 struct ath_hal *ah = sc->sc_ah;
2628 u_int32_t rfilt;
2629
2630 /* configure rx filter */
2631 rfilt = ath_calcrxfilter(sc);
2632 ath_hal_setrxfilter(ah, rfilt);
2633
2634 /* configure operational mode */
2635 ath_hal_setopmode(ah);
2636
2637 /* handle any link-level address change */
2638 ath_hal_setmac(ah, IF_LLADDR(ifp));
2639
2640 /* calculate and install multicast filter */
2641 ath_update_mcast(ifp);
2642}
2643
2644/*
2645 * Set the slot time based on the current setting.
2646 */
2647static void
2648ath_setslottime(struct ath_softc *sc)
2649{
2650 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2651 struct ath_hal *ah = sc->sc_ah;
2652 u_int usec;
2653
2654 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
2655 usec = 13;
2656 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
2657 usec = 21;
2658 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
2659 /* honor short/long slot time only in 11g */
2660 /* XXX shouldn't honor on pure g or turbo g channel */
2661 if (ic->ic_flags & IEEE80211_F_SHSLOT)
2662 usec = HAL_SLOT_TIME_9;
2663 else
2664 usec = HAL_SLOT_TIME_20;
2665 } else
2666 usec = HAL_SLOT_TIME_9;
2667
2668 DPRINTF(sc, ATH_DEBUG_RESET,
2669 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
2670 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
2671 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
2672
2673 ath_hal_setslottime(ah, usec);
2674 sc->sc_updateslot = OK;
2675}
2676
2677/*
2678 * Callback from the 802.11 layer to update the
2679 * slot time based on the current setting.
2680 */
2681static void
2682ath_updateslot(struct ifnet *ifp)
2683{
2684 struct ath_softc *sc = ifp->if_softc;
2685 struct ieee80211com *ic = ifp->if_l2com;
2686
2687 /*
2688 * When not coordinating the BSS, change the hardware
2689 * immediately. For other operation we defer the change
2690 * until beacon updates have propagated to the stations.
2691 */
2692 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2693 ic->ic_opmode == IEEE80211_M_MBSS)
2694 sc->sc_updateslot = UPDATE;
2695 else
2696 ath_setslottime(sc);
2697}
2698
2699/*
2700 * Setup a h/w transmit queue for beacons.
2701 */
2702static int
2703ath_beaconq_setup(struct ath_hal *ah)
2704{
2705 HAL_TXQ_INFO qi;
2706
2707 memset(&qi, 0, sizeof(qi));
2708 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2709 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2710 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2711 /* NB: for dynamic turbo, don't enable any other interrupts */
2712 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
2713 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
2714}
2715
2716/*
2717 * Setup the transmit queue parameters for the beacon queue.
2718 */
2719static int
2720ath_beaconq_config(struct ath_softc *sc)
2721{
2722#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
2723 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2724 struct ath_hal *ah = sc->sc_ah;
2725 HAL_TXQ_INFO qi;
2726
2727 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
2728 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2729 ic->ic_opmode == IEEE80211_M_MBSS) {
2730 /*
2731 * Always burst out beacon and CAB traffic.
2732 */
2733 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
2734 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
2735 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
2736 } else {
2737 struct wmeParams *wmep =
2738 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
2739 /*
2740 * Adhoc mode; important thing is to use 2x cwmin.
2741 */
2742 qi.tqi_aifs = wmep->wmep_aifsn;
2743 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
2744 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
2745 }
2746
2747 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
2748 device_printf(sc->sc_dev, "unable to update parameters for "
2749 "beacon hardware queue!\n");
2750 return 0;
2751 } else {
2752 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
2753 return 1;
2754 }
2755#undef ATH_EXPONENT_TO_VALUE
2756}
2757
2758/*
2759 * Allocate and setup an initial beacon frame.
2760 */
2761static int
2762ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
2763{
2764 struct ieee80211vap *vap = ni->ni_vap;
2765 struct ath_vap *avp = ATH_VAP(vap);
2766 struct ath_buf *bf;
2767 struct mbuf *m;
2768 int error;
2769
2770 bf = avp->av_bcbuf;
2771 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n",
2772 __func__, bf->bf_m, bf->bf_node);
2773 if (bf->bf_m != NULL) {
2774 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2775 m_freem(bf->bf_m);
2776 bf->bf_m = NULL;
2777 }
2778 if (bf->bf_node != NULL) {
2779 ieee80211_free_node(bf->bf_node);
2780 bf->bf_node = NULL;
2781 }
2782
2783 /*
2784 * NB: the beacon data buffer must be 32-bit aligned;
2785 * we assume the mbuf routines will return us something
2786 * with this alignment (perhaps should assert).
2787 */
2788 m = ieee80211_beacon_alloc(ni, &avp->av_boff);
2789 if (m == NULL) {
2790 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
2791 sc->sc_stats.ast_be_nombuf++;
2792 return ENOMEM;
2793 }
2794 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2795 bf->bf_segs, &bf->bf_nseg,
2796 BUS_DMA_NOWAIT);
2797 if (error != 0) {
2798 device_printf(sc->sc_dev,
2799 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
2800 __func__, error);
2801 m_freem(m);
2802 return error;
2803 }
2804
2805 /*
2806 * Calculate a TSF adjustment factor required for staggered
2807 * beacons. Note that we assume the format of the beacon
2808 * frame leaves the tstamp field immediately following the
2809 * header.
2810 */
2811 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
2812 uint64_t tsfadjust;
2813 struct ieee80211_frame *wh;
2814
2815 /*
2816 * The beacon interval is in TU's; the TSF is in usecs.
2817 * We figure out how many TU's to add to align the timestamp
2818 * then convert to TSF units and handle byte swapping before
2819 * inserting it in the frame. The hardware will then add this
2820 * each time a beacon frame is sent. Note that we align vap's
2821 * 1..N and leave vap 0 untouched. This means vap 0 has a
2822 * timestamp in one beacon interval while the others get a
2823 * timstamp aligned to the next interval.
2824 */
2825 tsfadjust = ni->ni_intval *
2826 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
2827 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
2828
2829 DPRINTF(sc, ATH_DEBUG_BEACON,
2830 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
2831 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
2832 avp->av_bslot, ni->ni_intval,
2833 (long long unsigned) le64toh(tsfadjust));
2834
2835 wh = mtod(m, struct ieee80211_frame *);
2836 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
2837 }
2838 bf->bf_m = m;
2839 bf->bf_node = ieee80211_ref_node(ni);
2840
2841 return 0;
2842}
2843
2844/*
2845 * Setup the beacon frame for transmit.
2846 */
2847static void
2848ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2849{
2850#define USE_SHPREAMBLE(_ic) \
2851 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2852 == IEEE80211_F_SHPREAMBLE)
2853 struct ieee80211_node *ni = bf->bf_node;
2854 struct ieee80211com *ic = ni->ni_ic;
2855 struct mbuf *m = bf->bf_m;
2856 struct ath_hal *ah = sc->sc_ah;
2857 struct ath_desc *ds;
2858 int flags, antenna;
2859 const HAL_RATE_TABLE *rt;
2860 u_int8_t rix, rate;
2861
2862 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2863 __func__, m, m->m_len);
2864
2865 /* setup descriptors */
2866 ds = bf->bf_desc;
2867 bf->bf_last = bf;
2868 bf->bf_lastds = ds;
2869
2870 flags = HAL_TXDESC_NOACK;
2871 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2872 ds->ds_link = bf->bf_daddr; /* self-linked */
2873 flags |= HAL_TXDESC_VEOL;
2874 /*
2875 * Let hardware handle antenna switching.
2876 */
2877 antenna = sc->sc_txantenna;
2878 } else {
2879 ds->ds_link = 0;
2880 /*
2881 * Switch antenna every 4 beacons.
2882 * XXX assumes two antenna
2883 */
2884 if (sc->sc_txantenna != 0)
2885 antenna = sc->sc_txantenna;
2886 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
2887 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
2888 else
2889 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2890 }
2891
2892 KASSERT(bf->bf_nseg == 1,
2893 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2894 ds->ds_data = bf->bf_segs[0].ds_addr;
2895 /*
2896 * Calculate rate code.
2897 * XXX everything at min xmit rate
2898 */
2899 rix = 0;
2900 rt = sc->sc_currates;
2901 rate = rt->info[rix].rateCode;
2902 if (USE_SHPREAMBLE(ic))
2903 rate |= rt->info[rix].shortPreamble;
2904 ath_hal_setuptxdesc(ah, ds
2905 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2906 , sizeof(struct ieee80211_frame)/* header length */
2907 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2908 , ni->ni_txpower /* txpower XXX */
2909 , rate, 1 /* series 0 rate/tries */
2910 , HAL_TXKEYIX_INVALID /* no encryption */
2911 , antenna /* antenna mode */
2912 , flags /* no ack, veol for beacons */
2913 , 0 /* rts/cts rate */
2914 , 0 /* rts/cts duration */
2915 );
2916 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2917 ath_hal_filltxdesc(ah, ds
2918 , roundup(m->m_len, 4) /* buffer length */
2919 , AH_TRUE /* first segment */
2920 , AH_TRUE /* last segment */
2921 , ds /* first descriptor */
2922 );
2923#if 0
2924 ath_desc_swap(ds);
2925#endif
2926#undef USE_SHPREAMBLE
2927}
2928
2929static void
2930ath_beacon_update(struct ieee80211vap *vap, int item)
2931{
2932 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
2933
2934 setbit(bo->bo_flags, item);
2935}
2936
2937/*
2938 * Append the contents of src to dst; both queues
2939 * are assumed to be locked.
2940 */
2941static void
2942ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2943{
2944
2945 ATH_TXQ_LOCK_ASSERT(dst);
2946 ATH_TXQ_LOCK_ASSERT(src);
2947
2948 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
2949 dst->axq_link = src->axq_link;
2950 src->axq_link = NULL;
2951 dst->axq_depth += src->axq_depth;
2952 dst->axq_aggr_depth += src->axq_aggr_depth;
2953 src->axq_depth = 0;
2954 src->axq_aggr_depth = 0;
2955}
2956
2957/*
2958 * Transmit a beacon frame at SWBA. Dynamic updates to the
2959 * frame contents are done as needed and the slot time is
2960 * also adjusted based on current state.
2961 */
2962static void
2963ath_beacon_proc(void *arg, int pending)
2964{
2965 struct ath_softc *sc = arg;
2966 struct ath_hal *ah = sc->sc_ah;
2967 struct ieee80211vap *vap;
2968 struct ath_buf *bf;
2969 int slot, otherant;
2970 uint32_t bfaddr;
2971
2972 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
2973 __func__, pending);
2974 /*
2975 * Check if the previous beacon has gone out. If
2976 * not don't try to post another, skip this period
2977 * and wait for the next. Missed beacons indicate
2978 * a problem and should not occur. If we miss too
2979 * many consecutive beacons reset the device.
2980 */
2981 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2982 sc->sc_bmisscount++;
2983 sc->sc_stats.ast_be_missed++;
2984 DPRINTF(sc, ATH_DEBUG_BEACON,
2985 "%s: missed %u consecutive beacons\n",
2986 __func__, sc->sc_bmisscount);
2987 if (sc->sc_bmisscount >= ath_bstuck_threshold)
2988 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
2989 return;
2990 }
2991 if (sc->sc_bmisscount != 0) {
2992 DPRINTF(sc, ATH_DEBUG_BEACON,
2993 "%s: resume beacon xmit after %u misses\n",
2994 __func__, sc->sc_bmisscount);
2995 sc->sc_bmisscount = 0;
2996 }
2997
2998 if (sc->sc_stagbeacons) { /* staggered beacons */
2999 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3000 uint32_t tsftu;
3001
3002 tsftu = ath_hal_gettsf32(ah) >> 10;
3003 /* XXX lintval */
3004 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
3005 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
3006 bfaddr = 0;
3007 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
3008 bf = ath_beacon_generate(sc, vap);
3009 if (bf != NULL)
3010 bfaddr = bf->bf_daddr;
3011 }
3012 } else { /* burst'd beacons */
3013 uint32_t *bflink = &bfaddr;
3014
3015 for (slot = 0; slot < ATH_BCBUF; slot++) {
3016 vap = sc->sc_bslot[slot];
3017 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
3018 bf = ath_beacon_generate(sc, vap);
3019 if (bf != NULL) {
3020 *bflink = bf->bf_daddr;
3021 bflink = &bf->bf_desc->ds_link;
3022 }
3023 }
3024 }
3025 *bflink = 0; /* terminate list */
3026 }
3027
3028 /*
3029 * Handle slot time change when a non-ERP station joins/leaves
3030 * an 11g network. The 802.11 layer notifies us via callback,
3031 * we mark updateslot, then wait one beacon before effecting
3032 * the change. This gives associated stations at least one
3033 * beacon interval to note the state change.
3034 */
3035 /* XXX locking */
3036 if (sc->sc_updateslot == UPDATE) {
3037 sc->sc_updateslot = COMMIT; /* commit next beacon */
3038 sc->sc_slotupdate = slot;
3039 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
3040 ath_setslottime(sc); /* commit change to h/w */
3041
3042 /*
3043 * Check recent per-antenna transmit statistics and flip
3044 * the default antenna if noticeably more frames went out
3045 * on the non-default antenna.
3046 * XXX assumes 2 anntenae
3047 */
3048 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
3049 otherant = sc->sc_defant & 1 ? 2 : 1;
3050 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
3051 ath_setdefantenna(sc, otherant);
3052 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
3053 }
3054
3055 if (bfaddr != 0) {
3056 /*
3057 * Stop any current dma and put the new frame on the queue.
3058 * This should never fail since we check above that no frames
3059 * are still pending on the queue.
3060 */
3061 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
3062 DPRINTF(sc, ATH_DEBUG_ANY,
3063 "%s: beacon queue %u did not stop?\n",
3064 __func__, sc->sc_bhalq);
3065 }
3066 /* NB: cabq traffic should already be queued and primed */
3067 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
3068 ath_hal_txstart(ah, sc->sc_bhalq);
3069
3070 sc->sc_stats.ast_be_xmit++;
3071 }
3072}
3073
3074static struct ath_buf *
3075ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
3076{
3077 struct ath_vap *avp = ATH_VAP(vap);
3078 struct ath_txq *cabq = sc->sc_cabq;
3079 struct ath_buf *bf;
3080 struct mbuf *m;
3081 int nmcastq, error;
3082
3083 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
3084 ("not running, state %d", vap->iv_state));
3085 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3086
3087 /*
3088 * Update dynamic beacon contents. If this returns
3089 * non-zero then we need to remap the memory because
3090 * the beacon frame changed size (probably because
3091 * of the TIM bitmap).
3092 */
3093 bf = avp->av_bcbuf;
3094 m = bf->bf_m;
3095 /* XXX lock mcastq? */
3096 nmcastq = avp->av_mcastq.axq_depth;
3097
3098 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
3099 /* XXX too conservative? */
3100 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3101 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3102 bf->bf_segs, &bf->bf_nseg,
3103 BUS_DMA_NOWAIT);
3104 if (error != 0) {
3105 if_printf(vap->iv_ifp,
3106 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3107 __func__, error);
3108 return NULL;
3109 }
3110 }
3111 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
3112 DPRINTF(sc, ATH_DEBUG_BEACON,
3113 "%s: cabq did not drain, mcastq %u cabq %u\n",
3114 __func__, nmcastq, cabq->axq_depth);
3115 sc->sc_stats.ast_cabq_busy++;
3116 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
3117 /*
3118 * CABQ traffic from a previous vap is still pending.
3119 * We must drain the q before this beacon frame goes
3120 * out as otherwise this vap's stations will get cab
3121 * frames from a different vap.
3122 * XXX could be slow causing us to miss DBA
3123 */
3124 ath_tx_draintxq(sc, cabq);
3125 }
3126 }
3127 ath_beacon_setup(sc, bf);
3128 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3129
3130 /*
3131 * Enable the CAB queue before the beacon queue to
3132 * insure cab frames are triggered by this beacon.
3133 */
3134 if (avp->av_boff.bo_tim[4] & 1) {
3135 struct ath_hal *ah = sc->sc_ah;
3136
3137 /* NB: only at DTIM */
3138 ATH_TXQ_LOCK(cabq);
3139 ATH_TXQ_LOCK(&avp->av_mcastq);
3140 if (nmcastq) {
3141 struct ath_buf *bfm;
3142
3143 /*
3144 * Move frames from the s/w mcast q to the h/w cab q.
3145 * XXX MORE_DATA bit
3146 */
3147 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q);
3148 if (cabq->axq_link != NULL) {
3149 *cabq->axq_link = bfm->bf_daddr;
3150 } else
3151 ath_hal_puttxbuf(ah, cabq->axq_qnum,
3152 bfm->bf_daddr);
3153 ath_txqmove(cabq, &avp->av_mcastq);
3154
3155 sc->sc_stats.ast_cabq_xmit += nmcastq;
3156 }
3157 /* NB: gated by beacon so safe to start here */
3158 if (! TAILQ_EMPTY(&(cabq->axq_q)))
3159 ath_hal_txstart(ah, cabq->axq_qnum);
3160 ATH_TXQ_UNLOCK(&avp->av_mcastq);
3161 ATH_TXQ_UNLOCK(cabq);
3162 }
3163 return bf;
3164}
3165
3166static void
3167ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
3168{
3169 struct ath_vap *avp = ATH_VAP(vap);
3170 struct ath_hal *ah = sc->sc_ah;
3171 struct ath_buf *bf;
3172 struct mbuf *m;
3173 int error;
3174
3175 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3176
3177 /*
3178 * Update dynamic beacon contents. If this returns
3179 * non-zero then we need to remap the memory because
3180 * the beacon frame changed size (probably because
3181 * of the TIM bitmap).
3182 */
3183 bf = avp->av_bcbuf;
3184 m = bf->bf_m;
3185 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
3186 /* XXX too conservative? */
3187 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3188 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3189 bf->bf_segs, &bf->bf_nseg,
3190 BUS_DMA_NOWAIT);
3191 if (error != 0) {
3192 if_printf(vap->iv_ifp,
3193 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3194 __func__, error);
3195 return;
3196 }
3197 }
3198 ath_beacon_setup(sc, bf);
3199 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3200
3201 /* NB: caller is known to have already stopped tx dma */
3202 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
3203 ath_hal_txstart(ah, sc->sc_bhalq);
3204}
3205
3206/*
3207 * Reset the hardware, with no loss.
3208 *
3209 * This can't be used for a general case reset.
3210 */
3211static void
3212ath_reset_proc(void *arg, int pending)
3213{
3214 struct ath_softc *sc = arg;
3215 struct ifnet *ifp = sc->sc_ifp;
3216
3217#if 0
3218 if_printf(ifp, "%s: resetting\n", __func__);
3219#endif
3220 ath_reset(ifp, ATH_RESET_NOLOSS);
3221}
3222
3223/*
3224 * Reset the hardware after detecting beacons have stopped.
3225 */
3226static void
3227ath_bstuck_proc(void *arg, int pending)
3228{
3229 struct ath_softc *sc = arg;
3230 struct ifnet *ifp = sc->sc_ifp;
3231 uint32_t hangs = 0;
3232
3233 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3234 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
3235
3236 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3237 sc->sc_bmisscount);
3238 sc->sc_stats.ast_bstuck++;
3239 /*
3240 * This assumes that there's no simultaneous channel mode change
3241 * occuring.
3242 */
3243 ath_reset(ifp, ATH_RESET_NOLOSS);
3244}
3245
3246/*
3247 * Reclaim beacon resources and return buffer to the pool.
3248 */
3249static void
3250ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
3251{
3252
3253 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
3254 __func__, bf, bf->bf_m, bf->bf_node);
3255 if (bf->bf_m != NULL) {
3256 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3257 m_freem(bf->bf_m);
3258 bf->bf_m = NULL;
3259 }
3260 if (bf->bf_node != NULL) {
3261 ieee80211_free_node(bf->bf_node);
3262 bf->bf_node = NULL;
3263 }
3264 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
3265}
3266
3267/*
3268 * Reclaim beacon resources.
3269 */
3270static void
3271ath_beacon_free(struct ath_softc *sc)
3272{
3273 struct ath_buf *bf;
3274
3275 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
3276 DPRINTF(sc, ATH_DEBUG_NODE,
3277 "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
3278 __func__, bf, bf->bf_m, bf->bf_node);
3279 if (bf->bf_m != NULL) {
3280 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3281 m_freem(bf->bf_m);
3282 bf->bf_m = NULL;
3283 }
3284 if (bf->bf_node != NULL) {
3285 ieee80211_free_node(bf->bf_node);
3286 bf->bf_node = NULL;
3287 }
3288 }
3289}
3290
3291/*
3292 * Configure the beacon and sleep timers.
3293 *
3294 * When operating as an AP this resets the TSF and sets
3295 * up the hardware to notify us when we need to issue beacons.
3296 *
3297 * When operating in station mode this sets up the beacon
3298 * timers according to the timestamp of the last received
3299 * beacon and the current TSF, configures PCF and DTIM
3300 * handling, programs the sleep registers so the hardware
3301 * will wakeup in time to receive beacons, and configures
3302 * the beacon miss handling so we'll receive a BMISS
3303 * interrupt when we stop seeing beacons from the AP
3304 * we've associated with.
3305 */
3306static void
3307ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
3308{
3309#define TSF_TO_TU(_h,_l) \
3310 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
3311#define FUDGE 2
3312 struct ath_hal *ah = sc->sc_ah;
3313 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3314 struct ieee80211_node *ni;
3315 u_int32_t nexttbtt, intval, tsftu;
3316 u_int64_t tsf;
3317
3318 if (vap == NULL)
3319 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
3320 ni = ieee80211_ref_node(vap->iv_bss);
3321
3322 /* extract tstamp from last beacon and convert to TU */
3323 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
3324 LE_READ_4(ni->ni_tstamp.data));
3325 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3326 ic->ic_opmode == IEEE80211_M_MBSS) {
3327 /*
3328 * For multi-bss ap/mesh support beacons are either staggered
3329 * evenly over N slots or burst together. For the former
3330 * arrange for the SWBA to be delivered for each slot.
3331 * Slots that are not occupied will generate nothing.
3332 */
3333 /* NB: the beacon interval is kept internally in TU's */
3334 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3335 if (sc->sc_stagbeacons)
3336 intval /= ATH_BCBUF;
3337 } else {
3338 /* NB: the beacon interval is kept internally in TU's */
3339 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3340 }
3341 if (nexttbtt == 0) /* e.g. for ap mode */
3342 nexttbtt = intval;
3343 else if (intval) /* NB: can be 0 for monitor mode */
3344 nexttbtt = roundup(nexttbtt, intval);
3345 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
3346 __func__, nexttbtt, intval, ni->ni_intval);
3347 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
3348 HAL_BEACON_STATE bs;
3349 int dtimperiod, dtimcount;
3350 int cfpperiod, cfpcount;
3351
3352 /*
3353 * Setup dtim and cfp parameters according to
3354 * last beacon we received (which may be none).
3355 */
3356 dtimperiod = ni->ni_dtim_period;
3357 if (dtimperiod <= 0) /* NB: 0 if not known */
3358 dtimperiod = 1;
3359 dtimcount = ni->ni_dtim_count;
3360 if (dtimcount >= dtimperiod) /* NB: sanity check */
3361 dtimcount = 0; /* XXX? */
3362 cfpperiod = 1; /* NB: no PCF support yet */
3363 cfpcount = 0;
3364 /*
3365 * Pull nexttbtt forward to reflect the current
3366 * TSF and calculate dtim+cfp state for the result.
3367 */
3368 tsf = ath_hal_gettsf64(ah);
3369 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3370 do {
3371 nexttbtt += intval;
3372 if (--dtimcount < 0) {
3373 dtimcount = dtimperiod - 1;
3374 if (--cfpcount < 0)
3375 cfpcount = cfpperiod - 1;
3376 }
3377 } while (nexttbtt < tsftu);
3378 memset(&bs, 0, sizeof(bs));
3379 bs.bs_intval = intval;
3380 bs.bs_nexttbtt = nexttbtt;
3381 bs.bs_dtimperiod = dtimperiod*intval;
3382 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
3383 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
3384 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
3385 bs.bs_cfpmaxduration = 0;
3386#if 0
3387 /*
3388 * The 802.11 layer records the offset to the DTIM
3389 * bitmap while receiving beacons; use it here to
3390 * enable h/w detection of our AID being marked in
3391 * the bitmap vector (to indicate frames for us are
3392 * pending at the AP).
3393 * XXX do DTIM handling in s/w to WAR old h/w bugs
3394 * XXX enable based on h/w rev for newer chips
3395 */
3396 bs.bs_timoffset = ni->ni_timoff;
3397#endif
3398 /*
3399 * Calculate the number of consecutive beacons to miss
3400 * before taking a BMISS interrupt.
3401 * Note that we clamp the result to at most 10 beacons.
3402 */
3403 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
3404 if (bs.bs_bmissthreshold > 10)
3405 bs.bs_bmissthreshold = 10;
3406 else if (bs.bs_bmissthreshold <= 0)
3407 bs.bs_bmissthreshold = 1;
3408
3409 /*
3410 * Calculate sleep duration. The configuration is
3411 * given in ms. We insure a multiple of the beacon
3412 * period is used. Also, if the sleep duration is
3413 * greater than the DTIM period then it makes senses
3414 * to make it a multiple of that.
3415 *
3416 * XXX fixed at 100ms
3417 */
3418 bs.bs_sleepduration =
3419 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
3420 if (bs.bs_sleepduration > bs.bs_dtimperiod)
3421 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
3422
3423 DPRINTF(sc, ATH_DEBUG_BEACON,
3424 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
3425 , __func__
3426 , tsf, tsftu
3427 , bs.bs_intval
3428 , bs.bs_nexttbtt
3429 , bs.bs_dtimperiod
3430 , bs.bs_nextdtim
3431 , bs.bs_bmissthreshold
3432 , bs.bs_sleepduration
3433 , bs.bs_cfpperiod
3434 , bs.bs_cfpmaxduration
3435 , bs.bs_cfpnext
3436 , bs.bs_timoffset
3437 );
3438 ath_hal_intrset(ah, 0);
3439 ath_hal_beacontimers(ah, &bs);
3440 sc->sc_imask |= HAL_INT_BMISS;
3441 ath_hal_intrset(ah, sc->sc_imask);
3442 } else {
3443 ath_hal_intrset(ah, 0);
3444 if (nexttbtt == intval)
3445 intval |= HAL_BEACON_RESET_TSF;
3446 if (ic->ic_opmode == IEEE80211_M_IBSS) {
3447 /*
3448 * In IBSS mode enable the beacon timers but only
3449 * enable SWBA interrupts if we need to manually
3450 * prepare beacon frames. Otherwise we use a
3451 * self-linked tx descriptor and let the hardware
3452 * deal with things.
3453 */
3454 intval |= HAL_BEACON_ENA;
3455 if (!sc->sc_hasveol)
3456 sc->sc_imask |= HAL_INT_SWBA;
3457 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
3458 /*
3459 * Pull nexttbtt forward to reflect
3460 * the current TSF.
3461 */
3462 tsf = ath_hal_gettsf64(ah);
3463 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3464 do {
3465 nexttbtt += intval;
3466 } while (nexttbtt < tsftu);
3467 }
3468 ath_beaconq_config(sc);
3469 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3470 ic->ic_opmode == IEEE80211_M_MBSS) {
3471 /*
3472 * In AP/mesh mode we enable the beacon timers
3473 * and SWBA interrupts to prepare beacon frames.
3474 */
3475 intval |= HAL_BEACON_ENA;
3476 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
3477 ath_beaconq_config(sc);
3478 }
3479 ath_hal_beaconinit(ah, nexttbtt, intval);
3480 sc->sc_bmisscount = 0;
3481 ath_hal_intrset(ah, sc->sc_imask);
3482 /*
3483 * When using a self-linked beacon descriptor in
3484 * ibss mode load it once here.
3485 */
3486 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
3487 ath_beacon_start_adhoc(sc, vap);
3488 }
3489 sc->sc_syncbeacon = 0;
3490 ieee80211_free_node(ni);
3491#undef FUDGE
3492#undef TSF_TO_TU
3493}
3494
3495static void
3496ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3497{
3498 bus_addr_t *paddr = (bus_addr_t*) arg;
3499 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3500 *paddr = segs->ds_addr;
3501}
3502
3503static int
3504ath_descdma_setup(struct ath_softc *sc,
3505 struct ath_descdma *dd, ath_bufhead *head,
3506 const char *name, int nbuf, int ndesc)
3507{
3508#define DS2PHYS(_dd, _ds) \
3509 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3510#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3511 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3512 struct ifnet *ifp = sc->sc_ifp;
3513 uint8_t *ds;
3514 struct ath_buf *bf;
3515 int i, bsize, error;
3516 int desc_len;
3517
3518 desc_len = sizeof(struct ath_desc);
3519
3520 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
3521 __func__, name, nbuf, ndesc);
3522
3523 dd->dd_name = name;
3524 dd->dd_desc_len = desc_len * nbuf * ndesc;
3525
3526 /*
3527 * Merlin work-around:
3528 * Descriptors that cross the 4KB boundary can't be used.
3529 * Assume one skipped descriptor per 4KB page.
3530 */
3531 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3532 int numdescpage = 4096 / (desc_len * ndesc);
3533 dd->dd_desc_len = (nbuf / numdescpage + 1) * 4096;
3534 }
3535
3536 /*
3537 * Setup DMA descriptor area.
3538 */
3539 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3540 PAGE_SIZE, 0, /* alignment, bounds */
3541 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3542 BUS_SPACE_MAXADDR, /* highaddr */
3543 NULL, NULL, /* filter, filterarg */
3544 dd->dd_desc_len, /* maxsize */
3545 1, /* nsegments */
3546 dd->dd_desc_len, /* maxsegsize */
3547 BUS_DMA_ALLOCNOW, /* flags */
3548 NULL, /* lockfunc */
3549 NULL, /* lockarg */
3550 &dd->dd_dmat);
3551 if (error != 0) {
3552 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3553 return error;
3554 }
3555
3556 /* allocate descriptors */
3557 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
3558 if (error != 0) {
3559 if_printf(ifp, "unable to create dmamap for %s descriptors, "
3560 "error %u\n", dd->dd_name, error);
3561 goto fail0;
3562 }
3563
3564 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3565 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3566 &dd->dd_dmamap);
3567 if (error != 0) {
3568 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3569 "error %u\n", nbuf * ndesc, dd->dd_name, error);
3570 goto fail1;
3571 }
3572
3573 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3574 dd->dd_desc, dd->dd_desc_len,
3575 ath_load_cb, &dd->dd_desc_paddr,
3576 BUS_DMA_NOWAIT);
3577 if (error != 0) {
3578 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3579 dd->dd_name, error);
3580 goto fail2;
3581 }
3582
3583 ds = (uint8_t *) dd->dd_desc;
3584 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3585 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
3586 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
3587
3588 /* allocate rx buffers */
3589 bsize = sizeof(struct ath_buf) * nbuf;
3590 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3591 if (bf == NULL) {
3592 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3593 dd->dd_name, bsize);
3594 goto fail3;
3595 }
3596 dd->dd_bufptr = bf;
3597
3598 TAILQ_INIT(head);
3599 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * desc_len)) {
3600 bf->bf_desc = (struct ath_desc *) ds;
3601 bf->bf_daddr = DS2PHYS(dd, ds);
3602 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3603 /*
3604 * Merlin WAR: Skip descriptor addresses which
3605 * cause 4KB boundary crossing along any point
3606 * in the descriptor.
3607 */
3608 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
3609 desc_len * ndesc)) {
3610 /* Start at the next page */
3611 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
3612 bf->bf_desc = (struct ath_desc *) ds;
3613 bf->bf_daddr = DS2PHYS(dd, ds);
3614 }
3615 }
3616 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3617 &bf->bf_dmamap);
3618 if (error != 0) {
3619 if_printf(ifp, "unable to create dmamap for %s "
3620 "buffer %u, error %u\n", dd->dd_name, i, error);
3621 ath_descdma_cleanup(sc, dd, head);
3622 return error;
3623 }
3624 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
3625 TAILQ_INSERT_TAIL(head, bf, bf_list);
3626 }
3627 return 0;
3628fail3:
3629 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3630fail2:
3631 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3632fail1:
3633 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3634fail0:
3635 bus_dma_tag_destroy(dd->dd_dmat);
3636 memset(dd, 0, sizeof(*dd));
3637 return error;
3638#undef DS2PHYS
3639#undef ATH_DESC_4KB_BOUND_CHECK
3640}
3641
3642static void
3643ath_descdma_cleanup(struct ath_softc *sc,
3644 struct ath_descdma *dd, ath_bufhead *head)
3645{
3646 struct ath_buf *bf;
3647 struct ieee80211_node *ni;
3648
3649 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3650 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3651 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3652 bus_dma_tag_destroy(dd->dd_dmat);
3653
3654 TAILQ_FOREACH(bf, head, bf_list) {
3655 if (bf->bf_m) {
3656 m_freem(bf->bf_m);
3657 bf->bf_m = NULL;
3658 }
3659 if (bf->bf_dmamap != NULL) {
3660 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3661 bf->bf_dmamap = NULL;
3662 }
3663 ni = bf->bf_node;
3664 bf->bf_node = NULL;
3665 if (ni != NULL) {
3666 /*
3667 * Reclaim node reference.
3668 */
3669 ieee80211_free_node(ni);
3670 }
3671 }
3672
3673 TAILQ_INIT(head);
3674 free(dd->dd_bufptr, M_ATHDEV);
3675 memset(dd, 0, sizeof(*dd));
3676}
3677
3678static int
3679ath_desc_alloc(struct ath_softc *sc)
3680{
3681 int error;
3682
3683 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
3684 "rx", ath_rxbuf, 1);
3685 if (error != 0)
3686 return error;
3687
3688 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3689 "tx", ath_txbuf, ATH_TXDESC);
3690 if (error != 0) {
3691 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3692 return error;
3693 }
3694
3695 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3696 "beacon", ATH_BCBUF, 1);
3697 if (error != 0) {
3698 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3699 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3700 return error;
3701 }
3702 return 0;
3703}
3704
3705static void
3706ath_desc_free(struct ath_softc *sc)
3707{
3708
3709 if (sc->sc_bdma.dd_desc_len != 0)
3710 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3711 if (sc->sc_txdma.dd_desc_len != 0)
3712 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3713 if (sc->sc_rxdma.dd_desc_len != 0)
3714 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3715}
3716
3717static struct ieee80211_node *
3718ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3719{
3720 struct ieee80211com *ic = vap->iv_ic;
3721 struct ath_softc *sc = ic->ic_ifp->if_softc;
3722 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3723 struct ath_node *an;
3724
3725 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3726 if (an == NULL) {
3727 /* XXX stat+msg */
3728 return NULL;
3729 }
3730 ath_rate_node_init(sc, an);
3731
3732 /* Setup the mutex - there's no associd yet so set the name to NULL */
3733 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3734 device_get_nameunit(sc->sc_dev), an);
3735 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3736
3737 /* XXX setup ath_tid */
3738 ath_tx_tid_init(sc, an);
3739
3740 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
3741 return &an->an_node;
3742}
3743
3744static void
3745ath_node_cleanup(struct ieee80211_node *ni)
3746{
3747 struct ieee80211com *ic = ni->ni_ic;
3748 struct ath_softc *sc = ic->ic_ifp->if_softc;
3749
3750 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3751 ath_tx_node_flush(sc, ATH_NODE(ni));
3752 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3753 sc->sc_node_cleanup(ni);
3754}
3755
3756static void
3757ath_node_free(struct ieee80211_node *ni)
3758{
3759 struct ieee80211com *ic = ni->ni_ic;
3760 struct ath_softc *sc = ic->ic_ifp->if_softc;
3761
3762 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
3763 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3764 sc->sc_node_free(ni);
3765}
3766
3767static void
3768ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3769{
3770 struct ieee80211com *ic = ni->ni_ic;
3771 struct ath_softc *sc = ic->ic_ifp->if_softc;
3772 struct ath_hal *ah = sc->sc_ah;
3773
3774 *rssi = ic->ic_node_getrssi(ni);
3775 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3776 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3777 else
3778 *noise = -95; /* nominally correct */
3779}
3780
3781static int
3782ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
3783{
3784 struct ath_hal *ah = sc->sc_ah;
3785 int error;
3786 struct mbuf *m;
3787 struct ath_desc *ds;
3788
3789 m = bf->bf_m;
3790 if (m == NULL) {
3791 /*
3792 * NB: by assigning a page to the rx dma buffer we
3793 * implicitly satisfy the Atheros requirement that
3794 * this buffer be cache-line-aligned and sized to be
3795 * multiple of the cache line size. Not doing this
3796 * causes weird stuff to happen (for the 5210 at least).
3797 */
3798 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3799 if (m == NULL) {
3800 DPRINTF(sc, ATH_DEBUG_ANY,
3801 "%s: no mbuf/cluster\n", __func__);
3802 sc->sc_stats.ast_rx_nombuf++;
3803 return ENOMEM;
3804 }
3805 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
3806
3807 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
3808 bf->bf_dmamap, m,
3809 bf->bf_segs, &bf->bf_nseg,
3810 BUS_DMA_NOWAIT);
3811 if (error != 0) {
3812 DPRINTF(sc, ATH_DEBUG_ANY,
3813 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
3814 __func__, error);
3815 sc->sc_stats.ast_rx_busdma++;
3816 m_freem(m);
3817 return error;
3818 }
3819 KASSERT(bf->bf_nseg == 1,
3820 ("multi-segment packet; nseg %u", bf->bf_nseg));
3821 bf->bf_m = m;
3822 }
3823 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
3824
3825 /*
3826 * Setup descriptors. For receive we always terminate
3827 * the descriptor list with a self-linked entry so we'll
3828 * not get overrun under high load (as can happen with a
3829 * 5212 when ANI processing enables PHY error frames).
3830 *
3831 * To insure the last descriptor is self-linked we create
3832 * each descriptor as self-linked and add it to the end. As
3833 * each additional descriptor is added the previous self-linked
3834 * entry is ``fixed'' naturally. This should be safe even
3835 * if DMA is happening. When processing RX interrupts we
3836 * never remove/process the last, self-linked, entry on the
3837 * descriptor list. This insures the hardware always has
3838 * someplace to write a new frame.
3839 */
3840 /*
3841 * 11N: we can no longer afford to self link the last descriptor.
3842 * MAC acknowledges BA status as long as it copies frames to host
3843 * buffer (or rx fifo). This can incorrectly acknowledge packets
3844 * to a sender if last desc is self-linked.
3845 */
3846 ds = bf->bf_desc;
3847 if (sc->sc_rxslink)
3848 ds->ds_link = bf->bf_daddr; /* link to self */
3849 else
3850 ds->ds_link = 0; /* terminate the list */
3851 ds->ds_data = bf->bf_segs[0].ds_addr;
3852 ath_hal_setuprxdesc(ah, ds
3853 , m->m_len /* buffer size */
3854 , 0
3855 );
3856
3857 if (sc->sc_rxlink != NULL)
3858 *sc->sc_rxlink = bf->bf_daddr;
3859 sc->sc_rxlink = &ds->ds_link;
3860 return 0;
3861}
3862
3863/*
3864 * Extend 15-bit time stamp from rx descriptor to
3865 * a full 64-bit TSF using the specified TSF.
3866 */
3867static __inline u_int64_t
3868ath_extend_tsf15(u_int32_t rstamp, u_int64_t tsf)
3869{
3870 if ((tsf & 0x7fff) < rstamp)
3871 tsf -= 0x8000;
3872
3873 return ((tsf &~ 0x7fff) | rstamp);
3874}
3875
3876/*
3877 * Extend 32-bit time stamp from rx descriptor to
3878 * a full 64-bit TSF using the specified TSF.
3879 */
3880static __inline u_int64_t
3881ath_extend_tsf32(u_int32_t rstamp, u_int64_t tsf)
3882{
3883 u_int32_t tsf_low = tsf & 0xffffffff;
3884 u_int64_t tsf64 = (tsf & ~0xffffffffULL) | rstamp;
3885
3886 if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
3887 tsf64 -= 0x100000000ULL;
3888
3889 if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
3890 tsf64 += 0x100000000ULL;
3891
3892 return tsf64;
3893}
3894
3895/*
3896 * Extend the TSF from the RX descriptor to a full 64 bit TSF.
3897 * Earlier hardware versions only wrote the low 15 bits of the
3898 * TSF into the RX descriptor; later versions (AR5416 and up)
3899 * include the 32 bit TSF value.
3900 */
3901static __inline u_int64_t
3902ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp, u_int64_t tsf)
3903{
3904 if (sc->sc_rxtsf32)
3905 return ath_extend_tsf32(rstamp, tsf);
3906 else
3907 return ath_extend_tsf15(rstamp, tsf);
3908}
3909
3910/*
3911 * Intercept management frames to collect beacon rssi data
3912 * and to do ibss merges.
3913 */
3914static void
3915ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
3916 int subtype, int rssi, int nf)
3917{
3918 struct ieee80211vap *vap = ni->ni_vap;
3919 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
3920
3921 /*
3922 * Call up first so subsequent work can use information
3923 * potentially stored in the node (e.g. for ibss merge).
3924 */
3925 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
3926 switch (subtype) {
3927 case IEEE80211_FC0_SUBTYPE_BEACON:
3928 /* update rssi statistics for use by the hal */
3929 /* XXX unlocked check against vap->iv_bss? */
3930 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
3931 if (sc->sc_syncbeacon &&
3932 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
3933 /*
3934 * Resync beacon timers using the tsf of the beacon
3935 * frame we just received.
3936 */
3937 ath_beacon_config(sc, vap);
3938 }
3939 /* fall thru... */
3940 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3941 if (vap->iv_opmode == IEEE80211_M_IBSS &&
3942 vap->iv_state == IEEE80211_S_RUN) {
3943 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
3944 uint64_t tsf = ath_extend_tsf(sc, rstamp,
3945 ath_hal_gettsf64(sc->sc_ah));
3946 /*
3947 * Handle ibss merge as needed; check the tsf on the
3948 * frame before attempting the merge. The 802.11 spec
3949 * says the station should change it's bssid to match
3950 * the oldest station with the same ssid, where oldest
3951 * is determined by the tsf. Note that hardware
3952 * reconfiguration happens through callback to
3953 * ath_newstate as the state machine will go from
3954 * RUN -> RUN when this happens.
3955 */
3956 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
3957 DPRINTF(sc, ATH_DEBUG_STATE,
3958 "ibss merge, rstamp %u tsf %ju "
3959 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
3960 (uintmax_t)ni->ni_tstamp.tsf);
3961 (void) ieee80211_ibss_merge(ni);
3962 }
3963 }
3964 break;
3965 }
3966}
3967
3968/*
3969 * Set the default antenna.
3970 */
3971static void
3972ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3973{
3974 struct ath_hal *ah = sc->sc_ah;
3975
3976 /* XXX block beacon interrupts */
3977 ath_hal_setdefantenna(ah, antenna);
3978 if (sc->sc_defant != antenna)
3979 sc->sc_stats.ast_ant_defswitch++;
3980 sc->sc_defant = antenna;
3981 sc->sc_rxotherant = 0;
3982}
3983
3984static void
3985ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
3986 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
3987{
3988#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
3989#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
3990#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
3991#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
3992 struct ath_softc *sc = ifp->if_softc;
3993 const HAL_RATE_TABLE *rt;
3994 uint8_t rix;
3995
3996 rt = sc->sc_currates;
3997 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3998 rix = rt->rateCodeToIndex[rs->rs_rate];
3999 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
4000 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
4001#ifdef AH_SUPPORT_AR5416
4002 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
4003 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
4004 struct ieee80211com *ic = ifp->if_l2com;
4005
4006 if ((rs->rs_flags & HAL_RX_2040) == 0)
4007 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
4008 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
4009 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
4010 else
4011 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
4012 if ((rs->rs_flags & HAL_RX_GI) == 0)
4013 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
4014 }
4015#endif
4016 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
4017 if (rs->rs_status & HAL_RXERR_CRC)
4018 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
4019 /* XXX propagate other error flags from descriptor */
4020 sc->sc_rx_th.wr_antnoise = nf;
4021 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
4022 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
4023#undef CHAN_HT
4024#undef CHAN_HT20
4025#undef CHAN_HT40U
4026#undef CHAN_HT40D
4027}
4028
4029static void
4030ath_handle_micerror(struct ieee80211com *ic,
4031 struct ieee80211_frame *wh, int keyix)
4032{
4033 struct ieee80211_node *ni;
4034
4035 /* XXX recheck MIC to deal w/ chips that lie */
4036 /* XXX discard MIC errors on !data frames */
4037 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
4038 if (ni != NULL) {
4039 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
4040 ieee80211_free_node(ni);
4041 }
4042}
4043
4044/*
4045 * Only run the RX proc if it's not already running.
4046 * Since this may get run as part of the reset/flush path,
4047 * the task can't clash with an existing, running tasklet.
4048 */
4049static void
4050ath_rx_tasklet(void *arg, int npending)
4051{
4052 struct ath_softc *sc = arg;
4053
4054 CTR1(ATH_KTR_INTR, "ath_rx_proc: pending=%d", npending);
4055 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
4056 ATH_PCU_LOCK(sc);
4057 if (sc->sc_inreset_cnt > 0) {
4058 device_printf(sc->sc_dev,
4059 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4060 ATH_PCU_UNLOCK(sc);
4061 return;
4062 }
4063 ATH_PCU_UNLOCK(sc);
4064 ath_rx_proc(sc, 1);
4065}
4066
4067static void
4068ath_rx_proc(struct ath_softc *sc, int resched)
4069{
4070#define PA2DESC(_sc, _pa) \
4071 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
4072 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
4073 struct ath_buf *bf;
4074 struct ifnet *ifp = sc->sc_ifp;
4075 struct ieee80211com *ic = ifp->if_l2com;
4076 struct ath_hal *ah = sc->sc_ah;
4077 struct ath_desc *ds;
4078 struct ath_rx_status *rs;
4079 struct mbuf *m;
4080 struct ieee80211_node *ni;
4081 int len, type, ngood;
4082 HAL_STATUS status;
4083 int16_t nf;
4084 u_int64_t tsf, rstamp;
4085 int npkts = 0;
4086
4087 /* XXX we must not hold the ATH_LOCK here */
4088 ATH_UNLOCK_ASSERT(sc);
4089 ATH_PCU_UNLOCK_ASSERT(sc);
4090
4091 ATH_PCU_LOCK(sc);
4092 sc->sc_rxproc_cnt++;
4093 ATH_PCU_UNLOCK(sc);
4094
4095 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
4096 ngood = 0;
4097 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
4098 sc->sc_stats.ast_rx_noise = nf;
4099 tsf = ath_hal_gettsf64(ah);
4100 do {
4101 bf = TAILQ_FIRST(&sc->sc_rxbuf);
4102 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
4103 if_printf(ifp, "%s: no buffer!\n", __func__);
4104 break;
4105 } else if (bf == NULL) {
4106 /*
4107 * End of List:
4108 * this can happen for non-self-linked RX chains
4109 */
4110 sc->sc_stats.ast_rx_hitqueueend++;
4111 break;
4112 }
4113 m = bf->bf_m;
4114 if (m == NULL) { /* NB: shouldn't happen */
4115 /*
4116 * If mbuf allocation failed previously there
4117 * will be no mbuf; try again to re-populate it.
4118 */
4119 /* XXX make debug msg */
4120 if_printf(ifp, "%s: no mbuf!\n", __func__);
4121 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
4122 goto rx_next;
4123 }
4124 ds = bf->bf_desc;
4125 if (ds->ds_link == bf->bf_daddr) {
4126 /* NB: never process the self-linked entry at the end */
4127 sc->sc_stats.ast_rx_hitqueueend++;
4128 break;
4129 }
4130 /* XXX sync descriptor memory */
4131 /*
4132 * Must provide the virtual address of the current
4133 * descriptor, the physical address, and the virtual
4134 * address of the next descriptor in the h/w chain.
4135 * This allows the HAL to look ahead to see if the
4136 * hardware is done with a descriptor by checking the
4137 * done bit in the following descriptor and the address
4138 * of the current descriptor the DMA engine is working
4139 * on. All this is necessary because of our use of
4140 * a self-linked list to avoid rx overruns.
4141 */
4142 rs = &bf->bf_status.ds_rxstat;
4143 status = ath_hal_rxprocdesc(ah, ds,
4144 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
4145#ifdef ATH_DEBUG
4146 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
4147 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
4148#endif
4149 if (status == HAL_EINPROGRESS)
4150 break;
4151
4152 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
4153 npkts++;
4154
4155 /*
4156 * Calculate the correct 64 bit TSF given
4157 * the TSF64 register value and rs_tstamp.
4158 */
4159 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
4160
4161 /* These aren't specifically errors */
4162#ifdef AH_SUPPORT_AR5416
4163 if (rs->rs_flags & HAL_RX_GI)
4164 sc->sc_stats.ast_rx_halfgi++;
4165 if (rs->rs_flags & HAL_RX_2040)
4166 sc->sc_stats.ast_rx_2040++;
4167 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
4168 sc->sc_stats.ast_rx_pre_crc_err++;
4169 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
4170 sc->sc_stats.ast_rx_post_crc_err++;
4171 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
4172 sc->sc_stats.ast_rx_decrypt_busy_err++;
4173 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
4174 sc->sc_stats.ast_rx_hi_rx_chain++;
4175#endif /* AH_SUPPORT_AR5416 */
4176
4177 if (rs->rs_status != 0) {
4178 if (rs->rs_status & HAL_RXERR_CRC)
4179 sc->sc_stats.ast_rx_crcerr++;
4180 if (rs->rs_status & HAL_RXERR_FIFO)
4181 sc->sc_stats.ast_rx_fifoerr++;
4182 if (rs->rs_status & HAL_RXERR_PHY) {
4183 sc->sc_stats.ast_rx_phyerr++;
4184 /* Process DFS radar events */
4185 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
4186 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
4187 /* Since we're touching the frame data, sync it */
4188 bus_dmamap_sync(sc->sc_dmat,
4189 bf->bf_dmamap,
4190 BUS_DMASYNC_POSTREAD);
4191 /* Now pass it to the radar processing code */
4192 ath_dfs_process_phy_err(sc, mtod(m, char *), rstamp, rs);
4193 }
4194
4195 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */
4196 if (rs->rs_phyerr < 64)
4197 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
4198 goto rx_error; /* NB: don't count in ierrors */
4199 }
4200 if (rs->rs_status & HAL_RXERR_DECRYPT) {
4201 /*
4202 * Decrypt error. If the error occurred
4203 * because there was no hardware key, then
4204 * let the frame through so the upper layers
4205 * can process it. This is necessary for 5210
4206 * parts which have no way to setup a ``clear''
4207 * key cache entry.
4208 *
4209 * XXX do key cache faulting
4210 */
4211 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
4212 goto rx_accept;
4213 sc->sc_stats.ast_rx_badcrypt++;
4214 }
4215 if (rs->rs_status & HAL_RXERR_MIC) {
4216 sc->sc_stats.ast_rx_badmic++;
4217 /*
4218 * Do minimal work required to hand off
4219 * the 802.11 header for notification.
4220 */
4221 /* XXX frag's and qos frames */
4222 len = rs->rs_datalen;
4223 if (len >= sizeof (struct ieee80211_frame)) {
4224 bus_dmamap_sync(sc->sc_dmat,
4225 bf->bf_dmamap,
4226 BUS_DMASYNC_POSTREAD);
4227 ath_handle_micerror(ic,
4228 mtod(m, struct ieee80211_frame *),
4229 sc->sc_splitmic ?
4230 rs->rs_keyix-32 : rs->rs_keyix);
4231 }
4232 }
4233 ifp->if_ierrors++;
4234rx_error:
4235 /*
4236 * Cleanup any pending partial frame.
4237 */
4238 if (sc->sc_rxpending != NULL) {
4239 m_freem(sc->sc_rxpending);
4240 sc->sc_rxpending = NULL;
4241 }
4242 /*
4243 * When a tap is present pass error frames
4244 * that have been requested. By default we
4245 * pass decrypt+mic errors but others may be
4246 * interesting (e.g. crc).
4247 */
4248 if (ieee80211_radiotap_active(ic) &&
4249 (rs->rs_status & sc->sc_monpass)) {
4250 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4251 BUS_DMASYNC_POSTREAD);
4252 /* NB: bpf needs the mbuf length setup */
4253 len = rs->rs_datalen;
4254 m->m_pkthdr.len = m->m_len = len;
4255 bf->bf_m = NULL;
4256 ath_rx_tap(ifp, m, rs, rstamp, nf);
4257 ieee80211_radiotap_rx_all(ic, m);
4258 m_freem(m);
4259 }
4260 /* XXX pass MIC errors up for s/w reclaculation */
4261 goto rx_next;
4262 }
4263rx_accept:
4264 /*
4265 * Sync and unmap the frame. At this point we're
4266 * committed to passing the mbuf somewhere so clear
4267 * bf_m; this means a new mbuf must be allocated
4268 * when the rx descriptor is setup again to receive
4269 * another frame.
4270 */
4271 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4272 BUS_DMASYNC_POSTREAD);
4273 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4274 bf->bf_m = NULL;
4275
4276 len = rs->rs_datalen;
4277 m->m_len = len;
4278
4279 if (rs->rs_more) {
4280 /*
4281 * Frame spans multiple descriptors; save
4282 * it for the next completed descriptor, it
4283 * will be used to construct a jumbogram.
4284 */
4285 if (sc->sc_rxpending != NULL) {
4286 /* NB: max frame size is currently 2 clusters */
4287 sc->sc_stats.ast_rx_toobig++;
4288 m_freem(sc->sc_rxpending);
4289 }
4290 m->m_pkthdr.rcvif = ifp;
4291 m->m_pkthdr.len = len;
4292 sc->sc_rxpending = m;
4293 goto rx_next;
4294 } else if (sc->sc_rxpending != NULL) {
4295 /*
4296 * This is the second part of a jumbogram,
4297 * chain it to the first mbuf, adjust the
4298 * frame length, and clear the rxpending state.
4299 */
4300 sc->sc_rxpending->m_next = m;
4301 sc->sc_rxpending->m_pkthdr.len += len;
4302 m = sc->sc_rxpending;
4303 sc->sc_rxpending = NULL;
4304 } else {
4305 /*
4306 * Normal single-descriptor receive; setup
4307 * the rcvif and packet length.
4308 */
4309 m->m_pkthdr.rcvif = ifp;
4310 m->m_pkthdr.len = len;
4311 }
4312
4313 /*
4314 * Validate rs->rs_antenna.
4315 *
4316 * Some users w/ AR9285 NICs have reported crashes
4317 * here because rs_antenna field is bogusly large.
4318 * Let's enforce the maximum antenna limit of 8
4319 * (and it shouldn't be hard coded, but that's a
4320 * separate problem) and if there's an issue, print
4321 * out an error and adjust rs_antenna to something
4322 * sensible.
4323 *
4324 * This code should be removed once the actual
4325 * root cause of the issue has been identified.
4326 * For example, it may be that the rs_antenna
4327 * field is only valid for the lsat frame of
4328 * an aggregate and it just happens that it is
4329 * "mostly" right. (This is a general statement -
4330 * the majority of the statistics are only valid
4331 * for the last frame in an aggregate.
4332 */
4333 if (rs->rs_antenna > 7) {
4334 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
4335 __func__, rs->rs_antenna);
4336#ifdef ATH_DEBUG
4337 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
4338#endif /* ATH_DEBUG */
4339 rs->rs_antenna = 0; /* XXX better than nothing */
4340 }
4341
4342 ifp->if_ipackets++;
4343 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
4344
4345 /*
4346 * Populate the rx status block. When there are bpf
4347 * listeners we do the additional work to provide
4348 * complete status. Otherwise we fill in only the
4349 * material required by ieee80211_input. Note that
4350 * noise setting is filled in above.
4351 */
4352 if (ieee80211_radiotap_active(ic))
4353 ath_rx_tap(ifp, m, rs, rstamp, nf);
4354
4355 /*
4356 * From this point on we assume the frame is at least
4357 * as large as ieee80211_frame_min; verify that.
4358 */
4359 if (len < IEEE80211_MIN_LEN) {
4360 if (!ieee80211_radiotap_active(ic)) {
4361 DPRINTF(sc, ATH_DEBUG_RECV,
4362 "%s: short packet %d\n", __func__, len);
4363 sc->sc_stats.ast_rx_tooshort++;
4364 } else {
4365 /* NB: in particular this captures ack's */
4366 ieee80211_radiotap_rx_all(ic, m);
4367 }
4368 m_freem(m);
4369 goto rx_next;
4370 }
4371
4372 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
4373 const HAL_RATE_TABLE *rt = sc->sc_currates;
4374 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
4375
4376 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
4377 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
4378 }
4379
4380 m_adj(m, -IEEE80211_CRC_LEN);
4381
4382 /*
4383 * Locate the node for sender, track state, and then
4384 * pass the (referenced) node up to the 802.11 layer
4385 * for its use.
4386 */
4387 ni = ieee80211_find_rxnode_withkey(ic,
4388 mtod(m, const struct ieee80211_frame_min *),
4389 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
4390 IEEE80211_KEYIX_NONE : rs->rs_keyix);
4391 sc->sc_lastrs = rs;
4392
4393#ifdef AH_SUPPORT_AR5416
4394 if (rs->rs_isaggr)
4395 sc->sc_stats.ast_rx_agg++;
4396#endif /* AH_SUPPORT_AR5416 */
4397
4398 if (ni != NULL) {
4399 /*
4400 * Only punt packets for ampdu reorder processing for
4401 * 11n nodes; net80211 enforces that M_AMPDU is only
4402 * set for 11n nodes.
4403 */
4404 if (ni->ni_flags & IEEE80211_NODE_HT)
4405 m->m_flags |= M_AMPDU;
4406
4407 /*
4408 * Sending station is known, dispatch directly.
4409 */
4410 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
4411 ieee80211_free_node(ni);
4412 /*
4413 * Arrange to update the last rx timestamp only for
4414 * frames from our ap when operating in station mode.
4415 * This assumes the rx key is always setup when
4416 * associated.
4417 */
4418 if (ic->ic_opmode == IEEE80211_M_STA &&
4419 rs->rs_keyix != HAL_RXKEYIX_INVALID)
4420 ngood++;
4421 } else {
4422 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
4423 }
4424 /*
4425 * Track rx rssi and do any rx antenna management.
4426 */
4427 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
4428 if (sc->sc_diversity) {
4429 /*
4430 * When using fast diversity, change the default rx
4431 * antenna if diversity chooses the other antenna 3
4432 * times in a row.
4433 */
4434 if (sc->sc_defant != rs->rs_antenna) {
4435 if (++sc->sc_rxotherant >= 3)
4436 ath_setdefantenna(sc, rs->rs_antenna);
4437 } else
4438 sc->sc_rxotherant = 0;
4439 }
4440
4441 /* Newer school diversity - kite specific for now */
4442 /* XXX perhaps migrate the normal diversity code to this? */
4443 if ((ah)->ah_rxAntCombDiversity)
4444 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz);
4445
4446 if (sc->sc_softled) {
4447 /*
4448 * Blink for any data frame. Otherwise do a
4449 * heartbeat-style blink when idle. The latter
4450 * is mainly for station mode where we depend on
4451 * periodic beacon frames to trigger the poll event.
4452 */
4453 if (type == IEEE80211_FC0_TYPE_DATA) {
4454 const HAL_RATE_TABLE *rt = sc->sc_currates;
4455 ath_led_event(sc,
4456 rt->rateCodeToIndex[rs->rs_rate]);
4457 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
4458 ath_led_event(sc, 0);
4459 }
4460rx_next:
4461 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
4462 } while (ath_rxbuf_init(sc, bf) == 0);
4463
4464 /* rx signal state monitoring */
4465 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
4466 if (ngood)
4467 sc->sc_lastrx = tsf;
4468
4469 CTR2(ATH_KTR_INTR, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
4470 /* Queue DFS tasklet if needed */
4471 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
4472 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
4473
4474 /*
4475 * Now that all the RX frames were handled that
4476 * need to be handled, kick the PCU if there's
4477 * been an RXEOL condition.
4478 */
4479 ATH_PCU_LOCK(sc);
4480 if (resched && sc->sc_kickpcu) {
4481 CTR0(ATH_KTR_ERR, "ath_rx_proc: kickpcu");
4482 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
4483 __func__, npkts);
4484
4485 /* XXX rxslink? */
4486 /*
4487 * XXX can we hold the PCU lock here?
4488 * Are there any net80211 buffer calls involved?
4489 */
4490 bf = TAILQ_FIRST(&sc->sc_rxbuf);
4491 ath_hal_putrxbuf(ah, bf->bf_daddr);
4492 ath_hal_rxena(ah); /* enable recv descriptors */
4493 ath_mode_init(sc); /* set filters, etc. */
4494 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
4495
4496 ath_hal_intrset(ah, sc->sc_imask);
4497 sc->sc_kickpcu = 0;
4498 }
4499 ATH_PCU_UNLOCK(sc);
4500
4501 /* XXX check this inside of IF_LOCK? */
4502 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
4503#ifdef IEEE80211_SUPPORT_SUPERG
4504 ieee80211_ff_age_all(ic, 100);
4505#endif
4506 if (!IFQ_IS_EMPTY(&ifp->if_snd))
4507 ath_start(ifp);
4508 }
4509#undef PA2DESC
4510
4511 ATH_PCU_LOCK(sc);
4512 sc->sc_rxproc_cnt--;
4513 ATH_PCU_UNLOCK(sc);
4514}
4515
4516static void
4517ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4518{
4519 txq->axq_qnum = qnum;
4520 txq->axq_ac = 0;
4521 txq->axq_depth = 0;
4522 txq->axq_aggr_depth = 0;
4523 txq->axq_intrcnt = 0;
4524 txq->axq_link = NULL;
4525 txq->axq_softc = sc;
4526 TAILQ_INIT(&txq->axq_q);
4527 TAILQ_INIT(&txq->axq_tidq);
4528 ATH_TXQ_LOCK_INIT(sc, txq);
4529}
4530
4531/*
4532 * Setup a h/w transmit queue.
4533 */
4534static struct ath_txq *
4535ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4536{
4537#define N(a) (sizeof(a)/sizeof(a[0]))
4538 struct ath_hal *ah = sc->sc_ah;
4539 HAL_TXQ_INFO qi;
4540 int qnum;
4541
4542 memset(&qi, 0, sizeof(qi));
4543 qi.tqi_subtype = subtype;
4544 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4545 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4546 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4547 /*
4548 * Enable interrupts only for EOL and DESC conditions.
4549 * We mark tx descriptors to receive a DESC interrupt
4550 * when a tx queue gets deep; otherwise waiting for the
4551 * EOL to reap descriptors. Note that this is done to
4552 * reduce interrupt load and this only defers reaping
4553 * descriptors, never transmitting frames. Aside from
4554 * reducing interrupts this also permits more concurrency.
4555 * The only potential downside is if the tx queue backs
4556 * up in which case the top half of the kernel may backup
4557 * due to a lack of tx descriptors.
4558 */
4559 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
4560 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4561 if (qnum == -1) {
4562 /*
4563 * NB: don't print a message, this happens
4564 * normally on parts with too few tx queues
4565 */
4566 return NULL;
4567 }
4568 if (qnum >= N(sc->sc_txq)) {
4569 device_printf(sc->sc_dev,
4570 "hal qnum %u out of range, max %zu!\n",
4571 qnum, N(sc->sc_txq));
4572 ath_hal_releasetxqueue(ah, qnum);
4573 return NULL;
4574 }
4575 if (!ATH_TXQ_SETUP(sc, qnum)) {
4576 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4577 sc->sc_txqsetup |= 1<<qnum;
4578 }
4579 return &sc->sc_txq[qnum];
4580#undef N
4581}
4582
4583/*
4584 * Setup a hardware data transmit queue for the specified
4585 * access control. The hal may not support all requested
4586 * queues in which case it will return a reference to a
4587 * previously setup queue. We record the mapping from ac's
4588 * to h/w queues for use by ath_tx_start and also track
4589 * the set of h/w queues being used to optimize work in the
4590 * transmit interrupt handler and related routines.
4591 */
4592static int
4593ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4594{
4595#define N(a) (sizeof(a)/sizeof(a[0]))
4596 struct ath_txq *txq;
4597
4598 if (ac >= N(sc->sc_ac2q)) {
4599 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4600 ac, N(sc->sc_ac2q));
4601 return 0;
4602 }
4603 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4604 if (txq != NULL) {
4605 txq->axq_ac = ac;
4606 sc->sc_ac2q[ac] = txq;
4607 return 1;
4608 } else
4609 return 0;
4610#undef N
4611}
4612
4613/*
4614 * Update WME parameters for a transmit queue.
4615 */
4616static int
4617ath_txq_update(struct ath_softc *sc, int ac)
4618{
4619#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4620#define ATH_TXOP_TO_US(v) (v<<5)
4621 struct ifnet *ifp = sc->sc_ifp;
4622 struct ieee80211com *ic = ifp->if_l2com;
4623 struct ath_txq *txq = sc->sc_ac2q[ac];
4624 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4625 struct ath_hal *ah = sc->sc_ah;
4626 HAL_TXQ_INFO qi;
4627
4628 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4629#ifdef IEEE80211_SUPPORT_TDMA
4630 if (sc->sc_tdma) {
4631 /*
4632 * AIFS is zero so there's no pre-transmit wait. The
4633 * burst time defines the slot duration and is configured
4634 * through net80211. The QCU is setup to not do post-xmit
4635 * back off, lockout all lower-priority QCU's, and fire
4636 * off the DMA beacon alert timer which is setup based
4637 * on the slot configuration.
4638 */
4639 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4640 | HAL_TXQ_TXERRINT_ENABLE
4641 | HAL_TXQ_TXURNINT_ENABLE
4642 | HAL_TXQ_TXEOLINT_ENABLE
4643 | HAL_TXQ_DBA_GATED
4644 | HAL_TXQ_BACKOFF_DISABLE
4645 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4646 ;
4647 qi.tqi_aifs = 0;
4648 /* XXX +dbaprep? */
4649 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4650 qi.tqi_burstTime = qi.tqi_readyTime;
4651 } else {
4652#endif
4653 /*
4654 * XXX shouldn't this just use the default flags
4655 * used in the previous queue setup?
4656 */
4657 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4658 | HAL_TXQ_TXERRINT_ENABLE
4659 | HAL_TXQ_TXDESCINT_ENABLE
4660 | HAL_TXQ_TXURNINT_ENABLE
4661 | HAL_TXQ_TXEOLINT_ENABLE
4662 ;
4663 qi.tqi_aifs = wmep->wmep_aifsn;
4664 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4665 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4666 qi.tqi_readyTime = 0;
4667 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4668#ifdef IEEE80211_SUPPORT_TDMA
4669 }
4670#endif
4671
4672 DPRINTF(sc, ATH_DEBUG_RESET,
4673 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4674 __func__, txq->axq_qnum, qi.tqi_qflags,
4675 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4676
4677 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4678 if_printf(ifp, "unable to update hardware queue "
4679 "parameters for %s traffic!\n",
4680 ieee80211_wme_acnames[ac]);
4681 return 0;
4682 } else {
4683 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4684 return 1;
4685 }
4686#undef ATH_TXOP_TO_US
4687#undef ATH_EXPONENT_TO_VALUE
4688}
4689
4690/*
4691 * Callback from the 802.11 layer to update WME parameters.
4692 */
4693static int
4694ath_wme_update(struct ieee80211com *ic)
4695{
4696 struct ath_softc *sc = ic->ic_ifp->if_softc;
4697
4698 return !ath_txq_update(sc, WME_AC_BE) ||
4699 !ath_txq_update(sc, WME_AC_BK) ||
4700 !ath_txq_update(sc, WME_AC_VI) ||
4701 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4702}
4703
4704/*
4705 * Reclaim resources for a setup queue.
4706 */
4707static void
4708ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4709{
4710
4711 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4712 ATH_TXQ_LOCK_DESTROY(txq);
4713 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4714}
4715
4716/*
4717 * Reclaim all tx queue resources.
4718 */
4719static void
4720ath_tx_cleanup(struct ath_softc *sc)
4721{
4722 int i;
4723
4724 ATH_TXBUF_LOCK_DESTROY(sc);
4725 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4726 if (ATH_TXQ_SETUP(sc, i))
4727 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4728}
4729
4730/*
4731 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4732 * using the current rates in sc_rixmap.
4733 */
4734int
4735ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4736{
4737 int rix = sc->sc_rixmap[rate];
4738 /* NB: return lowest rix for invalid rate */
4739 return (rix == 0xff ? 0 : rix);
4740}
4741
4742static void
4743ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
4744 struct ath_buf *bf)
4745{
4746 struct ieee80211_node *ni = bf->bf_node;
4747 struct ifnet *ifp = sc->sc_ifp;
4748 struct ieee80211com *ic = ifp->if_l2com;
4749 int sr, lr, pri;
4750
4751 if (ts->ts_status == 0) {
4752 u_int8_t txant = ts->ts_antenna;
4753 sc->sc_stats.ast_ant_tx[txant]++;
4754 sc->sc_ant_tx[txant]++;
4755 if (ts->ts_finaltsi != 0)
4756 sc->sc_stats.ast_tx_altrate++;
4757 pri = M_WME_GETAC(bf->bf_m);
4758 if (pri >= WME_AC_VO)
4759 ic->ic_wme.wme_hipri_traffic++;
4760 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
4761 ni->ni_inact = ni->ni_inact_reload;
4762 } else {
4763 if (ts->ts_status & HAL_TXERR_XRETRY)
4764 sc->sc_stats.ast_tx_xretries++;
4765 if (ts->ts_status & HAL_TXERR_FIFO)
4766 sc->sc_stats.ast_tx_fifoerr++;
4767 if (ts->ts_status & HAL_TXERR_FILT)
4768 sc->sc_stats.ast_tx_filtered++;
4769 if (ts->ts_status & HAL_TXERR_XTXOP)
4770 sc->sc_stats.ast_tx_xtxop++;
4771 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
4772 sc->sc_stats.ast_tx_timerexpired++;
4773
4774 if (ts->ts_status & HAL_TX_DATA_UNDERRUN)
4775 sc->sc_stats.ast_tx_data_underrun++;
4776 if (ts->ts_status & HAL_TX_DELIM_UNDERRUN)
4777 sc->sc_stats.ast_tx_delim_underrun++;
4778
4779 if (bf->bf_m->m_flags & M_FF)
4780 sc->sc_stats.ast_ff_txerr++;
4781 }
4782 /* XXX when is this valid? */
4783 if (ts->ts_status & HAL_TX_DESC_CFG_ERR)
4784 sc->sc_stats.ast_tx_desccfgerr++;
4785
4786 sr = ts->ts_shortretry;
4787 lr = ts->ts_longretry;
4788 sc->sc_stats.ast_tx_shortretry += sr;
4789 sc->sc_stats.ast_tx_longretry += lr;
4790
4791}
4792
4793/*
4794 * The default completion. If fail is 1, this means
4795 * "please don't retry the frame, and just return -1 status
4796 * to the net80211 stack.
4797 */
4798void
4799ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4800{
4801 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
4802 int st;
4803
4804 if (fail == 1)
4805 st = -1;
4806 else
4807 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
4808 ts->ts_status : HAL_TXERR_XRETRY;
4809
4810 if (bf->bf_state.bfs_dobaw)
4811 device_printf(sc->sc_dev,
4812 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
4813 __func__,
4814 bf,
4815 SEQNO(bf->bf_state.bfs_seqno));
4816 if (bf->bf_next != NULL)
4817 device_printf(sc->sc_dev,
4818 "%s: bf %p: seqno %d: bf_next not NULL!\n",
4819 __func__,
4820 bf,
4821 SEQNO(bf->bf_state.bfs_seqno));
4822
4823 /*
4824 * Do any tx complete callback. Note this must
4825 * be done before releasing the node reference.
4826 * This will free the mbuf, release the net80211
4827 * node and recycle the ath_buf.
4828 */
4829 ath_tx_freebuf(sc, bf, st);
4830}
4831
4832/*
4833 * Update rate control with the given completion status.
4834 */
4835void
4836ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4837 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
4838 int nframes, int nbad)
4839{
4840 struct ath_node *an;
4841
4842 /* Only for unicast frames */
4843 if (ni == NULL)
4844 return;
4845
4846 an = ATH_NODE(ni);
4847
4848 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
4849 ATH_NODE_LOCK(an);
4850 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
4851 ATH_NODE_UNLOCK(an);
4852 }
4853}
4854
4855/*
4856 * Update the busy status of the last frame on the free list.
4857 * When doing TDMA, the busy flag tracks whether the hardware
4858 * currently points to this buffer or not, and thus gated DMA
4859 * may restart by re-reading the last descriptor in this
4860 * buffer.
4861 *
4862 * This should be called in the completion function once one
4863 * of the buffers has been used.
4864 */
4865static void
4866ath_tx_update_busy(struct ath_softc *sc)
4867{
4868 struct ath_buf *last;
4869
4870 /*
4871 * Since the last frame may still be marked
4872 * as ATH_BUF_BUSY, unmark it here before
4873 * finishing the frame processing.
4874 * Since we've completed a frame (aggregate
4875 * or otherwise), the hardware has moved on
4876 * and is no longer referencing the previous
4877 * descriptor.
4878 */
4879 ATH_TXBUF_LOCK_ASSERT(sc);
4880 last = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s);
4881 if (last != NULL)
4882 last->bf_flags &= ~ATH_BUF_BUSY;
4883}
4884
4885
4886/*
4887 * Process completed xmit descriptors from the specified queue.
4888 * Kick the packet scheduler if needed. This can occur from this
4889 * particular task.
4890 */
4891static int
4892ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4893{
4894 struct ath_hal *ah = sc->sc_ah;
4895 struct ath_buf *bf;
4896 struct ath_desc *ds;
4897 struct ath_tx_status *ts;
4898 struct ieee80211_node *ni;
4899 struct ath_node *an;
4900 int nacked;
4901 HAL_STATUS status;
4902
4903 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4904 __func__, txq->axq_qnum,
4905 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4906 txq->axq_link);
4907 nacked = 0;
4908 for (;;) {
4909 ATH_TXQ_LOCK(txq);
4910 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4911 bf = TAILQ_FIRST(&txq->axq_q);
4912 if (bf == NULL) {
4913 ATH_TXQ_UNLOCK(txq);
4914 break;
4915 }
4916 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4917 ts = &bf->bf_status.ds_txstat;
4918 status = ath_hal_txprocdesc(ah, ds, ts);
4919#ifdef ATH_DEBUG
4920 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4921 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4922 status == HAL_OK);
4923 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) {
4924 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4925 status == HAL_OK);
4926 }
4927#endif
4928 if (status == HAL_EINPROGRESS) {
4929 ATH_TXQ_UNLOCK(txq);
4930 break;
4931 }
4932 ATH_TXQ_REMOVE(txq, bf, bf_list);
4933#ifdef IEEE80211_SUPPORT_TDMA
4934 if (txq->axq_depth > 0) {
4935 /*
4936 * More frames follow. Mark the buffer busy
4937 * so it's not re-used while the hardware may
4938 * still re-read the link field in the descriptor.
4939 *
4940 * Use the last buffer in an aggregate as that
4941 * is where the hardware may be - intermediate
4942 * descriptors won't be "busy".
4943 */
4944 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4945 } else
4946#else
4947 if (txq->axq_depth == 0)
4948#endif
4949 txq->axq_link = NULL;
4950 if (bf->bf_state.bfs_aggr)
4951 txq->axq_aggr_depth--;
4952
4953 ni = bf->bf_node;
4954 /*
4955 * If unicast frame was ack'd update RSSI,
4956 * including the last rx time used to
4957 * workaround phantom bmiss interrupts.
4958 */
4959 if (ni != NULL && ts->ts_status == 0 &&
4960 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4961 nacked++;
4962 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4963 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4964 ts->ts_rssi);
4965 }
4966 ATH_TXQ_UNLOCK(txq);
4967
4968 /* If unicast frame, update general statistics */
4969 if (ni != NULL) {
4970 an = ATH_NODE(ni);
4971 /* update statistics */
4972 ath_tx_update_stats(sc, ts, bf);
4973 }
4974
4975 /*
4976 * Call the completion handler.
4977 * The completion handler is responsible for
4978 * calling the rate control code.
4979 *
4980 * Frames with no completion handler get the
4981 * rate control code called here.
4982 */
4983 if (bf->bf_comp == NULL) {
4984 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4985 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
4986 /*
4987 * XXX assume this isn't an aggregate
4988 * frame.
4989 */
4990 ath_tx_update_ratectrl(sc, ni,
4991 bf->bf_state.bfs_rc, ts,
4992 bf->bf_state.bfs_pktlen, 1,
4993 (ts->ts_status == 0 ? 0 : 1));
4994 }
4995 ath_tx_default_comp(sc, bf, 0);
4996 } else
4997 bf->bf_comp(sc, bf, 0);
4998 }
4999#ifdef IEEE80211_SUPPORT_SUPERG
5000 /*
5001 * Flush fast-frame staging queue when traffic slows.
5002 */
5003 if (txq->axq_depth <= 1)
5004 ieee80211_ff_flush(ic, txq->axq_ac);
5005#endif
5006
5007 /* Kick the TXQ scheduler */
5008 if (dosched) {
5009 ATH_TXQ_LOCK(txq);
5010 ath_txq_sched(sc, txq);
5011 ATH_TXQ_UNLOCK(txq);
5012 }
5013
5014 return nacked;
5015}
5016
5017#define TXQACTIVE(t, q) ( (t) & (1 << (q)))
5018
5019/*
5020 * Deferred processing of transmit interrupt; special-cased
5021 * for a single hardware transmit queue (e.g. 5210 and 5211).
5022 */
5023static void
5024ath_tx_proc_q0(void *arg, int npending)
5025{
5026 struct ath_softc *sc = arg;
5027 struct ifnet *ifp = sc->sc_ifp;
5028 uint32_t txqs;
5029
5030 ATH_PCU_LOCK(sc);
5031 sc->sc_txproc_cnt++;
5032 txqs = sc->sc_txq_active;
5033 sc->sc_txq_active &= ~txqs;
5034 ATH_PCU_UNLOCK(sc);
5035
5036 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
5037 /* XXX why is lastrx updated in tx code? */
5038 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5039 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
5040 ath_tx_processq(sc, sc->sc_cabq, 1);
5041 IF_LOCK(&ifp->if_snd);
5042 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5043 IF_UNLOCK(&ifp->if_snd);
5044 sc->sc_wd_timer = 0;
5045
5046 if (sc->sc_softled)
5047 ath_led_event(sc, sc->sc_txrix);
5048
5049 ATH_PCU_LOCK(sc);
5050 sc->sc_txproc_cnt--;
5051 ATH_PCU_UNLOCK(sc);
5052
5053 ath_start(ifp);
5054}
5055
5056/*
5057 * Deferred processing of transmit interrupt; special-cased
5058 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
5059 */
5060static void
5061ath_tx_proc_q0123(void *arg, int npending)
5062{
5063 struct ath_softc *sc = arg;
5064 struct ifnet *ifp = sc->sc_ifp;
5065 int nacked;
5066 uint32_t txqs;
5067
5068 ATH_PCU_LOCK(sc);
5069 sc->sc_txproc_cnt++;
5070 txqs = sc->sc_txq_active;
5071 sc->sc_txq_active &= ~txqs;
5072 ATH_PCU_UNLOCK(sc);
5073
5074 /*
5075 * Process each active queue.
5076 */
5077 nacked = 0;
5078 if (TXQACTIVE(txqs, 0))
5079 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
5080 if (TXQACTIVE(txqs, 1))
5081 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
5082 if (TXQACTIVE(txqs, 2))
5083 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
5084 if (TXQACTIVE(txqs, 3))
5085 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
5086 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
5087 ath_tx_processq(sc, sc->sc_cabq, 1);
5088 if (nacked)
5089 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5090
5091 IF_LOCK(&ifp->if_snd);
5092 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5093 IF_UNLOCK(&ifp->if_snd);
5094 sc->sc_wd_timer = 0;
5095
5096 if (sc->sc_softled)
5097 ath_led_event(sc, sc->sc_txrix);
5098
5099 ATH_PCU_LOCK(sc);
5100 sc->sc_txproc_cnt--;
5101 ATH_PCU_UNLOCK(sc);
5102
5103 ath_start(ifp);
5104}
5105
5106/*
5107 * Deferred processing of transmit interrupt.
5108 */
5109static void
5110ath_tx_proc(void *arg, int npending)
5111{
5112 struct ath_softc *sc = arg;
5113 struct ifnet *ifp = sc->sc_ifp;
5114 int i, nacked;
5115 uint32_t txqs;
5116
5117 ATH_PCU_LOCK(sc);
5118 sc->sc_txproc_cnt++;
5119 txqs = sc->sc_txq_active;
5120 sc->sc_txq_active &= ~txqs;
5121 ATH_PCU_UNLOCK(sc);
5122
5123 /*
5124 * Process each active queue.
5125 */
5126 nacked = 0;
5127 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5128 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
5129 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
5130 if (nacked)
5131 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5132
5133 /* XXX check this inside of IF_LOCK? */
5134 IF_LOCK(&ifp->if_snd);
5135 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5136 IF_UNLOCK(&ifp->if_snd);
5137 sc->sc_wd_timer = 0;
5138
5139 if (sc->sc_softled)
5140 ath_led_event(sc, sc->sc_txrix);
5141
5142 ATH_PCU_LOCK(sc);
5143 sc->sc_txproc_cnt--;
5144 ATH_PCU_UNLOCK(sc);
5145
5146 ath_start(ifp);
5147}
5148#undef TXQACTIVE
5149
5150/*
5151 * Deferred processing of TXQ rescheduling.
5152 */
5153static void
5154ath_txq_sched_tasklet(void *arg, int npending)
5155{
5156 struct ath_softc *sc = arg;
5157 int i;
5158
5159 /* XXX is skipping ok? */
5160 ATH_PCU_LOCK(sc);
5161#if 0
5162 if (sc->sc_inreset_cnt > 0) {
5163 device_printf(sc->sc_dev,
5164 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
5165 ATH_PCU_UNLOCK(sc);
5166 return;
5167 }
5168#endif
5169 sc->sc_txproc_cnt++;
5170 ATH_PCU_UNLOCK(sc);
5171
5172 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5173 if (ATH_TXQ_SETUP(sc, i)) {
5174 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5175 ath_txq_sched(sc, &sc->sc_txq[i]);
5176 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5177 }
5178 }
5179
5180 ATH_PCU_LOCK(sc);
5181 sc->sc_txproc_cnt--;
5182 ATH_PCU_UNLOCK(sc);
5183}
5184
5185/*
5186 * Return a buffer to the pool and update the 'busy' flag on the
5187 * previous 'tail' entry.
5188 *
5189 * This _must_ only be called when the buffer is involved in a completed
5190 * TX. The logic is that if it was part of an active TX, the previous
5191 * buffer on the list is now not involved in a halted TX DMA queue, waiting
5192 * for restart (eg for TDMA.)
5193 *
5194 * The caller must free the mbuf and recycle the node reference.
5195 */
5196void
5197ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
5198{
5199 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5200 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTWRITE);
5201
5202 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
5203 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
5204
5205 ATH_TXBUF_LOCK(sc);
5206 ath_tx_update_busy(sc);
5207 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5208 ATH_TXBUF_UNLOCK(sc);
5209}
5210
5211/*
5212 * This is currently used by ath_tx_draintxq() and
5213 * ath_tx_tid_free_pkts().
5214 *
5215 * It recycles a single ath_buf.
5216 */
5217void
5218ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
5219{
5220 struct ieee80211_node *ni = bf->bf_node;
5221 struct mbuf *m0 = bf->bf_m;
5222
5223 bf->bf_node = NULL;
5224 bf->bf_m = NULL;
5225
5226 /* Free the buffer, it's not needed any longer */
5227 ath_freebuf(sc, bf);
5228
5229 if (ni != NULL) {
5230 /*
5231 * Do any callback and reclaim the node reference.
5232 */
5233 if (m0->m_flags & M_TXCB)
5234 ieee80211_process_callback(ni, m0, status);
5235 ieee80211_free_node(ni);
5236 }
5237 m_freem(m0);
5238
5239 /*
5240 * XXX the buffer used to be freed -after-, but the DMA map was
5241 * freed where ath_freebuf() now is. I've no idea what this
5242 * will do.
5243 */
5244}
5245
5246void
5247ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5248{
5249#ifdef ATH_DEBUG
5250 struct ath_hal *ah = sc->sc_ah;
5251#endif
5252 struct ath_buf *bf;
5253 u_int ix;
5254
5255 /*
5256 * NB: this assumes output has been stopped and
5257 * we do not need to block ath_tx_proc
5258 */
5259 ATH_TXBUF_LOCK(sc);
5260 bf = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s);
5261 if (bf != NULL)
5262 bf->bf_flags &= ~ATH_BUF_BUSY;
5263 ATH_TXBUF_UNLOCK(sc);
5264
5265 for (ix = 0;; ix++) {
5266 ATH_TXQ_LOCK(txq);
5267 bf = TAILQ_FIRST(&txq->axq_q);
5268 if (bf == NULL) {
5269 txq->axq_link = NULL;
5270 ATH_TXQ_UNLOCK(txq);
5271 break;
5272 }
5273 ATH_TXQ_REMOVE(txq, bf, bf_list);
5274 if (bf->bf_state.bfs_aggr)
5275 txq->axq_aggr_depth--;
5276#ifdef ATH_DEBUG
5277 if (sc->sc_debug & ATH_DEBUG_RESET) {
5278 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5279
5280 ath_printtxbuf(sc, bf, txq->axq_qnum, ix,
5281 ath_hal_txprocdesc(ah, bf->bf_lastds,
5282 &bf->bf_status.ds_txstat) == HAL_OK);
5283 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5284 bf->bf_m->m_len, 0, -1);
5285 }
5286#endif /* ATH_DEBUG */
5287 /*
5288 * Since we're now doing magic in the completion
5289 * functions, we -must- call it for aggregation
5290 * destinations or BAW tracking will get upset.
5291 */
5292 /*
5293 * Clear ATH_BUF_BUSY; the completion handler
5294 * will free the buffer.
5295 */
5296 ATH_TXQ_UNLOCK(txq);
5297 bf->bf_flags &= ~ATH_BUF_BUSY;
5298 if (bf->bf_comp)
5299 bf->bf_comp(sc, bf, 1);
5300 else
5301 ath_tx_default_comp(sc, bf, 1);
5302 }
5303
5304 /*
5305 * Drain software queued frames which are on
5306 * active TIDs.
5307 */
5308 ath_tx_txq_drain(sc, txq);
5309}
5310
5311static void
5312ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5313{
5314 struct ath_hal *ah = sc->sc_ah;
5315
5316 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5317 __func__, txq->axq_qnum,
5318 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5319 txq->axq_link);
5320 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5321}
5322
5323static int
5324ath_stoptxdma(struct ath_softc *sc)
5325{
5326 struct ath_hal *ah = sc->sc_ah;
5327 int i;
5328
5329 /* XXX return value */
5330 if (sc->sc_invalid)
5331 return 0;
5332
5333 if (!sc->sc_invalid) {
5334 /* don't touch the hardware if marked invalid */
5335 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5336 __func__, sc->sc_bhalq,
5337 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5338 NULL);
5339 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5340 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5341 if (ATH_TXQ_SETUP(sc, i))
5342 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5343 }
5344
5345 return 1;
5346}
5347
5348/*
5349 * Drain the transmit queues and reclaim resources.
5350 */
5351static void
5352ath_draintxq(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
5353{
5354#ifdef ATH_DEBUG
5355 struct ath_hal *ah = sc->sc_ah;
5356#endif
5357 struct ifnet *ifp = sc->sc_ifp;
5358 int i;
5359
5360 (void) ath_stoptxdma(sc);
5361
5362 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5363 /*
5364 * XXX TODO: should we just handle the completed TX frames
5365 * here, whether or not the reset is a full one or not?
5366 */
5367 if (ATH_TXQ_SETUP(sc, i)) {
5368 if (reset_type == ATH_RESET_NOLOSS)
5369 ath_tx_processq(sc, &sc->sc_txq[i], 0);
5370 else
5371 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5372 }
5373 }
5374#ifdef ATH_DEBUG
5375 if (sc->sc_debug & ATH_DEBUG_RESET) {
5376 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
5377 if (bf != NULL && bf->bf_m != NULL) {
5378 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5379 ath_hal_txprocdesc(ah, bf->bf_lastds,
5380 &bf->bf_status.ds_txstat) == HAL_OK);
5381 ieee80211_dump_pkt(ifp->if_l2com,
5382 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5383 0, -1);
5384 }
5385 }
5386#endif /* ATH_DEBUG */
5387 IF_LOCK(&ifp->if_snd);
5388 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5389 IF_UNLOCK(&ifp->if_snd);
5390 sc->sc_wd_timer = 0;
5391}
5392
5393/*
5394 * Disable the receive h/w in preparation for a reset.
5395 */
5396static void
5397ath_stoprecv(struct ath_softc *sc, int dodelay)
5398{
5399#define PA2DESC(_sc, _pa) \
5400 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
5401 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
5402 struct ath_hal *ah = sc->sc_ah;
5403
5404 ath_hal_stoppcurecv(ah); /* disable PCU */
5405 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
5406 ath_hal_stopdmarecv(ah); /* disable DMA engine */
5407 if (dodelay)
5408 DELAY(3000); /* 3ms is long enough for 1 frame */
5409#ifdef ATH_DEBUG
5410 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
5411 struct ath_buf *bf;
5412 u_int ix;
5413
5414 device_printf(sc->sc_dev,
5415 "%s: rx queue %p, link %p\n",
5416 __func__,
5417 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah),
5418 sc->sc_rxlink);
5419 ix = 0;
5420 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5421 struct ath_desc *ds = bf->bf_desc;
5422 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5423 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
5424 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
5425 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
5426 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
5427 ix++;
5428 }
5429 }
5430#endif
5431 if (sc->sc_rxpending != NULL) {
5432 m_freem(sc->sc_rxpending);
5433 sc->sc_rxpending = NULL;
5434 }
5435 sc->sc_rxlink = NULL; /* just in case */
5436#undef PA2DESC
5437}
5438
5439/*
5440 * Enable the receive h/w following a reset.
5441 */
5442static int
5443ath_startrecv(struct ath_softc *sc)
5444{
5445 struct ath_hal *ah = sc->sc_ah;
5446 struct ath_buf *bf;
5447
5448 sc->sc_rxlink = NULL;
5449 sc->sc_rxpending = NULL;
5450 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5451 int error = ath_rxbuf_init(sc, bf);
5452 if (error != 0) {
5453 DPRINTF(sc, ATH_DEBUG_RECV,
5454 "%s: ath_rxbuf_init failed %d\n",
5455 __func__, error);
5456 return error;
5457 }
5458 }
5459
5460 bf = TAILQ_FIRST(&sc->sc_rxbuf);
5461 ath_hal_putrxbuf(ah, bf->bf_daddr);
5462 ath_hal_rxena(ah); /* enable recv descriptors */
5463 ath_mode_init(sc); /* set filters, etc. */
5464 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
5465 return 0;
5466}
5467
5468/*
5469 * Update internal state after a channel change.
5470 */
5471static void
5472ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5473{
5474 enum ieee80211_phymode mode;
5475
5476 /*
5477 * Change channels and update the h/w rate map
5478 * if we're switching; e.g. 11a to 11b/g.
5479 */
5480 mode = ieee80211_chan2mode(chan);
5481 if (mode != sc->sc_curmode)
5482 ath_setcurmode(sc, mode);
5483 sc->sc_curchan = chan;
5484}
5485
5486/*
5487 * Set/change channels. If the channel is really being changed,
5488 * it's done by resetting the chip. To accomplish this we must
5489 * first cleanup any pending DMA, then restart stuff after a la
5490 * ath_init.
5491 */
5492static int
5493ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5494{
5495 struct ifnet *ifp = sc->sc_ifp;
5496 struct ieee80211com *ic = ifp->if_l2com;
5497 struct ath_hal *ah = sc->sc_ah;
5498 int ret = 0;
5499
5500 /* Treat this as an interface reset */
5501 ATH_PCU_UNLOCK_ASSERT(sc);
5502 ATH_UNLOCK_ASSERT(sc);
5503
5504 /* (Try to) stop TX/RX from occuring */
5505 taskqueue_block(sc->sc_tq);
5506
5507 ATH_PCU_LOCK(sc);
5508 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */
5509 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */
5510 if (ath_reset_grablock(sc, 1) == 0) {
5511 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
5512 __func__);
5513 }
5514 ATH_PCU_UNLOCK(sc);
5515
5516 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5517 __func__, ieee80211_chan2ieee(ic, chan),
5518 chan->ic_freq, chan->ic_flags);
5519 if (chan != sc->sc_curchan) {
5520 HAL_STATUS status;
5521 /*
5522 * To switch channels clear any pending DMA operations;
5523 * wait long enough for the RX fifo to drain, reset the
5524 * hardware at the new frequency, and then re-enable
5525 * the relevant bits of the h/w.
5526 */
5527#if 0
5528 ath_hal_intrset(ah, 0); /* disable interrupts */
5529#endif
5530 ath_stoprecv(sc, 1); /* turn off frame recv */
5531 /*
5532 * First, handle completed TX/RX frames.
5533 */
5534 ath_rx_proc(sc, 0);
5535 ath_draintxq(sc, ATH_RESET_NOLOSS);
5536 /*
5537 * Next, flush the non-scheduled frames.
5538 */
5539 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5540
5541 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5542 if_printf(ifp, "%s: unable to reset "
5543 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5544 __func__, ieee80211_chan2ieee(ic, chan),
5545 chan->ic_freq, chan->ic_flags, status);
5546 ret = EIO;
5547 goto finish;
5548 }
5549 sc->sc_diversity = ath_hal_getdiversity(ah);
5550
5551 /* Let DFS at it in case it's a DFS channel */
5552 ath_dfs_radar_enable(sc, chan);
5553
5554 /*
5555 * Re-enable rx framework.
5556 */
5557 if (ath_startrecv(sc) != 0) {
5558 if_printf(ifp, "%s: unable to restart recv logic\n",
5559 __func__);
5560 ret = EIO;
5561 goto finish;
5562 }
5563
5564 /*
5565 * Change channels and update the h/w rate map
5566 * if we're switching; e.g. 11a to 11b/g.
5567 */
5568 ath_chan_change(sc, chan);
5569
5570 /*
5571 * Reset clears the beacon timers; reset them
5572 * here if needed.
5573 */
5574 if (sc->sc_beacons) { /* restart beacons */
5575#ifdef IEEE80211_SUPPORT_TDMA
5576 if (sc->sc_tdma)
5577 ath_tdma_config(sc, NULL);
5578 else
5579#endif
5580 ath_beacon_config(sc, NULL);
5581 }
5582
5583 /*
5584 * Re-enable interrupts.
5585 */
5586#if 0
5587 ath_hal_intrset(ah, sc->sc_imask);
5588#endif
5589 }
5590
5591finish:
5592 ATH_PCU_LOCK(sc);
5593 sc->sc_inreset_cnt--;
5594 /* XXX only do this if sc_inreset_cnt == 0? */
5595 ath_hal_intrset(ah, sc->sc_imask);
5596 ATH_PCU_UNLOCK(sc);
5597
5598 IF_LOCK(&ifp->if_snd);
5599 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5600 IF_UNLOCK(&ifp->if_snd);
5601 ath_txrx_start(sc);
5602 /* XXX ath_start? */
5603
5604 return ret;
5605}
5606
5607/*
5608 * Periodically recalibrate the PHY to account
5609 * for temperature/environment changes.
5610 */
5611static void
5612ath_calibrate(void *arg)
5613{
5614 struct ath_softc *sc = arg;
5615 struct ath_hal *ah = sc->sc_ah;
5616 struct ifnet *ifp = sc->sc_ifp;
5617 struct ieee80211com *ic = ifp->if_l2com;
5618 HAL_BOOL longCal, isCalDone;
5619 HAL_BOOL aniCal, shortCal = AH_FALSE;
5620 int nextcal;
5621
5622 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5623 goto restart;
5624 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5625 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5626 if (sc->sc_doresetcal)
5627 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5628
5629 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5630 if (aniCal) {
5631 sc->sc_stats.ast_ani_cal++;
5632 sc->sc_lastani = ticks;
5633 ath_hal_ani_poll(ah, sc->sc_curchan);
5634 }
5635
5636 if (longCal) {
5637 sc->sc_stats.ast_per_cal++;
5638 sc->sc_lastlongcal = ticks;
5639 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5640 /*
5641 * Rfgain is out of bounds, reset the chip
5642 * to load new gain values.
5643 */
5644 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5645 "%s: rfgain change\n", __func__);
5646 sc->sc_stats.ast_per_rfgain++;
5647 sc->sc_resetcal = 0;
5648 sc->sc_doresetcal = AH_TRUE;
5649 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5650 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5651 return;
5652 }
5653 /*
5654 * If this long cal is after an idle period, then
5655 * reset the data collection state so we start fresh.
5656 */
5657 if (sc->sc_resetcal) {
5658 (void) ath_hal_calreset(ah, sc->sc_curchan);
5659 sc->sc_lastcalreset = ticks;
5660 sc->sc_lastshortcal = ticks;
5661 sc->sc_resetcal = 0;
5662 sc->sc_doresetcal = AH_TRUE;
5663 }
5664 }
5665
5666 /* Only call if we're doing a short/long cal, not for ANI calibration */
5667 if (shortCal || longCal) {
5668 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5669 if (longCal) {
5670 /*
5671 * Calibrate noise floor data again in case of change.
5672 */
5673 ath_hal_process_noisefloor(ah);
5674 }
5675 } else {
5676 DPRINTF(sc, ATH_DEBUG_ANY,
5677 "%s: calibration of channel %u failed\n",
5678 __func__, sc->sc_curchan->ic_freq);
5679 sc->sc_stats.ast_per_calfail++;
5680 }
5681 if (shortCal)
5682 sc->sc_lastshortcal = ticks;
5683 }
5684 if (!isCalDone) {
5685restart:
5686 /*
5687 * Use a shorter interval to potentially collect multiple
5688 * data samples required to complete calibration. Once
5689 * we're told the work is done we drop back to a longer
5690 * interval between requests. We're more aggressive doing
5691 * work when operating as an AP to improve operation right
5692 * after startup.
5693 */
5694 sc->sc_lastshortcal = ticks;
5695 nextcal = ath_shortcalinterval*hz/1000;
5696 if (sc->sc_opmode != HAL_M_HOSTAP)
5697 nextcal *= 10;
5698 sc->sc_doresetcal = AH_TRUE;
5699 } else {
5700 /* nextcal should be the shortest time for next event */
5701 nextcal = ath_longcalinterval*hz;
5702 if (sc->sc_lastcalreset == 0)
5703 sc->sc_lastcalreset = sc->sc_lastlongcal;
5704 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5705 sc->sc_resetcal = 1; /* setup reset next trip */
5706 sc->sc_doresetcal = AH_FALSE;
5707 }
5708 /* ANI calibration may occur more often than short/long/resetcal */
5709 if (ath_anicalinterval > 0)
5710 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5711
5712 if (nextcal != 0) {
5713 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5714 __func__, nextcal, isCalDone ? "" : "!");
5715 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5716 } else {
5717 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5718 __func__);
5719 /* NB: don't rearm timer */
5720 }
5721}
5722
5723static void
5724ath_scan_start(struct ieee80211com *ic)
5725{
5726 struct ifnet *ifp = ic->ic_ifp;
5727 struct ath_softc *sc = ifp->if_softc;
5728 struct ath_hal *ah = sc->sc_ah;
5729 u_int32_t rfilt;
5730
5731 /* XXX calibration timer? */
5732
5733 ATH_LOCK(sc);
5734 sc->sc_scanning = 1;
5735 sc->sc_syncbeacon = 0;
5736 rfilt = ath_calcrxfilter(sc);
5737 ATH_UNLOCK(sc);
5738
5739 ATH_PCU_LOCK(sc);
5740 ath_hal_setrxfilter(ah, rfilt);
5741 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5742 ATH_PCU_UNLOCK(sc);
5743
5744 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5745 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5746}
5747
5748static void
5749ath_scan_end(struct ieee80211com *ic)
5750{
5751 struct ifnet *ifp = ic->ic_ifp;
5752 struct ath_softc *sc = ifp->if_softc;
5753 struct ath_hal *ah = sc->sc_ah;
5754 u_int32_t rfilt;
5755
5756 ATH_LOCK(sc);
5757 sc->sc_scanning = 0;
5758 rfilt = ath_calcrxfilter(sc);
5759 ATH_UNLOCK(sc);
5760
5761 ATH_PCU_LOCK(sc);
5762 ath_hal_setrxfilter(ah, rfilt);
5763 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5764
5765 ath_hal_process_noisefloor(ah);
5766 ATH_PCU_UNLOCK(sc);
5767
5768 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5769 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5770 sc->sc_curaid);
5771}
5772
5773#ifdef ATH_ENABLE_11N
5774/*
5775 * For now, just do a channel change.
5776 *
5777 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5778 * control state and resetting the hardware without dropping frames out
5779 * of the queue.
5780 *
5781 * The unfortunate trouble here is making absolutely sure that the
5782 * channel width change has propagated enough so the hardware
5783 * absolutely isn't handed bogus frames for it's current operating
5784 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5785 * does occur in parallel, we need to make certain we've blocked
5786 * any further ongoing TX (and RX, that can cause raw TX)
5787 * before we do this.
5788 */
5789static void
5790ath_update_chw(struct ieee80211com *ic)
5791{
5792 struct ifnet *ifp = ic->ic_ifp;
5793 struct ath_softc *sc = ifp->if_softc;
5794
5795 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5796 ath_set_channel(ic);
5797}
5798#endif /* ATH_ENABLE_11N */
5799
5800static void
5801ath_set_channel(struct ieee80211com *ic)
5802{
5803 struct ifnet *ifp = ic->ic_ifp;
5804 struct ath_softc *sc = ifp->if_softc;
5805
5806 (void) ath_chan_set(sc, ic->ic_curchan);
5807 /*
5808 * If we are returning to our bss channel then mark state
5809 * so the next recv'd beacon's tsf will be used to sync the
5810 * beacon timers. Note that since we only hear beacons in
5811 * sta/ibss mode this has no effect in other operating modes.
5812 */
5813 ATH_LOCK(sc);
5814 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5815 sc->sc_syncbeacon = 1;
5816 ATH_UNLOCK(sc);
5817}
5818
5819/*
5820 * Walk the vap list and check if there any vap's in RUN state.
5821 */
5822static int
5823ath_isanyrunningvaps(struct ieee80211vap *this)
5824{
5825 struct ieee80211com *ic = this->iv_ic;
5826 struct ieee80211vap *vap;
5827
5828 IEEE80211_LOCK_ASSERT(ic);
5829
5830 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5831 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5832 return 1;
5833 }
5834 return 0;
5835}
5836
5837static int
5838ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5839{
5840 struct ieee80211com *ic = vap->iv_ic;
5841 struct ath_softc *sc = ic->ic_ifp->if_softc;
5842 struct ath_vap *avp = ATH_VAP(vap);
5843 struct ath_hal *ah = sc->sc_ah;
5844 struct ieee80211_node *ni = NULL;
5845 int i, error, stamode;
5846 u_int32_t rfilt;
5847 int csa_run_transition = 0;
5848 static const HAL_LED_STATE leds[] = {
5849 HAL_LED_INIT, /* IEEE80211_S_INIT */
5850 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5851 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5852 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5853 HAL_LED_RUN, /* IEEE80211_S_CAC */
5854 HAL_LED_RUN, /* IEEE80211_S_RUN */
5855 HAL_LED_RUN, /* IEEE80211_S_CSA */
5856 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5857 };
5858
5859 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5860 ieee80211_state_name[vap->iv_state],
5861 ieee80211_state_name[nstate]);
5862
5863 /*
5864 * net80211 _should_ have the comlock asserted at this point.
5865 * There are some comments around the calls to vap->iv_newstate
5866 * which indicate that it (newstate) may end up dropping the
5867 * lock. This and the subsequent lock assert check after newstate
5868 * are an attempt to catch these and figure out how/why.
5869 */
5870 IEEE80211_LOCK_ASSERT(ic);
5871
5872 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5873 csa_run_transition = 1;
5874
5875 callout_drain(&sc->sc_cal_ch);
5876 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5877
5878 if (nstate == IEEE80211_S_SCAN) {
5879 /*
5880 * Scanning: turn off beacon miss and don't beacon.
5881 * Mark beacon state so when we reach RUN state we'll
5882 * [re]setup beacons. Unblock the task q thread so
5883 * deferred interrupt processing is done.
5884 */
5885 ath_hal_intrset(ah,
5886 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5887 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5888 sc->sc_beacons = 0;
5889 taskqueue_unblock(sc->sc_tq);
5890 }
5891
5892 ni = ieee80211_ref_node(vap->iv_bss);
5893 rfilt = ath_calcrxfilter(sc);
5894 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5895 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5896 vap->iv_opmode == IEEE80211_M_IBSS);
5897 if (stamode && nstate == IEEE80211_S_RUN) {
5898 sc->sc_curaid = ni->ni_associd;
5899 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5900 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5901 }
5902 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5903 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5904 ath_hal_setrxfilter(ah, rfilt);
5905
5906 /* XXX is this to restore keycache on resume? */
5907 if (vap->iv_opmode != IEEE80211_M_STA &&
5908 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5909 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5910 if (ath_hal_keyisvalid(ah, i))
5911 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5912 }
5913
5914 /*
5915 * Invoke the parent method to do net80211 work.
5916 */
5917 error = avp->av_newstate(vap, nstate, arg);
5918 if (error != 0)
5919 goto bad;
5920
5921 /*
5922 * See above: ensure av_newstate() doesn't drop the lock
5923 * on us.
5924 */
5925 IEEE80211_LOCK_ASSERT(ic);
5926
5927 if (nstate == IEEE80211_S_RUN) {
5928 /* NB: collect bss node again, it may have changed */
5929 ieee80211_free_node(ni);
5930 ni = ieee80211_ref_node(vap->iv_bss);
5931
5932 DPRINTF(sc, ATH_DEBUG_STATE,
5933 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5934 "capinfo 0x%04x chan %d\n", __func__,
5935 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5936 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5937
5938 switch (vap->iv_opmode) {
5939#ifdef IEEE80211_SUPPORT_TDMA
5940 case IEEE80211_M_AHDEMO:
5941 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5942 break;
5943 /* fall thru... */
5944#endif
5945 case IEEE80211_M_HOSTAP:
5946 case IEEE80211_M_IBSS:
5947 case IEEE80211_M_MBSS:
5948 /*
5949 * Allocate and setup the beacon frame.
5950 *
5951 * Stop any previous beacon DMA. This may be
5952 * necessary, for example, when an ibss merge
5953 * causes reconfiguration; there will be a state
5954 * transition from RUN->RUN that means we may
5955 * be called with beacon transmission active.
5956 */
5957 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5958
5959 error = ath_beacon_alloc(sc, ni);
5960 if (error != 0)
5961 goto bad;
5962 /*
5963 * If joining an adhoc network defer beacon timer
5964 * configuration to the next beacon frame so we
5965 * have a current TSF to use. Otherwise we're
5966 * starting an ibss/bss so there's no need to delay;
5967 * if this is the first vap moving to RUN state, then
5968 * beacon state needs to be [re]configured.
5969 */
5970 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5971 ni->ni_tstamp.tsf != 0) {
5972 sc->sc_syncbeacon = 1;
5973 } else if (!sc->sc_beacons) {
5974#ifdef IEEE80211_SUPPORT_TDMA
5975 if (vap->iv_caps & IEEE80211_C_TDMA)
5976 ath_tdma_config(sc, vap);
5977 else
5978#endif
5979 ath_beacon_config(sc, vap);
5980 sc->sc_beacons = 1;
5981 }
5982 break;
5983 case IEEE80211_M_STA:
5984 /*
5985 * Defer beacon timer configuration to the next
5986 * beacon frame so we have a current TSF to use
5987 * (any TSF collected when scanning is likely old).
5988 * However if it's due to a CSA -> RUN transition,
5989 * force a beacon update so we pick up a lack of
5990 * beacons from an AP in CAC and thus force a
5991 * scan.
5992 */
5993 sc->sc_syncbeacon = 1;
5994 if (csa_run_transition)
5995 ath_beacon_config(sc, vap);
5996 break;
5997 case IEEE80211_M_MONITOR:
5998 /*
5999 * Monitor mode vaps have only INIT->RUN and RUN->RUN
6000 * transitions so we must re-enable interrupts here to
6001 * handle the case of a single monitor mode vap.
6002 */
6003 ath_hal_intrset(ah, sc->sc_imask);
6004 break;
6005 case IEEE80211_M_WDS:
6006 break;
6007 default:
6008 break;
6009 }
6010 /*
6011 * Let the hal process statistics collected during a
6012 * scan so it can provide calibrated noise floor data.
6013 */
6014 ath_hal_process_noisefloor(ah);
6015 /*
6016 * Reset rssi stats; maybe not the best place...
6017 */
6018 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
6019 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
6020 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
6021 /*
6022 * Finally, start any timers and the task q thread
6023 * (in case we didn't go through SCAN state).
6024 */
6025 if (ath_longcalinterval != 0) {
6026 /* start periodic recalibration timer */
6027 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6028 } else {
6029 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6030 "%s: calibration disabled\n", __func__);
6031 }
6032 taskqueue_unblock(sc->sc_tq);
6033 } else if (nstate == IEEE80211_S_INIT) {
6034 /*
6035 * If there are no vaps left in RUN state then
6036 * shutdown host/driver operation:
6037 * o disable interrupts
6038 * o disable the task queue thread
6039 * o mark beacon processing as stopped
6040 */
6041 if (!ath_isanyrunningvaps(vap)) {
6042 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6043 /* disable interrupts */
6044 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
6045 taskqueue_block(sc->sc_tq);
6046 sc->sc_beacons = 0;
6047 }
6048#ifdef IEEE80211_SUPPORT_TDMA
6049 ath_hal_setcca(ah, AH_TRUE);
6050#endif
6051 }
6052bad:
6053 ieee80211_free_node(ni);
6054 return error;
6055}
6056
6057/*
6058 * Allocate a key cache slot to the station so we can
6059 * setup a mapping from key index to node. The key cache
6060 * slot is needed for managing antenna state and for
6061 * compression when stations do not use crypto. We do
6062 * it uniliaterally here; if crypto is employed this slot
6063 * will be reassigned.
6064 */
6065static void
6066ath_setup_stationkey(struct ieee80211_node *ni)
6067{
6068 struct ieee80211vap *vap = ni->ni_vap;
6069 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6070 ieee80211_keyix keyix, rxkeyix;
6071
6072 /* XXX should take a locked ref to vap->iv_bss */
6073 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
6074 /*
6075 * Key cache is full; we'll fall back to doing
6076 * the more expensive lookup in software. Note
6077 * this also means no h/w compression.
6078 */
6079 /* XXX msg+statistic */
6080 } else {
6081 /* XXX locking? */
6082 ni->ni_ucastkey.wk_keyix = keyix;
6083 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
6084 /* NB: must mark device key to get called back on delete */
6085 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
6086 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
6087 /* NB: this will create a pass-thru key entry */
6088 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
6089 }
6090}
6091
6092/*
6093 * Setup driver-specific state for a newly associated node.
6094 * Note that we're called also on a re-associate, the isnew
6095 * param tells us if this is the first time or not.
6096 */
6097static void
6098ath_newassoc(struct ieee80211_node *ni, int isnew)
6099{
6100 struct ath_node *an = ATH_NODE(ni);
6101 struct ieee80211vap *vap = ni->ni_vap;
6102 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6103 const struct ieee80211_txparam *tp = ni->ni_txparms;
6104
6105 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
6106 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
6107
6108 ath_rate_newassoc(sc, an, isnew);
6109 if (isnew &&
6110 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
6111 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
6112 ath_setup_stationkey(ni);
6113}
6114
6115static int
6116ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
6117 int nchans, struct ieee80211_channel chans[])
6118{
6119 struct ath_softc *sc = ic->ic_ifp->if_softc;
6120 struct ath_hal *ah = sc->sc_ah;
6121 HAL_STATUS status;
6122
6123 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6124 "%s: rd %u cc %u location %c%s\n",
6125 __func__, reg->regdomain, reg->country, reg->location,
6126 reg->ecm ? " ecm" : "");
6127
6128 status = ath_hal_set_channels(ah, chans, nchans,
6129 reg->country, reg->regdomain);
6130 if (status != HAL_OK) {
6131 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
6132 __func__, status);
6133 return EINVAL; /* XXX */
6134 }
6135
6136 return 0;
6137}
6138
6139static void
6140ath_getradiocaps(struct ieee80211com *ic,
6141 int maxchans, int *nchans, struct ieee80211_channel chans[])
6142{
6143 struct ath_softc *sc = ic->ic_ifp->if_softc;
6144 struct ath_hal *ah = sc->sc_ah;
6145
6146 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
6147 __func__, SKU_DEBUG, CTRY_DEFAULT);
6148
6149 /* XXX check return */
6150 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
6151 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
6152
6153}
6154
6155static int
6156ath_getchannels(struct ath_softc *sc)
6157{
6158 struct ifnet *ifp = sc->sc_ifp;
6159 struct ieee80211com *ic = ifp->if_l2com;
6160 struct ath_hal *ah = sc->sc_ah;
6161 HAL_STATUS status;
6162
6163 /*
6164 * Collect channel set based on EEPROM contents.
6165 */
6166 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
6167 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
6168 if (status != HAL_OK) {
6169 if_printf(ifp, "%s: unable to collect channel list from hal, "
6170 "status %d\n", __func__, status);
6171 return EINVAL;
6172 }
6173 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
6174 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
6175 /* XXX map Atheros sku's to net80211 SKU's */
6176 /* XXX net80211 types too small */
6177 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
6178 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
6179 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
6180 ic->ic_regdomain.isocc[1] = ' ';
6181
6182 ic->ic_regdomain.ecm = 1;
6183 ic->ic_regdomain.location = 'I';
6184
6185 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6186 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
6187 __func__, sc->sc_eerd, sc->sc_eecc,
6188 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
6189 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
6190 return 0;
6191}
6192
6193static int
6194ath_rate_setup(struct ath_softc *sc, u_int mode)
6195{
6196 struct ath_hal *ah = sc->sc_ah;
6197 const HAL_RATE_TABLE *rt;
6198
6199 switch (mode) {
6200 case IEEE80211_MODE_11A:
6201 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
6202 break;
6203 case IEEE80211_MODE_HALF:
6204 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
6205 break;
6206 case IEEE80211_MODE_QUARTER:
6207 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
6208 break;
6209 case IEEE80211_MODE_11B:
6210 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
6211 break;
6212 case IEEE80211_MODE_11G:
6213 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
6214 break;
6215 case IEEE80211_MODE_TURBO_A:
6216 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
6217 break;
6218 case IEEE80211_MODE_TURBO_G:
6219 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
6220 break;
6221 case IEEE80211_MODE_STURBO_A:
6222 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6223 break;
6224 case IEEE80211_MODE_11NA:
6225 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
6226 break;
6227 case IEEE80211_MODE_11NG:
6228 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
6229 break;
6230 default:
6231 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6232 __func__, mode);
6233 return 0;
6234 }
6235 sc->sc_rates[mode] = rt;
6236 return (rt != NULL);
6237}
6238
6239static void
6240ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6241{
6242#define N(a) (sizeof(a)/sizeof(a[0]))
6243 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
6244 static const struct {
6245 u_int rate; /* tx/rx 802.11 rate */
6246 u_int16_t timeOn; /* LED on time (ms) */
6247 u_int16_t timeOff; /* LED off time (ms) */
6248 } blinkrates[] = {
6249 { 108, 40, 10 },
6250 { 96, 44, 11 },
6251 { 72, 50, 13 },
6252 { 48, 57, 14 },
6253 { 36, 67, 16 },
6254 { 24, 80, 20 },
6255 { 22, 100, 25 },
6256 { 18, 133, 34 },
6257 { 12, 160, 40 },
6258 { 10, 200, 50 },
6259 { 6, 240, 58 },
6260 { 4, 267, 66 },
6261 { 2, 400, 100 },
6262 { 0, 500, 130 },
6263 /* XXX half/quarter rates */
6264 };
6265 const HAL_RATE_TABLE *rt;
6266 int i, j;
6267
6268 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6269 rt = sc->sc_rates[mode];
6270 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6271 for (i = 0; i < rt->rateCount; i++) {
6272 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6273 if (rt->info[i].phy != IEEE80211_T_HT)
6274 sc->sc_rixmap[ieeerate] = i;
6275 else
6276 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6277 }
6278 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6279 for (i = 0; i < N(sc->sc_hwmap); i++) {
6280 if (i >= rt->rateCount) {
6281 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6282 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6283 continue;
6284 }
6285 sc->sc_hwmap[i].ieeerate =
6286 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6287 if (rt->info[i].phy == IEEE80211_T_HT)
6288 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6289 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6290 if (rt->info[i].shortPreamble ||
6291 rt->info[i].phy == IEEE80211_T_OFDM)
6292 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6293 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6294 for (j = 0; j < N(blinkrates)-1; j++)
6295 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6296 break;
6297 /* NB: this uses the last entry if the rate isn't found */
6298 /* XXX beware of overlow */
6299 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6300 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6301 }
6302 sc->sc_currates = rt;
6303 sc->sc_curmode = mode;
6304 /*
6305 * All protection frames are transmited at 2Mb/s for
6306 * 11g, otherwise at 1Mb/s.
6307 */
6308 if (mode == IEEE80211_MODE_11G)
6309 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6310 else
6311 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6312 /* NB: caller is responsible for resetting rate control state */
6313#undef N
6314}
6315
6316static void
6317ath_watchdog(void *arg)
6318{
6319 struct ath_softc *sc = arg;
6320 int do_reset = 0;
6321
6322 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6323 struct ifnet *ifp = sc->sc_ifp;
6324 uint32_t hangs;
6325
6326 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6327 hangs != 0) {
6328 if_printf(ifp, "%s hang detected (0x%x)\n",
6329 hangs & 0xff ? "bb" : "mac", hangs);
6330 } else
6331 if_printf(ifp, "device timeout\n");
6332 do_reset = 1;
6333 ifp->if_oerrors++;
6334 sc->sc_stats.ast_watchdog++;
6335 }
6336
6337 /*
6338 * We can't hold the lock across the ath_reset() call.
6339 *
6340 * And since this routine can't hold a lock and sleep,
6341 * do the reset deferred.
6342 */
6343 if (do_reset) {
6344 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
6345 }
6346
6347 callout_schedule(&sc->sc_wd_ch, hz);
6348}
6349
6350#ifdef ATH_DIAGAPI
6351/*
6352 * Diagnostic interface to the HAL. This is used by various
6353 * tools to do things like retrieve register contents for
6354 * debugging. The mechanism is intentionally opaque so that
6355 * it can change frequently w/o concern for compatiblity.
6356 */
6357static int
6358ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6359{
6360 struct ath_hal *ah = sc->sc_ah;
6361 u_int id = ad->ad_id & ATH_DIAG_ID;
6362 void *indata = NULL;
6363 void *outdata = NULL;
6364 u_int32_t insize = ad->ad_in_size;
6365 u_int32_t outsize = ad->ad_out_size;
6366 int error = 0;
6367
6368 if (ad->ad_id & ATH_DIAG_IN) {
6369 /*
6370 * Copy in data.
6371 */
6372 indata = malloc(insize, M_TEMP, M_NOWAIT);
6373 if (indata == NULL) {
6374 error = ENOMEM;
6375 goto bad;
6376 }
6377 error = copyin(ad->ad_in_data, indata, insize);
6378 if (error)
6379 goto bad;
6380 }
6381 if (ad->ad_id & ATH_DIAG_DYN) {
6382 /*
6383 * Allocate a buffer for the results (otherwise the HAL
6384 * returns a pointer to a buffer where we can read the
6385 * results). Note that we depend on the HAL leaving this
6386 * pointer for us to use below in reclaiming the buffer;
6387 * may want to be more defensive.
6388 */
6389 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
6390 if (outdata == NULL) {
6391 error = ENOMEM;
6392 goto bad;
6393 }
6394 }
6395 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6396 if (outsize < ad->ad_out_size)
6397 ad->ad_out_size = outsize;
6398 if (outdata != NULL)
6399 error = copyout(outdata, ad->ad_out_data,
6400 ad->ad_out_size);
6401 } else {
6402 error = EINVAL;
6403 }
6404bad:
6405 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6406 free(indata, M_TEMP);
6407 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6408 free(outdata, M_TEMP);
6409 return error;
6410}
6411#endif /* ATH_DIAGAPI */
6412
6413static int
6414ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6415{
6416#define IS_RUNNING(ifp) \
6417 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
6418 struct ath_softc *sc = ifp->if_softc;
6419 struct ieee80211com *ic = ifp->if_l2com;
6420 struct ifreq *ifr = (struct ifreq *)data;
6421 const HAL_RATE_TABLE *rt;
6422 int error = 0;
6423
6424 switch (cmd) {
6425 case SIOCSIFFLAGS:
6426 ATH_LOCK(sc);
6427 if (IS_RUNNING(ifp)) {
6428 /*
6429 * To avoid rescanning another access point,
6430 * do not call ath_init() here. Instead,
6431 * only reflect promisc mode settings.
6432 */
6433 ath_mode_init(sc);
6434 } else if (ifp->if_flags & IFF_UP) {
6435 /*
6436 * Beware of being called during attach/detach
6437 * to reset promiscuous mode. In that case we
6438 * will still be marked UP but not RUNNING.
6439 * However trying to re-init the interface
6440 * is the wrong thing to do as we've already
6441 * torn down much of our state. There's
6442 * probably a better way to deal with this.
6443 */
6444 if (!sc->sc_invalid)
6445 ath_init(sc); /* XXX lose error */
6446 } else {
6447 ath_stop_locked(ifp);
6448#ifdef notyet
6449 /* XXX must wakeup in places like ath_vap_delete */
6450 if (!sc->sc_invalid)
6451 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
6452#endif
6453 }
6454 ATH_UNLOCK(sc);
6455 break;
6456 case SIOCGIFMEDIA:
6457 case SIOCSIFMEDIA:
6458 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6459 break;
6460 case SIOCGATHSTATS:
6461 /* NB: embed these numbers to get a consistent view */
6462 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
6463 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
6464 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
6465 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
6466#ifdef IEEE80211_SUPPORT_TDMA
6467 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
6468 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
6469#endif
6470 rt = sc->sc_currates;
6471 sc->sc_stats.ast_tx_rate =
6472 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
6473 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
6474 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
6475 return copyout(&sc->sc_stats,
6476 ifr->ifr_data, sizeof (sc->sc_stats));
6477 case SIOCZATHSTATS:
6478 error = priv_check(curthread, PRIV_DRIVER);
6479 if (error == 0)
6480 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6481 break;
6482#ifdef ATH_DIAGAPI
6483 case SIOCGATHDIAG:
6484 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6485 break;
6486 case SIOCGATHPHYERR:
6487 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
6488 break;
6489#endif
6490 case SIOCGIFADDR:
6491 error = ether_ioctl(ifp, cmd, data);
6492 break;
6493 default:
6494 error = EINVAL;
6495 break;
6496 }
6497 return error;
6498#undef IS_RUNNING
6499}
6500
6501/*
6502 * Announce various information on device/driver attach.
6503 */
6504static void
6505ath_announce(struct ath_softc *sc)
6506{
6507 struct ifnet *ifp = sc->sc_ifp;
6508 struct ath_hal *ah = sc->sc_ah;
6509
6510 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6511 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6512 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6513 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6514 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
6515 if (bootverbose) {
6516 int i;
6517 for (i = 0; i <= WME_AC_VO; i++) {
6518 struct ath_txq *txq = sc->sc_ac2q[i];
6519 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6520 txq->axq_qnum, ieee80211_wme_acnames[i]);
6521 }
6522 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6523 sc->sc_cabq->axq_qnum);
6524 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6525 }
6526 if (ath_rxbuf != ATH_RXBUF)
6527 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6528 if (ath_txbuf != ATH_TXBUF)
6529 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6530 if (sc->sc_mcastkey && bootverbose)
6531 if_printf(ifp, "using multicast key search\n");
6532}
6533
6534#ifdef IEEE80211_SUPPORT_TDMA
6535static void
6536ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
6537{
6538 struct ath_hal *ah = sc->sc_ah;
6539 HAL_BEACON_TIMERS bt;
6540
6541 bt.bt_intval = bintval | HAL_BEACON_ENA;
6542 bt.bt_nexttbtt = nexttbtt;
6543 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
6544 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
6545 bt.bt_nextatim = nexttbtt+1;
6546 /* Enables TBTT, DBA, SWBA timers by default */
6547 bt.bt_flags = 0;
6548 ath_hal_beaconsettimers(ah, &bt);
6549}
6550
6551/*
6552 * Calculate the beacon interval. This is periodic in the
6553 * superframe for the bss. We assume each station is configured
6554 * identically wrt transmit rate so the guard time we calculate
6555 * above will be the same on all stations. Note we need to
6556 * factor in the xmit time because the hardware will schedule
6557 * a frame for transmit if the start of the frame is within
6558 * the burst time. When we get hardware that properly kills
6559 * frames in the PCU we can reduce/eliminate the guard time.
6560 *
6561 * Roundup to 1024 is so we have 1 TU buffer in the guard time
6562 * to deal with the granularity of the nexttbtt timer. 11n MAC's
6563 * with 1us timer granularity should allow us to reduce/eliminate
6564 * this.
6565 */
6566static void
6567ath_tdma_bintvalsetup(struct ath_softc *sc,
6568 const struct ieee80211_tdma_state *tdma)
6569{
6570 /* copy from vap state (XXX check all vaps have same value?) */
6571 sc->sc_tdmaslotlen = tdma->tdma_slotlen;
6572
6573 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
6574 tdma->tdma_slotcnt, 1024);
6575 sc->sc_tdmabintval >>= 10; /* TSF -> TU */
6576 if (sc->sc_tdmabintval & 1)
6577 sc->sc_tdmabintval++;
6578
6579 if (tdma->tdma_slot == 0) {
6580 /*
6581 * Only slot 0 beacons; other slots respond.
6582 */
6583 sc->sc_imask |= HAL_INT_SWBA;
6584 sc->sc_tdmaswba = 0; /* beacon immediately */
6585 } else {
6586 /* XXX all vaps must be slot 0 or slot !0 */
6587 sc->sc_imask &= ~HAL_INT_SWBA;
6588 }
6589}
6590
6591/*
6592 * Max 802.11 overhead. This assumes no 4-address frames and
6593 * the encapsulation done by ieee80211_encap (llc). We also
6594 * include potential crypto overhead.
6595 */
6596#define IEEE80211_MAXOVERHEAD \
6597 (sizeof(struct ieee80211_qosframe) \
6598 + sizeof(struct llc) \
6599 + IEEE80211_ADDR_LEN \
6600 + IEEE80211_WEP_IVLEN \
6601 + IEEE80211_WEP_KIDLEN \
6602 + IEEE80211_WEP_CRCLEN \
6603 + IEEE80211_WEP_MICLEN \
6604 + IEEE80211_CRC_LEN)
6605
6606/*
6607 * Setup initially for tdma operation. Start the beacon
6608 * timers and enable SWBA if we are slot 0. Otherwise
6609 * we wait for slot 0 to arrive so we can sync up before
6610 * starting to transmit.
6611 */
6612static void
6613ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
6614{
6615 struct ath_hal *ah = sc->sc_ah;
6616 struct ifnet *ifp = sc->sc_ifp;
6617 struct ieee80211com *ic = ifp->if_l2com;
6618 const struct ieee80211_txparam *tp;
6619 const struct ieee80211_tdma_state *tdma = NULL;
6620 int rix;
6621
6622 if (vap == NULL) {
6623 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
6624 if (vap == NULL) {
6625 if_printf(ifp, "%s: no vaps?\n", __func__);
6626 return;
6627 }
6628 }
6629 /* XXX should take a locked ref to iv_bss */
6630 tp = vap->iv_bss->ni_txparms;
6631 /*
6632 * Calculate the guard time for each slot. This is the
6633 * time to send a maximal-size frame according to the
6634 * fixed/lowest transmit rate. Note that the interface
6635 * mtu does not include the 802.11 overhead so we must
6636 * tack that on (ath_hal_computetxtime includes the
6637 * preamble and plcp in it's calculation).
6638 */
6639 tdma = vap->iv_tdma;
6640 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
6641 rix = ath_tx_findrix(sc, tp->ucastrate);
6642 else
6643 rix = ath_tx_findrix(sc, tp->mcastrate);
6644 /* XXX short preamble assumed */
6645 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
6646 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
6647
6648 ath_hal_intrset(ah, 0);
6649
6650 ath_beaconq_config(sc); /* setup h/w beacon q */
6651 if (sc->sc_setcca)
6652 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */
6653 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */
6654 ath_tdma_settimers(sc, sc->sc_tdmabintval,
6655 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
6656 sc->sc_syncbeacon = 0;
6657
6658 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
6659 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
6660
6661 ath_hal_intrset(ah, sc->sc_imask);
6662
6663 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
6664 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
6665 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
6666 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
6667 sc->sc_tdmadbaprep);
6668}
6669
6670/*
6671 * Update tdma operation. Called from the 802.11 layer
6672 * when a beacon is received from the TDMA station operating
6673 * in the slot immediately preceding us in the bss. Use
6674 * the rx timestamp for the beacon frame to update our
6675 * beacon timers so we follow their schedule. Note that
6676 * by using the rx timestamp we implicitly include the
6677 * propagation delay in our schedule.
6678 */
6679static void
6680ath_tdma_update(struct ieee80211_node *ni,
6681 const struct ieee80211_tdma_param *tdma, int changed)
6682{
6683#define TSF_TO_TU(_h,_l) \
6684 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
6685#define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
6686 struct ieee80211vap *vap = ni->ni_vap;
6687 struct ieee80211com *ic = ni->ni_ic;
6688 struct ath_softc *sc = ic->ic_ifp->if_softc;
6689 struct ath_hal *ah = sc->sc_ah;
6690 const HAL_RATE_TABLE *rt = sc->sc_currates;
6691 u_int64_t tsf, rstamp, nextslot, nexttbtt;
6692 u_int32_t txtime, nextslottu;
6693 int32_t tudelta, tsfdelta;
6694 const struct ath_rx_status *rs;
6695 int rix;
6696
6697 sc->sc_stats.ast_tdma_update++;
6698
6699 /*
6700 * Check for and adopt configuration changes.
6701 */
6702 if (changed != 0) {
6703 const struct ieee80211_tdma_state *ts = vap->iv_tdma;
6704
6705 ath_tdma_bintvalsetup(sc, ts);
6706 if (changed & TDMA_UPDATE_SLOTLEN)
6707 ath_wme_update(ic);
6708
6709 DPRINTF(sc, ATH_DEBUG_TDMA,
6710 "%s: adopt slot %u slotcnt %u slotlen %u us "
6711 "bintval %u TU\n", __func__,
6712 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
6713 sc->sc_tdmabintval);
6714
6715 /* XXX right? */
6716 ath_hal_intrset(ah, sc->sc_imask);
6717 /* NB: beacon timers programmed below */
6718 }
6719
6720 /* extend rx timestamp to 64 bits */
6721 rs = sc->sc_lastrs;
6722 tsf = ath_hal_gettsf64(ah);
6723 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
6724 /*
6725 * The rx timestamp is set by the hardware on completing
6726 * reception (at the point where the rx descriptor is DMA'd
6727 * to the host). To find the start of our next slot we
6728 * must adjust this time by the time required to send
6729 * the packet just received.
6730 */
6731 rix = rt->rateCodeToIndex[rs->rs_rate];
6732 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
6733 rt->info[rix].shortPreamble);
6734 /* NB: << 9 is to cvt to TU and /2 */
6735 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
6736 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD;
6737
6738 /*
6739 * Retrieve the hardware NextTBTT in usecs
6740 * and calculate the difference between what the
6741 * other station thinks and what we have programmed. This
6742 * lets us figure how to adjust our timers to match. The
6743 * adjustments are done by pulling the TSF forward and possibly
6744 * rewriting the beacon timers.
6745 */
6746 nexttbtt = ath_hal_getnexttbtt(ah);
6747 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt);
6748
6749 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
6750 "tsfdelta %d avg +%d/-%d\n", tsfdelta,
6751 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
6752
6753 if (tsfdelta < 0) {
6754 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
6755 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
6756 tsfdelta = -tsfdelta % 1024;
6757 nextslottu++;
6758 } else if (tsfdelta > 0) {
6759 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
6760 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
6761 tsfdelta = 1024 - (tsfdelta % 1024);
6762 nextslottu++;
6763 } else {
6764 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
6765 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
6766 }
6767 tudelta = nextslottu - TSF_TO_TU(nexttbtt >> 32, nexttbtt);
6768
6769 /*
6770 * Copy sender's timetstamp into tdma ie so they can
6771 * calculate roundtrip time. We submit a beacon frame
6772 * below after any timer adjustment. The frame goes out
6773 * at the next TBTT so the sender can calculate the
6774 * roundtrip by inspecting the tdma ie in our beacon frame.
6775 *
6776 * NB: This tstamp is subtlely preserved when
6777 * IEEE80211_BEACON_TDMA is marked (e.g. when the
6778 * slot position changes) because ieee80211_add_tdma
6779 * skips over the data.
6780 */
6781 memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
6782 __offsetof(struct ieee80211_tdma_param, tdma_tstamp),
6783 &ni->ni_tstamp.data, 8);
6784#if 0
6785 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
6786 "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n",
6787 (unsigned long long) tsf, (unsigned long long) nextslot,
6788 (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta);
6789#endif
6790 /*
6791 * Adjust the beacon timers only when pulling them forward
6792 * or when going back by less than the beacon interval.
6793 * Negative jumps larger than the beacon interval seem to
6794 * cause the timers to stop and generally cause instability.
6795 * This basically filters out jumps due to missed beacons.
6796 */
6797 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
6798 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
6799 sc->sc_stats.ast_tdma_timers++;
6800 }
6801 if (tsfdelta > 0) {
6802 ath_hal_adjusttsf(ah, tsfdelta);
6803 sc->sc_stats.ast_tdma_tsf++;
6804 }
6805 ath_tdma_beacon_send(sc, vap); /* prepare response */
6806#undef TU_TO_TSF
6807#undef TSF_TO_TU
6808}
6809
6810/*
6811 * Transmit a beacon frame at SWBA. Dynamic updates
6812 * to the frame contents are done as needed.
6813 */
6814static void
6815ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
6816{
6817 struct ath_hal *ah = sc->sc_ah;
6818 struct ath_buf *bf;
6819 int otherant;
6820
6821 /*
6822 * Check if the previous beacon has gone out. If
6823 * not don't try to post another, skip this period
6824 * and wait for the next. Missed beacons indicate
6825 * a problem and should not occur. If we miss too
6826 * many consecutive beacons reset the device.
6827 */
6828 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
6829 sc->sc_bmisscount++;
6830 DPRINTF(sc, ATH_DEBUG_BEACON,
6831 "%s: missed %u consecutive beacons\n",
6832 __func__, sc->sc_bmisscount);
6833 if (sc->sc_bmisscount >= ath_bstuck_threshold)
6834 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
6835 return;
6836 }
6837 if (sc->sc_bmisscount != 0) {
6838 DPRINTF(sc, ATH_DEBUG_BEACON,
6839 "%s: resume beacon xmit after %u misses\n",
6840 __func__, sc->sc_bmisscount);
6841 sc->sc_bmisscount = 0;
6842 }
6843
6844 /*
6845 * Check recent per-antenna transmit statistics and flip
6846 * the default antenna if noticeably more frames went out
6847 * on the non-default antenna.
6848 * XXX assumes 2 anntenae
6849 */
6850 if (!sc->sc_diversity) {
6851 otherant = sc->sc_defant & 1 ? 2 : 1;
6852 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
6853 ath_setdefantenna(sc, otherant);
6854 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
6855 }
6856
6857 bf = ath_beacon_generate(sc, vap);
6858 if (bf != NULL) {
6859 /*
6860 * Stop any current dma and put the new frame on the queue.
6861 * This should never fail since we check above that no frames
6862 * are still pending on the queue.
6863 */
6864 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
6865 DPRINTF(sc, ATH_DEBUG_ANY,
6866 "%s: beacon queue %u did not stop?\n",
6867 __func__, sc->sc_bhalq);
6868 /* NB: the HAL still stops DMA, so proceed */
6869 }
6870 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
6871 ath_hal_txstart(ah, sc->sc_bhalq);
6872
6873 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */
6874
6875 /*
6876 * Record local TSF for our last send for use
6877 * in arbitrating slot collisions.
6878 */
6879 /* XXX should take a locked ref to iv_bss */
6880 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
6881 }
6882}
6883#endif /* IEEE80211_SUPPORT_TDMA */
6884
6885static void
6886ath_dfs_tasklet(void *p, int npending)
6887{
6888 struct ath_softc *sc = (struct ath_softc *) p;
6889 struct ifnet *ifp = sc->sc_ifp;
6890 struct ieee80211com *ic = ifp->if_l2com;
6891
6892 /*
6893 * If previous processing has found a radar event,
6894 * signal this to the net80211 layer to begin DFS
6895 * processing.
6896 */
6897 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6898 /* DFS event found, initiate channel change */
6899 /*
6900 * XXX doesn't currently tell us whether the event
6901 * XXX was found in the primary or extension
6902 * XXX channel!
6903 */
6904 IEEE80211_LOCK(ic);
6905 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6906 IEEE80211_UNLOCK(ic);
6907 }
6908}
6909
6910MODULE_VERSION(if_ath, 1);
6911MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
6912#if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ)
6913MODULE_DEPEND(if_ath, alq, 1, 1, 1);
6914#endif