1/*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
| 1/*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
|
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280.c 219605 2011-03-13 13:00:45Z adrian $
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280.c 224519 2011-07-30 13:45:12Z adrian $
|
18 */
19#include "opt_ah.h"
20
21/*
22 * NB: Merlin and later have a simpler RF backend.
23 */
24#include "ah.h"
25#include "ah_internal.h"
26
27#include "ah_eeprom_v14.h"
28
29#include "ar9002/ar9280.h"
30#include "ar5416/ar5416reg.h"
31#include "ar5416/ar5416phy.h"
32
33#define N(a) (sizeof(a)/sizeof(a[0]))
34
35struct ar9280State {
36 RF_HAL_FUNCS base; /* public state, must be first */
37 uint16_t pcdacTable[1]; /* XXX */
38};
39#define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal)
40
41static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *,
42 const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow);
43int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
44
45static void
46ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
47 int writes)
48{
49 (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
50 freqIndex, writes);
51}
52
53/*
54 * Take the MHz channel value and set the Channel value
55 *
56 * ASSUMES: Writes enabled to analog bus
57 *
58 * Actual Expression,
59 *
60 * For 2GHz channel,
61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
62 * (freq_ref = 40MHz)
63 *
64 * For 5GHz channel,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
67 *
68 * For 5GHz channels which are 5MHz spaced,
69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
70 * (freq_ref = 40MHz)
71 */
72static HAL_BOOL
73ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
74{
75 uint16_t bMode, fracMode, aModeRefSel = 0;
76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
77 CHAN_CENTERS centers;
78 uint32_t refDivA = 24;
| 18 */
19#include "opt_ah.h"
20
21/*
22 * NB: Merlin and later have a simpler RF backend.
23 */
24#include "ah.h"
25#include "ah_internal.h"
26
27#include "ah_eeprom_v14.h"
28
29#include "ar9002/ar9280.h"
30#include "ar5416/ar5416reg.h"
31#include "ar5416/ar5416phy.h"
32
33#define N(a) (sizeof(a)/sizeof(a[0]))
34
35struct ar9280State {
36 RF_HAL_FUNCS base; /* public state, must be first */
37 uint16_t pcdacTable[1]; /* XXX */
38};
39#define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal)
40
41static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *,
42 const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow);
43int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
44
45static void
46ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
47 int writes)
48{
49 (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
50 freqIndex, writes);
51}
52
53/*
54 * Take the MHz channel value and set the Channel value
55 *
56 * ASSUMES: Writes enabled to analog bus
57 *
58 * Actual Expression,
59 *
60 * For 2GHz channel,
61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
62 * (freq_ref = 40MHz)
63 *
64 * For 5GHz channel,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
67 *
68 * For 5GHz channels which are 5MHz spaced,
69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
70 * (freq_ref = 40MHz)
71 */
72static HAL_BOOL
73ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
74{
75 uint16_t bMode, fracMode, aModeRefSel = 0;
76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
77 CHAN_CENTERS centers;
78 uint32_t refDivA = 24;
|
| 79 uint8_t frac_n_5g;
|
79
80 OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
81
82 ar5416GetChannelCenters(ah, chan, ¢ers);
83 freq = centers.synth_center;
84
85 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
86 reg32 &= 0xc0000000;
87
| 80
81 OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
82
83 ar5416GetChannelCenters(ah, chan, ¢ers);
84 freq = centers.synth_center;
85
86 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
87 reg32 &= 0xc0000000;
88
|
| 89 if (ath_hal_eepromGet(ah, AR_EEP_FRAC_N_5G, &frac_n_5g) != HAL_OK)
90 frac_n_5g = 0;
91
|
88 if (freq < 4800) { /* 2 GHz, fractional mode */
89 uint32_t txctl;
90
91 bMode = 1;
92 fracMode = 1;
93 aModeRefSel = 0;
94 channelSel = (freq * 0x10000)/15;
95
96 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
97 if (freq == 2484) {
98 /* Enable channel spreading for channel 14 */
99 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
100 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
101 } else {
102 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
103 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
104 }
105 } else {
106 bMode = 0;
107 fracMode = 0;
108
| 92 if (freq < 4800) { /* 2 GHz, fractional mode */
93 uint32_t txctl;
94
95 bMode = 1;
96 fracMode = 1;
97 aModeRefSel = 0;
98 channelSel = (freq * 0x10000)/15;
99
100 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
101 if (freq == 2484) {
102 /* Enable channel spreading for channel 14 */
103 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
104 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
105 } else {
106 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
107 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
108 }
109 } else {
110 bMode = 0;
111 fracMode = 0;
112
|
109 if ((freq % 20) == 0) {
110 aModeRefSel = 3;
111 } else if ((freq % 10) == 0) {
112 aModeRefSel = 2;
113 } else {
| 113 switch (frac_n_5g) {
114 case 0:
115 if ((freq % 20) == 0) {
116 aModeRefSel = 3;
117 } else if ((freq % 10) == 0) {
118 aModeRefSel = 2;
119 }
120 if (aModeRefSel) break;
121 case 1:
122 default:
|
114 aModeRefSel = 0;
115 /* Enable 2G (fractional) mode for channels which are 5MHz spaced */
116 fracMode = 1;
117 refDivA = 1;
118 channelSel = (freq * 0x8000)/15;
119
120 /* RefDivA setting */
121 OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
122 AR_AN_SYNTH9_REFDIVA, refDivA);
123 }
| 123 aModeRefSel = 0;
124 /* Enable 2G (fractional) mode for channels which are 5MHz spaced */
125 fracMode = 1;
126 refDivA = 1;
127 channelSel = (freq * 0x8000)/15;
128
129 /* RefDivA setting */
130 OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
131 AR_AN_SYNTH9_REFDIVA, refDivA);
132 }
|
| 133
|
124 if (!fracMode) {
125 ndiv = (freq * (refDivA >> aModeRefSel))/60;
126 channelSel = ndiv & 0x1ff;
127 channelFrac = (ndiv & 0xfffffe00) * 2;
128 channelSel = (channelSel << 17) | channelFrac;
129 }
130 }
131
132 reg32 = reg32 | (bMode << 29) | (fracMode << 28) |
133 (aModeRefSel << 26) | (channelSel);
134
135 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
136
137 AH_PRIVATE(ah)->ah_curchan = chan;
138
139 return AH_TRUE;
140}
141
142/*
143 * Return a reference to the requested RF Bank.
144 */
145static uint32_t *
146ar9280GetRfBank(struct ath_hal *ah, int bank)
147{
148 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
149 __func__, bank);
150 return AH_NULL;
151}
152
153/*
154 * Reads EEPROM header info from device structure and programs
155 * all rf registers
156 */
157static HAL_BOOL
158ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
159 uint16_t modesIndex, uint16_t *rfXpdGain)
160{
161 return AH_TRUE; /* nothing to do */
162}
163
164/*
165 * Read the transmit power levels from the structures taken from EEPROM
166 * Interpolate read transmit power values for this channel
167 * Organize the transmit power values into a table for writing into the hardware
168 */
169
170static HAL_BOOL
171ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
172 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
173{
174 return AH_TRUE;
175}
176
177#if 0
178static int16_t
179ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
180{
181 int i, minIndex;
182 int16_t minGain,minPwr,minPcdac,retVal;
183
184 /* Assume NUM_POINTS_XPD0 > 0 */
185 minGain = data->pDataPerXPD[0].xpd_gain;
186 for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
187 if (data->pDataPerXPD[i].xpd_gain < minGain) {
188 minIndex = i;
189 minGain = data->pDataPerXPD[i].xpd_gain;
190 }
191 }
192 minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
193 minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
194 for (i=1; i<NUM_POINTS_XPD0; i++) {
195 if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
196 minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
197 minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
198 }
199 }
200 retVal = minPwr - (minPcdac*2);
201 return(retVal);
202}
203#endif
204
205static HAL_BOOL
206ar9280GetChannelMaxMinPower(struct ath_hal *ah,
207 const struct ieee80211_channel *chan,
208 int16_t *maxPow, int16_t *minPow)
209{
210#if 0
211 struct ath_hal_5212 *ahp = AH5212(ah);
212 int numChannels=0,i,last;
213 int totalD, totalF,totalMin;
214 EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
215 EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
216
217 *maxPow = 0;
218 if (IS_CHAN_A(chan)) {
219 powerArray = ahp->ah_modePowerArray5112;
220 data = powerArray[headerInfo11A].pDataPerChannel;
221 numChannels = powerArray[headerInfo11A].numChannels;
222 } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
223 /* XXX - is this correct? Should we also use the same power for turbo G? */
224 powerArray = ahp->ah_modePowerArray5112;
225 data = powerArray[headerInfo11G].pDataPerChannel;
226 numChannels = powerArray[headerInfo11G].numChannels;
227 } else if (IS_CHAN_B(chan)) {
228 powerArray = ahp->ah_modePowerArray5112;
229 data = powerArray[headerInfo11B].pDataPerChannel;
230 numChannels = powerArray[headerInfo11B].numChannels;
231 } else {
232 return (AH_TRUE);
233 }
234 /* Make sure the channel is in the range of the TP values
235 * (freq piers)
236 */
237 if ((numChannels < 1) ||
238 (chan->channel < data[0].channelValue) ||
239 (chan->channel > data[numChannels-1].channelValue))
240 return(AH_FALSE);
241
242 /* Linearly interpolate the power value now */
243 for (last=0,i=0;
244 (i<numChannels) && (chan->channel > data[i].channelValue);
245 last=i++);
246 totalD = data[i].channelValue - data[last].channelValue;
247 if (totalD > 0) {
248 totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
249 *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
250
251 totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]);
252 *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD);
253 return (AH_TRUE);
254 } else {
255 if (chan->channel == data[i].channelValue) {
256 *maxPow = data[i].maxPower_t4;
257 *minPow = ar9280GetMinPower(ah, &data[i]);
258 return(AH_TRUE);
259 } else
260 return(AH_FALSE);
261 }
262#else
263 *maxPow = *minPow = 0;
264 return AH_FALSE;
265#endif
266}
267
268/*
269 * The ordering of nfarray is thus:
270 *
271 * nfarray[0]: Chain 0 ctl
272 * nfarray[1]: Chain 1 ctl
273 * nfarray[2]: Chain 2 ctl
274 * nfarray[3]: Chain 0 ext
275 * nfarray[4]: Chain 1 ext
276 * nfarray[5]: Chain 2 ext
277 */
278static void
279ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
280{
281 int16_t nf;
282
283 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
284 if (nf & 0x100)
285 nf = 0 - ((nf ^ 0x1ff) + 1);
286 HALDEBUG(ah, HAL_DEBUG_NFCAL,
287 "NF calibrated [ctl] [chain 0] is %d\n", nf);
288 nfarray[0] = nf;
289
290 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
291 if (nf & 0x100)
292 nf = 0 - ((nf ^ 0x1ff) + 1);
293 HALDEBUG(ah, HAL_DEBUG_NFCAL,
294 "NF calibrated [ctl] [chain 1] is %d\n", nf);
295 nfarray[1] = nf;
296
297 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
298 if (nf & 0x100)
299 nf = 0 - ((nf ^ 0x1ff) + 1);
300 HALDEBUG(ah, HAL_DEBUG_NFCAL,
301 "NF calibrated [ext] [chain 0] is %d\n", nf);
302 nfarray[3] = nf;
303
304 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
305 if (nf & 0x100)
306 nf = 0 - ((nf ^ 0x1ff) + 1);
307 HALDEBUG(ah, HAL_DEBUG_NFCAL,
308 "NF calibrated [ext] [chain 1] is %d\n", nf);
309 nfarray[4] = nf;
310
311 /* Chain 2 - invalid */
312 nfarray[2] = 0;
313 nfarray[5] = 0;
314
315}
316
317/*
318 * Adjust NF based on statistical values for 5GHz frequencies.
319 * Stubbed:Not used by Fowl
320 */
321int16_t
322ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
323{
324 return 0;
325}
326
327/*
328 * Free memory for analog bank scratch buffers
329 */
330static void
331ar9280RfDetach(struct ath_hal *ah)
332{
333 struct ath_hal_5212 *ahp = AH5212(ah);
334
335 HALASSERT(ahp->ah_rfHal != AH_NULL);
336 ath_hal_free(ahp->ah_rfHal);
337 ahp->ah_rfHal = AH_NULL;
338}
339
340HAL_BOOL
341ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)
342{
343 struct ath_hal_5212 *ahp = AH5212(ah);
344 struct ar9280State *priv;
345
346 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);
347
348 HALASSERT(ahp->ah_rfHal == AH_NULL);
349 priv = ath_hal_malloc(sizeof(struct ar9280State));
350 if (priv == AH_NULL) {
351 HALDEBUG(ah, HAL_DEBUG_ANY,
352 "%s: cannot allocate private state\n", __func__);
353 *status = HAL_ENOMEM; /* XXX */
354 return AH_FALSE;
355 }
356 priv->base.rfDetach = ar9280RfDetach;
357 priv->base.writeRegs = ar9280WriteRegs;
358 priv->base.getRfBank = ar9280GetRfBank;
359 priv->base.setChannel = ar9280SetChannel;
360 priv->base.setRfRegs = ar9280SetRfRegs;
361 priv->base.setPowerTable = ar9280SetPowerTable;
362 priv->base.getChannelMaxMinPower = ar9280GetChannelMaxMinPower;
363 priv->base.getNfAdjust = ar9280GetNfAdjust;
364
365 ahp->ah_pcdacTable = priv->pcdacTable;
366 ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
367 ahp->ah_rfHal = &priv->base;
368 /*
369 * Set noise floor adjust method; we arrange a
370 * direct call instead of thunking.
371 */
372 AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
373 AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor;
374
375 return AH_TRUE;
376}
| 134 if (!fracMode) {
135 ndiv = (freq * (refDivA >> aModeRefSel))/60;
136 channelSel = ndiv & 0x1ff;
137 channelFrac = (ndiv & 0xfffffe00) * 2;
138 channelSel = (channelSel << 17) | channelFrac;
139 }
140 }
141
142 reg32 = reg32 | (bMode << 29) | (fracMode << 28) |
143 (aModeRefSel << 26) | (channelSel);
144
145 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
146
147 AH_PRIVATE(ah)->ah_curchan = chan;
148
149 return AH_TRUE;
150}
151
152/*
153 * Return a reference to the requested RF Bank.
154 */
155static uint32_t *
156ar9280GetRfBank(struct ath_hal *ah, int bank)
157{
158 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
159 __func__, bank);
160 return AH_NULL;
161}
162
163/*
164 * Reads EEPROM header info from device structure and programs
165 * all rf registers
166 */
167static HAL_BOOL
168ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
169 uint16_t modesIndex, uint16_t *rfXpdGain)
170{
171 return AH_TRUE; /* nothing to do */
172}
173
174/*
175 * Read the transmit power levels from the structures taken from EEPROM
176 * Interpolate read transmit power values for this channel
177 * Organize the transmit power values into a table for writing into the hardware
178 */
179
180static HAL_BOOL
181ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
182 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
183{
184 return AH_TRUE;
185}
186
187#if 0
188static int16_t
189ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
190{
191 int i, minIndex;
192 int16_t minGain,minPwr,minPcdac,retVal;
193
194 /* Assume NUM_POINTS_XPD0 > 0 */
195 minGain = data->pDataPerXPD[0].xpd_gain;
196 for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
197 if (data->pDataPerXPD[i].xpd_gain < minGain) {
198 minIndex = i;
199 minGain = data->pDataPerXPD[i].xpd_gain;
200 }
201 }
202 minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
203 minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
204 for (i=1; i<NUM_POINTS_XPD0; i++) {
205 if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
206 minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
207 minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
208 }
209 }
210 retVal = minPwr - (minPcdac*2);
211 return(retVal);
212}
213#endif
214
215static HAL_BOOL
216ar9280GetChannelMaxMinPower(struct ath_hal *ah,
217 const struct ieee80211_channel *chan,
218 int16_t *maxPow, int16_t *minPow)
219{
220#if 0
221 struct ath_hal_5212 *ahp = AH5212(ah);
222 int numChannels=0,i,last;
223 int totalD, totalF,totalMin;
224 EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
225 EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
226
227 *maxPow = 0;
228 if (IS_CHAN_A(chan)) {
229 powerArray = ahp->ah_modePowerArray5112;
230 data = powerArray[headerInfo11A].pDataPerChannel;
231 numChannels = powerArray[headerInfo11A].numChannels;
232 } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
233 /* XXX - is this correct? Should we also use the same power for turbo G? */
234 powerArray = ahp->ah_modePowerArray5112;
235 data = powerArray[headerInfo11G].pDataPerChannel;
236 numChannels = powerArray[headerInfo11G].numChannels;
237 } else if (IS_CHAN_B(chan)) {
238 powerArray = ahp->ah_modePowerArray5112;
239 data = powerArray[headerInfo11B].pDataPerChannel;
240 numChannels = powerArray[headerInfo11B].numChannels;
241 } else {
242 return (AH_TRUE);
243 }
244 /* Make sure the channel is in the range of the TP values
245 * (freq piers)
246 */
247 if ((numChannels < 1) ||
248 (chan->channel < data[0].channelValue) ||
249 (chan->channel > data[numChannels-1].channelValue))
250 return(AH_FALSE);
251
252 /* Linearly interpolate the power value now */
253 for (last=0,i=0;
254 (i<numChannels) && (chan->channel > data[i].channelValue);
255 last=i++);
256 totalD = data[i].channelValue - data[last].channelValue;
257 if (totalD > 0) {
258 totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
259 *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
260
261 totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]);
262 *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD);
263 return (AH_TRUE);
264 } else {
265 if (chan->channel == data[i].channelValue) {
266 *maxPow = data[i].maxPower_t4;
267 *minPow = ar9280GetMinPower(ah, &data[i]);
268 return(AH_TRUE);
269 } else
270 return(AH_FALSE);
271 }
272#else
273 *maxPow = *minPow = 0;
274 return AH_FALSE;
275#endif
276}
277
278/*
279 * The ordering of nfarray is thus:
280 *
281 * nfarray[0]: Chain 0 ctl
282 * nfarray[1]: Chain 1 ctl
283 * nfarray[2]: Chain 2 ctl
284 * nfarray[3]: Chain 0 ext
285 * nfarray[4]: Chain 1 ext
286 * nfarray[5]: Chain 2 ext
287 */
288static void
289ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
290{
291 int16_t nf;
292
293 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
294 if (nf & 0x100)
295 nf = 0 - ((nf ^ 0x1ff) + 1);
296 HALDEBUG(ah, HAL_DEBUG_NFCAL,
297 "NF calibrated [ctl] [chain 0] is %d\n", nf);
298 nfarray[0] = nf;
299
300 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
301 if (nf & 0x100)
302 nf = 0 - ((nf ^ 0x1ff) + 1);
303 HALDEBUG(ah, HAL_DEBUG_NFCAL,
304 "NF calibrated [ctl] [chain 1] is %d\n", nf);
305 nfarray[1] = nf;
306
307 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
308 if (nf & 0x100)
309 nf = 0 - ((nf ^ 0x1ff) + 1);
310 HALDEBUG(ah, HAL_DEBUG_NFCAL,
311 "NF calibrated [ext] [chain 0] is %d\n", nf);
312 nfarray[3] = nf;
313
314 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
315 if (nf & 0x100)
316 nf = 0 - ((nf ^ 0x1ff) + 1);
317 HALDEBUG(ah, HAL_DEBUG_NFCAL,
318 "NF calibrated [ext] [chain 1] is %d\n", nf);
319 nfarray[4] = nf;
320
321 /* Chain 2 - invalid */
322 nfarray[2] = 0;
323 nfarray[5] = 0;
324
325}
326
327/*
328 * Adjust NF based on statistical values for 5GHz frequencies.
329 * Stubbed:Not used by Fowl
330 */
331int16_t
332ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
333{
334 return 0;
335}
336
337/*
338 * Free memory for analog bank scratch buffers
339 */
340static void
341ar9280RfDetach(struct ath_hal *ah)
342{
343 struct ath_hal_5212 *ahp = AH5212(ah);
344
345 HALASSERT(ahp->ah_rfHal != AH_NULL);
346 ath_hal_free(ahp->ah_rfHal);
347 ahp->ah_rfHal = AH_NULL;
348}
349
350HAL_BOOL
351ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)
352{
353 struct ath_hal_5212 *ahp = AH5212(ah);
354 struct ar9280State *priv;
355
356 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);
357
358 HALASSERT(ahp->ah_rfHal == AH_NULL);
359 priv = ath_hal_malloc(sizeof(struct ar9280State));
360 if (priv == AH_NULL) {
361 HALDEBUG(ah, HAL_DEBUG_ANY,
362 "%s: cannot allocate private state\n", __func__);
363 *status = HAL_ENOMEM; /* XXX */
364 return AH_FALSE;
365 }
366 priv->base.rfDetach = ar9280RfDetach;
367 priv->base.writeRegs = ar9280WriteRegs;
368 priv->base.getRfBank = ar9280GetRfBank;
369 priv->base.setChannel = ar9280SetChannel;
370 priv->base.setRfRegs = ar9280SetRfRegs;
371 priv->base.setPowerTable = ar9280SetPowerTable;
372 priv->base.getChannelMaxMinPower = ar9280GetChannelMaxMinPower;
373 priv->base.getNfAdjust = ar9280GetNfAdjust;
374
375 ahp->ah_pcdacTable = priv->pcdacTable;
376 ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
377 ahp->ah_rfHal = &priv->base;
378 /*
379 * Set noise floor adjust method; we arrange a
380 * direct call instead of thunking.
381 */
382 AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
383 AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor;
384
385 return AH_TRUE;
386}
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