| ar5416_reset.c (222300) | ar5416_reset.c (222301) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * | 1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * |
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 222300 2011-05-26 08:35:47Z adrian $ | 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 222301 2011-05-26 09:15:33Z adrian $ |
| 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" --- 136 unchanged lines hidden (view full) --- 162 ar5212SetTsf64(ah, tsf); 163 164 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 165 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 166 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 167 168 AH5416(ah)->ah_writeIni(ah, chan); 169 | 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" --- 136 unchanged lines hidden (view full) --- 162 ar5212SetTsf64(ah, tsf); 163 164 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 165 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 166 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 167 168 AH5416(ah)->ah_writeIni(ah, chan); 169 |
| 170 if(AR_SREV_KIWI_13_OR_LATER(ah) ) { 171 /* Enable ASYNC FIFO */ 172 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 173 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 174 OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 175 OS_REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 176 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 177 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 178 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 179 } 180 |
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| 170 /* Override ini values (that can be overriden in this fashion) */ 171 ar5416OverrideIni(ah, chan); 172 173 /* Setup 11n MAC/Phy mode registers */ 174 ar5416Set11nRegs(ah, chan); 175 176 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 177 --- 75 unchanged lines hidden (view full) --- 253 /* Restore previous led state */ 254 if (AR_SREV_HOWL(ah)) 255 OS_REG_WRITE(ah, AR_MAC_LED, 256 AR_MAC_LED_ASSOC_ACTIVE | AR_CFG_SCLK_32KHZ); 257 else 258 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | 259 saveLedState); 260 | 181 /* Override ini values (that can be overriden in this fashion) */ 182 ar5416OverrideIni(ah, chan); 183 184 /* Setup 11n MAC/Phy mode registers */ 185 ar5416Set11nRegs(ah, chan); 186 187 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 188 --- 75 unchanged lines hidden (view full) --- 264 /* Restore previous led state */ 265 if (AR_SREV_HOWL(ah)) 266 OS_REG_WRITE(ah, AR_MAC_LED, 267 AR_MAC_LED_ASSOC_ACTIVE | AR_CFG_SCLK_32KHZ); 268 else 269 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | 270 saveLedState); 271 |
| 272 /* Start TSF2 for generic timer 8-15 */ 273#ifdef NOTYET 274 if (AR_SREV_KIWI(ah)) 275 ar5416StartTsf2(ah); 276#endif 277 |
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| 261 /* Restore previous antenna */ 262 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 263 264 /* then our BSSID */ 265 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 266 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 267 268 /* Restore bmiss rssi & count thresholds */ --- 18 unchanged lines hidden (view full) --- 287 ah->ah_resetTxQueue(ah, i); 288 289 ar5416InitIMR(ah, opmode); 290 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 291 ar5416InitQoS(ah); 292 /* This may override the AR_DIAG_SW register */ 293 ar5416InitUserSettings(ah); 294 | 278 /* Restore previous antenna */ 279 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 280 281 /* then our BSSID */ 282 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 283 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 284 285 /* Restore bmiss rssi & count thresholds */ --- 18 unchanged lines hidden (view full) --- 304 ah->ah_resetTxQueue(ah, i); 305 306 ar5416InitIMR(ah, opmode); 307 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 308 ar5416InitQoS(ah); 309 /* This may override the AR_DIAG_SW register */ 310 ar5416InitUserSettings(ah); 311 |
| 312 if (AR_SREV_KIWI_13_OR_LATER(ah)) { 313 /* 314 * Enable ASYNC FIFO 315 * 316 * If Async FIFO is enabled, the following counters change 317 * as MAC now runs at 117 Mhz instead of 88/44MHz when 318 * async FIFO is disabled. 319 * 320 * Overwrite the delay/timeouts initialized in ProcessIni() 321 * above. 322 */ 323 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 324 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 325 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 326 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 327 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 328 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 329 330 OS_REG_WRITE(ah, AR_TIME_OUT, 331 AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 332 OS_REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 333 334 OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 335 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 336 OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 337 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 338 } 339 340 if (AR_SREV_KIWI_13_OR_LATER(ah)) { 341 /* Enable AGGWEP to accelerate encryption engine */ 342 OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 343 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 344 } 345 346 |
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| 295 /* 296 * disable seq number generation in hw 297 */ 298 OS_REG_WRITE(ah, AR_STA_ID1, 299 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 300 301 ar5416InitDMA(ah); 302 --- 2376 unchanged lines hidden --- | 347 /* 348 * disable seq number generation in hw 349 */ 350 OS_REG_WRITE(ah, AR_STA_ID1, 351 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 352 353 ar5416InitDMA(ah); 354 --- 2376 unchanged lines hidden --- |