18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"
26
27#include "ar5416/ar5416.h"
28#include "ar5416/ar5416reg.h"
29#include "ar5416/ar5416phy.h"
30
31/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
32#define EEP_MINOR(_ah) \
33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
34#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
35#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
36
37/* Additional Time delay to wait after activiting the Base band */
38#define BASE_ACTIVATE_DELAY 100 /* 100 usec */
39#define PLL_SETTLE_DELAY 300 /* 300 usec */
40#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
41
42static void ar5416InitDMA(struct ath_hal *ah);
43static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *);
44static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);
45static void ar5416InitQoS(struct ath_hal *ah);
46static void ar5416InitUserSettings(struct ath_hal *ah);
47static void ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht);
48static void ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *);
49
50#if 0
51static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *);
52#endif
53static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *);
54
55static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
56static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
57static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
58static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
59 struct ar5416eeprom *pEepData,
60 const struct ieee80211_channel *chan, int16_t *ratesArray,
61 uint16_t cfgCtl, uint16_t AntennaReduction,
62 uint16_t twiceMaxRegulatoryPower,
63 uint16_t powerLimit);
64static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
65static void ar5416MarkPhyInactive(struct ath_hal *ah);
66
67/*
68 * Places the device in and out of reset and then places sane
69 * values in the registers based on EEPROM config, initialization
70 * vectors (as determined by the mode), and station configuration
71 *
72 * bChannelChange is used to preserve DMA/PCU registers across
73 * a HW Reset during channel change.
74 */
75HAL_BOOL
76ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
77 struct ieee80211_channel *chan,
78 HAL_BOOL bChannelChange, HAL_STATUS *status)
79{
80#define N(a) (sizeof (a) / sizeof (a[0]))
81#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
82 struct ath_hal_5212 *ahp = AH5212(ah);
83 HAL_CHANNEL_INTERNAL *ichan;
84 uint32_t saveDefAntenna, saveLedState;
85 uint32_t macStaId1;
86 uint16_t rfXpdGain[2];
87 HAL_STATUS ecode;
88 uint32_t powerVal, rssiThrReg;
89 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow;
90 int i;
91 uint64_t tsf = 0;
92
93 OS_MARK(ah, AH_MARK_RESET, bChannelChange);
94
95 /* Bring out of sleep mode */
96 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
97 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n",
98 __func__);
99 FAIL(HAL_EIO);
100 }
101
102 /*
103 * Map public channel to private.
104 */
105 ichan = ath_hal_checkchannel(ah, chan);
106 if (ichan == AH_NULL)
107 FAIL(HAL_EINVAL);
108 switch (opmode) {
109 case HAL_M_STA:
110 case HAL_M_IBSS:
111 case HAL_M_HOSTAP:
112 case HAL_M_MONITOR:
113 break;
114 default:
115 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
116 __func__, opmode);
117 FAIL(HAL_EINVAL);
118 break;
119 }
120 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
121
122 /* XXX Turn on fast channel change for 5416 */
123 /*
124 * Preserve the bmiss rssi threshold and count threshold
125 * across resets
126 */
127 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR);
128 /* If reg is zero, first time thru set to default val */
129 if (rssiThrReg == 0)
130 rssiThrReg = INIT_RSSI_THR;
131
132 /*
133 * Preserve the antenna on a channel change
134 */
135 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
136 if (saveDefAntenna == 0) /* XXX magic constants */
137 saveDefAntenna = 1;
138
139 /* Save hardware flag before chip reset clears the register */
140 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
141 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
142
143 /* Save led state from pci config register */
144 saveLedState = OS_REG_READ(ah, AR_MAC_LED) &
145 (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE |
146 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW);
147
148 /* For chips on which the RTC reset is done, save TSF before it gets cleared */
149 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL))
150 tsf = ar5212GetTsf64(ah);
151
152 /* Mark PHY as inactive; marked active in ar5416InitBB() */
153 ar5416MarkPhyInactive(ah);
154
155 if (!ar5416ChipReset(ah, chan)) {
156 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
157 FAIL(HAL_EIO);
158 }
159
160 /* Restore bmiss rssi & count thresholds */
161 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg);
162
163 /* Restore TSF */
164 if (tsf)
165 ar5212SetTsf64(ah, tsf);
166
167 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
168 if (AR_SREV_MERLIN_10_OR_LATER(ah))
169 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
170
171 if (AR_SREV_KITE(ah)) {
172 uint32_t val;
173 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
174 val &= ~AR_PHY_RIFS_INIT_DELAY;
175 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
176 }
177
178 AH5416(ah)->ah_writeIni(ah, chan);
179
180 /* Override ini values (that can be overriden in this fashion) */
181 ar5416OverrideIni(ah, chan);
182
183 /* Setup 11n MAC/Phy mode registers */
184 ar5416Set11nRegs(ah, chan);
185
186 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
187
188 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n",
189 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK));
190 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n",
191 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL));
192
193 /* Set the mute mask to the correct default */
194 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2)
195 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
196
197 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
198 /* Clear reg to alllow RX_CLEAR line debug */
199 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
200 }
201 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
202#ifdef notyet
203 /* Enable burst prefetch for the data queues */
204 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
205 /* Enable double-buffering */
206 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
207#endif
208 }
209
210 /*
211 * Setup ah_tx_chainmask / ah_rx_chainmask before we fiddle
212 * with enabling the TX/RX radio chains.
213 */
214 ar5416UpdateChainMasks(ah, IEEE80211_IS_CHAN_HT(chan));
215 /*
216 * This routine swaps the analog chains - it should be done
217 * before any radio register twiddling is done.
218 */
219 ar5416InitChainMasks(ah);
220 AH5416(ah)->ah_olcInit(ah);
221
222 /* Setup the transmit power values. */
223 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {
224 HALDEBUG(ah, HAL_DEBUG_ANY,
225 "%s: error init'ing transmit power\n", __func__);
226 FAIL(HAL_EIO);
227 }
228
229 /* Write the analog registers */
230 if (!ahp->ah_rfHal->setRfRegs(ah, chan,
231 IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) {
232 HALDEBUG(ah, HAL_DEBUG_ANY,
233 "%s: ar5212SetRfRegs failed\n", __func__);
234 FAIL(HAL_EIO);
235 }
236
237 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */
238 if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan))
239 ar5416SetDeltaSlope(ah, chan);
240
241 AH5416(ah)->ah_spurMitigate(ah, chan);
242
243 /* Setup board specific options for EEPROM version 3 */
244 if (!ah->ah_setBoardValues(ah, chan)) {
245 HALDEBUG(ah, HAL_DEBUG_ANY,
246 "%s: error setting board options\n", __func__);
247 FAIL(HAL_EIO);
248 }
249
250 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
251
252 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
253 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
254 | macStaId1
255 | AR_STA_ID1_RTS_USE_DEF
256 | ahp->ah_staId1Defaults
257 );
258 ar5212SetOperatingMode(ah, opmode);
259
260 /* Set Venice BSSID mask according to current state */
261 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
262 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
263
264 /* Restore previous led state */
265 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState);
266
267 /* Restore previous antenna */
268 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
269
270 /* then our BSSID */
271 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
272 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
273
274 /* Restore bmiss rssi & count thresholds */
275 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
276
277 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
278
279 if (!ar5212SetChannel(ah, chan))
280 FAIL(HAL_EIO);
281
282 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
283
284 /* Set 1:1 QCU to DCU mapping for all queues */
285 for (i = 0; i < AR_NUM_DCU; i++)
286 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
287
288 ahp->ah_intrTxqs = 0;
289 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
290 ah->ah_resetTxQueue(ah, i);
291
292 ar5416InitIMR(ah, opmode);
293 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
294 ar5416InitQoS(ah);
295 ar5416InitUserSettings(ah);
296
297 /*
298 * disable seq number generation in hw
299 */
300 OS_REG_WRITE(ah, AR_STA_ID1,
301 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
302
303 ar5416InitDMA(ah);
304
305 /*
306 * program OBS bus to see MAC interrupts
307 */
308 OS_REG_WRITE(ah, AR_OBS, 8);
309
310#ifdef AH_AR5416_INTERRUPT_MITIGATION
311 OS_REG_WRITE(ah, AR_MIRT, 0);
312
313 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
314 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
315 OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
316 OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
317#endif
318
319 ar5416InitBB(ah, chan);
320
321 /* Setup compression registers */
322 ar5212SetCompRegs(ah); /* XXX not needed? */
323
324 /*
325 * 5416 baseband will check the per rate power table
326 * and select the lower of the two
327 */
328 ackTpcPow = 63;
329 ctsTpcPow = 63;
330 chirpTpcPow = 63;
331 powerVal = SM(ackTpcPow, AR_TPC_ACK) |
332 SM(ctsTpcPow, AR_TPC_CTS) |
333 SM(chirpTpcPow, AR_TPC_CHIRP);
334 OS_REG_WRITE(ah, AR_TPC, powerVal);
335
336 if (!ar5416InitCal(ah, chan))
337 FAIL(HAL_ESELFTEST);
338
339 ar5416RestoreChainMask(ah);
340
341 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
342
343 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
344 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
345
346 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
347
348 OS_MARK(ah, AH_MARK_RESET_DONE, 0);
349
350 return AH_TRUE;
351bad:
352 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
353 if (status != AH_NULL)
354 *status = ecode;
355 return AH_FALSE;
356#undef FAIL
357#undef N
358}
359
360#if 0
361/*
362 * This channel change evaluates whether the selected hardware can
363 * perform a synthesizer-only channel change (no reset). If the
364 * TX is not stopped, or the RFBus cannot be granted in the given
365 * time, the function returns false as a reset is necessary
366 */
367HAL_BOOL
368ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan)
369{
370 uint32_t ulCount;
371 uint32_t data, synthDelay, qnum;
372 uint16_t rfXpdGain[4];
373 struct ath_hal_5212 *ahp = AH5212(ah);
374 HAL_CHANNEL_INTERNAL *ichan;
375
376 /*
377 * Map public channel to private.
378 */
379 ichan = ath_hal_checkchannel(ah, chan);
380
381 /* TX must be stopped or RF Bus grant will not work */
382 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
383 if (ar5212NumTxPending(ah, qnum)) {
384 HALDEBUG(ah, HAL_DEBUG_ANY,
385 "%s: frames pending on queue %d\n", __func__, qnum);
386 return AH_FALSE;
387 }
388 }
389
390 /*
391 * Kill last Baseband Rx Frame - Request analog bus grant
392 */
393 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST);
394 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) {
395 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n",
396 __func__);
397 return AH_FALSE;
398 }
399
400 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */
401
402 /* Change the synth */
403 if (!ar5212SetChannel(ah, chan))
404 return AH_FALSE;
405
406 /* Setup the transmit power values. */
407 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {
408 HALDEBUG(ah, HAL_DEBUG_ANY,
409 "%s: error init'ing transmit power\n", __func__);
410 return AH_FALSE;
411 }
412
413 /*
414 * Wait for the frequency synth to settle (synth goes on
415 * via PHY_ACTIVE_EN). Read the phy active delay register.
416 * Value is in 100ns increments.
417 */
418 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
419 if (IS_CHAN_CCK(ichan)) {
420 synthDelay = (4 * data) / 22;
421 } else {
422 synthDelay = data / 10;
423 }
424
425 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
426
427 /* Release the RFBus Grant */
428 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
429
430 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */
431 if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) {
432 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3);
433 ar5212SetSpurMitigation(ah, chan);
434 ar5416SetDeltaSlope(ah, chan);
435 }
436
437 /* XXX spur mitigation for Melin */
438
439 if (!IEEE80211_IS_CHAN_DFS(chan))
440 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
441
442 ichan->channel_time = 0;
443 ichan->tsf_last = ar5212GetTsf64(ah);
444 ar5212TxEnable(ah, AH_TRUE);
445 return AH_TRUE;
446}
447#endif
448
449static void
450ar5416InitDMA(struct ath_hal *ah)
451{
452 struct ath_hal_5212 *ahp = AH5212(ah);
453
454 /*
455 * set AHB_MODE not to do cacheline prefetches
456 */
457 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
458
459 /*
460 * let mac dma reads be in 128 byte chunks
461 */
462 OS_REG_WRITE(ah, AR_TXCFG,
463 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B);
464
465 /*
466 * let mac dma writes be in 128 byte chunks
467 */
468 OS_REG_WRITE(ah, AR_RXCFG,
469 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B);
470
471 /* restore TX trigger level */
472 OS_REG_WRITE(ah, AR_TXCFG,
473 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) |
474 SM(ahp->ah_txTrigLev, AR_FTRIG));
475
476 /*
477 * Setup receive FIFO threshold to hold off TX activities
478 */
479 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
480
481 /*
482 * reduce the number of usable entries in PCU TXBUF to avoid
483 * wrap around.
484 */
485 if (AR_SREV_KITE(ah))
486 /*
487 * For AR9285 the number of Fifos are reduced to half.
488 * So set the usable tx buf size also to half to
489 * avoid data/delimiter underruns
490 */
491 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
492 else
493 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
494}
495
496static void
497ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan)
498{
499 uint32_t synthDelay;
500
501 /*
502 * Wait for the frequency synth to settle (synth goes on
503 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
504 * Value is in 100ns increments.
505 */
506 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
507 if (IEEE80211_IS_CHAN_CCK(chan)) {
508 synthDelay = (4 * synthDelay) / 22;
509 } else {
510 synthDelay /= 10;
511 }
512
513 /* Turn on PLL on 5416 */
514 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n",
515 __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz");
516 ar5416InitPLL(ah, chan);
517
518 /* Activate the PHY (includes baseband activate and synthesizer on) */
519 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
520
521 /*
522 * If the AP starts the calibration before the base band timeout
523 * completes we could get rx_clear false triggering. Add an
524 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
525 * does not happen.
526 */
527 if (IEEE80211_IS_CHAN_HALF(chan)) {
528 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
529 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
530 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
531 } else {
532 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
533 }
534}
535
536static void
537ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode)
538{
539 struct ath_hal_5212 *ahp = AH5212(ah);
540
541 /*
542 * Setup interrupt handling. Note that ar5212ResetTxQueue
543 * manipulates the secondary IMR's as queues are enabled
544 * and disabled. This is done with RMW ops to insure the
545 * settings we make here are preserved.
546 */
547 ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN
548 | AR_IMR_RXERR | AR_IMR_RXORN
549 | AR_IMR_BCNMISC;
550
551#ifdef AH_AR5416_INTERRUPT_MITIGATION
552 ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM
553 | AR_IMR_TXMINTR | AR_IMR_RXMINTR;
554#else
555 ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK;
556#endif
557 if (opmode == HAL_M_HOSTAP)
558 ahp->ah_maskReg |= AR_IMR_MIB;
559 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
560 /* Enable bus errors that are OR'd to set the HIUERR bit */
561#if 0
562 OS_REG_WRITE(ah, AR_IMR_S2,
563 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);
564#endif
565}
566
567static void
568ar5416InitQoS(struct ath_hal *ah)
569{
570 /* QoS support */
571 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */
572 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */
573
574 /* Turn on NOACK Support for QoS packets */
575 OS_REG_WRITE(ah, AR_NOACK,
576 SM(2, AR_NOACK_2BIT_VALUE) |
577 SM(5, AR_NOACK_BIT_OFFSET) |
578 SM(0, AR_NOACK_BYTE_OFFSET));
579
580 /*
581 * initialize TXOP for all TIDs
582 */
583 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
584 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
585 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
586 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
587 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
588}
589
590static void
591ar5416InitUserSettings(struct ath_hal *ah)
592{
593 struct ath_hal_5212 *ahp = AH5212(ah);
594
595 /* Restore user-specified settings */
596 if (ahp->ah_miscMode != 0)
597 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
598 if (ahp->ah_sifstime != (u_int) -1)
599 ar5212SetSifsTime(ah, ahp->ah_sifstime);
600 if (ahp->ah_slottime != (u_int) -1)
601 ar5212SetSlotTime(ah, ahp->ah_slottime);
602 if (ahp->ah_acktimeout != (u_int) -1)
603 ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
604 if (ahp->ah_ctstimeout != (u_int) -1)
605 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
606 if (AH_PRIVATE(ah)->ah_diagreg != 0)
607 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
|
610}
611
612static void
613ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan)
614{
615 uint32_t rfMode;
616
617 if (chan == AH_NULL)
618 return;
619
620 /* treat channel B as channel G , no B mode suport in owl */
621 rfMode = IEEE80211_IS_CHAN_CCK(chan) ?
622 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
623
624 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
625 /* phy mode bits for 5GHz channels require Fast Clock */
626 rfMode |= AR_PHY_MODE_DYNAMIC
627 | AR_PHY_MODE_DYN_CCK_DISABLE;
628 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) {
629 rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ?
630 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
631 }
632 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
633}
634
635/*
636 * Places the hardware into reset and then pulls it out of reset
637 */
638HAL_BOOL
639ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
640{
641 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
642 /*
643 * Warm reset is optimistic.
644 */
645 if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
646 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
647 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))
648 return AH_FALSE;
649 } else {
650 if (!ar5416SetResetReg(ah, HAL_RESET_WARM))
651 return AH_FALSE;
652 }
653
654 /* Bring out of sleep mode (AGAIN) */
655 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
656 return AH_FALSE;
657
658 ar5416InitPLL(ah, chan);
659
660 /*
661 * Perform warm reset before the mode/PLL/turbo registers
662 * are changed in order to deactivate the radio. Mode changes
663 * with an active radio can result in corrupted shifts to the
664 * radio device.
665 */
666 if (chan != AH_NULL)
667 ar5416SetRfMode(ah, chan);
668
669 return AH_TRUE;
670}
671
672/*
673 * Delta slope coefficient computation.
674 * Required for OFDM operation.
675 */
676static void
677ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled,
678 uint32_t *coef_mantissa, uint32_t *coef_exponent)
679{
680#define COEF_SCALE_S 24
681 uint32_t coef_exp, coef_man;
682 /*
683 * ALGO -> coef_exp = 14-floor(log2(coef));
684 * floor(log2(x)) is the highest set bit position
685 */
686 for (coef_exp = 31; coef_exp > 0; coef_exp--)
687 if ((coef_scaled >> coef_exp) & 0x1)
688 break;
689 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */
690 HALASSERT(coef_exp);
691 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
692
693 /*
694 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5);
695 * The coefficient is already shifted up for scaling
696 */
697 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
698
699 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
700 *coef_exponent = coef_exp - 16;
701
702#undef COEF_SCALE_S
703}
704
705void
706ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan)
707{
708#define INIT_CLOCKMHZSCALED 0x64000000
709 uint32_t coef_scaled, ds_coef_exp, ds_coef_man;
710 uint32_t clockMhzScaled;
711
712 CHAN_CENTERS centers;
713
714 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */
715 /* scale for selected channel bandwidth */
716 clockMhzScaled = INIT_CLOCKMHZSCALED;
717 if (IEEE80211_IS_CHAN_TURBO(chan))
718 clockMhzScaled <<= 1;
719 else if (IEEE80211_IS_CHAN_HALF(chan))
720 clockMhzScaled >>= 1;
721 else if (IEEE80211_IS_CHAN_QUARTER(chan))
722 clockMhzScaled >>= 2;
723
724 /*
725 * ALGO -> coef = 1e8/fcarrier*fclock/40;
726 * scaled coef to provide precision for this floating calculation
727 */
728 ar5416GetChannelCenters(ah, chan, ¢ers);
729 coef_scaled = clockMhzScaled / centers.synth_center;
730
731 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
732
733 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
734 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
735 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
736 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
737
738 /*
739 * For Short GI,
740 * scaled coeff is 9/10 that of normal coeff
741 */
742 coef_scaled = (9 * coef_scaled)/10;
743
744 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
745
746 /* for short gi */
747 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
748 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
749 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
750 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
751#undef INIT_CLOCKMHZSCALED
752}
753
754/*
755 * Set a limit on the overall output power. Used for dynamic
756 * transmit power control and the like.
757 *
758 * NB: limit is in units of 0.5 dbM.
759 */
760HAL_BOOL
761ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
762{
763 uint16_t dummyXpdGains[2];
764
765 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
766 return ah->ah_setTxPower(ah, AH_PRIVATE(ah)->ah_curchan,
767 dummyXpdGains);
768}
769
770HAL_BOOL
771ar5416GetChipPowerLimits(struct ath_hal *ah,
772 struct ieee80211_channel *chan)
773{
774 struct ath_hal_5212 *ahp = AH5212(ah);
775 int16_t minPower, maxPower;
776
777 /*
778 * Get Pier table max and min powers.
779 */
780 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
781 /* NB: rf code returns 1/4 dBm units, convert */
782 chan->ic_maxpower = maxPower / 2;
783 chan->ic_minpower = minPower / 2;
784 } else {
785 HALDEBUG(ah, HAL_DEBUG_ANY,
786 "%s: no min/max power for %u/0x%x\n",
787 __func__, chan->ic_freq, chan->ic_flags);
788 chan->ic_maxpower = AR5416_MAX_RATE_POWER;
789 chan->ic_minpower = 0;
790 }
791 HALDEBUG(ah, HAL_DEBUG_RESET,
792 "Chan %d: MaxPow = %d MinPow = %d\n",
793 chan->ic_freq, chan->ic_maxpower, chan->ic_minpower);
794 return AH_TRUE;
795}
796
797/**************************************************************
798 * ar5416SetTransmitPower
799 *
800 * Set the transmit power in the baseband for the given
801 * operating channel and mode.
802 */
803HAL_BOOL
804ar5416SetTransmitPower(struct ath_hal *ah,
805 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
806{
807#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
808#define N(a) (sizeof (a) / sizeof (a[0]))
809
810 MODAL_EEP_HEADER *pModal;
811 struct ath_hal_5212 *ahp = AH5212(ah);
812 int16_t ratesArray[Ar5416RateSize];
813 int16_t txPowerIndexOffset = 0;
814 uint8_t ht40PowerIncForPdadc = 2;
815 int i;
816
817 uint16_t cfgCtl;
818 uint16_t powerLimit;
819 uint16_t twiceAntennaReduction;
820 uint16_t twiceMaxRegulatoryPower;
821 int16_t maxPower;
822 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
823 struct ar5416eeprom *pEepData = &ee->ee_base;
824
825 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
826
827 /* Setup info for the actual eeprom */
828 OS_MEMZERO(ratesArray, sizeof(ratesArray));
829 cfgCtl = ath_hal_getctl(ah, chan);
830 powerLimit = chan->ic_maxregpower * 2;
831 twiceAntennaReduction = chan->ic_maxantgain;
832 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
833 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
834 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
835 __func__,chan->ic_freq, cfgCtl );
836
837 if (IS_EEP_MINOR_V2(ah)) {
838 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
839 }
840
841 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan,
842 &ratesArray[0],cfgCtl,
843 twiceAntennaReduction,
844 twiceMaxRegulatoryPower, powerLimit)) {
845 HALDEBUG(ah, HAL_DEBUG_ANY,
846 "%s: unable to set tx power per rate table\n", __func__);
847 return AH_FALSE;
848 }
849
850 if (!AH5416(ah)->ah_setPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
851 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
852 __func__);
853 return AH_FALSE;
854 }
855
856 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
857
858 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
859 maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
860 }
861
862 if (IEEE80211_IS_CHAN_HT40(chan)) {
863 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
864 }
865
866 ahp->ah_tx6PowerInHalfDbm = maxPower;
867 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
868 ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
869
870 /*
871 * txPowerIndexOffset is set by the SetPowerTable() call -
872 * adjust the rate table (0 offset if rates EEPROM not loaded)
873 */
874 for (i = 0; i < N(ratesArray); i++) {
875 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
876 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
877 ratesArray[i] = AR5416_MAX_RATE_POWER;
878 }
879
880#ifdef AH_EEPROM_DUMP
881 /*
882 * Dump the rate array whilst it represents the intended dBm*2
883 * values versus what's being adjusted before being programmed
884 * in. Keep this in mind if you code up this function and enable
885 * this debugging; the values won't necessarily be what's being
886 * programmed into the hardware.
887 */
888 ar5416PrintPowerPerRate(ah, ratesArray);
889#endif
890
891 /*
892 * Merlin and later have a power offset, so subtract
893 * pwr_table_offset * 2 from each value. The default
894 * power offset is -5 dBm - ie, a register value of 0
895 * equates to a TX power of -5 dBm.
896 */
897 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
898 int8_t pwr_table_offset;
899
900 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET,
901 &pwr_table_offset);
902 /* Underflow power gets clamped at raw value 0 */
903 /* Overflow power gets camped at AR5416_MAX_RATE_POWER */
904 for (i = 0; i < N(ratesArray); i++) {
905 /*
906 * + pwr_table_offset is in dBm
907 * + ratesArray is in 1/2 dBm
908 */
909 ratesArray[i] -= (pwr_table_offset * 2);
910 if (ratesArray[i] < 0)
911 ratesArray[i] = 0;
912 else if (ratesArray[i] > AR5416_MAX_RATE_POWER)
913 ratesArray[i] = AR5416_MAX_RATE_POWER;
914 }
915 }
916
917 /*
918 * Adjust rates for OLC where needed
919 *
920 * The following CCK rates need adjusting when doing 2.4ghz
921 * CCK transmission.
922 *
923 * + rate2s, rate2l, rate1l, rate11s, rate11l, rate5_5s, rate5_5l
924 * + rateExtCck, rateDupCck
925 *
926 * They're adjusted here regardless. The hardware then gets
927 * programmed as needed. 5GHz operation doesn't program in CCK
928 * rates for legacy mode but they seem to be initialised for
929 * HT40 regardless of channel type.
930 */
931 if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
932 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
933 int adj[] = {
934 rate2s, rate2l, rate1l, rate11s, rate11l,
935 rate5_5s, rate5_5l, rateExtCck, rateDupCck
936 };
937 int cck_ofdm_delta = 2;
938 int i;
939 for (i = 0; i < N(adj); i++) {
940 ratesArray[i] -= cck_ofdm_delta;
941 if (ratesArray[i] < 0)
942 ratesArray[i] = 0;
943 }
944 }
945
946 /* Write the OFDM power per rate set */
947 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
948 POW_SM(ratesArray[rate18mb], 24)
949 | POW_SM(ratesArray[rate12mb], 16)
950 | POW_SM(ratesArray[rate9mb], 8)
951 | POW_SM(ratesArray[rate6mb], 0)
952 );
953 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
954 POW_SM(ratesArray[rate54mb], 24)
955 | POW_SM(ratesArray[rate48mb], 16)
956 | POW_SM(ratesArray[rate36mb], 8)
957 | POW_SM(ratesArray[rate24mb], 0)
958 );
959
960 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
961 /* Write the CCK power per rate set */
962 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
963 POW_SM(ratesArray[rate2s], 24)
964 | POW_SM(ratesArray[rate2l], 16)
965 | POW_SM(ratesArray[rateXr], 8) /* XR target power */
966 | POW_SM(ratesArray[rate1l], 0)
967 );
968 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
969 POW_SM(ratesArray[rate11s], 24)
970 | POW_SM(ratesArray[rate11l], 16)
971 | POW_SM(ratesArray[rate5_5s], 8)
972 | POW_SM(ratesArray[rate5_5l], 0)
973 );
974 HALDEBUG(ah, HAL_DEBUG_RESET,
975 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
976 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
977 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));
978 }
979
980 /* Write the HT20 power per rate set */
981 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
982 POW_SM(ratesArray[rateHt20_3], 24)
983 | POW_SM(ratesArray[rateHt20_2], 16)
984 | POW_SM(ratesArray[rateHt20_1], 8)
985 | POW_SM(ratesArray[rateHt20_0], 0)
986 );
987 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
988 POW_SM(ratesArray[rateHt20_7], 24)
989 | POW_SM(ratesArray[rateHt20_6], 16)
990 | POW_SM(ratesArray[rateHt20_5], 8)
991 | POW_SM(ratesArray[rateHt20_4], 0)
992 );
993
994 if (IEEE80211_IS_CHAN_HT40(chan)) {
995 /* Write the HT40 power per rate set */
996 /* Correct PAR difference between HT40 and HT20/LEGACY */
997 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
998 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
999 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
1000 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
1001 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
1002 );
1003 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1004 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
1005 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
1006 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
1007 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
1008 );
1009 /* Write the Dup/Ext 40 power per rate set */
1010 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1011 POW_SM(ratesArray[rateExtOfdm], 24)
1012 | POW_SM(ratesArray[rateExtCck], 16)
1013 | POW_SM(ratesArray[rateDupOfdm], 8)
1014 | POW_SM(ratesArray[rateDupCck], 0)
1015 );
1016 }
1017
1018 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
1019 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1020 POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1021 | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
1022 );
1023 return AH_TRUE;
1024#undef POW_SM
1025#undef N
1026}
1027
1028/*
1029 * Exported call to check for a recent gain reading and return
1030 * the current state of the thermal calibration gain engine.
1031 */
1032HAL_RFGAIN
1033ar5416GetRfgain(struct ath_hal *ah)
1034{
1035 return HAL_RFGAIN_INACTIVE;
1036}
1037
1038/*
1039 * Places all of hardware into reset
1040 */
1041HAL_BOOL
1042ar5416Disable(struct ath_hal *ah)
1043{
1044 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
1045 return AH_FALSE;
1046 return ar5416SetResetReg(ah, HAL_RESET_COLD);
1047}
1048
1049/*
1050 * Places the PHY and Radio chips into reset. A full reset
1051 * must be called to leave this state. The PCI/MAC/PCU are
1052 * not placed into reset as we must receive interrupt to
1053 * re-enable the hardware.
1054 */
1055HAL_BOOL
1056ar5416PhyDisable(struct ath_hal *ah)
1057{
1058 return ar5416SetResetReg(ah, HAL_RESET_WARM);
1059}
1060
1061/*
1062 * Write the given reset bit mask into the reset register
1063 */
1064HAL_BOOL
1065ar5416SetResetReg(struct ath_hal *ah, uint32_t type)
1066{
1067 switch (type) {
1068 case HAL_RESET_POWER_ON:
1069 return ar5416SetResetPowerOn(ah);
1070 case HAL_RESET_WARM:
1071 case HAL_RESET_COLD:
1072 return ar5416SetReset(ah, type);
1073 default:
1074 HALASSERT(AH_FALSE);
1075 return AH_FALSE;
1076 }
1077}
1078
1079static HAL_BOOL
1080ar5416SetResetPowerOn(struct ath_hal *ah)
1081{
1082 /* Power On Reset (Hard Reset) */
1083
1084 /*
1085 * Set force wake
1086 *
1087 * If the MAC was running, previously calling
1088 * reset will wake up the MAC but it may go back to sleep
1089 * before we can start polling.
1090 * Set force wake stops that
1091 * This must be called before initiating a hard reset.
1092 */
1093 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1094 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1095
1096 /*
1097 * RTC reset and clear
1098 */
1099 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
1100 OS_REG_WRITE(ah, AR_RTC_RESET, 0);
1101 OS_DELAY(20);
1102 OS_REG_WRITE(ah, AR_RC, 0);
1103
1104 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1105
1106 /*
1107 * Poll till RTC is ON
1108 */
1109 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) {
1110 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__);
1111 return AH_FALSE;
1112 }
1113
1114 return ar5416SetReset(ah, HAL_RESET_COLD);
1115}
1116
1117static HAL_BOOL
1118ar5416SetReset(struct ath_hal *ah, int type)
1119{
1120 uint32_t tmpReg, mask;
1121
1122 /*
1123 * Force wake
1124 */
1125 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1126 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1127
1128 /*
1129 * Reset AHB
1130 */
1131 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
1132 if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1133 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1134 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
1135 } else {
1136 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
1137 }
1138
1139 /*
1140 * Set Mac(BB,Phy) Warm Reset
1141 */
1142 switch (type) {
1143 case HAL_RESET_WARM:
1144 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM);
1145 break;
1146 case HAL_RESET_COLD:
1147 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD);
1148 break;
1149 default:
1150 HALASSERT(AH_FALSE);
1151 break;
1152 }
1153
1154 /*
1155 * Clear resets and force wakeup
1156 */
1157 OS_REG_WRITE(ah, AR_RTC_RC, 0);
1158 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1159 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__);
1160 return AH_FALSE;
1161 }
1162
1163 /* Clear AHB reset */
1164 OS_REG_WRITE(ah, AR_RC, 0);
1165
1166 if (type == HAL_RESET_COLD) {
1167 if (isBigEndian()) {
1168 /*
1169 * Set CFG, little-endian for register
1170 * and descriptor accesses.
1171 */
1172 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
1173#ifndef AH_NEED_DESC_SWAP
1174 mask |= AR_CFG_SWTD;
1175#endif
1176 HALDEBUG(ah, HAL_DEBUG_RESET,
1177 "%s Applying descriptor swap\n", __func__);
1178 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
1179 } else
1180 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
1181 }
1182
1183 ar5416InitPLL(ah, AH_NULL);
1184
1185 return AH_TRUE;
1186}
1187
1188void
1189ar5416InitChainMasks(struct ath_hal *ah)
1190{
1191 if (AH5416(ah)->ah_rx_chainmask == 0x5 ||
1192 AH5416(ah)->ah_tx_chainmask == 0x5)
1193 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
1194 /* Setup Chain Masks */
1195 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
1196 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
1197 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);
1198}
1199
1200void
1201ar5416RestoreChainMask(struct ath_hal *ah)
1202{
1203 int rx_chainmask = AH5416(ah)->ah_rx_chainmask;
1204
1205 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
1206 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1207 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1208 }
1209}
1210
1211/*
1212 * Update the chainmask based on the current channel configuration.
1213 *
1214 * XXX ath9k checks bluetooth co-existence here
1215 * XXX ath9k checks whether the current state is "off-channel".
1216 * XXX ath9k sticks the hardware into 1x1 mode for legacy;
1217 * we're going to leave multi-RX on for multi-path cancellation.
1218 */
1219static void
1220ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht)
1221{
1222 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1223 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
1224
1225 if (is_ht) {
1226 AH5416(ah)->ah_tx_chainmask = pCap->halTxChainMask;
1227 } else {
1228 AH5416(ah)->ah_tx_chainmask = 1;
1229 }
1230 AH5416(ah)->ah_rx_chainmask = pCap->halRxChainMask;
1231 HALDEBUG(ah, HAL_DEBUG_RESET, "TX chainmask: 0x%x; RX chainmask: 0x%x\n",
1232 AH5416(ah)->ah_tx_chainmask,
1233 AH5416(ah)->ah_rx_chainmask);
1234}
1235
1236#ifndef IS_5GHZ_FAST_CLOCK_EN
1237#define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE
1238#endif
1239
1240static void
1241ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
1242{
1243 uint32_t pll;
1244
1245 if (AR_SREV_MERLIN_20(ah) &&
1246 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) {
1247 /*
1248 * PLL WAR for Merlin 2.0/2.1
1249 * When doing fast clock, set PLL to 0x142c
1250 * Else, set PLL to 0x2850 to prevent reset-to-reset variation
1251 */
1252 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
1253 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1254 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1255 if (chan != AH_NULL) {
1256 if (IEEE80211_IS_CHAN_HALF(chan))
1257 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1258 else if (IEEE80211_IS_CHAN_QUARTER(chan))
1259 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
1260 else if (IEEE80211_IS_CHAN_5GHZ(chan))
1261 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
1262 else
1263 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
1264 } else
1265 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
1266 } else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
1267 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1268 if (chan != AH_NULL) {
1269 if (IEEE80211_IS_CHAN_HALF(chan))
1270 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1271 else if (IEEE80211_IS_CHAN_QUARTER(chan))
1272 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
1273 else if (IEEE80211_IS_CHAN_5GHZ(chan))
1274 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
1275 else
1276 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
1277 } else
1278 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
1279 } else {
1280 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1281 if (chan != AH_NULL) {
1282 if (IEEE80211_IS_CHAN_HALF(chan))
1283 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1284 else if (IEEE80211_IS_CHAN_QUARTER(chan))
1285 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1286 else if (IEEE80211_IS_CHAN_5GHZ(chan))
1287 pll |= SM(0xa, AR_RTC_PLL_DIV);
1288 else
1289 pll |= SM(0xb, AR_RTC_PLL_DIV);
1290 } else
1291 pll |= SM(0xb, AR_RTC_PLL_DIV);
1292 }
1293 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1294
1295 /* TODO:
1296 * For multi-band owl, switch between bands by reiniting the PLL.
1297 */
1298
1299 OS_DELAY(RTC_PLL_SETTLE_DELAY);
1300
1301 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
1302}
1303
1304static void
1305ar5416SetDefGainValues(struct ath_hal *ah,
1306 const MODAL_EEP_HEADER *pModal,
1307 const struct ar5416eeprom *eep,
1308 uint8_t txRxAttenLocal, int regChainOffset, int i)
1309{
1310 if (IS_EEP_MINOR_V3(ah)) {
1311 txRxAttenLocal = pModal->txRxAttenCh[i];
1312
1313 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
1314 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1315 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1316 pModal->bswMargin[i]);
1317 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1318 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1319 pModal->bswAtten[i]);
1320 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1321 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1322 pModal->xatten2Margin[i]);
1323 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1324 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1325 pModal->xatten2Db[i]);
1326 } else {
1327 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1328 AR_PHY_GAIN_2GHZ_BSW_MARGIN,
1329 pModal->bswMargin[i]);
1330 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1331 AR_PHY_GAIN_2GHZ_BSW_ATTEN,
1332 pModal->bswAtten[i]);
1333 }
1334 }
1335
1336 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
1337 OS_REG_RMW_FIELD(ah,
1338 AR_PHY_RXGAIN + regChainOffset,
1339 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1340 OS_REG_RMW_FIELD(ah,
1341 AR_PHY_RXGAIN + regChainOffset,
1342 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
1343 } else {
1344 OS_REG_RMW_FIELD(ah,
1345 AR_PHY_RXGAIN + regChainOffset,
1346 AR_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1347 OS_REG_RMW_FIELD(ah,
1348 AR_PHY_GAIN_2GHZ + regChainOffset,
1349 AR_PHY_GAIN_2GHZ_RXTX_MARGIN, pModal->rxTxMarginCh[i]);
1350 }
1351}
1352
1353/*
1354 * Get the register chain offset for the given chain.
1355 *
1356 * Take into account the register chain swapping with AR5416 v2.0.
1357 *
1358 * XXX make sure that the reg chain swapping is only done for
1359 * XXX AR5416 v2.0 or greater, and not later chips?
1360 */
1361int
1362ar5416GetRegChainOffset(struct ath_hal *ah, int i)
1363{
1364 int regChainOffset;
1365
1366 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1367 (AH5416(ah)->ah_rx_chainmask == 0x5 ||
1368 AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
1369 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1370 * only chains 0 and 2 populated
1371 */
1372 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1373 } else {
1374 regChainOffset = i * 0x1000;
1375 }
1376
1377 return regChainOffset;
1378}
1379
1380/*
1381 * Read EEPROM header info and program the device for correct operation
1382 * given the channel value.
1383 */
1384HAL_BOOL
1385ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
1386{
1387 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
1388 const struct ar5416eeprom *eep = &ee->ee_base;
1389 const MODAL_EEP_HEADER *pModal;
1390 int i, regChainOffset;
1391 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
1392
1393 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
1394 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
1395
1396 /* NB: workaround for eeprom versions <= 14.2 */
1397 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;
1398
1399 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
1400 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1401 if (AR_SREV_MERLIN(ah)) {
1402 if (i >= 2) break;
1403 }
1404 regChainOffset = ar5416GetRegChainOffset(ah, i);
1405
1406 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
1407
1408 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
1409 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
1410 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1411 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1412 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1413
1414 /*
1415 * Large signal upgrade.
1416 * XXX update
1417 */
1418
1419 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah))
1420 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i);
1421
1422 }
1423
1424 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
1425 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1426 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob);
1427 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db);
1428 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1);
1429 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1);
1430 } else {
1431 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob);
1432 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db);
1433 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1);
1434 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1);
1435 }
1436 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl);
1437 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS);
1438 OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON);
1439 }
1440
1441 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1442 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1443
1444 if (! AR_SREV_MERLIN_20_OR_LATER(ah))
1445 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
1446
1447 OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
1448 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1449 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1450 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1451 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1452
1453 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1454
1455 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1456 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1457 pModal->thresh62);
1458 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1459 pModal->thresh62);
1460 } else {
1461 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1462 pModal->thresh62);
1463 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62,
1464 pModal->thresh62);
1465 }
1466
1467 /* Minor Version Specific application */
1468 if (IS_EEP_MINOR_V2(ah)) {
1469 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
1470 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
1471 }
1472
1473 if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan))
1474 /* Overwrite switch settling with HT40 value */
1475 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1476
1477 if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19)
1478 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits);
1479
1480 if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) {
1481 if (IEEE80211_IS_CHAN_2GHZ(chan))
1482 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode);
1483 else if (eep->baseEepHeader.dacHiPwrMode_5G)
1484 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1485 else
1486 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode);
1487
1488 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, pModal->miscBits >> 2);
1489 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, eep->baseEepHeader.desiredScaleCCK);
1490 }
1491
1492 return AH_TRUE;
1493}
1494
1495/*
1496 * Helper functions common for AP/CB/XB
1497 */
1498
1499/*
1500 * ar5416SetPowerPerRateTable
1501 *
1502 * Sets the transmit power in the baseband for the given
1503 * operating channel and mode.
1504 */
1505static HAL_BOOL
1506ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1507 const struct ieee80211_channel *chan,
1508 int16_t *ratesArray, uint16_t cfgCtl,
1509 uint16_t AntennaReduction,
1510 uint16_t twiceMaxRegulatoryPower,
1511 uint16_t powerLimit)
1512{
1513#define N(a) (sizeof(a)/sizeof(a[0]))
1514/* Local defines to distinguish between extension and control CTL's */
1515#define EXT_ADDITIVE (0x8000)
1516#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
1517#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
1518#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
1519
1520 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1521 int i;
1522 int16_t twiceLargestAntenna;
1523 CAL_CTL_DATA *rep;
1524 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
1525 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
1526 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
1527 int16_t scaledPower, minCtlPower;
1528
1529#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
1530#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
1531 static const uint16_t ctlModesFor11a[] = {
1532 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1533 };
1534 static const uint16_t ctlModesFor11g[] = {
1535 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1536 };
1537 const uint16_t *pCtlMode;
1538 uint16_t numCtlModes, ctlMode, freq;
1539 CHAN_CENTERS centers;
1540
1541 ar5416GetChannelCenters(ah, chan, ¢ers);
1542
1543 /* Compute TxPower reduction due to Antenna Gain */
1544
1545 twiceLargestAntenna = AH_MAX(AH_MAX(
1546 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1547 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
1548 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1549#if 0
1550 /* Turn it back on if we need to calculate per chain antenna gain reduction */
1551 /* Use only if the expected gain > 6dbi */
1552 /* Chain 0 is always used */
1553 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0];
1554
1555 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */
1556 if (ahp->ah_tx_chainmask & 0x2)
1557 twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
1558 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1559
1560 if (ahp->ah_tx_chainmask & 0x4)
1561 twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
1562 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1563#endif
1564 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
1565
1566 /* XXX setup for 5212 use (really used?) */
1567 ath_hal_eepromSet(ah,
1568 IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5,
1569 twiceLargestAntenna);
1570
1571 /*
1572 * scaledPower is the minimum of the user input power level and
1573 * the regulatory allowed power level
1574 */
1575 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
1576
1577 /* Reduce scaled Power by number of chains active to get to per chain tx power level */
1578 /* TODO: better value than these? */
1579 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {
1580 case 1:
1581 break;
1582 case 2:
1583 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
1584 break;
1585 case 3:
1586 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
1587 break;
1588 default:
1589 return AH_FALSE; /* Unsupported number of chains */
1590 }
1591
1592 scaledPower = AH_MAX(0, scaledPower);
1593
1594 /* Get target powers from EEPROM - our baseline for TX Power */
1595 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1596 /* Setup for CTL modes */
1597 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
1598 pCtlMode = ctlModesFor11g;
1599
1600 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
1601 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
1602 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
1603 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1604 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
1605 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1606
1607 if (IEEE80211_IS_CHAN_HT40(chan)) {
1608 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
1609
1610 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
1611 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
1612 /* Get target powers for extension channels */
1613 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
1614 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
1615 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
1616 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
1617 }
1618 } else {
1619 /* Setup for CTL modes */
1620 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
1621 pCtlMode = ctlModesFor11a;
1622
1623 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
1624 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1625 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,
1626 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1627
1628 if (IEEE80211_IS_CHAN_HT40(chan)) {
1629 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */
1630
1631 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40,
1632 AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
1633 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
1634 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
1635 }
1636 }
1637
1638 /*
1639 * For MIMO, need to apply regulatory caps individually across dynamically
1640 * running modes: CCK, OFDM, HT20, HT40
1641 *
1642 * The outer loop walks through each possible applicable runtime mode.
1643 * The inner loop walks through each ctlIndex entry in EEPROM.
1644 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
1645 *
1646 */
1647 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1648 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1649 (pCtlMode[ctlMode] == CTL_2GHT40);
1650 if (isHt40CtlMode) {
1651 freq = centers.ctl_center;
1652 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
1653 freq = centers.ext_center;
1654 } else {
1655 freq = centers.ctl_center;
1656 }
1657
1658 /* walk through each CTL index stored in EEPROM */
1659 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1660 uint16_t twiceMinEdgePower;
1661
1662 /* compare test group from regulatory channel list with test mode from pCtlMode list */
1663 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
1664 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1665 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1666 rep = &(pEepData->ctlData[i]);
1667 twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
1668 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
1669 IEEE80211_IS_CHAN_2GHZ(chan));
1670 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1671 /* Find the minimum of all CTL edge powers that apply to this channel */
1672 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
1673 } else {
1674 /* specific */
1675 twiceMaxEdgePower = twiceMinEdgePower;
1676 break;
1677 }
1678 }
1679 }
1680 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
1681 /* Apply ctl mode to correct target power set */
1682 switch(pCtlMode[ctlMode]) {
1683 case CTL_11B:
1684 for (i = 0; i < N(targetPowerCck.tPow2x); i++) {
1685 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
1686 }
1687 break;
1688 case CTL_11A:
1689 case CTL_11G:
1690 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) {
1691 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
1692 }
1693 break;
1694 case CTL_5GHT20:
1695 case CTL_2GHT20:
1696 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
1697 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
1698 }
1699 break;
1700 case CTL_11B_EXT:
1701 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
1702 break;
1703 case CTL_11A_EXT:
1704 case CTL_11G_EXT:
1705 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
1706 break;
1707 case CTL_5GHT40:
1708 case CTL_2GHT40:
1709 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
1710 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
1711 }
1712 break;
1713 default:
1714 return AH_FALSE;
1715 break;
1716 }
1717 } /* end ctl mode checking */
1718
1719 /* Set rates Array from collected data */
1720 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
1721 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1722 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1723 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1724 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1725
1726 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
1727 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1728 }
1729
1730 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1731 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1732 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1733 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1734 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1735 }
1736 if (IEEE80211_IS_CHAN_HT40(chan)) {
1737 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
1738 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
1739 }
1740 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1741 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1742 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1743 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1744 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1745 }
1746 }
1747 return AH_TRUE;
1748#undef EXT_ADDITIVE
1749#undef CTL_11A_EXT
1750#undef CTL_11G_EXT
1751#undef CTL_11B_EXT
1752#undef SUB_NUM_CTL_MODES_AT_5G_40
1753#undef SUB_NUM_CTL_MODES_AT_2G_40
1754#undef N
1755}
1756
1757/**************************************************************************
1758 * fbin2freq
1759 *
1760 * Get channel value from binary representation held in eeprom
1761 * RETURNS: the frequency in MHz
1762 */
1763static uint16_t
1764fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
1765{
1766 /*
1767 * Reserved value 0xFF provides an empty definition both as
1768 * an fbin and as a frequency - do not convert
1769 */
1770 if (fbin == AR5416_BCHAN_UNUSED) {
1771 return fbin;
1772 }
1773
1774 return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1775}
1776
1777/*
1778 * ar5416GetMaxEdgePower
1779 *
1780 * Find the maximum conformance test limit for the given channel and CTL info
1781 */
1782uint16_t
1783ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
1784{
1785 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1786 int i;
1787
1788 /* Get the edge power */
1789 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
1790 /*
1791 * If there's an exact channel match or an inband flag set
1792 * on the lower channel use the given rdEdgePower
1793 */
1794 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
1795 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
1796 break;
1797 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) {
1798 if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
1799 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
1800 }
1801 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
1802 break;
1803 }
1804 }
1805 HALASSERT(twiceMaxEdgePower > 0);
1806 return twiceMaxEdgePower;
1807}
1808
1809/**************************************************************
1810 * ar5416GetTargetPowers
1811 *
1812 * Return the rates of target power for the given target power table
1813 * channel, and number of channels
1814 */
1815void
1816ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
1817 CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels,
1818 CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates,
1819 HAL_BOOL isHt40Target)
1820{
1821 uint16_t clo, chi;
1822 int i;
1823 int matchIndex = -1, lowIndex = -1;
1824 uint16_t freq;
1825 CHAN_CENTERS centers;
1826
1827 ar5416GetChannelCenters(ah, chan, ¢ers);
1828 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
1829
1830 /* Copy the target powers into the temp channel list */
1831 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1832 matchIndex = 0;
1833 } else {
1834 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
1835 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1836 matchIndex = i;
1837 break;
1838 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) &&
1839 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))))
1840 {
1841 lowIndex = i - 1;
1842 break;
1843 }
1844 }
1845 if ((matchIndex == -1) && (lowIndex == -1)) {
1846 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)));
1847 matchIndex = i - 1;
1848 }
1849 }
1850
1851 if (matchIndex != -1) {
1852 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower));
1853 } else {
1854 HALASSERT(lowIndex != -1);
1855 /*
1856 * Get the lower and upper channels, target powers,
1857 * and interpolate between them.
1858 */
1859 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1860 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1861
1862 for (i = 0; i < numRates; i++) {
1863 pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi,
1864 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]);
1865 }
1866 }
1867}
1868/**************************************************************
1869 * ar5416GetTargetPowersLeg
1870 *
1871 * Return the four rates of target power for the given target power table
1872 * channel, and number of channels
1873 */
1874void
1875ar5416GetTargetPowersLeg(struct ath_hal *ah,
1876 const struct ieee80211_channel *chan,
1877 CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels,
1878 CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates,
1879 HAL_BOOL isExtTarget)
1880{
1881 uint16_t clo, chi;
1882 int i;
1883 int matchIndex = -1, lowIndex = -1;
1884 uint16_t freq;
1885 CHAN_CENTERS centers;
1886
1887 ar5416GetChannelCenters(ah, chan, ¢ers);
1888 freq = (isExtTarget) ? centers.ext_center :centers.ctl_center;
1889
1890 /* Copy the target powers into the temp channel list */
1891 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1892 matchIndex = 0;
1893 } else {
1894 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
1895 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1896 matchIndex = i;
1897 break;
1898 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) &&
1899 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))))
1900 {
1901 lowIndex = i - 1;
1902 break;
1903 }
1904 }
1905 if ((matchIndex == -1) && (lowIndex == -1)) {
1906 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)));
1907 matchIndex = i - 1;
1908 }
1909 }
1910
1911 if (matchIndex != -1) {
1912 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower));
1913 } else {
1914 HALASSERT(lowIndex != -1);
1915 /*
1916 * Get the lower and upper channels, target powers,
1917 * and interpolate between them.
1918 */
1919 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1920 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1921
1922 for (i = 0; i < numRates; i++) {
1923 pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi,
1924 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]);
1925 }
1926 }
1927}
1928
1929/*
1930 * Set the gain boundaries for the given radio chain.
1931 *
1932 * The gain boundaries tell the hardware at what point in the
1933 * PDADC array to "switch over" from one PD gain setting
1934 * to another. There's also a gain overlap between two
1935 * PDADC array gain curves where there's valid PD values
1936 * for 2 gain settings.
1937 *
1938 * The hardware uses the gain overlap and gain boundaries
1939 * to determine which gain curve to use for the given
1940 * target TX power.
1941 */
1942void
1943ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i,
1944 uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[])
1945{
1946 int regChainOffset;
1947
1948 regChainOffset = ar5416GetRegChainOffset(ah, i);
1949
1950 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: gainOverlap_t2: %d,"
1951 " gainBoundaries: %d, %d, %d, %d\n", __func__, i, pdGainOverlap_t2,
1952 gainBoundaries[0], gainBoundaries[1], gainBoundaries[2],
1953 gainBoundaries[3]);
1954 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
1955 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
1956 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
1957 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
1958 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
1959 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1960}
1961
1962/*
1963 * Get the gain values and the number of gain levels given
1964 * in xpdMask.
1965 *
1966 * The EEPROM xpdMask determines which power detector gain
1967 * levels were used during calibration. Each of these mask
1968 * bits maps to a fixed gain level in hardware.
1969 */
1970uint16_t
1971ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask,
1972 uint16_t xpdGainValues[])
1973{
1974 int i;
1975 uint16_t numXpdGain = 0;
1976
1977 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
1978 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
1979 if (numXpdGain >= AR5416_NUM_PD_GAINS) {
1980 HALASSERT(0);
1981 break;
1982 }
1983 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
1984 numXpdGain++;
1985 }
1986 }
1987 return numXpdGain;
1988}
1989
1990/*
1991 * Write the detector gain and biases.
1992 *
1993 * There are four power detector gain levels. The xpdMask in the EEPROM
1994 * determines which power detector gain levels have TX power calibration
1995 * data associated with them. This function writes the number of
1996 * PD gain levels and their values into the hardware.
1997 *
1998 * This is valid for all TX chains - the calibration data itself however
1999 * will likely differ per-chain.
2000 */
2001void
2002ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain,
2003 uint16_t xpdGainValues[])
2004{
2005 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: numXpdGain: %d,"
2006 " xpdGainValues: %d, %d, %d\n", __func__, numXpdGain,
2007 xpdGainValues[0], xpdGainValues[1], xpdGainValues[2]);
2008
2009 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
2010 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 |
2011 AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
2012 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) |
2013 SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
2014 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) |
2015 SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
2016}
2017
2018/*
2019 * Write the PDADC array to the given radio chain i.
2020 *
2021 * The 32 PDADC registers are written without any care about
2022 * their contents - so if various chips treat values as "special",
2023 * this routine will not care.
2024 */
2025void
2026ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[])
2027{
2028 int regOffset, regChainOffset;
2029 int j;
2030 int reg32;
2031
2032 regChainOffset = ar5416GetRegChainOffset(ah, i);
2033 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2034
2035 for (j = 0; j < 32; j++) {
2036 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) |
2037 ((pdadcValues[4*j + 1] & 0xFF) << 8) |
2038 ((pdadcValues[4*j + 2] & 0xFF) << 16) |
2039 ((pdadcValues[4*j + 3] & 0xFF) << 24) ;
2040 OS_REG_WRITE(ah, regOffset, reg32);
2041 HALDEBUG(ah, HAL_DEBUG_EEPROM, "PDADC: Chain %d |"
2042 " PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d"
2043 " Value %3d | PDADC %3d Value %3d |\n",
2044 i,
2045 4*j, pdadcValues[4*j],
2046 4*j+1, pdadcValues[4*j + 1],
2047 4*j+2, pdadcValues[4*j + 2],
2048 4*j+3, pdadcValues[4*j + 3]);
2049 regOffset += 4;
2050 }
2051}
2052
2053/**************************************************************
2054 * ar5416SetPowerCalTable
2055 *
2056 * Pull the PDADC piers from cal data and interpolate them across the given
2057 * points as well as from the nearest pier(s) to get a power detector
2058 * linear voltage to power level table.
2059 */
2060HAL_BOOL
2061ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
2062 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
2063{
2064 CAL_DATA_PER_FREQ *pRawDataset;
2065 uint8_t *pCalBChans = AH_NULL;
2066 uint16_t pdGainOverlap_t2;
2067 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
2068 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2069 uint16_t numPiers, i;
2070 int16_t tMinCalPower;
2071 uint16_t numXpdGain, xpdMask;
2072 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
2073 uint32_t regChainOffset;
2074
2075 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
2076
2077 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
2078
2079 if (IS_EEP_MINOR_V2(ah)) {
2080 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
2081 } else {
2082 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2083 }
2084
2085 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2086 pCalBChans = pEepData->calFreqPier2G;
2087 numPiers = AR5416_NUM_2G_CAL_PIERS;
2088 } else {
2089 pCalBChans = pEepData->calFreqPier5G;
2090 numPiers = AR5416_NUM_5G_CAL_PIERS;
2091 }
2092
2093 /* Calculate the value of xpdgains from the xpdGain Mask */
2094 numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues);
2095
2096 /* Write the detector gain biases and their number */
2097 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues);
2098
2099 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2100 regChainOffset = ar5416GetRegChainOffset(ah, i);
2101
2102 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2103 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
2104 pRawDataset = pEepData->calPierData2G[i];
2105 } else {
2106 pRawDataset = pEepData->calPierData5G[i];
2107 }
2108
2109 /* Fetch the gain boundaries and the PDADC values */
2110 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
2111 pCalBChans, numPiers,
2112 pdGainOverlap_t2,
2113 &tMinCalPower, gainBoundaries,
2114 pdadcValues, numXpdGain);
2115
2116 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
2117 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2,
2118 gainBoundaries);
2119 }
2120
2121 /* Write the power values into the baseband power table */
2122 ar5416WritePdadcValues(ah, i, pdadcValues);
2123 }
2124 }
2125 *pTxPowerIndexOffset = 0;
2126
2127 return AH_TRUE;
2128}
2129
2130/**************************************************************
2131 * ar5416GetGainBoundariesAndPdadcs
2132 *
2133 * Uses the data points read from EEPROM to reconstruct the pdadc power table
2134 * Called by ar5416SetPowerCalTable only.
2135 */
2136void
2137ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
2138 const struct ieee80211_channel *chan,
2139 CAL_DATA_PER_FREQ *pRawDataSet,
2140 uint8_t * bChans, uint16_t availPiers,
2141 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
2142 uint8_t * pPDADCValues, uint16_t numXpdGains)
2143{
2144
2145 int i, j, k;
2146 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
2147 uint16_t idxL, idxR, numPiers; /* Pier indexes */
2148
2149 /* filled out Vpd table for all pdGains (chanL) */
2150 static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2151
2152 /* filled out Vpd table for all pdGains (chanR) */
2153 static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2154
2155 /* filled out Vpd table for all pdGains (interpolated) */
2156 static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2157
2158 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
2159 uint8_t minPwrT4[AR5416_NUM_PD_GAINS];
2160 uint8_t maxPwrT4[AR5416_NUM_PD_GAINS];
2161 int16_t vpdStep;
2162 int16_t tmpVal;
2163 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
2164 HAL_BOOL match;
2165 int16_t minDelta = 0;
2166 CHAN_CENTERS centers;
2167
2168 ar5416GetChannelCenters(ah, chan, ¢ers);
2169
2170 /* Trim numPiers for the number of populated channel Piers */
2171 for (numPiers = 0; numPiers < availPiers; numPiers++) {
2172 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
2173 break;
2174 }
2175 }
2176
2177 /* Find pier indexes around the current channel */
2178 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center,
2179 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR);
2180
2181 if (match) {
2182 /* Directly fill both vpd tables from the matching index */
2183 for (i = 0; i < numXpdGains; i++) {
2184 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2185 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2186 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i],
2187 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
2188 }
2189 } else {
2190 for (i = 0; i < numXpdGains; i++) {
2191 pVpdL = pRawDataSet[idxL].vpdPdg[i];
2192 pPwrL = pRawDataSet[idxL].pwrPdg[i];
2193 pVpdR = pRawDataSet[idxR].vpdPdg[i];
2194 pPwrR = pRawDataSet[idxR].pwrPdg[i];
2195
2196 /* Start Vpd interpolation from the max of the minimum powers */
2197 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
2198
2199 /* End Vpd interpolation from the min of the max powers */
2200 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2201 HALASSERT(maxPwrT4[i] > minPwrT4[i]);
2202
2203 /* Fill pier Vpds */
2204 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
2205 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
2206
2207 /* Interpolate the final vpd */
2208 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
2209 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center,
2210 IEEE80211_IS_CHAN_2GHZ(chan)),
2211 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
2212 }
2213 }
2214 }
2215 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2216
2217 k = 0; /* index for the final table */
2218 for (i = 0; i < numXpdGains; i++) {
2219 if (i == (numXpdGains - 1)) {
2220 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
2221 } else {
2222 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
2223 }
2224
2225 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2226
2227 /* NB: only applies to owl 1.0 */
2228 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
2229 /*
2230 * fix the gain delta, but get a delta that can be applied to min to
2231 * keep the upper power values accurate, don't think max needs to
2232 * be adjusted because should not be at that area of the table?
2233 */
2234 minDelta = pPdGainBoundaries[0] - 23;
2235 pPdGainBoundaries[0] = 23;
2236 }
2237 else {
2238 minDelta = 0;
2239 }
2240
2241 /* Find starting index for this pdGain */
2242 if (i == 0) {
2243 if (AR_SREV_MERLIN_20_OR_LATER(ah))
2244 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2245 else
2246 ss = 0; /* for the first pdGain, start from index 0 */
2247 } else {
2248 /* need overlap entries extrapolated below. */
2249 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
2250 }
2251 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2252 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2253 /*
2254 *-ve ss indicates need to extrapolate data below for this pdGain
2255 */
2256 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2257 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2258 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
2259 ss++;
2260 }
2261
2262 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
2263 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
2264 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
2265
2266 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2267 pPDADCValues[k++] = vpdTableI[i][ss++];
2268 }
2269
2270 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
2271 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2272 /*
2273 * for last gain, pdGainBoundary == Pmax_t2, so will
2274 * have to extrapolate
2275 */
2276 if (tgtIndex >= maxIndex) { /* need to extrapolate above */
2277 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2278 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2279 (ss - maxIndex +1) * vpdStep));
2280 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
2281 ss++;
2282 }
2283 } /* extrapolated above */
2284 } /* for all pdGainUsed */
2285
2286 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
2287 while (i < AR5416_PD_GAINS_IN_MASK) {
2288 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
2289 i++;
2290 }
2291
2292 while (k < AR5416_NUM_PDADC_VALUES) {
2293 pPDADCValues[k] = pPDADCValues[k-1];
2294 k++;
2295 }
2296 return;
2297}
2298
2299/*
2300 * The linux ath9k driver and (from what I've been told) the reference
2301 * Atheros driver enables the 11n PHY by default whether or not it's
2302 * configured.
2303 */
2304static void
2305ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)
2306{
2307 uint32_t phymode;
2308 uint32_t enableDacFifo = 0;
2309 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */
2310
2311 if (AR_SREV_KITE_10_OR_LATER(ah))
2312 enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO);
2313
2314 /* Enable 11n HT, 20 MHz */
2315 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
2316 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
2317
2318 /* Configure baseband for dynamic 20/40 operation */
2319 if (IEEE80211_IS_CHAN_HT40(chan)) {
2320 phymode |= AR_PHY_FC_DYN2040_EN;
2321
2322 /* Configure control (primary) channel at +-10MHz */
2323 if (IEEE80211_IS_CHAN_HT40U(chan))
2324 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
2325#if 0
2326 /* Configure 20/25 spacing */
2327 if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25)
2328 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
2329#endif
2330 macmode = HAL_HT_MACMODE_2040;
2331 } else
2332 macmode = HAL_HT_MACMODE_20;
2333 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode);
2334
2335 /* Configure MAC for 20/40 operation */
2336 ar5416Set11nMac2040(ah, macmode);
2337
2338 /* global transmit timeout (25 TUs default)*/
2339 /* XXX - put this elsewhere??? */
2340 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ;
2341
2342 /* carrier sense timeout */
2343 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC);
2344 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
2345}
2346
2347void
2348ar5416GetChannelCenters(struct ath_hal *ah,
2349 const struct ieee80211_channel *chan, CHAN_CENTERS *centers)
2350{
2351 uint16_t freq = ath_hal_gethwchannel(ah, chan);
2352
2353 centers->ctl_center = freq;
2354 centers->synth_center = freq;
2355 /*
2356 * In 20/40 phy mode, the center frequency is
2357 * "between" the control and extension channels.
2358 */
2359 if (IEEE80211_IS_CHAN_HT40U(chan)) {
2360 centers->synth_center += HT40_CHANNEL_CENTER_SHIFT;
2361 centers->ext_center =
2362 centers->synth_center + HT40_CHANNEL_CENTER_SHIFT;
2363 } else if (IEEE80211_IS_CHAN_HT40D(chan)) {
2364 centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT;
2365 centers->ext_center =
2366 centers->synth_center - HT40_CHANNEL_CENTER_SHIFT;
2367 } else {
2368 centers->ext_center = freq;
2369 }
2370}
2371
2372/*
2373 * Override the INI vals being programmed.
2374 */
2375static void
2376ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
2377{
2378 uint32_t val;
2379
2380 /*
2381 * Set the RX_ABORT and RX_DIS and clear if off only after
2382 * RXE is set for MAC. This prevents frames with corrupted
2383 * descriptor status.
2384 */
2385 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
2386
2387 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
2388 val = OS_REG_READ(ah, AR_PCU_MISC_MODE2);
2389
2390 if (!AR_SREV_9271(ah))
2391 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
2392
2393 if (AR_SREV_9287_11_OR_LATER(ah))
2394 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
2395
2396 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
2397 }
2398
2399 /*
2400 * The AR5416 initvals have this already set to 0x11; AR9160 has
2401 * the register set to 0x0. Figure out whether AR9100/AR9160 needs
2402 * this before moving forward with it.
2403 */
2404#if 0
2405 /* Disable BB clock gating for AR5416v2, AR9100, AR9160 */
2406 if (AR_SREV_OWL_20_OR_LATER(ah) || AR_SREV_9100(ah) || AR_SREV_SOWL(ah)) {
2407 /*
2408 * Disable BB clock gating
2409 * Necessary to avoid issues on AR5416 2.0
2410 */
2411 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
2412 }
2413#endif
2414
2415 /*
2416 * Disable RIFS search on some chips to avoid baseband
2417 * hang issues.
2418 */
2419 if (AR_SREV_9100(ah) || AR_SREV_SOWL(ah)) {
2420 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
2421 val &= ~AR_PHY_RIFS_INIT_DELAY;
2422 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
2423 }
2424}
2425
2426struct ini {
2427 uint32_t *data; /* NB: !const */
2428 int rows, cols;
2429};
2430
2431/*
2432 * Override XPA bias level based on operating frequency.
2433 * This is a v14 EEPROM specific thing for the AR9160.
2434 */
2435void
2436ar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan)
2437{
2438#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
2439 MODAL_EEP_HEADER *pModal;
2440 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
2441 struct ar5416eeprom *eep = &ee->ee_base;
2442 uint8_t biaslevel;
2443
2444 if (! AR_SREV_SOWL(ah))
2445 return;
2446
2447 if (EEP_MINOR(ah) < AR5416_EEP_MINOR_VER_7)
2448 return;
2449
2450 pModal = &(eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]);
2451
2452 if (pModal->xpaBiasLvl != 0xff)
2453 biaslevel = pModal->xpaBiasLvl;
2454 else {
2455 uint16_t resetFreqBin, freqBin, freqCount = 0;
2456 CHAN_CENTERS centers;
2457
2458 ar5416GetChannelCenters(ah, chan, ¢ers);
2459
2460 resetFreqBin = FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan));
2461 freqBin = XPA_LVL_FREQ(0) & 0xff;
2462 biaslevel = (uint8_t) (XPA_LVL_FREQ(0) >> 14);
2463
2464 freqCount++;
2465
2466 while (freqCount < 3) {
2467 if (XPA_LVL_FREQ(freqCount) == 0x0)
2468 break;
2469
2470 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
2471 if (resetFreqBin >= freqBin)
2472 biaslevel = (uint8_t)(XPA_LVL_FREQ(freqCount) >> 14);
2473 else
2474 break;
2475 freqCount++;
2476 }
2477 }
2478
2479 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: overriding XPA bias level = %d\n",
2480 __func__, biaslevel);
2481
2482 /*
2483 * This is a dirty workaround for the const initval data,
2484 * which will upset multiple AR9160's on the same board.
2485 *
2486 * The HAL should likely just have a private copy of the addac
2487 * data per instance.
2488 */
2489 if (IEEE80211_IS_CHAN_2GHZ(chan))
2490 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 7, 1) =
2491 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3;
2492 else
2493 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 6, 1) =
2494 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6;
2495#undef XPA_LVL_FREQ
2496}
2497
2498static void
2499ar5416MarkPhyInactive(struct ath_hal *ah)
2500{
2501 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2502}
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