| ar5416_misc.c (234752) | ar5416_misc.c (234873) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * | 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * |
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c 234752 2012-04-28 08:29:46Z adrian $ | 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c 234873 2012-05-01 14:48:51Z adrian $ |
| 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 25 --- 153 unchanged lines hidden (view full) --- 179ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 180{ 181 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 182} 183 184/* 185 * Return the busy for rx_frame, rx_clear, and tx_frame 186 */ | 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 25 --- 153 unchanged lines hidden (view full) --- 179ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 180{ 181 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 182} 183 184/* 185 * Return the busy for rx_frame, rx_clear, and tx_frame 186 */ |
| 187uint32_t | 187HAL_BOOL |
| 188ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) 189{ 190 struct ath_hal_5416 *ahp = AH5416(ah); | 188ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) 189{ 190 struct ath_hal_5416 *ahp = AH5416(ah); |
| 191 u_int32_t good = 1; | 191 u_int32_t good = AH_TRUE; |
| 192 193 /* XXX freeze/unfreeze mib counters */ 194 uint32_t rc = OS_REG_READ(ah, AR_RCCNT); 195 uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT); 196 uint32_t rf = OS_REG_READ(ah, AR_RFCNT); 197 uint32_t tf = OS_REG_READ(ah, AR_TFCNT); 198 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 199 200 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) { 201 /* 202 * Cycle counter wrap (or initial call); it's not possible 203 * to accurately calculate a value because the registers 204 * right shift rather than wrap--so punt and return 0. 205 */ 206 HALDEBUG(ah, HAL_DEBUG_ANY, 207 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); | 192 193 /* XXX freeze/unfreeze mib counters */ 194 uint32_t rc = OS_REG_READ(ah, AR_RCCNT); 195 uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT); 196 uint32_t rf = OS_REG_READ(ah, AR_RFCNT); 197 uint32_t tf = OS_REG_READ(ah, AR_TFCNT); 198 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 199 200 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) { 201 /* 202 * Cycle counter wrap (or initial call); it's not possible 203 * to accurately calculate a value because the registers 204 * right shift rather than wrap--so punt and return 0. 205 */ 206 HALDEBUG(ah, HAL_DEBUG_ANY, 207 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); |
| 208 good = 0; | 208 good = AH_FALSE; |
| 209 } else { 210 hsample->cycle_count = cc - ahp->ah_cycleCount; 211 hsample->chan_busy = rc - ahp->ah_ctlBusy; 212 hsample->ext_chan_busy = ec - ahp->ah_extBusy; 213 hsample->rx_busy = rf - ahp->ah_rxBusy; 214 hsample->tx_busy = tf - ahp->ah_txBusy; 215 } 216 217 /* 218 * Keep a copy of the MIB results so the next sample has something 219 * to work from. 220 */ 221 ahp->ah_cycleCount = cc; 222 ahp->ah_rxBusy = rf; 223 ahp->ah_ctlBusy = rc; 224 ahp->ah_txBusy = tf; 225 ahp->ah_extBusy = ec; 226 | 209 } else { 210 hsample->cycle_count = cc - ahp->ah_cycleCount; 211 hsample->chan_busy = rc - ahp->ah_ctlBusy; 212 hsample->ext_chan_busy = ec - ahp->ah_extBusy; 213 hsample->rx_busy = rf - ahp->ah_rxBusy; 214 hsample->tx_busy = tf - ahp->ah_txBusy; 215 } 216 217 /* 218 * Keep a copy of the MIB results so the next sample has something 219 * to work from. 220 */ 221 ahp->ah_cycleCount = cc; 222 ahp->ah_rxBusy = rf; 223 ahp->ah_ctlBusy = rc; 224 ahp->ah_txBusy = tf; 225 ahp->ah_extBusy = ec; 226 |
| 227 return good; | 227 return (good); |
| 228} 229 230/* 231 * Return approximation of extension channel busy over an time interval 232 * 0% (clear) -> 100% (busy) 233 * 234 * XXX TODO: update this to correctly sample all the counters, 235 * rather than a subset of it. --- 484 unchanged lines hidden --- | 228} 229 230/* 231 * Return approximation of extension channel busy over an time interval 232 * 0% (clear) -> 100% (busy) 233 * 234 * XXX TODO: update this to correctly sample all the counters, 235 * rather than a subset of it. --- 484 unchanged lines hidden --- |