18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63} 64 65/* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68static void 69ar5416olcInit(struct ath_hal *ah) 70{ 71} 72 73static void 74ar5416olcTempCompensation(struct ath_hal *ah) 75{ 76} 77 78/* 79 * Attach for an AR5416 part. 80 */ 81void 82ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84{ 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_startPcuReceive = ar5416StartPcuReceive; 121 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 122 ah->ah_setupRxDesc = ar5416SetupRxDesc; 123 ah->ah_procRxDesc = ar5416ProcRxDesc; 124 ah->ah_rxMonitor = ar5416RxMonitor; 125 ah->ah_aniPoll = ar5416AniPoll; 126 ah->ah_procMibEvent = ar5416ProcessMibIntr; 127 128 /* Misc Functions */ 129 ah->ah_getCapability = ar5416GetCapability; 130 ah->ah_getDiagState = ar5416GetDiagState; 131 ah->ah_setLedState = ar5416SetLedState; 132 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 133 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 134 ah->ah_gpioGet = ar5416GpioGet; 135 ah->ah_gpioSet = ar5416GpioSet; 136 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 137 ah->ah_resetTsf = ar5416ResetTsf; 138 ah->ah_getRfGain = ar5416GetRfgain; 139 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 140 ah->ah_setDecompMask = ar5416SetDecompMask; 141 ah->ah_setCoverageClass = ar5416SetCoverageClass; 142 143 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 144 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 145 146 /* Power Management Functions */ 147 ah->ah_setPowerMode = ar5416SetPowerMode; 148 149 /* Beacon Management Functions */ 150 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 151 ah->ah_beaconInit = ar5416BeaconInit; 152 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 153 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 154 155 /* 802.11n Functions */ 156 ah->ah_chainTxDesc = ar5416ChainTxDesc; 157 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 158 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 159 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 160 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 161 ah->ah_clr11nAggr = ar5416Clr11nAggr; 162 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 163 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 164 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 165 ah->ah_get11nRxClear = ar5416Get11nRxClear; 166 ah->ah_set11nRxClear = ar5416Set11nRxClear; 167 168 /* Interrupt functions */ 169 ah->ah_isInterruptPending = ar5416IsInterruptPending; 170 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 171 ah->ah_setInterrupts = ar5416SetInterrupts; 172 173 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 174 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 175#ifdef AH_SUPPORT_WRITE_EEPROM 176 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 177#endif 178 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 179 180 /* Internal ops */ 181 AH5416(ah)->ah_writeIni = ar5416WriteIni; 182 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 183 184 /* Internal baseband ops */ 185 AH5416(ah)->ah_initPLL = ar5416InitPLL; 186 187 /* Internal calibration ops */ 188 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 189 190 /* Internal TX power control related operations */ 191 AH5416(ah)->ah_olcInit = ar5416olcInit; 192 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 193 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 194 195 /* 196 * Start by setting all Owl devices to 2x2 197 */ 198 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 199 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 200 201 /* Enable all ANI functions to begin with */ 202 AH5416(ah)->ah_ani_function = HAL_ANI_ALL;
|
206} 207 208uint32_t 209ar5416GetRadioRev(struct ath_hal *ah) 210{ 211 uint32_t val; 212 int i; 213 214 /* Read Radio Chip Rev Extract */ 215 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 216 for (i = 0; i < 8; i++) 217 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 218 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 219 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 220 return ath_hal_reverseBits(val, 8); 221} 222 223/* 224 * Attach for an AR5416 part. 225 */ 226static struct ath_hal * 227ar5416Attach(uint16_t devid, HAL_SOFTC sc, 228 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 229 HAL_STATUS *status) 230{ 231 struct ath_hal_5416 *ahp5416; 232 struct ath_hal_5212 *ahp; 233 struct ath_hal *ah; 234 uint32_t val; 235 HAL_STATUS ecode; 236 HAL_BOOL rfStatus; 237 238 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 239 __func__, sc, (void*) st, (void*) sh); 240 241 /* NB: memory is returned zero'd */ 242 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 243 /* extra space for Owl 2.1/2.2 WAR */ 244 sizeof(ar5416Addac) 245 ); 246 if (ahp5416 == AH_NULL) { 247 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 248 "%s: cannot allocate memory for state block\n", __func__); 249 *status = HAL_ENOMEM; 250 return AH_NULL; 251 } 252 ar5416InitState(ahp5416, devid, sc, st, sh, status); 253 ahp = &ahp5416->ah_5212; 254 ah = &ahp->ah_priv.h; 255 256 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 257 /* reset chip */ 258 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 259 ecode = HAL_EIO; 260 goto bad; 261 } 262 263 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 264 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 265 ecode = HAL_EIO; 266 goto bad; 267 } 268 /* Read Revisions from Chips before taking out of reset */ 269 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 270 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 271 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 272 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 273 274 /* setup common ini data; rf backends handle remainder */ 275 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 276 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 277 278 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 279 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 280 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 281 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 282 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 283 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 284 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 285 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 286 287 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 288 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 289 struct ini { 290 uint32_t *data; /* NB: !const */ 291 int rows, cols; 292 }; 293 /* override CLKDRV value */ 294 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 295 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 296 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 297 } 298 299 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 300 ar5416AttachPCIE(ah); 301 302 ecode = ath_hal_v14EepromAttach(ah); 303 if (ecode != HAL_OK) 304 goto bad; 305 306 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 307 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 308 __func__); 309 ecode = HAL_EIO; 310 goto bad; 311 } 312 313 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 314 315 if (!ar5212ChipTest(ah)) { 316 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 317 __func__); 318 ecode = HAL_ESELFTEST; 319 goto bad; 320 } 321 322 /* 323 * Set correct Baseband to analog shift 324 * setting to access analog chips. 325 */ 326 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 327 328 /* Read Radio Chip Rev Extract */ 329 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 330 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 331 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 332 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 333 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 334 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 335 break; 336 default: 337 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 338 /* 339 * When RF_Silen is used the analog chip is reset. 340 * So when the system boots with radio switch off 341 * the RF chip rev reads back as zero and we need 342 * to use the mac+phy revs to set the radio rev. 343 */ 344 AH_PRIVATE(ah)->ah_analog5GhzRev = 345 AR_RAD5133_SREV_MAJOR; 346 break; 347 } 348 /* NB: silently accept anything in release code per Atheros */ 349#ifdef AH_DEBUG 350 HALDEBUG(ah, HAL_DEBUG_ANY, 351 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 352 "this driver\n", __func__, 353 AH_PRIVATE(ah)->ah_analog5GhzRev); 354 ecode = HAL_ENOTSUPP; 355 goto bad; 356#endif 357 } 358 359 /* 360 * Got everything we need now to setup the capabilities. 361 */ 362 if (!ar5416FillCapabilityInfo(ah)) { 363 ecode = HAL_EEREAD; 364 goto bad; 365 } 366 367 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 368 if (ecode != HAL_OK) { 369 HALDEBUG(ah, HAL_DEBUG_ANY, 370 "%s: error getting mac address from EEPROM\n", __func__); 371 goto bad; 372 } 373 /* XXX How about the serial number ? */ 374 /* Read Reg Domain */ 375 AH_PRIVATE(ah)->ah_currentRD = 376 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 377 AH_PRIVATE(ah)->ah_currentRDext = 378 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 379 380 /* 381 * ah_miscMode is populated by ar5416FillCapabilityInfo() 382 * starting from griffin. Set here to make sure that 383 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 384 * placed into hardware. 385 */ 386 if (ahp->ah_miscMode != 0) 387 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 388 389 rfStatus = ar2133RfAttach(ah, &ecode); 390 if (!rfStatus) { 391 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 392 __func__, ecode); 393 goto bad; 394 } 395 396 ar5416AniSetup(ah); /* Anti Noise Immunity */ 397 398 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 399 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 400 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 401 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 402 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 403 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 404 405 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 406 407 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 408 409 return ah; 410bad: 411 if (ahp) 412 ar5416Detach((struct ath_hal *) ahp); 413 if (status) 414 *status = ecode; 415 return AH_NULL; 416} 417 418void 419ar5416Detach(struct ath_hal *ah) 420{ 421 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 422 423 HALASSERT(ah != AH_NULL); 424 HALASSERT(ah->ah_magic == AR5416_MAGIC); 425 426 /* Make sure that chip is awake before writing to it */ 427 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 428 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 429 "%s: failed to wake up chip\n", 430 __func__); 431 432 ar5416AniDetach(ah); 433 ar5212RfDetach(ah); 434 ah->ah_disable(ah); 435 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 436 ath_hal_eepromDetach(ah); 437 ath_hal_free(ah); 438} 439 440void 441ar5416AttachPCIE(struct ath_hal *ah) 442{ 443 if (AH_PRIVATE(ah)->ah_ispcie) 444 ath_hal_configPCIE(ah, AH_FALSE); 445 else 446 ath_hal_disablePCIE(ah); 447} 448 449static void 450ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 451{ 452 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 453 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 454 OS_DELAY(1000); 455 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 456 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 457 } 458} 459 460static void 461ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 462{ 463 u_int modesIndex, freqIndex; 464 int regWrites = 0; 465 466 /* Setup the indices for the next set of register array writes */ 467 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 468 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 469 freqIndex = 2; 470 if (IEEE80211_IS_CHAN_HT40(chan)) 471 modesIndex = 3; 472 else if (IEEE80211_IS_CHAN_108G(chan)) 473 modesIndex = 5; 474 else 475 modesIndex = 4; 476 } else { 477 freqIndex = 1; 478 if (IEEE80211_IS_CHAN_HT40(chan) || 479 IEEE80211_IS_CHAN_TURBO(chan)) 480 modesIndex = 2; 481 else 482 modesIndex = 1; 483 } 484 485 /* Set correct Baseband to analog shift setting to access analog chips. */ 486 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 487 488 /* 489 * Write addac shifts 490 */ 491 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 492 493 /* NB: only required for Sowl */ 494 if (AR_SREV_SOWL(ah)) 495 ar5416EepromSetAddac(ah, chan); 496 497 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 498 regWrites); 499 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 500 501 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 502 modesIndex, regWrites); 503 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 504 1, regWrites); 505 506 /* XXX updated regWrites? */ 507 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 508} 509 510/* 511 * Convert to baseband spur frequency given input channel frequency 512 * and compute register settings below. 513 */ 514 515static void 516ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 517{ 518 uint16_t freq = ath_hal_gethwchannel(ah, chan); 519 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 520 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 521 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 522 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 523 static const int inc[4] = { 0, 100, 0, 0 }; 524 525 int bb_spur = AR_NO_SPUR; 526 int bin, cur_bin; 527 int spur_freq_sd; 528 int spur_delta_phase; 529 int denominator; 530 int upper, lower, cur_vit_mask; 531 int tmp, new; 532 int i; 533 534 int8_t mask_m[123]; 535 int8_t mask_p[123]; 536 int8_t mask_amt; 537 int tmp_mask; 538 int cur_bb_spur; 539 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 540 541 OS_MEMZERO(mask_m, sizeof(mask_m)); 542 OS_MEMZERO(mask_p, sizeof(mask_p)); 543 544 /* 545 * Need to verify range +/- 9.5 for static ht20, otherwise spur 546 * is out-of-band and can be ignored. 547 */ 548 /* XXX ath9k changes */ 549 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 550 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 551 if (AR_NO_SPUR == cur_bb_spur) 552 break; 553 cur_bb_spur = cur_bb_spur - (freq * 10); 554 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 555 bb_spur = cur_bb_spur; 556 break; 557 } 558 } 559 if (AR_NO_SPUR == bb_spur) 560 return; 561 562 bin = bb_spur * 32; 563 564 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 565 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 566 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 567 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 568 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 569 570 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 571 572 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 573 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 574 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 575 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 576 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 577 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 578 /* 579 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 580 * config, no offset for HT20. 581 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 582 * /80 for dyn2040. 583 */ 584 spur_delta_phase = ((bb_spur * 524288) / 100) & 585 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 586 /* 587 * in 11A mode the denominator of spur_freq_sd should be 40 and 588 * it should be 44 in 11G 589 */ 590 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 591 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 592 593 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 594 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 595 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 596 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 597 598 599 /* 600 * ============================================ 601 * pilot mask 1 [31:0] = +6..-26, no 0 bin 602 * pilot mask 2 [19:0] = +26..+7 603 * 604 * channel mask 1 [31:0] = +6..-26, no 0 bin 605 * channel mask 2 [19:0] = +26..+7 606 */ 607 //cur_bin = -26; 608 cur_bin = -6000; 609 upper = bin + 100; 610 lower = bin - 100; 611 612 for (i = 0; i < 4; i++) { 613 int pilot_mask = 0; 614 int chan_mask = 0; 615 int bp = 0; 616 for (bp = 0; bp < 30; bp++) { 617 if ((cur_bin > lower) && (cur_bin < upper)) { 618 pilot_mask = pilot_mask | 0x1 << bp; 619 chan_mask = chan_mask | 0x1 << bp; 620 } 621 cur_bin += 100; 622 } 623 cur_bin += inc[i]; 624 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 625 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 626 } 627 628 /* ================================================= 629 * viterbi mask 1 based on channel magnitude 630 * four levels 0-3 631 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 632 * [1 2 2 1] for -9.6 or [1 2 1] for +16 633 * - enable_mask_ppm, all bins move with freq 634 * 635 * - mask_select, 8 bits for rates (reg 67,0x990c) 636 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 637 * choose which mask to use mask or mask2 638 */ 639 640 /* 641 * viterbi mask 2 2nd set for per data rate puncturing 642 * four levels 0-3 643 * - mask_select, 8 bits for rates (reg 67) 644 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 645 * [1 2 2 1] for -9.6 or [1 2 1] for +16 646 */ 647 cur_vit_mask = 6100; 648 upper = bin + 120; 649 lower = bin - 120; 650 651 for (i = 0; i < 123; i++) { 652 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 653 if ((abs(cur_vit_mask - bin)) < 75) { 654 mask_amt = 1; 655 } else { 656 mask_amt = 0; 657 } 658 if (cur_vit_mask < 0) { 659 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 660 } else { 661 mask_p[cur_vit_mask / 100] = mask_amt; 662 } 663 } 664 cur_vit_mask -= 100; 665 } 666 667 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 668 | (mask_m[48] << 26) | (mask_m[49] << 24) 669 | (mask_m[50] << 22) | (mask_m[51] << 20) 670 | (mask_m[52] << 18) | (mask_m[53] << 16) 671 | (mask_m[54] << 14) | (mask_m[55] << 12) 672 | (mask_m[56] << 10) | (mask_m[57] << 8) 673 | (mask_m[58] << 6) | (mask_m[59] << 4) 674 | (mask_m[60] << 2) | (mask_m[61] << 0); 675 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 676 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 677 678 tmp_mask = (mask_m[31] << 28) 679 | (mask_m[32] << 26) | (mask_m[33] << 24) 680 | (mask_m[34] << 22) | (mask_m[35] << 20) 681 | (mask_m[36] << 18) | (mask_m[37] << 16) 682 | (mask_m[48] << 14) | (mask_m[39] << 12) 683 | (mask_m[40] << 10) | (mask_m[41] << 8) 684 | (mask_m[42] << 6) | (mask_m[43] << 4) 685 | (mask_m[44] << 2) | (mask_m[45] << 0); 686 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 687 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 688 689 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 690 | (mask_m[18] << 26) | (mask_m[18] << 24) 691 | (mask_m[20] << 22) | (mask_m[20] << 20) 692 | (mask_m[22] << 18) | (mask_m[22] << 16) 693 | (mask_m[24] << 14) | (mask_m[24] << 12) 694 | (mask_m[25] << 10) | (mask_m[26] << 8) 695 | (mask_m[27] << 6) | (mask_m[28] << 4) 696 | (mask_m[29] << 2) | (mask_m[30] << 0); 697 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 698 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 699 700 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 701 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 702 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 703 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 704 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 705 | (mask_m[10] << 10) | (mask_m[11] << 8) 706 | (mask_m[12] << 6) | (mask_m[13] << 4) 707 | (mask_m[14] << 2) | (mask_m[15] << 0); 708 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 709 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 710 711 tmp_mask = (mask_p[15] << 28) 712 | (mask_p[14] << 26) | (mask_p[13] << 24) 713 | (mask_p[12] << 22) | (mask_p[11] << 20) 714 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 715 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 716 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 717 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 718 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 719 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 720 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 721 722 tmp_mask = (mask_p[30] << 28) 723 | (mask_p[29] << 26) | (mask_p[28] << 24) 724 | (mask_p[27] << 22) | (mask_p[26] << 20) 725 | (mask_p[25] << 18) | (mask_p[24] << 16) 726 | (mask_p[23] << 14) | (mask_p[22] << 12) 727 | (mask_p[21] << 10) | (mask_p[20] << 8) 728 | (mask_p[19] << 6) | (mask_p[18] << 4) 729 | (mask_p[17] << 2) | (mask_p[16] << 0); 730 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 731 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 732 733 tmp_mask = (mask_p[45] << 28) 734 | (mask_p[44] << 26) | (mask_p[43] << 24) 735 | (mask_p[42] << 22) | (mask_p[41] << 20) 736 | (mask_p[40] << 18) | (mask_p[39] << 16) 737 | (mask_p[38] << 14) | (mask_p[37] << 12) 738 | (mask_p[36] << 10) | (mask_p[35] << 8) 739 | (mask_p[34] << 6) | (mask_p[33] << 4) 740 | (mask_p[32] << 2) | (mask_p[31] << 0); 741 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 742 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 743 744 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 745 | (mask_p[59] << 26) | (mask_p[58] << 24) 746 | (mask_p[57] << 22) | (mask_p[56] << 20) 747 | (mask_p[55] << 18) | (mask_p[54] << 16) 748 | (mask_p[53] << 14) | (mask_p[52] << 12) 749 | (mask_p[51] << 10) | (mask_p[50] << 8) 750 | (mask_p[49] << 6) | (mask_p[48] << 4) 751 | (mask_p[47] << 2) | (mask_p[46] << 0); 752 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 753 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 754} 755 756/* 757 * Fill all software cached or static hardware state information. 758 * Return failure if capabilities are to come from EEPROM and 759 * cannot be read. 760 */ 761HAL_BOOL 762ar5416FillCapabilityInfo(struct ath_hal *ah) 763{ 764 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 765 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 766 uint16_t val; 767 768 /* Construct wireless mode from EEPROM */ 769 pCap->halWirelessModes = 0; 770 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 771 pCap->halWirelessModes |= HAL_MODE_11A 772 | HAL_MODE_11NA_HT20 773 | HAL_MODE_11NA_HT40PLUS 774 | HAL_MODE_11NA_HT40MINUS 775 ; 776 } 777 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 778 pCap->halWirelessModes |= HAL_MODE_11G 779 | HAL_MODE_11NG_HT20 780 | HAL_MODE_11NG_HT40PLUS 781 | HAL_MODE_11NG_HT40MINUS 782 ; 783 pCap->halWirelessModes |= HAL_MODE_11A 784 | HAL_MODE_11NA_HT20 785 | HAL_MODE_11NA_HT40PLUS 786 | HAL_MODE_11NA_HT40MINUS 787 ; 788 } 789 790 pCap->halLow2GhzChan = 2312; 791 pCap->halHigh2GhzChan = 2732; 792 793 pCap->halLow5GhzChan = 4915; 794 pCap->halHigh5GhzChan = 6100; 795 796 pCap->halCipherCkipSupport = AH_FALSE; 797 pCap->halCipherTkipSupport = AH_TRUE; 798 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 799 800 pCap->halMicCkipSupport = AH_FALSE; 801 pCap->halMicTkipSupport = AH_TRUE; 802 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 803 /* 804 * Starting with Griffin TX+RX mic keys can be combined 805 * in one key cache slot. 806 */ 807 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 808 pCap->halChanSpreadSupport = AH_TRUE; 809 pCap->halSleepAfterBeaconBroken = AH_TRUE; 810 811 pCap->halCompressSupport = AH_FALSE; 812 pCap->halBurstSupport = AH_TRUE; 813 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 814 pCap->halChapTuningSupport = AH_TRUE; 815 pCap->halTurboPrimeSupport = AH_TRUE; 816 817 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 818 819 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 820 pCap->halVEOLSupport = AH_TRUE; 821 pCap->halBssIdMaskSupport = AH_TRUE; 822 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 823 pCap->halTsfAddSupport = AH_TRUE; 824 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 825 826 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 827 pCap->halTotalQueues = val; 828 else 829 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 830 831 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 832 pCap->halKeyCacheSize = val; 833 else 834 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 835 836 /* XXX not needed */ 837 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 838 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 839 840 pCap->halTstampPrecision = 32; 841 pCap->halHwPhyCounterSupport = AH_TRUE; 842 pCap->halIntrMask = HAL_INT_COMMON 843 | HAL_INT_RX 844 | HAL_INT_TX 845 | HAL_INT_FATAL 846 | HAL_INT_BNR 847 | HAL_INT_BMISC 848 | HAL_INT_DTIMSYNC 849 | HAL_INT_TSFOOR 850 | HAL_INT_CST 851 | HAL_INT_GTT 852 ; 853 854 pCap->halFastCCSupport = AH_TRUE; 855 pCap->halNumGpioPins = 6; 856 pCap->halWowSupport = AH_FALSE; 857 pCap->halWowMatchPatternExact = AH_FALSE; 858 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 859 pCap->halAutoSleepSupport = AH_FALSE; 860 pCap->hal4kbSplitTransSupport = AH_TRUE; 861 /* Disable this so Block-ACK works correctly */ 862 pCap->halHasRxSelfLinkedTail = AH_FALSE; 863#if 0 /* XXX not yet */ 864 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 865 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 866#endif 867 pCap->halHTSupport = AH_TRUE; 868 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 869 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 870 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 871 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 872 pCap->halTxStreams = 2; 873 pCap->halRxStreams = 2; 874 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 875 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 876 pCap->halForcePpmSupport = AH_TRUE; 877 pCap->halEnhancedPmSupport = AH_TRUE; 878 pCap->halBssidMatchSupport = AH_TRUE; 879 pCap->halGTTSupport = AH_TRUE; 880 pCap->halCSTSupport = AH_TRUE; 881 882 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 883 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 884 /* NB: enabled by default */ 885 ahpriv->ah_rfkillEnabled = AH_TRUE; 886 pCap->halRfSilentSupport = AH_TRUE; 887 } 888 889 ahpriv->ah_rxornIsFatal = AH_FALSE; 890 891 return AH_TRUE; 892} 893 894static const char* 895ar5416Probe(uint16_t vendorid, uint16_t devid) 896{ 897 if (vendorid == ATHEROS_VENDOR_ID && 898 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 899 return "Atheros 5416"; 900 return AH_NULL; 901} 902AH_CHIP(AR5416, ar5416Probe, ar5416Attach);
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