1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 218763 2011-02-17 05:52:53Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"
26
27#include "ar5416/ar5416.h"
28#include "ar5416/ar5416reg.h"
29#include "ar5416/ar5416phy.h"
30
31#include "ar5416/ar5416.ini"
32
33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
34static void ar5416WriteIni(struct ath_hal *ah,
35 const struct ieee80211_channel *chan);
36static void ar5416SpurMitigate(struct ath_hal *ah,
37 const struct ieee80211_channel *chan);
38
39static void
40ar5416AniSetup(struct ath_hal *ah)
41{
42 static const struct ar5212AniParams aniparams = {
43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
44 .totalSizeDesired = { -55, -55, -55, -55, -62 },
45 .coarseHigh = { -14, -14, -14, -14, -12 },
46 .coarseLow = { -64, -64, -64, -64, -70 },
47 .firpwr = { -78, -78, -78, -78, -80 },
48 .maxSpurImmunityLevel = 2,
49 .cycPwrThr1 = { 2, 4, 6 },
50 .maxFirstepLevel = 2, /* levels 0..2 */
51 .firstep = { 0, 4, 8 },
52 .ofdmTrigHigh = 500,
53 .ofdmTrigLow = 200,
54 .cckTrigHigh = 200,
55 .cckTrigLow = 100,
56 .rssiThrHigh = 40,
57 .rssiThrLow = 7,
58 .period = 100,
59 };
60 /* NB: ANI is not enabled yet */
61 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
62}
63
64/*
65 * Attach for an AR5416 part.
66 */
67void
68ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
69 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
70{
71 struct ath_hal_5212 *ahp;
72 struct ath_hal *ah;
73
74 ahp = &ahp5416->ah_5212;
75 ar5212InitState(ahp, devid, sc, st, sh, status);
76 ah = &ahp->ah_priv.h;
77
78 /* override 5212 methods for our needs */
79 ah->ah_magic = AR5416_MAGIC;
80 ah->ah_getRateTable = ar5416GetRateTable;
81 ah->ah_detach = ar5416Detach;
82
83 /* Reset functions */
84 ah->ah_reset = ar5416Reset;
85 ah->ah_phyDisable = ar5416PhyDisable;
86 ah->ah_disable = ar5416Disable;
87 ah->ah_configPCIE = ar5416ConfigPCIE;
88 ah->ah_perCalibration = ar5416PerCalibration;
89 ah->ah_perCalibrationN = ar5416PerCalibrationN,
90 ah->ah_resetCalValid = ar5416ResetCalValid,
91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
92 ah->ah_setTxPower = ar5416SetTransmitPower;
93 ah->ah_setBoardValues = ar5416SetBoardValues;
94
95 /* Transmit functions */
96 ah->ah_stopTxDma = ar5416StopTxDma;
97 ah->ah_setupTxDesc = ar5416SetupTxDesc;
98 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
99 ah->ah_fillTxDesc = ar5416FillTxDesc;
100 ah->ah_procTxDesc = ar5416ProcTxDesc;
101 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;
102
103 /* Receive Functions */
104 ah->ah_startPcuReceive = ar5416StartPcuReceive;
105 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
106 ah->ah_setupRxDesc = ar5416SetupRxDesc;
107 ah->ah_procRxDesc = ar5416ProcRxDesc;
108 ah->ah_rxMonitor = ar5416RxMonitor;
109 ah->ah_aniPoll = ar5416AniPoll;
110 ah->ah_procMibEvent = ar5416ProcessMibIntr;
111
112 /* Misc Functions */
113 ah->ah_getCapability = ar5416GetCapability;
114 ah->ah_getDiagState = ar5416GetDiagState;
115 ah->ah_setLedState = ar5416SetLedState;
116 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
117 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
118 ah->ah_gpioGet = ar5416GpioGet;
119 ah->ah_gpioSet = ar5416GpioSet;
120 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
121 ah->ah_resetTsf = ar5416ResetTsf;
122 ah->ah_getRfGain = ar5416GetRfgain;
123 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
124 ah->ah_setDecompMask = ar5416SetDecompMask;
125 ah->ah_setCoverageClass = ar5416SetCoverageClass;
126
127 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
128 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
129
130 /* Power Management Functions */
131 ah->ah_setPowerMode = ar5416SetPowerMode;
132
133 /* Beacon Management Functions */
134 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
135 ah->ah_beaconInit = ar5416BeaconInit;
136 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
137 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
138
139 /* 802.11n Functions */
140 ah->ah_chainTxDesc = ar5416ChainTxDesc;
141 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
142 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
143 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
144 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
145 ah->ah_clr11nAggr = ar5416Clr11nAggr;
146 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
147 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
148 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
149 ah->ah_get11nRxClear = ar5416Get11nRxClear;
150 ah->ah_set11nRxClear = ar5416Set11nRxClear;
151
152 /* Interrupt functions */
153 ah->ah_isInterruptPending = ar5416IsInterruptPending;
154 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
155 ah->ah_setInterrupts = ar5416SetInterrupts;
156
157 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
158 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
159#ifdef AH_SUPPORT_WRITE_EEPROM
160 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
161#endif
162 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
163
164 AH5416(ah)->ah_writeIni = ar5416WriteIni;
165 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
166 /*
167 * Start by setting all Owl devices to 2x2
168 */
169 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
170 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
171
172 /* Enable all ANI functions to begin with */
173 AH5416(ah)->ah_ani_function = HAL_ANI_ALL;
174}
175
176uint32_t
177ar5416GetRadioRev(struct ath_hal *ah)
178{
179 uint32_t val;
180 int i;
181
182 /* Read Radio Chip Rev Extract */
183 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
184 for (i = 0; i < 8; i++)
185 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
186 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
187 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
188 return ath_hal_reverseBits(val, 8);
189}
190
191/*
192 * Attach for an AR5416 part.
193 */
194static struct ath_hal *
195ar5416Attach(uint16_t devid, HAL_SOFTC sc,
196 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
197 HAL_STATUS *status)
198{
199 struct ath_hal_5416 *ahp5416;
200 struct ath_hal_5212 *ahp;
201 struct ath_hal *ah;
202 uint32_t val;
203 HAL_STATUS ecode;
204 HAL_BOOL rfStatus;
205
206 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
207 __func__, sc, (void*) st, (void*) sh);
208
209 /* NB: memory is returned zero'd */
210 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
211 /* extra space for Owl 2.1/2.2 WAR */
212 sizeof(ar5416Addac)
213 );
214 if (ahp5416 == AH_NULL) {
215 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
216 "%s: cannot allocate memory for state block\n", __func__);
217 *status = HAL_ENOMEM;
218 return AH_NULL;
219 }
220 ar5416InitState(ahp5416, devid, sc, st, sh, status);
221 ahp = &ahp5416->ah_5212;
222 ah = &ahp->ah_priv.h;
223
224 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
225 /* reset chip */
226 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
227 ecode = HAL_EIO;
228 goto bad;
229 }
230
231 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
232 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
233 ecode = HAL_EIO;
234 goto bad;
235 }
236 /* Read Revisions from Chips before taking out of reset */
237 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
238 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
239 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
240 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
241
242 /* setup common ini data; rf backends handle remainder */
243 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
244 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
245
246 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
247 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
248 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
249 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
250 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
251 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
252 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
253 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
254
255 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
256 struct ini {
257 uint32_t *data; /* NB: !const */
258 int rows, cols;
259 };
260 /* override CLKDRV value */
261 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
262 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
263 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
264 }
265
266 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
267 ar5416AttachPCIE(ah);
268
269 ecode = ath_hal_v14EepromAttach(ah);
270 if (ecode != HAL_OK)
271 goto bad;
272
273 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
274 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
275 __func__);
276 ecode = HAL_EIO;
277 goto bad;
278 }
279
280 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
281
282 if (!ar5212ChipTest(ah)) {
283 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
284 __func__);
285 ecode = HAL_ESELFTEST;
286 goto bad;
287 }
288
289 /*
290 * Set correct Baseband to analog shift
291 * setting to access analog chips.
292 */
293 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
294
295 /* Read Radio Chip Rev Extract */
296 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
297 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
298 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
299 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
300 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
301 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
302 break;
303 default:
304 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
305 /*
306 * When RF_Silen is used the analog chip is reset.
307 * So when the system boots with radio switch off
308 * the RF chip rev reads back as zero and we need
309 * to use the mac+phy revs to set the radio rev.
310 */
311 AH_PRIVATE(ah)->ah_analog5GhzRev =
312 AR_RAD5133_SREV_MAJOR;
313 break;
314 }
315 /* NB: silently accept anything in release code per Atheros */
316#ifdef AH_DEBUG
317 HALDEBUG(ah, HAL_DEBUG_ANY,
318 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
319 "this driver\n", __func__,
320 AH_PRIVATE(ah)->ah_analog5GhzRev);
321 ecode = HAL_ENOTSUPP;
322 goto bad;
323#endif
324 }
325
326 /*
327 * Got everything we need now to setup the capabilities.
328 */
329 if (!ar5416FillCapabilityInfo(ah)) {
330 ecode = HAL_EEREAD;
331 goto bad;
332 }
333
334 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
335 if (ecode != HAL_OK) {
336 HALDEBUG(ah, HAL_DEBUG_ANY,
337 "%s: error getting mac address from EEPROM\n", __func__);
338 goto bad;
339 }
340 /* XXX How about the serial number ? */
341 /* Read Reg Domain */
342 AH_PRIVATE(ah)->ah_currentRD =
343 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
344
345 /*
346 * ah_miscMode is populated by ar5416FillCapabilityInfo()
347 * starting from griffin. Set here to make sure that
348 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
349 * placed into hardware.
350 */
351 if (ahp->ah_miscMode != 0)
352 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
353
354 rfStatus = ar2133RfAttach(ah, &ecode);
355 if (!rfStatus) {
356 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
357 __func__, ecode);
358 goto bad;
359 }
360
361 ar5416AniSetup(ah); /* Anti Noise Immunity */
362
363 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
364 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
365 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
366 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
367 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
368 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
369
370 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
371
372 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
373
374 return ah;
375bad:
376 if (ahp)
377 ar5416Detach((struct ath_hal *) ahp);
378 if (status)
379 *status = ecode;
380 return AH_NULL;
381}
382
383void
384ar5416Detach(struct ath_hal *ah)
385{
386 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
387
388 HALASSERT(ah != AH_NULL);
389 HALASSERT(ah->ah_magic == AR5416_MAGIC);
390
391 ar5416AniDetach(ah);
392 ar5212RfDetach(ah);
393 ah->ah_disable(ah);
394 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
395 ath_hal_eepromDetach(ah);
396 ath_hal_free(ah);
397}
398
399void
400ar5416AttachPCIE(struct ath_hal *ah)
401{
402 if (AH_PRIVATE(ah)->ah_ispcie)
403 ath_hal_configPCIE(ah, AH_FALSE);
404 else
405 ath_hal_disablePCIE(ah);
406}
407
408static void
409ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
410{
411 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
412 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
413 OS_DELAY(1000);
414 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
415 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
416 }
417}
418
419static void
420ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
421{
422 u_int modesIndex, freqIndex;
423 int regWrites = 0;
424
425 /* Setup the indices for the next set of register array writes */
426 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
427 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
428 freqIndex = 2;
429 if (IEEE80211_IS_CHAN_HT40(chan))
430 modesIndex = 3;
431 else if (IEEE80211_IS_CHAN_108G(chan))
432 modesIndex = 5;
433 else
434 modesIndex = 4;
435 } else {
436 freqIndex = 1;
437 if (IEEE80211_IS_CHAN_HT40(chan) ||
438 IEEE80211_IS_CHAN_TURBO(chan))
439 modesIndex = 2;
440 else
441 modesIndex = 1;
442 }
443
444 /* Set correct Baseband to analog shift setting to access analog chips. */
445 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
446
447 /*
448 * Write addac shifts
449 */
450 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
451#if 0
452 /* NB: only required for Sowl */
453 ar5416EepromSetAddac(ah, chan);
454#endif
455 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
456 regWrites);
457 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
458
459 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
460 modesIndex, regWrites);
461 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
462 1, regWrites);
463
464 /* XXX updated regWrites? */
465 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
466}
467
468/*
469 * Convert to baseband spur frequency given input channel frequency
470 * and compute register settings below.
471 */
472
473static void
474ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
475{
476 uint16_t freq = ath_hal_gethwchannel(ah, chan);
477 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
478 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
479 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
480 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
481 static const int inc[4] = { 0, 100, 0, 0 };
482
483 int bb_spur = AR_NO_SPUR;
484 int bin, cur_bin;
485 int spur_freq_sd;
486 int spur_delta_phase;
487 int denominator;
488 int upper, lower, cur_vit_mask;
489 int tmp, new;
490 int i;
491
492 int8_t mask_m[123];
493 int8_t mask_p[123];
494 int8_t mask_amt;
495 int tmp_mask;
496 int cur_bb_spur;
497 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
498
499 OS_MEMZERO(mask_m, sizeof(mask_m));
500 OS_MEMZERO(mask_p, sizeof(mask_p));
501
502 /*
503 * Need to verify range +/- 9.5 for static ht20, otherwise spur
504 * is out-of-band and can be ignored.
505 */
506 /* XXX ath9k changes */
507 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
508 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
509 if (AR_NO_SPUR == cur_bb_spur)
510 break;
511 cur_bb_spur = cur_bb_spur - (freq * 10);
512 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
513 bb_spur = cur_bb_spur;
514 break;
515 }
516 }
517 if (AR_NO_SPUR == bb_spur)
518 return;
519
520 bin = bb_spur * 32;
521
522 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
523 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
524 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
525 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
526 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
527
528 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
529
530 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
531 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
532 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
533 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
534 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
535 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
536 /*
537 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
538 * config, no offset for HT20.
539 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
540 * /80 for dyn2040.
541 */
542 spur_delta_phase = ((bb_spur * 524288) / 100) &
543 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
544 /*
545 * in 11A mode the denominator of spur_freq_sd should be 40 and
546 * it should be 44 in 11G
547 */
548 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
549 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
550
551 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
552 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
553 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
554 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
555
556
557 /*
558 * ============================================
559 * pilot mask 1 [31:0] = +6..-26, no 0 bin
560 * pilot mask 2 [19:0] = +26..+7
561 *
562 * channel mask 1 [31:0] = +6..-26, no 0 bin
563 * channel mask 2 [19:0] = +26..+7
564 */
565 //cur_bin = -26;
566 cur_bin = -6000;
567 upper = bin + 100;
568 lower = bin - 100;
569
570 for (i = 0; i < 4; i++) {
571 int pilot_mask = 0;
572 int chan_mask = 0;
573 int bp = 0;
574 for (bp = 0; bp < 30; bp++) {
575 if ((cur_bin > lower) && (cur_bin < upper)) {
576 pilot_mask = pilot_mask | 0x1 << bp;
577 chan_mask = chan_mask | 0x1 << bp;
578 }
579 cur_bin += 100;
580 }
581 cur_bin += inc[i];
582 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
583 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
584 }
585
586 /* =================================================
587 * viterbi mask 1 based on channel magnitude
588 * four levels 0-3
589 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
590 * [1 2 2 1] for -9.6 or [1 2 1] for +16
591 * - enable_mask_ppm, all bins move with freq
592 *
593 * - mask_select, 8 bits for rates (reg 67,0x990c)
594 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
595 * choose which mask to use mask or mask2
596 */
597
598 /*
599 * viterbi mask 2 2nd set for per data rate puncturing
600 * four levels 0-3
601 * - mask_select, 8 bits for rates (reg 67)
602 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
603 * [1 2 2 1] for -9.6 or [1 2 1] for +16
604 */
605 cur_vit_mask = 6100;
606 upper = bin + 120;
607 lower = bin - 120;
608
609 for (i = 0; i < 123; i++) {
610 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
611 if ((abs(cur_vit_mask - bin)) < 75) {
612 mask_amt = 1;
613 } else {
614 mask_amt = 0;
615 }
616 if (cur_vit_mask < 0) {
617 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
618 } else {
619 mask_p[cur_vit_mask / 100] = mask_amt;
620 }
621 }
622 cur_vit_mask -= 100;
623 }
624
625 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
626 | (mask_m[48] << 26) | (mask_m[49] << 24)
627 | (mask_m[50] << 22) | (mask_m[51] << 20)
628 | (mask_m[52] << 18) | (mask_m[53] << 16)
629 | (mask_m[54] << 14) | (mask_m[55] << 12)
630 | (mask_m[56] << 10) | (mask_m[57] << 8)
631 | (mask_m[58] << 6) | (mask_m[59] << 4)
632 | (mask_m[60] << 2) | (mask_m[61] << 0);
633 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
634 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
635
636 tmp_mask = (mask_m[31] << 28)
637 | (mask_m[32] << 26) | (mask_m[33] << 24)
638 | (mask_m[34] << 22) | (mask_m[35] << 20)
639 | (mask_m[36] << 18) | (mask_m[37] << 16)
640 | (mask_m[48] << 14) | (mask_m[39] << 12)
641 | (mask_m[40] << 10) | (mask_m[41] << 8)
642 | (mask_m[42] << 6) | (mask_m[43] << 4)
643 | (mask_m[44] << 2) | (mask_m[45] << 0);
644 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
645 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
646
647 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
648 | (mask_m[18] << 26) | (mask_m[18] << 24)
649 | (mask_m[20] << 22) | (mask_m[20] << 20)
650 | (mask_m[22] << 18) | (mask_m[22] << 16)
651 | (mask_m[24] << 14) | (mask_m[24] << 12)
652 | (mask_m[25] << 10) | (mask_m[26] << 8)
653 | (mask_m[27] << 6) | (mask_m[28] << 4)
654 | (mask_m[29] << 2) | (mask_m[30] << 0);
655 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
656 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
657
658 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
659 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
660 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
661 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
662 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
663 | (mask_m[10] << 10) | (mask_m[11] << 8)
664 | (mask_m[12] << 6) | (mask_m[13] << 4)
665 | (mask_m[14] << 2) | (mask_m[15] << 0);
666 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
667 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
668
669 tmp_mask = (mask_p[15] << 28)
670 | (mask_p[14] << 26) | (mask_p[13] << 24)
671 | (mask_p[12] << 22) | (mask_p[11] << 20)
672 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
673 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
674 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
675 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
676 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
677 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
678 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
679
680 tmp_mask = (mask_p[30] << 28)
681 | (mask_p[29] << 26) | (mask_p[28] << 24)
682 | (mask_p[27] << 22) | (mask_p[26] << 20)
683 | (mask_p[25] << 18) | (mask_p[24] << 16)
684 | (mask_p[23] << 14) | (mask_p[22] << 12)
685 | (mask_p[21] << 10) | (mask_p[20] << 8)
686 | (mask_p[19] << 6) | (mask_p[18] << 4)
687 | (mask_p[17] << 2) | (mask_p[16] << 0);
688 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
689 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
690
691 tmp_mask = (mask_p[45] << 28)
692 | (mask_p[44] << 26) | (mask_p[43] << 24)
693 | (mask_p[42] << 22) | (mask_p[41] << 20)
694 | (mask_p[40] << 18) | (mask_p[39] << 16)
695 | (mask_p[38] << 14) | (mask_p[37] << 12)
696 | (mask_p[36] << 10) | (mask_p[35] << 8)
697 | (mask_p[34] << 6) | (mask_p[33] << 4)
698 | (mask_p[32] << 2) | (mask_p[31] << 0);
699 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
700 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
701
702 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
703 | (mask_p[59] << 26) | (mask_p[58] << 24)
704 | (mask_p[57] << 22) | (mask_p[56] << 20)
705 | (mask_p[55] << 18) | (mask_p[54] << 16)
706 | (mask_p[53] << 14) | (mask_p[52] << 12)
707 | (mask_p[51] << 10) | (mask_p[50] << 8)
708 | (mask_p[49] << 6) | (mask_p[48] << 4)
709 | (mask_p[47] << 2) | (mask_p[46] << 0);
710 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
711 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
712}
713
714/*
715 * Fill all software cached or static hardware state information.
716 * Return failure if capabilities are to come from EEPROM and
717 * cannot be read.
718 */
719HAL_BOOL
720ar5416FillCapabilityInfo(struct ath_hal *ah)
721{
722 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
723 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
724 uint16_t val;
725
726 /* Construct wireless mode from EEPROM */
727 pCap->halWirelessModes = 0;
728 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
729 pCap->halWirelessModes |= HAL_MODE_11A
730 | HAL_MODE_11NA_HT20
731 | HAL_MODE_11NA_HT40PLUS
732 | HAL_MODE_11NA_HT40MINUS
733 ;
734 }
735 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
736 pCap->halWirelessModes |= HAL_MODE_11G
737 | HAL_MODE_11NG_HT20
738 | HAL_MODE_11NG_HT40PLUS
739 | HAL_MODE_11NG_HT40MINUS
740 ;
741 pCap->halWirelessModes |= HAL_MODE_11A
742 | HAL_MODE_11NA_HT20
743 | HAL_MODE_11NA_HT40PLUS
744 | HAL_MODE_11NA_HT40MINUS
745 ;
746 }
747
748 pCap->halLow2GhzChan = 2312;
749 pCap->halHigh2GhzChan = 2732;
750
751 pCap->halLow5GhzChan = 4915;
752 pCap->halHigh5GhzChan = 6100;
753
754 pCap->halCipherCkipSupport = AH_FALSE;
755 pCap->halCipherTkipSupport = AH_TRUE;
756 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
757
758 pCap->halMicCkipSupport = AH_FALSE;
759 pCap->halMicTkipSupport = AH_TRUE;
760 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
761 /*
762 * Starting with Griffin TX+RX mic keys can be combined
763 * in one key cache slot.
764 */
765 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
766 pCap->halChanSpreadSupport = AH_TRUE;
767 pCap->halSleepAfterBeaconBroken = AH_TRUE;
768
769 pCap->halCompressSupport = AH_FALSE;
770 pCap->halBurstSupport = AH_TRUE;
771 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */
772 pCap->halChapTuningSupport = AH_TRUE;
773 pCap->halTurboPrimeSupport = AH_TRUE;
774
775 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
776
777 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
778 pCap->halVEOLSupport = AH_TRUE;
779 pCap->halBssIdMaskSupport = AH_TRUE;
780 pCap->halMcastKeySrchSupport = AH_FALSE;
781 pCap->halTsfAddSupport = AH_TRUE;
782
783 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
784 pCap->halTotalQueues = val;
785 else
786 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
787
788 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
789 pCap->halKeyCacheSize = val;
790 else
791 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
792
793 /* XXX not needed */
794 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */
795 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */
796
797 pCap->halTstampPrecision = 32;
798 pCap->halHwPhyCounterSupport = AH_TRUE;
799 pCap->halIntrMask = HAL_INT_COMMON
800 | HAL_INT_RX
801 | HAL_INT_TX
802 | HAL_INT_FATAL
803 | HAL_INT_BNR
804 | HAL_INT_BMISC
805 | HAL_INT_DTIMSYNC
806 | HAL_INT_TSFOOR
807 | HAL_INT_CST
808 | HAL_INT_GTT
809 ;
810
811 pCap->halFastCCSupport = AH_TRUE;
812 pCap->halNumGpioPins = 6;
813 pCap->halWowSupport = AH_FALSE;
814 pCap->halWowMatchPatternExact = AH_FALSE;
815 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
816 pCap->halAutoSleepSupport = AH_FALSE;
817 pCap->hal4kbSplitTransSupport = AH_TRUE;
818#if 0 /* XXX not yet */
819 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
820 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
821#endif
822 pCap->halHTSupport = AH_TRUE;
823 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
824 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
825 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
826 /* AR5416 may have 3 antennas but is a 2x2 stream device */
827 pCap->halTxStreams = 2;
828 pCap->halRxStreams = 2;
829 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
830 pCap->halMbssidAggrSupport = AH_TRUE;
831 pCap->halForcePpmSupport = AH_TRUE;
832 pCap->halEnhancedPmSupport = AH_TRUE;
833 pCap->halBssidMatchSupport = AH_TRUE;
834
835 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
836 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
837 /* NB: enabled by default */
838 ahpriv->ah_rfkillEnabled = AH_TRUE;
839 pCap->halRfSilentSupport = AH_TRUE;
840 }
841
842 ahpriv->ah_rxornIsFatal = AH_FALSE;
843
844 return AH_TRUE;
845}
846
847static const char*
848ar5416Probe(uint16_t vendorid, uint16_t devid)
849{
850 if (vendorid == ATHEROS_VENDOR_ID &&
851 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE))
852 return "Atheros 5416";
853 return AH_NULL;
854}
855AH_CHIP(AR5416, ar5416Probe, ar5416Attach);
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 218763 2011-02-17 05:52:53Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"
26
27#include "ar5416/ar5416.h"
28#include "ar5416/ar5416reg.h"
29#include "ar5416/ar5416phy.h"
30
31#include "ar5416/ar5416.ini"
32
33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
34static void ar5416WriteIni(struct ath_hal *ah,
35 const struct ieee80211_channel *chan);
36static void ar5416SpurMitigate(struct ath_hal *ah,
37 const struct ieee80211_channel *chan);
38
39static void
40ar5416AniSetup(struct ath_hal *ah)
41{
42 static const struct ar5212AniParams aniparams = {
43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
44 .totalSizeDesired = { -55, -55, -55, -55, -62 },
45 .coarseHigh = { -14, -14, -14, -14, -12 },
46 .coarseLow = { -64, -64, -64, -64, -70 },
47 .firpwr = { -78, -78, -78, -78, -80 },
48 .maxSpurImmunityLevel = 2,
49 .cycPwrThr1 = { 2, 4, 6 },
50 .maxFirstepLevel = 2, /* levels 0..2 */
51 .firstep = { 0, 4, 8 },
52 .ofdmTrigHigh = 500,
53 .ofdmTrigLow = 200,
54 .cckTrigHigh = 200,
55 .cckTrigLow = 100,
56 .rssiThrHigh = 40,
57 .rssiThrLow = 7,
58 .period = 100,
59 };
60 /* NB: ANI is not enabled yet */
61 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
62}
63
64/*
65 * Attach for an AR5416 part.
66 */
67void
68ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
69 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
70{
71 struct ath_hal_5212 *ahp;
72 struct ath_hal *ah;
73
74 ahp = &ahp5416->ah_5212;
75 ar5212InitState(ahp, devid, sc, st, sh, status);
76 ah = &ahp->ah_priv.h;
77
78 /* override 5212 methods for our needs */
79 ah->ah_magic = AR5416_MAGIC;
80 ah->ah_getRateTable = ar5416GetRateTable;
81 ah->ah_detach = ar5416Detach;
82
83 /* Reset functions */
84 ah->ah_reset = ar5416Reset;
85 ah->ah_phyDisable = ar5416PhyDisable;
86 ah->ah_disable = ar5416Disable;
87 ah->ah_configPCIE = ar5416ConfigPCIE;
88 ah->ah_perCalibration = ar5416PerCalibration;
89 ah->ah_perCalibrationN = ar5416PerCalibrationN,
90 ah->ah_resetCalValid = ar5416ResetCalValid,
91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
92 ah->ah_setTxPower = ar5416SetTransmitPower;
93 ah->ah_setBoardValues = ar5416SetBoardValues;
94
95 /* Transmit functions */
96 ah->ah_stopTxDma = ar5416StopTxDma;
97 ah->ah_setupTxDesc = ar5416SetupTxDesc;
98 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
99 ah->ah_fillTxDesc = ar5416FillTxDesc;
100 ah->ah_procTxDesc = ar5416ProcTxDesc;
101 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;
102
103 /* Receive Functions */
104 ah->ah_startPcuReceive = ar5416StartPcuReceive;
105 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
106 ah->ah_setupRxDesc = ar5416SetupRxDesc;
107 ah->ah_procRxDesc = ar5416ProcRxDesc;
108 ah->ah_rxMonitor = ar5416RxMonitor;
109 ah->ah_aniPoll = ar5416AniPoll;
110 ah->ah_procMibEvent = ar5416ProcessMibIntr;
111
112 /* Misc Functions */
113 ah->ah_getCapability = ar5416GetCapability;
114 ah->ah_getDiagState = ar5416GetDiagState;
115 ah->ah_setLedState = ar5416SetLedState;
116 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
117 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
118 ah->ah_gpioGet = ar5416GpioGet;
119 ah->ah_gpioSet = ar5416GpioSet;
120 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
121 ah->ah_resetTsf = ar5416ResetTsf;
122 ah->ah_getRfGain = ar5416GetRfgain;
123 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
124 ah->ah_setDecompMask = ar5416SetDecompMask;
125 ah->ah_setCoverageClass = ar5416SetCoverageClass;
126
127 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
128 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
129
130 /* Power Management Functions */
131 ah->ah_setPowerMode = ar5416SetPowerMode;
132
133 /* Beacon Management Functions */
134 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
135 ah->ah_beaconInit = ar5416BeaconInit;
136 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
137 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
138
139 /* 802.11n Functions */
140 ah->ah_chainTxDesc = ar5416ChainTxDesc;
141 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
142 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
143 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
144 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
145 ah->ah_clr11nAggr = ar5416Clr11nAggr;
146 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
147 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
148 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
149 ah->ah_get11nRxClear = ar5416Get11nRxClear;
150 ah->ah_set11nRxClear = ar5416Set11nRxClear;
151
152 /* Interrupt functions */
153 ah->ah_isInterruptPending = ar5416IsInterruptPending;
154 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
155 ah->ah_setInterrupts = ar5416SetInterrupts;
156
157 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
158 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
159#ifdef AH_SUPPORT_WRITE_EEPROM
160 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
161#endif
162 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
163
164 AH5416(ah)->ah_writeIni = ar5416WriteIni;
165 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
166 /*
167 * Start by setting all Owl devices to 2x2
168 */
169 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
170 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
171
172 /* Enable all ANI functions to begin with */
173 AH5416(ah)->ah_ani_function = HAL_ANI_ALL;
174}
175
176uint32_t
177ar5416GetRadioRev(struct ath_hal *ah)
178{
179 uint32_t val;
180 int i;
181
182 /* Read Radio Chip Rev Extract */
183 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
184 for (i = 0; i < 8; i++)
185 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
186 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
187 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
188 return ath_hal_reverseBits(val, 8);
189}
190
191/*
192 * Attach for an AR5416 part.
193 */
194static struct ath_hal *
195ar5416Attach(uint16_t devid, HAL_SOFTC sc,
196 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
197 HAL_STATUS *status)
198{
199 struct ath_hal_5416 *ahp5416;
200 struct ath_hal_5212 *ahp;
201 struct ath_hal *ah;
202 uint32_t val;
203 HAL_STATUS ecode;
204 HAL_BOOL rfStatus;
205
206 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
207 __func__, sc, (void*) st, (void*) sh);
208
209 /* NB: memory is returned zero'd */
210 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
211 /* extra space for Owl 2.1/2.2 WAR */
212 sizeof(ar5416Addac)
213 );
214 if (ahp5416 == AH_NULL) {
215 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
216 "%s: cannot allocate memory for state block\n", __func__);
217 *status = HAL_ENOMEM;
218 return AH_NULL;
219 }
220 ar5416InitState(ahp5416, devid, sc, st, sh, status);
221 ahp = &ahp5416->ah_5212;
222 ah = &ahp->ah_priv.h;
223
224 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
225 /* reset chip */
226 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
227 ecode = HAL_EIO;
228 goto bad;
229 }
230
231 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
232 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
233 ecode = HAL_EIO;
234 goto bad;
235 }
236 /* Read Revisions from Chips before taking out of reset */
237 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
238 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
239 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
240 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
241
242 /* setup common ini data; rf backends handle remainder */
243 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
244 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
245
246 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
247 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
248 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
249 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
250 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
251 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
252 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
253 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
254
255 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
256 struct ini {
257 uint32_t *data; /* NB: !const */
258 int rows, cols;
259 };
260 /* override CLKDRV value */
261 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
262 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
263 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
264 }
265
266 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
267 ar5416AttachPCIE(ah);
268
269 ecode = ath_hal_v14EepromAttach(ah);
270 if (ecode != HAL_OK)
271 goto bad;
272
273 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
274 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
275 __func__);
276 ecode = HAL_EIO;
277 goto bad;
278 }
279
280 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
281
282 if (!ar5212ChipTest(ah)) {
283 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
284 __func__);
285 ecode = HAL_ESELFTEST;
286 goto bad;
287 }
288
289 /*
290 * Set correct Baseband to analog shift
291 * setting to access analog chips.
292 */
293 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
294
295 /* Read Radio Chip Rev Extract */
296 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
297 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
298 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
299 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
300 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
301 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
302 break;
303 default:
304 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
305 /*
306 * When RF_Silen is used the analog chip is reset.
307 * So when the system boots with radio switch off
308 * the RF chip rev reads back as zero and we need
309 * to use the mac+phy revs to set the radio rev.
310 */
311 AH_PRIVATE(ah)->ah_analog5GhzRev =
312 AR_RAD5133_SREV_MAJOR;
313 break;
314 }
315 /* NB: silently accept anything in release code per Atheros */
316#ifdef AH_DEBUG
317 HALDEBUG(ah, HAL_DEBUG_ANY,
318 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
319 "this driver\n", __func__,
320 AH_PRIVATE(ah)->ah_analog5GhzRev);
321 ecode = HAL_ENOTSUPP;
322 goto bad;
323#endif
324 }
325
326 /*
327 * Got everything we need now to setup the capabilities.
328 */
329 if (!ar5416FillCapabilityInfo(ah)) {
330 ecode = HAL_EEREAD;
331 goto bad;
332 }
333
334 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
335 if (ecode != HAL_OK) {
336 HALDEBUG(ah, HAL_DEBUG_ANY,
337 "%s: error getting mac address from EEPROM\n", __func__);
338 goto bad;
339 }
340 /* XXX How about the serial number ? */
341 /* Read Reg Domain */
342 AH_PRIVATE(ah)->ah_currentRD =
343 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
344
345 /*
346 * ah_miscMode is populated by ar5416FillCapabilityInfo()
347 * starting from griffin. Set here to make sure that
348 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
349 * placed into hardware.
350 */
351 if (ahp->ah_miscMode != 0)
352 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
353
354 rfStatus = ar2133RfAttach(ah, &ecode);
355 if (!rfStatus) {
356 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
357 __func__, ecode);
358 goto bad;
359 }
360
361 ar5416AniSetup(ah); /* Anti Noise Immunity */
362
363 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
364 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
365 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
366 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
367 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
368 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
369
370 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
371
372 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
373
374 return ah;
375bad:
376 if (ahp)
377 ar5416Detach((struct ath_hal *) ahp);
378 if (status)
379 *status = ecode;
380 return AH_NULL;
381}
382
383void
384ar5416Detach(struct ath_hal *ah)
385{
386 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
387
388 HALASSERT(ah != AH_NULL);
389 HALASSERT(ah->ah_magic == AR5416_MAGIC);
390
391 ar5416AniDetach(ah);
392 ar5212RfDetach(ah);
393 ah->ah_disable(ah);
394 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
395 ath_hal_eepromDetach(ah);
396 ath_hal_free(ah);
397}
398
399void
400ar5416AttachPCIE(struct ath_hal *ah)
401{
402 if (AH_PRIVATE(ah)->ah_ispcie)
403 ath_hal_configPCIE(ah, AH_FALSE);
404 else
405 ath_hal_disablePCIE(ah);
406}
407
408static void
409ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
410{
411 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
412 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
413 OS_DELAY(1000);
414 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
415 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
416 }
417}
418
419static void
420ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
421{
422 u_int modesIndex, freqIndex;
423 int regWrites = 0;
424
425 /* Setup the indices for the next set of register array writes */
426 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
427 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
428 freqIndex = 2;
429 if (IEEE80211_IS_CHAN_HT40(chan))
430 modesIndex = 3;
431 else if (IEEE80211_IS_CHAN_108G(chan))
432 modesIndex = 5;
433 else
434 modesIndex = 4;
435 } else {
436 freqIndex = 1;
437 if (IEEE80211_IS_CHAN_HT40(chan) ||
438 IEEE80211_IS_CHAN_TURBO(chan))
439 modesIndex = 2;
440 else
441 modesIndex = 1;
442 }
443
444 /* Set correct Baseband to analog shift setting to access analog chips. */
445 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
446
447 /*
448 * Write addac shifts
449 */
450 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
451#if 0
452 /* NB: only required for Sowl */
453 ar5416EepromSetAddac(ah, chan);
454#endif
455 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
456 regWrites);
457 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
458
459 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
460 modesIndex, regWrites);
461 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
462 1, regWrites);
463
464 /* XXX updated regWrites? */
465 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
466}
467
468/*
469 * Convert to baseband spur frequency given input channel frequency
470 * and compute register settings below.
471 */
472
473static void
474ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
475{
476 uint16_t freq = ath_hal_gethwchannel(ah, chan);
477 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
478 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
479 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
480 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
481 static const int inc[4] = { 0, 100, 0, 0 };
482
483 int bb_spur = AR_NO_SPUR;
484 int bin, cur_bin;
485 int spur_freq_sd;
486 int spur_delta_phase;
487 int denominator;
488 int upper, lower, cur_vit_mask;
489 int tmp, new;
490 int i;
491
492 int8_t mask_m[123];
493 int8_t mask_p[123];
494 int8_t mask_amt;
495 int tmp_mask;
496 int cur_bb_spur;
497 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
498
499 OS_MEMZERO(mask_m, sizeof(mask_m));
500 OS_MEMZERO(mask_p, sizeof(mask_p));
501
502 /*
503 * Need to verify range +/- 9.5 for static ht20, otherwise spur
504 * is out-of-band and can be ignored.
505 */
506 /* XXX ath9k changes */
507 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
508 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
509 if (AR_NO_SPUR == cur_bb_spur)
510 break;
511 cur_bb_spur = cur_bb_spur - (freq * 10);
512 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
513 bb_spur = cur_bb_spur;
514 break;
515 }
516 }
517 if (AR_NO_SPUR == bb_spur)
518 return;
519
520 bin = bb_spur * 32;
521
522 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
523 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
524 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
525 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
526 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
527
528 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
529
530 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
531 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
532 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
533 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
534 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
535 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
536 /*
537 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
538 * config, no offset for HT20.
539 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
540 * /80 for dyn2040.
541 */
542 spur_delta_phase = ((bb_spur * 524288) / 100) &
543 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
544 /*
545 * in 11A mode the denominator of spur_freq_sd should be 40 and
546 * it should be 44 in 11G
547 */
548 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
549 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
550
551 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
552 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
553 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
554 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
555
556
557 /*
558 * ============================================
559 * pilot mask 1 [31:0] = +6..-26, no 0 bin
560 * pilot mask 2 [19:0] = +26..+7
561 *
562 * channel mask 1 [31:0] = +6..-26, no 0 bin
563 * channel mask 2 [19:0] = +26..+7
564 */
565 //cur_bin = -26;
566 cur_bin = -6000;
567 upper = bin + 100;
568 lower = bin - 100;
569
570 for (i = 0; i < 4; i++) {
571 int pilot_mask = 0;
572 int chan_mask = 0;
573 int bp = 0;
574 for (bp = 0; bp < 30; bp++) {
575 if ((cur_bin > lower) && (cur_bin < upper)) {
576 pilot_mask = pilot_mask | 0x1 << bp;
577 chan_mask = chan_mask | 0x1 << bp;
578 }
579 cur_bin += 100;
580 }
581 cur_bin += inc[i];
582 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
583 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
584 }
585
586 /* =================================================
587 * viterbi mask 1 based on channel magnitude
588 * four levels 0-3
589 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
590 * [1 2 2 1] for -9.6 or [1 2 1] for +16
591 * - enable_mask_ppm, all bins move with freq
592 *
593 * - mask_select, 8 bits for rates (reg 67,0x990c)
594 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
595 * choose which mask to use mask or mask2
596 */
597
598 /*
599 * viterbi mask 2 2nd set for per data rate puncturing
600 * four levels 0-3
601 * - mask_select, 8 bits for rates (reg 67)
602 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
603 * [1 2 2 1] for -9.6 or [1 2 1] for +16
604 */
605 cur_vit_mask = 6100;
606 upper = bin + 120;
607 lower = bin - 120;
608
609 for (i = 0; i < 123; i++) {
610 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
611 if ((abs(cur_vit_mask - bin)) < 75) {
612 mask_amt = 1;
613 } else {
614 mask_amt = 0;
615 }
616 if (cur_vit_mask < 0) {
617 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
618 } else {
619 mask_p[cur_vit_mask / 100] = mask_amt;
620 }
621 }
622 cur_vit_mask -= 100;
623 }
624
625 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
626 | (mask_m[48] << 26) | (mask_m[49] << 24)
627 | (mask_m[50] << 22) | (mask_m[51] << 20)
628 | (mask_m[52] << 18) | (mask_m[53] << 16)
629 | (mask_m[54] << 14) | (mask_m[55] << 12)
630 | (mask_m[56] << 10) | (mask_m[57] << 8)
631 | (mask_m[58] << 6) | (mask_m[59] << 4)
632 | (mask_m[60] << 2) | (mask_m[61] << 0);
633 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
634 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
635
636 tmp_mask = (mask_m[31] << 28)
637 | (mask_m[32] << 26) | (mask_m[33] << 24)
638 | (mask_m[34] << 22) | (mask_m[35] << 20)
639 | (mask_m[36] << 18) | (mask_m[37] << 16)
640 | (mask_m[48] << 14) | (mask_m[39] << 12)
641 | (mask_m[40] << 10) | (mask_m[41] << 8)
642 | (mask_m[42] << 6) | (mask_m[43] << 4)
643 | (mask_m[44] << 2) | (mask_m[45] << 0);
644 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
645 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
646
647 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
648 | (mask_m[18] << 26) | (mask_m[18] << 24)
649 | (mask_m[20] << 22) | (mask_m[20] << 20)
650 | (mask_m[22] << 18) | (mask_m[22] << 16)
651 | (mask_m[24] << 14) | (mask_m[24] << 12)
652 | (mask_m[25] << 10) | (mask_m[26] << 8)
653 | (mask_m[27] << 6) | (mask_m[28] << 4)
654 | (mask_m[29] << 2) | (mask_m[30] << 0);
655 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
656 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
657
658 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
659 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
660 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
661 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
662 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
663 | (mask_m[10] << 10) | (mask_m[11] << 8)
664 | (mask_m[12] << 6) | (mask_m[13] << 4)
665 | (mask_m[14] << 2) | (mask_m[15] << 0);
666 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
667 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
668
669 tmp_mask = (mask_p[15] << 28)
670 | (mask_p[14] << 26) | (mask_p[13] << 24)
671 | (mask_p[12] << 22) | (mask_p[11] << 20)
672 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
673 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
674 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
675 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
676 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
677 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
678 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
679
680 tmp_mask = (mask_p[30] << 28)
681 | (mask_p[29] << 26) | (mask_p[28] << 24)
682 | (mask_p[27] << 22) | (mask_p[26] << 20)
683 | (mask_p[25] << 18) | (mask_p[24] << 16)
684 | (mask_p[23] << 14) | (mask_p[22] << 12)
685 | (mask_p[21] << 10) | (mask_p[20] << 8)
686 | (mask_p[19] << 6) | (mask_p[18] << 4)
687 | (mask_p[17] << 2) | (mask_p[16] << 0);
688 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
689 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
690
691 tmp_mask = (mask_p[45] << 28)
692 | (mask_p[44] << 26) | (mask_p[43] << 24)
693 | (mask_p[42] << 22) | (mask_p[41] << 20)
694 | (mask_p[40] << 18) | (mask_p[39] << 16)
695 | (mask_p[38] << 14) | (mask_p[37] << 12)
696 | (mask_p[36] << 10) | (mask_p[35] << 8)
697 | (mask_p[34] << 6) | (mask_p[33] << 4)
698 | (mask_p[32] << 2) | (mask_p[31] << 0);
699 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
700 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
701
702 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
703 | (mask_p[59] << 26) | (mask_p[58] << 24)
704 | (mask_p[57] << 22) | (mask_p[56] << 20)
705 | (mask_p[55] << 18) | (mask_p[54] << 16)
706 | (mask_p[53] << 14) | (mask_p[52] << 12)
707 | (mask_p[51] << 10) | (mask_p[50] << 8)
708 | (mask_p[49] << 6) | (mask_p[48] << 4)
709 | (mask_p[47] << 2) | (mask_p[46] << 0);
710 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
711 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
712}
713
714/*
715 * Fill all software cached or static hardware state information.
716 * Return failure if capabilities are to come from EEPROM and
717 * cannot be read.
718 */
719HAL_BOOL
720ar5416FillCapabilityInfo(struct ath_hal *ah)
721{
722 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
723 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
724 uint16_t val;
725
726 /* Construct wireless mode from EEPROM */
727 pCap->halWirelessModes = 0;
728 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
729 pCap->halWirelessModes |= HAL_MODE_11A
730 | HAL_MODE_11NA_HT20
731 | HAL_MODE_11NA_HT40PLUS
732 | HAL_MODE_11NA_HT40MINUS
733 ;
734 }
735 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
736 pCap->halWirelessModes |= HAL_MODE_11G
737 | HAL_MODE_11NG_HT20
738 | HAL_MODE_11NG_HT40PLUS
739 | HAL_MODE_11NG_HT40MINUS
740 ;
741 pCap->halWirelessModes |= HAL_MODE_11A
742 | HAL_MODE_11NA_HT20
743 | HAL_MODE_11NA_HT40PLUS
744 | HAL_MODE_11NA_HT40MINUS
745 ;
746 }
747
748 pCap->halLow2GhzChan = 2312;
749 pCap->halHigh2GhzChan = 2732;
750
751 pCap->halLow5GhzChan = 4915;
752 pCap->halHigh5GhzChan = 6100;
753
754 pCap->halCipherCkipSupport = AH_FALSE;
755 pCap->halCipherTkipSupport = AH_TRUE;
756 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
757
758 pCap->halMicCkipSupport = AH_FALSE;
759 pCap->halMicTkipSupport = AH_TRUE;
760 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
761 /*
762 * Starting with Griffin TX+RX mic keys can be combined
763 * in one key cache slot.
764 */
765 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
766 pCap->halChanSpreadSupport = AH_TRUE;
767 pCap->halSleepAfterBeaconBroken = AH_TRUE;
768
769 pCap->halCompressSupport = AH_FALSE;
770 pCap->halBurstSupport = AH_TRUE;
771 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */
772 pCap->halChapTuningSupport = AH_TRUE;
773 pCap->halTurboPrimeSupport = AH_TRUE;
774
775 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
776
777 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
778 pCap->halVEOLSupport = AH_TRUE;
779 pCap->halBssIdMaskSupport = AH_TRUE;
780 pCap->halMcastKeySrchSupport = AH_FALSE;
781 pCap->halTsfAddSupport = AH_TRUE;
782
783 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
784 pCap->halTotalQueues = val;
785 else
786 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
787
788 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
789 pCap->halKeyCacheSize = val;
790 else
791 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
792
793 /* XXX not needed */
794 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */
795 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */
796
797 pCap->halTstampPrecision = 32;
798 pCap->halHwPhyCounterSupport = AH_TRUE;
799 pCap->halIntrMask = HAL_INT_COMMON
800 | HAL_INT_RX
801 | HAL_INT_TX
802 | HAL_INT_FATAL
803 | HAL_INT_BNR
804 | HAL_INT_BMISC
805 | HAL_INT_DTIMSYNC
806 | HAL_INT_TSFOOR
807 | HAL_INT_CST
808 | HAL_INT_GTT
809 ;
810
811 pCap->halFastCCSupport = AH_TRUE;
812 pCap->halNumGpioPins = 6;
813 pCap->halWowSupport = AH_FALSE;
814 pCap->halWowMatchPatternExact = AH_FALSE;
815 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
816 pCap->halAutoSleepSupport = AH_FALSE;
817 pCap->hal4kbSplitTransSupport = AH_TRUE;
818#if 0 /* XXX not yet */
819 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
820 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
821#endif
822 pCap->halHTSupport = AH_TRUE;
823 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
824 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
825 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
826 /* AR5416 may have 3 antennas but is a 2x2 stream device */
827 pCap->halTxStreams = 2;
828 pCap->halRxStreams = 2;
829 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
830 pCap->halMbssidAggrSupport = AH_TRUE;
831 pCap->halForcePpmSupport = AH_TRUE;
832 pCap->halEnhancedPmSupport = AH_TRUE;
833 pCap->halBssidMatchSupport = AH_TRUE;
834
835 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
836 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
837 /* NB: enabled by default */
838 ahpriv->ah_rfkillEnabled = AH_TRUE;
839 pCap->halRfSilentSupport = AH_TRUE;
840 }
841
842 ahpriv->ah_rxornIsFatal = AH_FALSE;
843
844 return AH_TRUE;
845}
846
847static const char*
848ar5416Probe(uint16_t vendorid, uint16_t devid)
849{
850 if (vendorid == ATHEROS_VENDOR_ID &&
851 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE))
852 return "Atheros 5416";
853 return AH_NULL;
854}
855AH_CHIP(AR5416, ar5416Probe, ar5416Attach);