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ar5212_misc.c (222027) ar5212_misc.c (222265)
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c 222027 2011-05-17 15:03:39Z adrian $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c 222265 2011-05-24 18:25:40Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24#ifdef AH_DEBUG
25#include "ah_desc.h" /* NB: for HAL_PHYERR* */
26#endif
27
28#include "ar5212/ar5212.h"
29#include "ar5212/ar5212reg.h"
30#include "ar5212/ar5212phy.h"
31
32#include "ah_eeprom_v3.h"
33
34#define AR_NUM_GPIO 6 /* 6 GPIO pins */
35#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
36
37void
38ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
39{
40 struct ath_hal_5212 *ahp = AH5212(ah);
41
42 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
43}
44
45HAL_BOOL
46ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
47{
48 struct ath_hal_5212 *ahp = AH5212(ah);
49
50 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
51 return AH_TRUE;
52}
53
54void
55ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
56{
57 struct ath_hal_5212 *ahp = AH5212(ah);
58
59 OS_MEMCPY(mask, ahp->ah_bssidmask, IEEE80211_ADDR_LEN);
60}
61
62HAL_BOOL
63ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
64{
65 struct ath_hal_5212 *ahp = AH5212(ah);
66
67 /* save it since it must be rewritten on reset */
68 OS_MEMCPY(ahp->ah_bssidmask, mask, IEEE80211_ADDR_LEN);
69
70 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
71 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
72 return AH_TRUE;
73}
74
75/*
76 * Attempt to change the cards operating regulatory domain to the given value
77 */
78HAL_BOOL
79ar5212SetRegulatoryDomain(struct ath_hal *ah,
80 uint16_t regDomain, HAL_STATUS *status)
81{
82 HAL_STATUS ecode;
83
84 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
85 ecode = HAL_EINVAL;
86 goto bad;
87 }
88 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
89 ecode = HAL_EEWRITE;
90 goto bad;
91 }
92#ifdef AH_SUPPORT_WRITE_REGDOMAIN
93 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
94 HALDEBUG(ah, HAL_DEBUG_ANY,
95 "%s: set regulatory domain to %u (0x%x)\n",
96 __func__, regDomain, regDomain);
97 AH_PRIVATE(ah)->ah_currentRD = regDomain;
98 return AH_TRUE;
99 }
100#endif
101 ecode = HAL_EIO;
102bad:
103 if (status)
104 *status = ecode;
105 return AH_FALSE;
106}
107
108/*
109 * Return the wireless modes (a,b,g,t) supported by hardware.
110 *
111 * This value is what is actually supported by the hardware
112 * and is unaffected by regulatory/country code settings.
113 */
114u_int
115ar5212GetWirelessModes(struct ath_hal *ah)
116{
117 u_int mode = 0;
118
119 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
120 mode = HAL_MODE_11A;
121 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
122 mode |= HAL_MODE_TURBO | HAL_MODE_108A;
123 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
124 mode |= HAL_MODE_11A_HALF_RATE;
125 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
126 mode |= HAL_MODE_11A_QUARTER_RATE;
127 }
128 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
129 mode |= HAL_MODE_11B;
130 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
131 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
132 mode |= HAL_MODE_11G;
133 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
134 mode |= HAL_MODE_108G;
135 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
136 mode |= HAL_MODE_11G_HALF_RATE;
137 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
138 mode |= HAL_MODE_11G_QUARTER_RATE;
139 }
140 return mode;
141}
142
143/*
144 * Set the interrupt and GPIO values so the ISR can disable RF
145 * on a switch signal. Assumes GPIO port and interrupt polarity
146 * are set prior to call.
147 */
148void
149ar5212EnableRfKill(struct ath_hal *ah)
150{
151 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
152 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
153 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
154
155 /*
156 * Configure the desired GPIO port for input
157 * and enable baseband rf silence.
158 */
159 ath_hal_gpioCfgInput(ah, select);
160 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
161 /*
162 * If radio disable switch connection to GPIO bit x is enabled
163 * program GPIO interrupt.
164 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
165 * verified that it is a later version of eeprom, it has a place for
166 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
167 * connection is present.
168 */
169 ath_hal_gpioSetIntr(ah, select,
170 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
171}
172
173/*
174 * Change the LED blinking pattern to correspond to the connectivity
175 */
176void
177ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
178{
179 static const uint32_t ledbits[8] = {
180 AR_PCICFG_LEDCTL_NONE, /* HAL_LED_INIT */
181 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_SCAN */
182 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_AUTH */
183 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_ASSOC*/
184 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_RUN */
185 AR_PCICFG_LEDCTL_NONE,
186 AR_PCICFG_LEDCTL_NONE,
187 AR_PCICFG_LEDCTL_NONE,
188 };
189 uint32_t bits;
190
191 bits = OS_REG_READ(ah, AR_PCICFG);
192 if (IS_2417(ah)) {
193 /*
194 * Enable LED for Nala. There is a bit marked reserved
195 * that must be set and we also turn on the power led.
196 * Because we mark s/w LED control setting the control
197 * status bits below is meangless (the driver must flash
198 * the LED(s) using the GPIO lines).
199 */
200 bits = (bits &~ AR_PCICFG_LEDMODE)
201 | SM(AR_PCICFG_LEDMODE_POWON, AR_PCICFG_LEDMODE)
202#if 0
203 | SM(AR_PCICFG_LEDMODE_NETON, AR_PCICFG_LEDMODE)
204#endif
205 | 0x08000000;
206 }
207 bits = (bits &~ AR_PCICFG_LEDCTL)
208 | SM(ledbits[state & 0x7], AR_PCICFG_LEDCTL);
209 OS_REG_WRITE(ah, AR_PCICFG, bits);
210}
211
212/*
213 * Change association related fields programmed into the hardware.
214 * Writing a valid BSSID to the hardware effectively enables the hardware
215 * to synchronize its TSF to the correct beacons and receive frames coming
216 * from that BSSID. It is called by the SME JOIN operation.
217 */
218void
219ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
220{
221 struct ath_hal_5212 *ahp = AH5212(ah);
222
223 /* XXX save bssid for possible re-use on reset */
224 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
225 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
226 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
227 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
228}
229
230/*
231 * Get the current hardware tsf for stamlme
232 */
233uint64_t
234ar5212GetTsf64(struct ath_hal *ah)
235{
236 uint32_t low1, low2, u32;
237
238 /* sync multi-word read */
239 low1 = OS_REG_READ(ah, AR_TSF_L32);
240 u32 = OS_REG_READ(ah, AR_TSF_U32);
241 low2 = OS_REG_READ(ah, AR_TSF_L32);
242 if (low2 < low1) { /* roll over */
243 /*
244 * If we are not preempted this will work. If we are
245 * then we re-reading AR_TSF_U32 does no good as the
246 * low bits will be meaningless. Likewise reading
247 * L32, U32, U32, then comparing the last two reads
248 * to check for rollover doesn't help if preempted--so
249 * we take this approach as it costs one less PCI read
250 * which can be noticeable when doing things like
251 * timestamping packets in monitor mode.
252 */
253 u32++;
254 }
255 return (((uint64_t) u32) << 32) | ((uint64_t) low2);
256}
257
258/*
259 * Get the current hardware tsf for stamlme
260 */
261uint32_t
262ar5212GetTsf32(struct ath_hal *ah)
263{
264 return OS_REG_READ(ah, AR_TSF_L32);
265}
266
267void
268ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64)
269{
270 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
271 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
272}
273
274/*
275 * Reset the current hardware tsf for stamlme.
276 */
277void
278ar5212ResetTsf(struct ath_hal *ah)
279{
280
281 uint32_t val = OS_REG_READ(ah, AR_BEACON);
282
283 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
284 /*
285 * When resetting the TSF, write twice to the
286 * corresponding register; each write to the RESET_TSF bit toggles
287 * the internal signal to cause a reset of the TSF - but if the signal
288 * is left high, it will reset the TSF on the next chip reset also!
289 * writing the bit an even number of times fixes this issue
290 */
291 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
292}
293
294/*
295 * Set or clear hardware basic rate bit
296 * Set hardware basic rate set if basic rate is found
297 * and basic rate is equal or less than 2Mbps
298 */
299void
300ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
301{
302 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
303 uint32_t reg;
304 uint8_t xset;
305 int i;
306
307 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan))
308 return;
309 xset = 0;
310 for (i = 0; i < rs->rs_count; i++) {
311 uint8_t rset = rs->rs_rates[i];
312 /* Basic rate defined? */
313 if ((rset & 0x80) && (rset &= 0x7f) >= xset)
314 xset = rset;
315 }
316 /*
317 * Set the h/w bit to reflect whether or not the basic
318 * rate is found to be equal or less than 2Mbps.
319 */
320 reg = OS_REG_READ(ah, AR_STA_ID1);
321 if (xset && xset/2 <= 2)
322 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
323 else
324 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
325}
326
327/*
328 * Grab a semi-random value from hardware registers - may not
329 * change often
330 */
331uint32_t
332ar5212GetRandomSeed(struct ath_hal *ah)
333{
334 uint32_t nf;
335
336 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
337 if (nf & 0x100)
338 nf = 0 - ((nf ^ 0x1ff) + 1);
339 return (OS_REG_READ(ah, AR_TSF_U32) ^
340 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
341}
342
343/*
344 * Detect if our card is present
345 */
346HAL_BOOL
347ar5212DetectCardPresent(struct ath_hal *ah)
348{
349 uint16_t macVersion, macRev;
350 uint32_t v;
351
352 /*
353 * Read the Silicon Revision register and compare that
354 * to what we read at attach time. If the same, we say
355 * a card/device is present.
356 */
357 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
358 macVersion = v >> AR_SREV_ID_S;
359 macRev = v & AR_SREV_REVISION;
360 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
361 AH_PRIVATE(ah)->ah_macRev == macRev);
362}
363
364void
365ar5212EnableMibCounters(struct ath_hal *ah)
366{
367 /* NB: this just resets the mib counter machinery */
368 OS_REG_WRITE(ah, AR_MIBC,
369 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f);
370}
371
372void
373ar5212DisableMibCounters(struct ath_hal *ah)
374{
375 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);
376}
377
378/*
379 * Update MIB Counters
380 */
381void
382ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
383{
384 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
385 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
386 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
387 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
388 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
389}
390
391/*
392 * Detect if the HW supports spreading a CCK signal on channel 14
393 */
394HAL_BOOL
395ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
396{
397 return AH_TRUE;
398}
399
400/*
401 * Get the rssi of frame curently being received.
402 */
403uint32_t
404ar5212GetCurRssi(struct ath_hal *ah)
405{
406 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
407}
408
409u_int
410ar5212GetDefAntenna(struct ath_hal *ah)
411{
412 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
413}
414
415void
416ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
417{
418 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
419}
420
421HAL_ANT_SETTING
422ar5212GetAntennaSwitch(struct ath_hal *ah)
423{
424 return AH5212(ah)->ah_antControl;
425}
426
427HAL_BOOL
428ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
429{
430 struct ath_hal_5212 *ahp = AH5212(ah);
431 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
432
433 if (!ahp->ah_phyPowerOn || chan == AH_NULL) {
434 /* PHY powered off, just stash settings */
435 ahp->ah_antControl = setting;
436 ahp->ah_diversity = (setting == HAL_ANT_VARIABLE);
437 return AH_TRUE;
438 }
439 return ar5212SetAntennaSwitchInternal(ah, setting, chan);
440}
441
442HAL_BOOL
443ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
444{
445 return AH_TRUE;
446}
447
448HAL_BOOL
449ar5212SetSifsTime(struct ath_hal *ah, u_int us)
450{
451 struct ath_hal_5212 *ahp = AH5212(ah);
452
453 if (us > ath_hal_mac_usec(ah, 0xffff)) {
454 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
455 __func__, us);
456 ahp->ah_sifstime = (u_int) -1; /* restore default handling */
457 return AH_FALSE;
458 } else {
459 /* convert to system clocks */
460 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
461 ahp->ah_sifstime = us;
462 return AH_TRUE;
463 }
464}
465
466u_int
467ar5212GetSifsTime(struct ath_hal *ah)
468{
469 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
470 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
471}
472
473HAL_BOOL
474ar5212SetSlotTime(struct ath_hal *ah, u_int us)
475{
476 struct ath_hal_5212 *ahp = AH5212(ah);
477
478 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
479 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
480 __func__, us);
481 ahp->ah_slottime = (u_int) -1; /* restore default handling */
482 return AH_FALSE;
483 } else {
484 /* convert to system clocks */
485 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
486 ahp->ah_slottime = us;
487 return AH_TRUE;
488 }
489}
490
491u_int
492ar5212GetSlotTime(struct ath_hal *ah)
493{
494 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
495 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
496}
497
498HAL_BOOL
499ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
500{
501 struct ath_hal_5212 *ahp = AH5212(ah);
502
503 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
504 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
505 __func__, us);
506 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
507 return AH_FALSE;
508 } else {
509 /* convert to system clocks */
510 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
511 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
512 ahp->ah_acktimeout = us;
513 return AH_TRUE;
514 }
515}
516
517u_int
518ar5212GetAckTimeout(struct ath_hal *ah)
519{
520 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
521 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
522}
523
524u_int
525ar5212GetAckCTSRate(struct ath_hal *ah)
526{
527 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
528}
529
530HAL_BOOL
531ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
532{
533 struct ath_hal_5212 *ahp = AH5212(ah);
534
535 if (high) {
536 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
537 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
538 } else {
539 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
540 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
541 }
542 return AH_TRUE;
543}
544
545HAL_BOOL
546ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
547{
548 struct ath_hal_5212 *ahp = AH5212(ah);
549
550 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
551 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
552 __func__, us);
553 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
554 return AH_FALSE;
555 } else {
556 /* convert to system clocks */
557 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
558 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
559 ahp->ah_ctstimeout = us;
560 return AH_TRUE;
561 }
562}
563
564u_int
565ar5212GetCTSTimeout(struct ath_hal *ah)
566{
567 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
568 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
569}
570
571/* Setup decompression for given key index */
572HAL_BOOL
573ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
574{
575 struct ath_hal_5212 *ahp = AH5212(ah);
576
577 if (keyidx >= HAL_DECOMP_MASK_SIZE)
578 return HAL_EINVAL;
579 OS_REG_WRITE(ah, AR_DCM_A, keyidx);
580 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
581 ahp->ah_decompMask[keyidx] = en;
582
583 return AH_TRUE;
584}
585
586/* Setup coverage class */
587void
588ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
589{
590 uint32_t slot, timeout, eifs;
591 u_int clkRate;
592
593 AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
594
595 if (now) {
596 if (AH_PRIVATE(ah)->ah_coverageClass == 0)
597 return;
598
599 /* Don't apply coverage class to non A channels */
600 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
601 return;
602
603 /* Get core clock rate */
604 clkRate = ath_hal_mac_clks(ah, 1);
605
606 /* Compute EIFS */
607 slot = coverageclass * 3 * clkRate;
608 eifs = coverageclass * 6 * clkRate;
609 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
610 slot += IFS_SLOT_HALF_RATE;
611 eifs += IFS_EIFS_HALF_RATE;
612 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
613 slot += IFS_SLOT_QUARTER_RATE;
614 eifs += IFS_EIFS_QUARTER_RATE;
615 } else { /* full rate */
616 slot += IFS_SLOT_FULL_RATE;
617 eifs += IFS_EIFS_FULL_RATE;
618 }
619
620 /*
621 * Add additional time for air propagation for ACK and CTS
622 * timeouts. This value is in core clocks.
623 */
624 timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate);
625
626 /*
627 * Write the values: slot, eifs, ack/cts timeouts.
628 */
629 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
630 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
631 OS_REG_WRITE(ah, AR_TIME_OUT,
632 SM(timeout, AR_TIME_OUT_CTS)
633 | SM(timeout, AR_TIME_OUT_ACK));
634 }
635}
636
637void
638ar5212SetPCUConfig(struct ath_hal *ah)
639{
640 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
641}
642
643/*
644 * Return whether an external 32KHz crystal should be used
645 * to reduce power consumption when sleeping. We do so if
646 * the crystal is present (obtained from EEPROM) and if we
647 * are not running as an AP and are configured to use it.
648 */
649HAL_BOOL
650ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
651{
652 if (opmode != HAL_M_HOSTAP) {
653 struct ath_hal_5212 *ahp = AH5212(ah);
654 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
655 (ahp->ah_enable32kHzClock == USE_32KHZ ||
656 ahp->ah_enable32kHzClock == AUTO_32KHZ);
657 } else
658 return AH_FALSE;
659}
660
661/*
662 * If 32KHz clock exists, use it to lower power consumption during sleep
663 *
664 * Note: If clock is set to 32 KHz, delays on accessing certain
665 * baseband registers (27-31, 124-127) are required.
666 */
667void
668ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
669{
670 if (ar5212Use32KHzclock(ah, opmode)) {
671 /*
672 * Enable clocks to be turned OFF in BB during sleep
673 * and also enable turning OFF 32MHz/40MHz Refclk
674 * from A2.
675 */
676 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
677 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
678 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
679 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
680 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
681 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
682
683 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
684 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);
685 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);
686 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);
687 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);
688 /* # Set sleep clock rate to 32 KHz. */
689 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
690 } else {
691 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);
692 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
693 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
694 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);
695 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
696 }
697 } else {
698 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
699 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
700
701 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */
702
703 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
704 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
705
706 if (IS_2417(ah))
707 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
708 else if (IS_HB63(ah))
709 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
710 else
711 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
712 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
713 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
714 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
715 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
716 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
717 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
718 }
719}
720
721/*
722 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
723 */
724void
725ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
726{
727 if (ar5212Use32KHzclock(ah, opmode)) {
728 /* # Set sleep clock rate back to 32 MHz. */
729 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
730 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
731
732 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
733 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
734 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
735
736 /*
737 * Restore BB registers to power-on defaults
738 */
739 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
740 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
741 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
742 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
743 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
744 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
745 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
746 }
747}
748
749/*
750 * Adjust NF based on statistical values for 5GHz frequencies.
751 * Default method: this may be overridden by the rf backend.
752 */
753int16_t
754ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
755{
756 static const struct {
757 uint16_t freqLow;
758 int16_t adjust;
759 } adjustDef[] = {
760 { 5790, 11 }, /* NB: ordered high -> low */
761 { 5730, 10 },
762 { 5690, 9 },
763 { 5660, 8 },
764 { 5610, 7 },
765 { 5530, 5 },
766 { 5450, 4 },
767 { 5379, 2 },
768 { 5209, 0 },
769 { 3000, 1 },
770 { 0, 0 },
771 };
772 int i;
773
774 for (i = 0; c->channel <= adjustDef[i].freqLow; i++)
775 ;
776 return adjustDef[i].adjust;
777}
778
779HAL_STATUS
780ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
781 uint32_t capability, uint32_t *result)
782{
783#define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion
784 struct ath_hal_5212 *ahp = AH5212(ah);
785 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
786 const struct ar5212AniState *ani;
787
788 switch (type) {
789 case HAL_CAP_CIPHER: /* cipher handled in hardware */
790 switch (capability) {
791 case HAL_CIPHER_AES_CCM:
792 return pCap->halCipherAesCcmSupport ?
793 HAL_OK : HAL_ENOTSUPP;
794 case HAL_CIPHER_AES_OCB:
795 case HAL_CIPHER_TKIP:
796 case HAL_CIPHER_WEP:
797 case HAL_CIPHER_MIC:
798 case HAL_CIPHER_CLR:
799 return HAL_OK;
800 default:
801 return HAL_ENOTSUPP;
802 }
803 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
804 switch (capability) {
805 case 0: /* hardware capability */
806 return HAL_OK;
807 case 1:
808 return (ahp->ah_staId1Defaults &
809 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
810 }
811 return HAL_EINVAL;
812 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
813 switch (capability) {
814 case 0: /* hardware capability */
815 return pCap->halTkipMicTxRxKeySupport ?
816 HAL_ENXIO : HAL_OK;
817 case 1: /* current setting */
818 return (ahp->ah_miscMode &
819 AR_MISC_MODE_MIC_NEW_LOC_ENABLE) ? HAL_ENXIO : HAL_OK;
820 }
821 return HAL_EINVAL;
822 case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC w/ WMM */
823 /* XXX move to capability bit */
824 return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
825 (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
826 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
827 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
828 switch (capability) {
829 case 0: /* hardware capability */
830 return HAL_OK;
831 case 1: /* current setting */
832 return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
833 }
834 return HAL_EINVAL;
835 case HAL_CAP_DIAG:
836 *result = AH_PRIVATE(ah)->ah_diagreg;
837 return HAL_OK;
838 case HAL_CAP_TPC:
839 switch (capability) {
840 case 0: /* hardware capability */
841 return HAL_OK;
842 case 1:
843 return ahp->ah_tpcEnabled ? HAL_OK : HAL_ENXIO;
844 }
845 return HAL_OK;
846 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
847 switch (capability) {
848 case HAL_CAP_RADAR:
849 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
850 HAL_OK: HAL_ENXIO;
851 case HAL_CAP_AR:
852 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
853 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
854 HAL_OK: HAL_ENXIO;
855 }
856 return HAL_ENXIO;
857 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
858 switch (capability) {
859 case 0: /* hardware capability */
860 return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENXIO;
861 case 1:
862 return (ahp->ah_staId1Defaults &
863 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
864 }
865 return HAL_EINVAL;
866 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
867 switch (capability) {
868 case 0: /* hardware capability */
869 return pCap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
870 case 1:
871 return (ahp->ah_miscMode & AR_MISC_MODE_TX_ADD_TSF) ?
872 HAL_OK : HAL_ENXIO;
873 }
874 return HAL_EINVAL;
875 case HAL_CAP_TPC_ACK:
876 *result = MS(ahp->ah_macTPC, AR_TPC_ACK);
877 return HAL_OK;
878 case HAL_CAP_TPC_CTS:
879 *result = MS(ahp->ah_macTPC, AR_TPC_CTS);
880 return HAL_OK;
881 case HAL_CAP_INTMIT: /* interference mitigation */
882 switch (capability) {
883 case 0: /* hardware capability */
884 return HAL_OK;
885 case 1:
886 return (ahp->ah_procPhyErr & HAL_ANI_ENA) ?
887 HAL_OK : HAL_ENXIO;
888 case 2: /* HAL_ANI_NOISE_IMMUNITY_LEVEL */
889 case 3: /* HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION */
890 case 4: /* HAL_ANI_CCK_WEAK_SIGNAL_THR */
891 case 5: /* HAL_ANI_FIRSTEP_LEVEL */
892 case 6: /* HAL_ANI_SPUR_IMMUNITY_LEVEL */
893 ani = ar5212AniGetCurrentState(ah);
894 if (ani == AH_NULL)
895 return HAL_ENXIO;
896 switch (capability) {
897 case 2: *result = ani->noiseImmunityLevel; break;
898 case 3: *result = !ani->ofdmWeakSigDetectOff; break;
899 case 4: *result = ani->cckWeakSigThreshold; break;
900 case 5: *result = ani->firstepLevel; break;
901 case 6: *result = ani->spurImmunityLevel; break;
902 }
903 return HAL_OK;
904 }
905 return HAL_EINVAL;
906 default:
907 return ath_hal_getcapability(ah, type, capability, result);
908 }
909#undef MACVERSION
910}
911
912HAL_BOOL
913ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
914 uint32_t capability, uint32_t setting, HAL_STATUS *status)
915{
916#define N(a) (sizeof(a)/sizeof(a[0]))
917 struct ath_hal_5212 *ahp = AH5212(ah);
918 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
919 uint32_t v;
920
921 switch (type) {
922 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
923 if (setting)
924 ahp->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
925 else
926 ahp->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
927 return AH_TRUE;
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (!pCap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931 /* NB: true =>'s use split key cache layout */
932 if (setting)
933 ahp->ah_miscMode &= ~AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
934 else
935 ahp->ah_miscMode |= AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
936 /* NB: write here so keys can be setup w/o a reset */
937 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
938 return AH_TRUE;
939 case HAL_CAP_DIVERSITY:
940 if (ahp->ah_phyPowerOn) {
941 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
942 if (setting)
943 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
944 else
945 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
946 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
947 }
948 ahp->ah_diversity = (setting != 0);
949 return AH_TRUE;
950 case HAL_CAP_DIAG: /* hardware diagnostic support */
951 /*
952 * NB: could split this up into virtual capabilities,
953 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
954 * seems worth the additional complexity.
955 */
956 AH_PRIVATE(ah)->ah_diagreg = setting;
957 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
958 return AH_TRUE;
959 case HAL_CAP_TPC:
960 ahp->ah_tpcEnabled = (setting != 0);
961 return AH_TRUE;
962 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
963 if (setting)
964 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
965 else
966 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
967 return AH_TRUE;
968 case HAL_CAP_TPC_ACK:
969 case HAL_CAP_TPC_CTS:
970 setting += ahp->ah_txPowerIndexOffset;
971 if (setting > 63)
972 setting = 63;
973 if (type == HAL_CAP_TPC_ACK) {
974 ahp->ah_macTPC &= AR_TPC_ACK;
975 ahp->ah_macTPC |= MS(setting, AR_TPC_ACK);
976 } else {
977 ahp->ah_macTPC &= AR_TPC_CTS;
978 ahp->ah_macTPC |= MS(setting, AR_TPC_CTS);
979 }
980 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
981 return AH_TRUE;
982 case HAL_CAP_INTMIT: { /* interference mitigation */
983 static const HAL_ANI_CMD cmds[] = {
984 HAL_ANI_PRESENT,
985 HAL_ANI_MODE,
986 HAL_ANI_NOISE_IMMUNITY_LEVEL,
987 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
988 HAL_ANI_CCK_WEAK_SIGNAL_THR,
989 HAL_ANI_FIRSTEP_LEVEL,
990 HAL_ANI_SPUR_IMMUNITY_LEVEL,
991 };
992 return capability < N(cmds) ?
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24#ifdef AH_DEBUG
25#include "ah_desc.h" /* NB: for HAL_PHYERR* */
26#endif
27
28#include "ar5212/ar5212.h"
29#include "ar5212/ar5212reg.h"
30#include "ar5212/ar5212phy.h"
31
32#include "ah_eeprom_v3.h"
33
34#define AR_NUM_GPIO 6 /* 6 GPIO pins */
35#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
36
37void
38ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
39{
40 struct ath_hal_5212 *ahp = AH5212(ah);
41
42 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
43}
44
45HAL_BOOL
46ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
47{
48 struct ath_hal_5212 *ahp = AH5212(ah);
49
50 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
51 return AH_TRUE;
52}
53
54void
55ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
56{
57 struct ath_hal_5212 *ahp = AH5212(ah);
58
59 OS_MEMCPY(mask, ahp->ah_bssidmask, IEEE80211_ADDR_LEN);
60}
61
62HAL_BOOL
63ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
64{
65 struct ath_hal_5212 *ahp = AH5212(ah);
66
67 /* save it since it must be rewritten on reset */
68 OS_MEMCPY(ahp->ah_bssidmask, mask, IEEE80211_ADDR_LEN);
69
70 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
71 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
72 return AH_TRUE;
73}
74
75/*
76 * Attempt to change the cards operating regulatory domain to the given value
77 */
78HAL_BOOL
79ar5212SetRegulatoryDomain(struct ath_hal *ah,
80 uint16_t regDomain, HAL_STATUS *status)
81{
82 HAL_STATUS ecode;
83
84 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
85 ecode = HAL_EINVAL;
86 goto bad;
87 }
88 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
89 ecode = HAL_EEWRITE;
90 goto bad;
91 }
92#ifdef AH_SUPPORT_WRITE_REGDOMAIN
93 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
94 HALDEBUG(ah, HAL_DEBUG_ANY,
95 "%s: set regulatory domain to %u (0x%x)\n",
96 __func__, regDomain, regDomain);
97 AH_PRIVATE(ah)->ah_currentRD = regDomain;
98 return AH_TRUE;
99 }
100#endif
101 ecode = HAL_EIO;
102bad:
103 if (status)
104 *status = ecode;
105 return AH_FALSE;
106}
107
108/*
109 * Return the wireless modes (a,b,g,t) supported by hardware.
110 *
111 * This value is what is actually supported by the hardware
112 * and is unaffected by regulatory/country code settings.
113 */
114u_int
115ar5212GetWirelessModes(struct ath_hal *ah)
116{
117 u_int mode = 0;
118
119 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
120 mode = HAL_MODE_11A;
121 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
122 mode |= HAL_MODE_TURBO | HAL_MODE_108A;
123 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
124 mode |= HAL_MODE_11A_HALF_RATE;
125 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
126 mode |= HAL_MODE_11A_QUARTER_RATE;
127 }
128 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
129 mode |= HAL_MODE_11B;
130 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
131 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
132 mode |= HAL_MODE_11G;
133 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
134 mode |= HAL_MODE_108G;
135 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
136 mode |= HAL_MODE_11G_HALF_RATE;
137 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
138 mode |= HAL_MODE_11G_QUARTER_RATE;
139 }
140 return mode;
141}
142
143/*
144 * Set the interrupt and GPIO values so the ISR can disable RF
145 * on a switch signal. Assumes GPIO port and interrupt polarity
146 * are set prior to call.
147 */
148void
149ar5212EnableRfKill(struct ath_hal *ah)
150{
151 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
152 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
153 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
154
155 /*
156 * Configure the desired GPIO port for input
157 * and enable baseband rf silence.
158 */
159 ath_hal_gpioCfgInput(ah, select);
160 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
161 /*
162 * If radio disable switch connection to GPIO bit x is enabled
163 * program GPIO interrupt.
164 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
165 * verified that it is a later version of eeprom, it has a place for
166 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
167 * connection is present.
168 */
169 ath_hal_gpioSetIntr(ah, select,
170 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
171}
172
173/*
174 * Change the LED blinking pattern to correspond to the connectivity
175 */
176void
177ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
178{
179 static const uint32_t ledbits[8] = {
180 AR_PCICFG_LEDCTL_NONE, /* HAL_LED_INIT */
181 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_SCAN */
182 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_AUTH */
183 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_ASSOC*/
184 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_RUN */
185 AR_PCICFG_LEDCTL_NONE,
186 AR_PCICFG_LEDCTL_NONE,
187 AR_PCICFG_LEDCTL_NONE,
188 };
189 uint32_t bits;
190
191 bits = OS_REG_READ(ah, AR_PCICFG);
192 if (IS_2417(ah)) {
193 /*
194 * Enable LED for Nala. There is a bit marked reserved
195 * that must be set and we also turn on the power led.
196 * Because we mark s/w LED control setting the control
197 * status bits below is meangless (the driver must flash
198 * the LED(s) using the GPIO lines).
199 */
200 bits = (bits &~ AR_PCICFG_LEDMODE)
201 | SM(AR_PCICFG_LEDMODE_POWON, AR_PCICFG_LEDMODE)
202#if 0
203 | SM(AR_PCICFG_LEDMODE_NETON, AR_PCICFG_LEDMODE)
204#endif
205 | 0x08000000;
206 }
207 bits = (bits &~ AR_PCICFG_LEDCTL)
208 | SM(ledbits[state & 0x7], AR_PCICFG_LEDCTL);
209 OS_REG_WRITE(ah, AR_PCICFG, bits);
210}
211
212/*
213 * Change association related fields programmed into the hardware.
214 * Writing a valid BSSID to the hardware effectively enables the hardware
215 * to synchronize its TSF to the correct beacons and receive frames coming
216 * from that BSSID. It is called by the SME JOIN operation.
217 */
218void
219ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
220{
221 struct ath_hal_5212 *ahp = AH5212(ah);
222
223 /* XXX save bssid for possible re-use on reset */
224 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
225 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
226 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
227 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
228}
229
230/*
231 * Get the current hardware tsf for stamlme
232 */
233uint64_t
234ar5212GetTsf64(struct ath_hal *ah)
235{
236 uint32_t low1, low2, u32;
237
238 /* sync multi-word read */
239 low1 = OS_REG_READ(ah, AR_TSF_L32);
240 u32 = OS_REG_READ(ah, AR_TSF_U32);
241 low2 = OS_REG_READ(ah, AR_TSF_L32);
242 if (low2 < low1) { /* roll over */
243 /*
244 * If we are not preempted this will work. If we are
245 * then we re-reading AR_TSF_U32 does no good as the
246 * low bits will be meaningless. Likewise reading
247 * L32, U32, U32, then comparing the last two reads
248 * to check for rollover doesn't help if preempted--so
249 * we take this approach as it costs one less PCI read
250 * which can be noticeable when doing things like
251 * timestamping packets in monitor mode.
252 */
253 u32++;
254 }
255 return (((uint64_t) u32) << 32) | ((uint64_t) low2);
256}
257
258/*
259 * Get the current hardware tsf for stamlme
260 */
261uint32_t
262ar5212GetTsf32(struct ath_hal *ah)
263{
264 return OS_REG_READ(ah, AR_TSF_L32);
265}
266
267void
268ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64)
269{
270 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
271 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
272}
273
274/*
275 * Reset the current hardware tsf for stamlme.
276 */
277void
278ar5212ResetTsf(struct ath_hal *ah)
279{
280
281 uint32_t val = OS_REG_READ(ah, AR_BEACON);
282
283 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
284 /*
285 * When resetting the TSF, write twice to the
286 * corresponding register; each write to the RESET_TSF bit toggles
287 * the internal signal to cause a reset of the TSF - but if the signal
288 * is left high, it will reset the TSF on the next chip reset also!
289 * writing the bit an even number of times fixes this issue
290 */
291 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
292}
293
294/*
295 * Set or clear hardware basic rate bit
296 * Set hardware basic rate set if basic rate is found
297 * and basic rate is equal or less than 2Mbps
298 */
299void
300ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
301{
302 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
303 uint32_t reg;
304 uint8_t xset;
305 int i;
306
307 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan))
308 return;
309 xset = 0;
310 for (i = 0; i < rs->rs_count; i++) {
311 uint8_t rset = rs->rs_rates[i];
312 /* Basic rate defined? */
313 if ((rset & 0x80) && (rset &= 0x7f) >= xset)
314 xset = rset;
315 }
316 /*
317 * Set the h/w bit to reflect whether or not the basic
318 * rate is found to be equal or less than 2Mbps.
319 */
320 reg = OS_REG_READ(ah, AR_STA_ID1);
321 if (xset && xset/2 <= 2)
322 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
323 else
324 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
325}
326
327/*
328 * Grab a semi-random value from hardware registers - may not
329 * change often
330 */
331uint32_t
332ar5212GetRandomSeed(struct ath_hal *ah)
333{
334 uint32_t nf;
335
336 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
337 if (nf & 0x100)
338 nf = 0 - ((nf ^ 0x1ff) + 1);
339 return (OS_REG_READ(ah, AR_TSF_U32) ^
340 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
341}
342
343/*
344 * Detect if our card is present
345 */
346HAL_BOOL
347ar5212DetectCardPresent(struct ath_hal *ah)
348{
349 uint16_t macVersion, macRev;
350 uint32_t v;
351
352 /*
353 * Read the Silicon Revision register and compare that
354 * to what we read at attach time. If the same, we say
355 * a card/device is present.
356 */
357 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
358 macVersion = v >> AR_SREV_ID_S;
359 macRev = v & AR_SREV_REVISION;
360 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
361 AH_PRIVATE(ah)->ah_macRev == macRev);
362}
363
364void
365ar5212EnableMibCounters(struct ath_hal *ah)
366{
367 /* NB: this just resets the mib counter machinery */
368 OS_REG_WRITE(ah, AR_MIBC,
369 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f);
370}
371
372void
373ar5212DisableMibCounters(struct ath_hal *ah)
374{
375 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);
376}
377
378/*
379 * Update MIB Counters
380 */
381void
382ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
383{
384 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
385 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
386 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
387 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
388 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
389}
390
391/*
392 * Detect if the HW supports spreading a CCK signal on channel 14
393 */
394HAL_BOOL
395ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
396{
397 return AH_TRUE;
398}
399
400/*
401 * Get the rssi of frame curently being received.
402 */
403uint32_t
404ar5212GetCurRssi(struct ath_hal *ah)
405{
406 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
407}
408
409u_int
410ar5212GetDefAntenna(struct ath_hal *ah)
411{
412 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
413}
414
415void
416ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
417{
418 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
419}
420
421HAL_ANT_SETTING
422ar5212GetAntennaSwitch(struct ath_hal *ah)
423{
424 return AH5212(ah)->ah_antControl;
425}
426
427HAL_BOOL
428ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
429{
430 struct ath_hal_5212 *ahp = AH5212(ah);
431 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
432
433 if (!ahp->ah_phyPowerOn || chan == AH_NULL) {
434 /* PHY powered off, just stash settings */
435 ahp->ah_antControl = setting;
436 ahp->ah_diversity = (setting == HAL_ANT_VARIABLE);
437 return AH_TRUE;
438 }
439 return ar5212SetAntennaSwitchInternal(ah, setting, chan);
440}
441
442HAL_BOOL
443ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
444{
445 return AH_TRUE;
446}
447
448HAL_BOOL
449ar5212SetSifsTime(struct ath_hal *ah, u_int us)
450{
451 struct ath_hal_5212 *ahp = AH5212(ah);
452
453 if (us > ath_hal_mac_usec(ah, 0xffff)) {
454 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
455 __func__, us);
456 ahp->ah_sifstime = (u_int) -1; /* restore default handling */
457 return AH_FALSE;
458 } else {
459 /* convert to system clocks */
460 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
461 ahp->ah_sifstime = us;
462 return AH_TRUE;
463 }
464}
465
466u_int
467ar5212GetSifsTime(struct ath_hal *ah)
468{
469 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
470 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
471}
472
473HAL_BOOL
474ar5212SetSlotTime(struct ath_hal *ah, u_int us)
475{
476 struct ath_hal_5212 *ahp = AH5212(ah);
477
478 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
479 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
480 __func__, us);
481 ahp->ah_slottime = (u_int) -1; /* restore default handling */
482 return AH_FALSE;
483 } else {
484 /* convert to system clocks */
485 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
486 ahp->ah_slottime = us;
487 return AH_TRUE;
488 }
489}
490
491u_int
492ar5212GetSlotTime(struct ath_hal *ah)
493{
494 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
495 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
496}
497
498HAL_BOOL
499ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
500{
501 struct ath_hal_5212 *ahp = AH5212(ah);
502
503 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
504 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
505 __func__, us);
506 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
507 return AH_FALSE;
508 } else {
509 /* convert to system clocks */
510 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
511 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
512 ahp->ah_acktimeout = us;
513 return AH_TRUE;
514 }
515}
516
517u_int
518ar5212GetAckTimeout(struct ath_hal *ah)
519{
520 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
521 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
522}
523
524u_int
525ar5212GetAckCTSRate(struct ath_hal *ah)
526{
527 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
528}
529
530HAL_BOOL
531ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
532{
533 struct ath_hal_5212 *ahp = AH5212(ah);
534
535 if (high) {
536 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
537 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
538 } else {
539 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
540 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
541 }
542 return AH_TRUE;
543}
544
545HAL_BOOL
546ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
547{
548 struct ath_hal_5212 *ahp = AH5212(ah);
549
550 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
551 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
552 __func__, us);
553 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
554 return AH_FALSE;
555 } else {
556 /* convert to system clocks */
557 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
558 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
559 ahp->ah_ctstimeout = us;
560 return AH_TRUE;
561 }
562}
563
564u_int
565ar5212GetCTSTimeout(struct ath_hal *ah)
566{
567 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
568 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
569}
570
571/* Setup decompression for given key index */
572HAL_BOOL
573ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
574{
575 struct ath_hal_5212 *ahp = AH5212(ah);
576
577 if (keyidx >= HAL_DECOMP_MASK_SIZE)
578 return HAL_EINVAL;
579 OS_REG_WRITE(ah, AR_DCM_A, keyidx);
580 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
581 ahp->ah_decompMask[keyidx] = en;
582
583 return AH_TRUE;
584}
585
586/* Setup coverage class */
587void
588ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
589{
590 uint32_t slot, timeout, eifs;
591 u_int clkRate;
592
593 AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
594
595 if (now) {
596 if (AH_PRIVATE(ah)->ah_coverageClass == 0)
597 return;
598
599 /* Don't apply coverage class to non A channels */
600 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
601 return;
602
603 /* Get core clock rate */
604 clkRate = ath_hal_mac_clks(ah, 1);
605
606 /* Compute EIFS */
607 slot = coverageclass * 3 * clkRate;
608 eifs = coverageclass * 6 * clkRate;
609 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
610 slot += IFS_SLOT_HALF_RATE;
611 eifs += IFS_EIFS_HALF_RATE;
612 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
613 slot += IFS_SLOT_QUARTER_RATE;
614 eifs += IFS_EIFS_QUARTER_RATE;
615 } else { /* full rate */
616 slot += IFS_SLOT_FULL_RATE;
617 eifs += IFS_EIFS_FULL_RATE;
618 }
619
620 /*
621 * Add additional time for air propagation for ACK and CTS
622 * timeouts. This value is in core clocks.
623 */
624 timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate);
625
626 /*
627 * Write the values: slot, eifs, ack/cts timeouts.
628 */
629 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
630 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
631 OS_REG_WRITE(ah, AR_TIME_OUT,
632 SM(timeout, AR_TIME_OUT_CTS)
633 | SM(timeout, AR_TIME_OUT_ACK));
634 }
635}
636
637void
638ar5212SetPCUConfig(struct ath_hal *ah)
639{
640 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
641}
642
643/*
644 * Return whether an external 32KHz crystal should be used
645 * to reduce power consumption when sleeping. We do so if
646 * the crystal is present (obtained from EEPROM) and if we
647 * are not running as an AP and are configured to use it.
648 */
649HAL_BOOL
650ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
651{
652 if (opmode != HAL_M_HOSTAP) {
653 struct ath_hal_5212 *ahp = AH5212(ah);
654 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
655 (ahp->ah_enable32kHzClock == USE_32KHZ ||
656 ahp->ah_enable32kHzClock == AUTO_32KHZ);
657 } else
658 return AH_FALSE;
659}
660
661/*
662 * If 32KHz clock exists, use it to lower power consumption during sleep
663 *
664 * Note: If clock is set to 32 KHz, delays on accessing certain
665 * baseband registers (27-31, 124-127) are required.
666 */
667void
668ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
669{
670 if (ar5212Use32KHzclock(ah, opmode)) {
671 /*
672 * Enable clocks to be turned OFF in BB during sleep
673 * and also enable turning OFF 32MHz/40MHz Refclk
674 * from A2.
675 */
676 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
677 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
678 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
679 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
680 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
681 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
682
683 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
684 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);
685 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);
686 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);
687 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);
688 /* # Set sleep clock rate to 32 KHz. */
689 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
690 } else {
691 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);
692 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
693 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
694 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);
695 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
696 }
697 } else {
698 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
699 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
700
701 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */
702
703 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
704 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
705
706 if (IS_2417(ah))
707 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
708 else if (IS_HB63(ah))
709 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
710 else
711 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
712 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
713 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
714 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
715 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
716 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
717 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
718 }
719}
720
721/*
722 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
723 */
724void
725ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
726{
727 if (ar5212Use32KHzclock(ah, opmode)) {
728 /* # Set sleep clock rate back to 32 MHz. */
729 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
730 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
731
732 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
733 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
734 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
735
736 /*
737 * Restore BB registers to power-on defaults
738 */
739 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
740 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
741 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
742 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
743 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
744 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
745 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
746 }
747}
748
749/*
750 * Adjust NF based on statistical values for 5GHz frequencies.
751 * Default method: this may be overridden by the rf backend.
752 */
753int16_t
754ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
755{
756 static const struct {
757 uint16_t freqLow;
758 int16_t adjust;
759 } adjustDef[] = {
760 { 5790, 11 }, /* NB: ordered high -> low */
761 { 5730, 10 },
762 { 5690, 9 },
763 { 5660, 8 },
764 { 5610, 7 },
765 { 5530, 5 },
766 { 5450, 4 },
767 { 5379, 2 },
768 { 5209, 0 },
769 { 3000, 1 },
770 { 0, 0 },
771 };
772 int i;
773
774 for (i = 0; c->channel <= adjustDef[i].freqLow; i++)
775 ;
776 return adjustDef[i].adjust;
777}
778
779HAL_STATUS
780ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
781 uint32_t capability, uint32_t *result)
782{
783#define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion
784 struct ath_hal_5212 *ahp = AH5212(ah);
785 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
786 const struct ar5212AniState *ani;
787
788 switch (type) {
789 case HAL_CAP_CIPHER: /* cipher handled in hardware */
790 switch (capability) {
791 case HAL_CIPHER_AES_CCM:
792 return pCap->halCipherAesCcmSupport ?
793 HAL_OK : HAL_ENOTSUPP;
794 case HAL_CIPHER_AES_OCB:
795 case HAL_CIPHER_TKIP:
796 case HAL_CIPHER_WEP:
797 case HAL_CIPHER_MIC:
798 case HAL_CIPHER_CLR:
799 return HAL_OK;
800 default:
801 return HAL_ENOTSUPP;
802 }
803 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
804 switch (capability) {
805 case 0: /* hardware capability */
806 return HAL_OK;
807 case 1:
808 return (ahp->ah_staId1Defaults &
809 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
810 }
811 return HAL_EINVAL;
812 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
813 switch (capability) {
814 case 0: /* hardware capability */
815 return pCap->halTkipMicTxRxKeySupport ?
816 HAL_ENXIO : HAL_OK;
817 case 1: /* current setting */
818 return (ahp->ah_miscMode &
819 AR_MISC_MODE_MIC_NEW_LOC_ENABLE) ? HAL_ENXIO : HAL_OK;
820 }
821 return HAL_EINVAL;
822 case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC w/ WMM */
823 /* XXX move to capability bit */
824 return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
825 (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
826 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
827 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
828 switch (capability) {
829 case 0: /* hardware capability */
830 return HAL_OK;
831 case 1: /* current setting */
832 return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
833 }
834 return HAL_EINVAL;
835 case HAL_CAP_DIAG:
836 *result = AH_PRIVATE(ah)->ah_diagreg;
837 return HAL_OK;
838 case HAL_CAP_TPC:
839 switch (capability) {
840 case 0: /* hardware capability */
841 return HAL_OK;
842 case 1:
843 return ahp->ah_tpcEnabled ? HAL_OK : HAL_ENXIO;
844 }
845 return HAL_OK;
846 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
847 switch (capability) {
848 case HAL_CAP_RADAR:
849 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
850 HAL_OK: HAL_ENXIO;
851 case HAL_CAP_AR:
852 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
853 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
854 HAL_OK: HAL_ENXIO;
855 }
856 return HAL_ENXIO;
857 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
858 switch (capability) {
859 case 0: /* hardware capability */
860 return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENXIO;
861 case 1:
862 return (ahp->ah_staId1Defaults &
863 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
864 }
865 return HAL_EINVAL;
866 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
867 switch (capability) {
868 case 0: /* hardware capability */
869 return pCap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
870 case 1:
871 return (ahp->ah_miscMode & AR_MISC_MODE_TX_ADD_TSF) ?
872 HAL_OK : HAL_ENXIO;
873 }
874 return HAL_EINVAL;
875 case HAL_CAP_TPC_ACK:
876 *result = MS(ahp->ah_macTPC, AR_TPC_ACK);
877 return HAL_OK;
878 case HAL_CAP_TPC_CTS:
879 *result = MS(ahp->ah_macTPC, AR_TPC_CTS);
880 return HAL_OK;
881 case HAL_CAP_INTMIT: /* interference mitigation */
882 switch (capability) {
883 case 0: /* hardware capability */
884 return HAL_OK;
885 case 1:
886 return (ahp->ah_procPhyErr & HAL_ANI_ENA) ?
887 HAL_OK : HAL_ENXIO;
888 case 2: /* HAL_ANI_NOISE_IMMUNITY_LEVEL */
889 case 3: /* HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION */
890 case 4: /* HAL_ANI_CCK_WEAK_SIGNAL_THR */
891 case 5: /* HAL_ANI_FIRSTEP_LEVEL */
892 case 6: /* HAL_ANI_SPUR_IMMUNITY_LEVEL */
893 ani = ar5212AniGetCurrentState(ah);
894 if (ani == AH_NULL)
895 return HAL_ENXIO;
896 switch (capability) {
897 case 2: *result = ani->noiseImmunityLevel; break;
898 case 3: *result = !ani->ofdmWeakSigDetectOff; break;
899 case 4: *result = ani->cckWeakSigThreshold; break;
900 case 5: *result = ani->firstepLevel; break;
901 case 6: *result = ani->spurImmunityLevel; break;
902 }
903 return HAL_OK;
904 }
905 return HAL_EINVAL;
906 default:
907 return ath_hal_getcapability(ah, type, capability, result);
908 }
909#undef MACVERSION
910}
911
912HAL_BOOL
913ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
914 uint32_t capability, uint32_t setting, HAL_STATUS *status)
915{
916#define N(a) (sizeof(a)/sizeof(a[0]))
917 struct ath_hal_5212 *ahp = AH5212(ah);
918 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
919 uint32_t v;
920
921 switch (type) {
922 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
923 if (setting)
924 ahp->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
925 else
926 ahp->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
927 return AH_TRUE;
928 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
929 if (!pCap->halTkipMicTxRxKeySupport)
930 return AH_FALSE;
931 /* NB: true =>'s use split key cache layout */
932 if (setting)
933 ahp->ah_miscMode &= ~AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
934 else
935 ahp->ah_miscMode |= AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
936 /* NB: write here so keys can be setup w/o a reset */
937 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
938 return AH_TRUE;
939 case HAL_CAP_DIVERSITY:
940 if (ahp->ah_phyPowerOn) {
941 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
942 if (setting)
943 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
944 else
945 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
946 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
947 }
948 ahp->ah_diversity = (setting != 0);
949 return AH_TRUE;
950 case HAL_CAP_DIAG: /* hardware diagnostic support */
951 /*
952 * NB: could split this up into virtual capabilities,
953 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
954 * seems worth the additional complexity.
955 */
956 AH_PRIVATE(ah)->ah_diagreg = setting;
957 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
958 return AH_TRUE;
959 case HAL_CAP_TPC:
960 ahp->ah_tpcEnabled = (setting != 0);
961 return AH_TRUE;
962 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
963 if (setting)
964 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
965 else
966 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
967 return AH_TRUE;
968 case HAL_CAP_TPC_ACK:
969 case HAL_CAP_TPC_CTS:
970 setting += ahp->ah_txPowerIndexOffset;
971 if (setting > 63)
972 setting = 63;
973 if (type == HAL_CAP_TPC_ACK) {
974 ahp->ah_macTPC &= AR_TPC_ACK;
975 ahp->ah_macTPC |= MS(setting, AR_TPC_ACK);
976 } else {
977 ahp->ah_macTPC &= AR_TPC_CTS;
978 ahp->ah_macTPC |= MS(setting, AR_TPC_CTS);
979 }
980 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
981 return AH_TRUE;
982 case HAL_CAP_INTMIT: { /* interference mitigation */
983 static const HAL_ANI_CMD cmds[] = {
984 HAL_ANI_PRESENT,
985 HAL_ANI_MODE,
986 HAL_ANI_NOISE_IMMUNITY_LEVEL,
987 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
988 HAL_ANI_CCK_WEAK_SIGNAL_THR,
989 HAL_ANI_FIRSTEP_LEVEL,
990 HAL_ANI_SPUR_IMMUNITY_LEVEL,
991 };
992 return capability < N(cmds) ?
993 ar5212AniControl(ah, cmds[capability], setting) :
993 AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) :
994 AH_FALSE;
995 }
996 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
997 if (pCap->halTsfAddSupport) {
998 if (setting)
999 ahp->ah_miscMode |= AR_MISC_MODE_TX_ADD_TSF;
1000 else
1001 ahp->ah_miscMode &= ~AR_MISC_MODE_TX_ADD_TSF;
1002 return AH_TRUE;
1003 }
1004 /* fall thru... */
1005 default:
1006 return ath_hal_setcapability(ah, type, capability,
1007 setting, status);
1008 }
1009#undef N
1010}
1011
1012HAL_BOOL
1013ar5212GetDiagState(struct ath_hal *ah, int request,
1014 const void *args, uint32_t argsize,
1015 void **result, uint32_t *resultsize)
1016{
1017 struct ath_hal_5212 *ahp = AH5212(ah);
1018
1019 (void) ahp;
1020 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1021 return AH_TRUE;
1022 switch (request) {
1023 case HAL_DIAG_EEPROM:
1024 case HAL_DIAG_EEPROM_EXP_11A:
1025 case HAL_DIAG_EEPROM_EXP_11B:
1026 case HAL_DIAG_EEPROM_EXP_11G:
1027 case HAL_DIAG_RFGAIN:
1028 return ath_hal_eepromDiag(ah, request,
1029 args, argsize, result, resultsize);
1030 case HAL_DIAG_RFGAIN_CURSTEP:
1031 *result = __DECONST(void *, ahp->ah_gainValues.currStep);
1032 *resultsize = (*result == AH_NULL) ?
1033 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1034 return AH_TRUE;
1035 case HAL_DIAG_PCDAC:
1036 *result = ahp->ah_pcdacTable;
1037 *resultsize = ahp->ah_pcdacTableSize;
1038 return AH_TRUE;
1039 case HAL_DIAG_TXRATES:
1040 *result = &ahp->ah_ratesArray[0];
1041 *resultsize = sizeof(ahp->ah_ratesArray);
1042 return AH_TRUE;
1043 case HAL_DIAG_ANI_CURRENT:
1044 *result = ar5212AniGetCurrentState(ah);
1045 *resultsize = (*result == AH_NULL) ?
1046 0 : sizeof(struct ar5212AniState);
1047 return AH_TRUE;
1048 case HAL_DIAG_ANI_STATS:
1049 *result = ar5212AniGetCurrentStats(ah);
1050 *resultsize = (*result == AH_NULL) ?
1051 0 : sizeof(struct ar5212Stats);
1052 return AH_TRUE;
1053 case HAL_DIAG_ANI_CMD:
1054 if (argsize != 2*sizeof(uint32_t))
1055 return AH_FALSE;
994 AH_FALSE;
995 }
996 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
997 if (pCap->halTsfAddSupport) {
998 if (setting)
999 ahp->ah_miscMode |= AR_MISC_MODE_TX_ADD_TSF;
1000 else
1001 ahp->ah_miscMode &= ~AR_MISC_MODE_TX_ADD_TSF;
1002 return AH_TRUE;
1003 }
1004 /* fall thru... */
1005 default:
1006 return ath_hal_setcapability(ah, type, capability,
1007 setting, status);
1008 }
1009#undef N
1010}
1011
1012HAL_BOOL
1013ar5212GetDiagState(struct ath_hal *ah, int request,
1014 const void *args, uint32_t argsize,
1015 void **result, uint32_t *resultsize)
1016{
1017 struct ath_hal_5212 *ahp = AH5212(ah);
1018
1019 (void) ahp;
1020 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1021 return AH_TRUE;
1022 switch (request) {
1023 case HAL_DIAG_EEPROM:
1024 case HAL_DIAG_EEPROM_EXP_11A:
1025 case HAL_DIAG_EEPROM_EXP_11B:
1026 case HAL_DIAG_EEPROM_EXP_11G:
1027 case HAL_DIAG_RFGAIN:
1028 return ath_hal_eepromDiag(ah, request,
1029 args, argsize, result, resultsize);
1030 case HAL_DIAG_RFGAIN_CURSTEP:
1031 *result = __DECONST(void *, ahp->ah_gainValues.currStep);
1032 *resultsize = (*result == AH_NULL) ?
1033 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1034 return AH_TRUE;
1035 case HAL_DIAG_PCDAC:
1036 *result = ahp->ah_pcdacTable;
1037 *resultsize = ahp->ah_pcdacTableSize;
1038 return AH_TRUE;
1039 case HAL_DIAG_TXRATES:
1040 *result = &ahp->ah_ratesArray[0];
1041 *resultsize = sizeof(ahp->ah_ratesArray);
1042 return AH_TRUE;
1043 case HAL_DIAG_ANI_CURRENT:
1044 *result = ar5212AniGetCurrentState(ah);
1045 *resultsize = (*result == AH_NULL) ?
1046 0 : sizeof(struct ar5212AniState);
1047 return AH_TRUE;
1048 case HAL_DIAG_ANI_STATS:
1049 *result = ar5212AniGetCurrentStats(ah);
1050 *resultsize = (*result == AH_NULL) ?
1051 0 : sizeof(struct ar5212Stats);
1052 return AH_TRUE;
1053 case HAL_DIAG_ANI_CMD:
1054 if (argsize != 2*sizeof(uint32_t))
1055 return AH_FALSE;
1056 ar5212AniControl(ah, ((const uint32_t *)args)[0],
1056 AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0],
1057 ((const uint32_t *)args)[1]);
1058 return AH_TRUE;
1059 case HAL_DIAG_ANI_PARAMS:
1060 /*
1061 * NB: We assume struct ar5212AniParams is identical
1062 * to HAL_ANI_PARAMS; if they diverge then we'll need
1063 * to handle it here
1064 */
1065 if (argsize == 0 && args == AH_NULL) {
1066 struct ar5212AniState *aniState =
1067 ar5212AniGetCurrentState(ah);
1068 if (aniState == AH_NULL)
1069 return AH_FALSE;
1070 *result = __DECONST(void *, aniState->params);
1071 *resultsize = sizeof(struct ar5212AniParams);
1072 return AH_TRUE;
1073 } else {
1074 if (argsize != sizeof(struct ar5212AniParams))
1075 return AH_FALSE;
1076 return ar5212AniSetParams(ah, args, args);
1077 }
1078 }
1079 return AH_FALSE;
1080}
1081
1082/*
1083 * Check whether there's an in-progress NF completion.
1084 *
1085 * Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE
1086 * otherwise.
1087 */
1088HAL_BOOL
1089ar5212IsNFCalInProgress(struct ath_hal *ah)
1090{
1091 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1092 return AH_TRUE;
1093 return AH_FALSE;
1094}
1095
1096/*
1097 * Wait for an in-progress NF calibration to complete.
1098 *
1099 * The completion function waits "i" times 10uS.
1100 * It returns AH_TRUE if the NF calibration completed (or was never
1101 * in progress); AH_FALSE if it was still in progress after "i" checks.
1102 */
1103HAL_BOOL
1104ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1105{
1106 int j;
1107 if (i <= 0)
1108 i = 1; /* it should run at least once */
1109 for (j = 0; j < i; j++) {
1110 if (! ar5212IsNFCalInProgress(ah))
1111 return AH_TRUE;
1112 OS_DELAY(10);
1113 }
1114 return AH_FALSE;
1115}
1057 ((const uint32_t *)args)[1]);
1058 return AH_TRUE;
1059 case HAL_DIAG_ANI_PARAMS:
1060 /*
1061 * NB: We assume struct ar5212AniParams is identical
1062 * to HAL_ANI_PARAMS; if they diverge then we'll need
1063 * to handle it here
1064 */
1065 if (argsize == 0 && args == AH_NULL) {
1066 struct ar5212AniState *aniState =
1067 ar5212AniGetCurrentState(ah);
1068 if (aniState == AH_NULL)
1069 return AH_FALSE;
1070 *result = __DECONST(void *, aniState->params);
1071 *resultsize = sizeof(struct ar5212AniParams);
1072 return AH_TRUE;
1073 } else {
1074 if (argsize != sizeof(struct ar5212AniParams))
1075 return AH_FALSE;
1076 return ar5212AniSetParams(ah, args, args);
1077 }
1078 }
1079 return AH_FALSE;
1080}
1081
1082/*
1083 * Check whether there's an in-progress NF completion.
1084 *
1085 * Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE
1086 * otherwise.
1087 */
1088HAL_BOOL
1089ar5212IsNFCalInProgress(struct ath_hal *ah)
1090{
1091 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1092 return AH_TRUE;
1093 return AH_FALSE;
1094}
1095
1096/*
1097 * Wait for an in-progress NF calibration to complete.
1098 *
1099 * The completion function waits "i" times 10uS.
1100 * It returns AH_TRUE if the NF calibration completed (or was never
1101 * in progress); AH_FALSE if it was still in progress after "i" checks.
1102 */
1103HAL_BOOL
1104ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1105{
1106 int j;
1107 if (i <= 0)
1108 i = 1; /* it should run at least once */
1109 for (j = 0; j < i; j++) {
1110 if (! ar5212IsNFCalInProgress(ah))
1111 return AH_TRUE;
1112 OS_DELAY(10);
1113 }
1114 return AH_FALSE;
1115}