1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ar5212_attach.c,v 1.18 2008/11/19 22:10:42 sam Exp $
18 */
19#include "opt_ah.h"
20
| 1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ar5212_attach.c,v 1.18 2008/11/19 22:10:42 sam Exp $
18 */
19#include "opt_ah.h"
20
|
21#ifdef AH_SUPPORT_AR5212
22
23#if !defined(AH_SUPPORT_5112) && \
24 !defined(AH_SUPPORT_5111) && \
25 !defined(AH_SUPPORT_2413) && \
26 !defined(AH_SUPPORT_5413) && \
27 !defined(AH_SUPPORT_AR5312)
28#error "No 5212 RF support defined"
29#endif
30
| |
31#include "ah.h"
32#include "ah_internal.h"
33#include "ah_devid.h"
34
35#include "ar5212/ar5212.h"
36#include "ar5212/ar5212reg.h"
37#include "ar5212/ar5212phy.h"
| 21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ar5212/ar5212.h"
26#include "ar5212/ar5212reg.h"
27#include "ar5212/ar5212phy.h"
|
38#ifdef AH_SUPPORT_AR5311
39#include "ar5212/ar5311reg.h"
40#endif
| |
41
42#define AH_5212_COMMON
43#include "ar5212/ar5212.ini"
44
45static const struct ath_hal_private ar5212hal = {{
46 .ah_magic = AR5212_MAGIC,
47 .ah_abi = HAL_ABI_VERSION,
48 .ah_countryCode = CTRY_DEFAULT,
49
50 .ah_getRateTable = ar5212GetRateTable,
51 .ah_detach = ar5212Detach,
52
53 /* Reset Functions */
54 .ah_reset = ar5212Reset,
55 .ah_phyDisable = ar5212PhyDisable,
56 .ah_disable = ar5212Disable,
57 .ah_setPCUConfig = ar5212SetPCUConfig,
58 .ah_perCalibration = ar5212PerCalibration,
59 .ah_perCalibrationN = ar5212PerCalibrationN,
60 .ah_resetCalValid = ar5212ResetCalValid,
61 .ah_setTxPowerLimit = ar5212SetTxPowerLimit,
62 .ah_getChanNoise = ath_hal_getChanNoise,
63
64 /* Transmit functions */
65 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel,
66 .ah_setupTxQueue = ar5212SetupTxQueue,
67 .ah_setTxQueueProps = ar5212SetTxQueueProps,
68 .ah_getTxQueueProps = ar5212GetTxQueueProps,
69 .ah_releaseTxQueue = ar5212ReleaseTxQueue,
70 .ah_resetTxQueue = ar5212ResetTxQueue,
71 .ah_getTxDP = ar5212GetTxDP,
72 .ah_setTxDP = ar5212SetTxDP,
73 .ah_numTxPending = ar5212NumTxPending,
74 .ah_startTxDma = ar5212StartTxDma,
75 .ah_stopTxDma = ar5212StopTxDma,
76 .ah_setupTxDesc = ar5212SetupTxDesc,
77 .ah_setupXTxDesc = ar5212SetupXTxDesc,
78 .ah_fillTxDesc = ar5212FillTxDesc,
79 .ah_procTxDesc = ar5212ProcTxDesc,
80 .ah_getTxIntrQueue = ar5212GetTxIntrQueue,
81 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc,
82
83 /* RX Functions */
84 .ah_getRxDP = ar5212GetRxDP,
85 .ah_setRxDP = ar5212SetRxDP,
86 .ah_enableReceive = ar5212EnableReceive,
87 .ah_stopDmaReceive = ar5212StopDmaReceive,
88 .ah_startPcuReceive = ar5212StartPcuReceive,
89 .ah_stopPcuReceive = ar5212StopPcuReceive,
90 .ah_setMulticastFilter = ar5212SetMulticastFilter,
91 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex,
92 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex,
93 .ah_getRxFilter = ar5212GetRxFilter,
94 .ah_setRxFilter = ar5212SetRxFilter,
95 .ah_setupRxDesc = ar5212SetupRxDesc,
96 .ah_procRxDesc = ar5212ProcRxDesc,
97 .ah_rxMonitor = ar5212AniPoll,
98 .ah_procMibEvent = ar5212ProcessMibIntr,
99
100 /* Misc Functions */
101 .ah_getCapability = ar5212GetCapability,
102 .ah_setCapability = ar5212SetCapability,
103 .ah_getDiagState = ar5212GetDiagState,
104 .ah_getMacAddress = ar5212GetMacAddress,
105 .ah_setMacAddress = ar5212SetMacAddress,
106 .ah_getBssIdMask = ar5212GetBssIdMask,
107 .ah_setBssIdMask = ar5212SetBssIdMask,
108 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain,
109 .ah_setLedState = ar5212SetLedState,
110 .ah_writeAssocid = ar5212WriteAssocid,
111 .ah_gpioCfgInput = ar5212GpioCfgInput,
112 .ah_gpioCfgOutput = ar5212GpioCfgOutput,
113 .ah_gpioGet = ar5212GpioGet,
114 .ah_gpioSet = ar5212GpioSet,
115 .ah_gpioSetIntr = ar5212GpioSetIntr,
116 .ah_getTsf32 = ar5212GetTsf32,
117 .ah_getTsf64 = ar5212GetTsf64,
118 .ah_resetTsf = ar5212ResetTsf,
119 .ah_detectCardPresent = ar5212DetectCardPresent,
120 .ah_updateMibCounters = ar5212UpdateMibCounters,
121 .ah_getRfGain = ar5212GetRfgain,
122 .ah_getDefAntenna = ar5212GetDefAntenna,
123 .ah_setDefAntenna = ar5212SetDefAntenna,
124 .ah_getAntennaSwitch = ar5212GetAntennaSwitch,
125 .ah_setAntennaSwitch = ar5212SetAntennaSwitch,
126 .ah_setSifsTime = ar5212SetSifsTime,
127 .ah_getSifsTime = ar5212GetSifsTime,
128 .ah_setSlotTime = ar5212SetSlotTime,
129 .ah_getSlotTime = ar5212GetSlotTime,
130 .ah_setAckTimeout = ar5212SetAckTimeout,
131 .ah_getAckTimeout = ar5212GetAckTimeout,
132 .ah_setAckCTSRate = ar5212SetAckCTSRate,
133 .ah_getAckCTSRate = ar5212GetAckCTSRate,
134 .ah_setCTSTimeout = ar5212SetCTSTimeout,
135 .ah_getCTSTimeout = ar5212GetCTSTimeout,
136 .ah_setDecompMask = ar5212SetDecompMask,
137 .ah_setCoverageClass = ar5212SetCoverageClass,
138
139 /* Key Cache Functions */
140 .ah_getKeyCacheSize = ar5212GetKeyCacheSize,
141 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry,
142 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid,
143 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry,
144 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac,
145
146 /* Power Management Functions */
147 .ah_setPowerMode = ar5212SetPowerMode,
148 .ah_getPowerMode = ar5212GetPowerMode,
149
150 /* Beacon Functions */
151 .ah_setBeaconTimers = ar5212SetBeaconTimers,
152 .ah_beaconInit = ar5212BeaconInit,
153 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers,
154 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers,
155
156 /* Interrupt Functions */
157 .ah_isInterruptPending = ar5212IsInterruptPending,
158 .ah_getPendingInterrupts = ar5212GetPendingInterrupts,
159 .ah_getInterrupts = ar5212GetInterrupts,
160 .ah_setInterrupts = ar5212SetInterrupts },
161
162 .ah_getChannelEdges = ar5212GetChannelEdges,
163 .ah_getWirelessModes = ar5212GetWirelessModes,
164 .ah_eepromRead = ar5212EepromRead,
165#ifdef AH_SUPPORT_WRITE_EEPROM
166 .ah_eepromWrite = ar5212EepromWrite,
167#endif
168 .ah_gpioCfgOutput = ar5212GpioCfgOutput,
169 .ah_gpioCfgInput = ar5212GpioCfgInput,
170 .ah_gpioGet = ar5212GpioGet,
171 .ah_gpioSet = ar5212GpioSet,
172 .ah_gpioSetIntr = ar5212GpioSetIntr,
173 .ah_getChipPowerLimits = ar5212GetChipPowerLimits,
174};
175
176/*
177 * Disable PLL when in L0s as well as receiver clock when in L1.
178 * This power saving option must be enabled through the Serdes.
179 *
180 * Programming the Serdes must go through the same 288 bit serial shift
181 * register as the other analog registers. Hence the 9 writes.
182 *
183 * XXX Clean up the magic numbers.
184 */
185static void
186configurePciePowerSave(struct ath_hal *ah)
187{
188 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
189 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
190
191 /* RX shut off when elecidle is asserted */
192 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
193 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
194 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
195
196 /* Shut off PLL and CLKREQ active in L1 */
197 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
198 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
199 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
200 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
201
202 /* Load the new settings */
203 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
204}
205
206uint32_t
207ar5212GetRadioRev(struct ath_hal *ah)
208{
209 uint32_t val;
210 int i;
211
212 /* Read Radio Chip Rev Extract */
213 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
214 for (i = 0; i < 8; i++)
215 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
216 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
217 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
218 return ath_hal_reverseBits(val, 8);
219}
220
221static void
222ar5212AniSetup(struct ath_hal *ah)
223{
224 static const struct ar5212AniParams aniparams = {
225 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
226 .totalSizeDesired = { -55, -55, -55, -55, -62 },
227 .coarseHigh = { -14, -14, -14, -14, -12 },
228 .coarseLow = { -64, -64, -64, -64, -70 },
229 .firpwr = { -78, -78, -78, -78, -80 },
230 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */
231 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
232 .maxFirstepLevel = 2, /* levels 0..2 */
233 .firstep = { 0, 4, 8 },
234 .ofdmTrigHigh = 500,
235 .ofdmTrigLow = 200,
236 .cckTrigHigh = 200,
237 .cckTrigLow = 100,
238 .rssiThrHigh = 40,
239 .rssiThrLow = 7,
240 .period = 100,
241 };
242 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
243 struct ar5212AniParams tmp;
244 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
245 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */
246 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
247 } else
248 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
249}
250
251/*
252 * Attach for an AR5212 part.
253 */
254void
255ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
256 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
257{
258#define N(a) (sizeof(a)/sizeof(a[0]))
259 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
260 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
261 struct ath_hal *ah;
262
263 ah = &ahp->ah_priv.h;
264 /* set initial values */
265 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
266 ah->ah_sc = sc;
267 ah->ah_st = st;
268 ah->ah_sh = sh;
269
270 ah->ah_devid = devid; /* NB: for alq */
271 AH_PRIVATE(ah)->ah_devid = devid;
272 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */
273
274 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
275 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
276
277 ahp->ah_antControl = HAL_ANT_VARIABLE;
278 ahp->ah_diversity = AH_TRUE;
279 ahp->ah_bIQCalibration = AH_FALSE;
280 /*
281 * Enable MIC handling.
282 */
283 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
284 ahp->ah_rssiThr = INIT_RSSI_THR;
285 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */
286 ahp->ah_phyPowerOn = AH_FALSE;
287 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
288 | SM(MAX_RATE_POWER, AR_TPC_CTS)
289 | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
290 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */
291 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
292 ahp->ah_slottime = (u_int) -1;
293 ahp->ah_acktimeout = (u_int) -1;
294 ahp->ah_ctstimeout = (u_int) -1;
295 ahp->ah_sifstime = (u_int) -1;
296 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
297#undef N
298}
299
300/*
301 * Validate MAC version and revision.
302 */
303static HAL_BOOL
304ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
305{
306#define N(a) (sizeof(a)/sizeof(a[0]))
307 static const struct {
308 uint8_t version;
309 uint8_t revMin, revMax;
310 } macs[] = {
311 { AR_SREV_VERSION_VENICE,
312 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
313 { AR_SREV_VERSION_GRIFFIN,
314 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
315 { AR_SREV_5413,
316 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
317 { AR_SREV_5424,
318 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
319 { AR_SREV_2425,
320 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
321 { AR_SREV_2417,
322 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
323 };
324 int i;
325
326 for (i = 0; i < N(macs); i++)
327 if (macs[i].version == macVersion &&
328 macs[i].revMin <= macRev && macRev <= macs[i].revMax)
329 return AH_TRUE;
330 return AH_FALSE;
331#undef N
332}
333
334/*
335 * Attach for an AR5212 part.
336 */
| 28
29#define AH_5212_COMMON
30#include "ar5212/ar5212.ini"
31
32static const struct ath_hal_private ar5212hal = {{
33 .ah_magic = AR5212_MAGIC,
34 .ah_abi = HAL_ABI_VERSION,
35 .ah_countryCode = CTRY_DEFAULT,
36
37 .ah_getRateTable = ar5212GetRateTable,
38 .ah_detach = ar5212Detach,
39
40 /* Reset Functions */
41 .ah_reset = ar5212Reset,
42 .ah_phyDisable = ar5212PhyDisable,
43 .ah_disable = ar5212Disable,
44 .ah_setPCUConfig = ar5212SetPCUConfig,
45 .ah_perCalibration = ar5212PerCalibration,
46 .ah_perCalibrationN = ar5212PerCalibrationN,
47 .ah_resetCalValid = ar5212ResetCalValid,
48 .ah_setTxPowerLimit = ar5212SetTxPowerLimit,
49 .ah_getChanNoise = ath_hal_getChanNoise,
50
51 /* Transmit functions */
52 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel,
53 .ah_setupTxQueue = ar5212SetupTxQueue,
54 .ah_setTxQueueProps = ar5212SetTxQueueProps,
55 .ah_getTxQueueProps = ar5212GetTxQueueProps,
56 .ah_releaseTxQueue = ar5212ReleaseTxQueue,
57 .ah_resetTxQueue = ar5212ResetTxQueue,
58 .ah_getTxDP = ar5212GetTxDP,
59 .ah_setTxDP = ar5212SetTxDP,
60 .ah_numTxPending = ar5212NumTxPending,
61 .ah_startTxDma = ar5212StartTxDma,
62 .ah_stopTxDma = ar5212StopTxDma,
63 .ah_setupTxDesc = ar5212SetupTxDesc,
64 .ah_setupXTxDesc = ar5212SetupXTxDesc,
65 .ah_fillTxDesc = ar5212FillTxDesc,
66 .ah_procTxDesc = ar5212ProcTxDesc,
67 .ah_getTxIntrQueue = ar5212GetTxIntrQueue,
68 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc,
69
70 /* RX Functions */
71 .ah_getRxDP = ar5212GetRxDP,
72 .ah_setRxDP = ar5212SetRxDP,
73 .ah_enableReceive = ar5212EnableReceive,
74 .ah_stopDmaReceive = ar5212StopDmaReceive,
75 .ah_startPcuReceive = ar5212StartPcuReceive,
76 .ah_stopPcuReceive = ar5212StopPcuReceive,
77 .ah_setMulticastFilter = ar5212SetMulticastFilter,
78 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex,
79 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex,
80 .ah_getRxFilter = ar5212GetRxFilter,
81 .ah_setRxFilter = ar5212SetRxFilter,
82 .ah_setupRxDesc = ar5212SetupRxDesc,
83 .ah_procRxDesc = ar5212ProcRxDesc,
84 .ah_rxMonitor = ar5212AniPoll,
85 .ah_procMibEvent = ar5212ProcessMibIntr,
86
87 /* Misc Functions */
88 .ah_getCapability = ar5212GetCapability,
89 .ah_setCapability = ar5212SetCapability,
90 .ah_getDiagState = ar5212GetDiagState,
91 .ah_getMacAddress = ar5212GetMacAddress,
92 .ah_setMacAddress = ar5212SetMacAddress,
93 .ah_getBssIdMask = ar5212GetBssIdMask,
94 .ah_setBssIdMask = ar5212SetBssIdMask,
95 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain,
96 .ah_setLedState = ar5212SetLedState,
97 .ah_writeAssocid = ar5212WriteAssocid,
98 .ah_gpioCfgInput = ar5212GpioCfgInput,
99 .ah_gpioCfgOutput = ar5212GpioCfgOutput,
100 .ah_gpioGet = ar5212GpioGet,
101 .ah_gpioSet = ar5212GpioSet,
102 .ah_gpioSetIntr = ar5212GpioSetIntr,
103 .ah_getTsf32 = ar5212GetTsf32,
104 .ah_getTsf64 = ar5212GetTsf64,
105 .ah_resetTsf = ar5212ResetTsf,
106 .ah_detectCardPresent = ar5212DetectCardPresent,
107 .ah_updateMibCounters = ar5212UpdateMibCounters,
108 .ah_getRfGain = ar5212GetRfgain,
109 .ah_getDefAntenna = ar5212GetDefAntenna,
110 .ah_setDefAntenna = ar5212SetDefAntenna,
111 .ah_getAntennaSwitch = ar5212GetAntennaSwitch,
112 .ah_setAntennaSwitch = ar5212SetAntennaSwitch,
113 .ah_setSifsTime = ar5212SetSifsTime,
114 .ah_getSifsTime = ar5212GetSifsTime,
115 .ah_setSlotTime = ar5212SetSlotTime,
116 .ah_getSlotTime = ar5212GetSlotTime,
117 .ah_setAckTimeout = ar5212SetAckTimeout,
118 .ah_getAckTimeout = ar5212GetAckTimeout,
119 .ah_setAckCTSRate = ar5212SetAckCTSRate,
120 .ah_getAckCTSRate = ar5212GetAckCTSRate,
121 .ah_setCTSTimeout = ar5212SetCTSTimeout,
122 .ah_getCTSTimeout = ar5212GetCTSTimeout,
123 .ah_setDecompMask = ar5212SetDecompMask,
124 .ah_setCoverageClass = ar5212SetCoverageClass,
125
126 /* Key Cache Functions */
127 .ah_getKeyCacheSize = ar5212GetKeyCacheSize,
128 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry,
129 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid,
130 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry,
131 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac,
132
133 /* Power Management Functions */
134 .ah_setPowerMode = ar5212SetPowerMode,
135 .ah_getPowerMode = ar5212GetPowerMode,
136
137 /* Beacon Functions */
138 .ah_setBeaconTimers = ar5212SetBeaconTimers,
139 .ah_beaconInit = ar5212BeaconInit,
140 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers,
141 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers,
142
143 /* Interrupt Functions */
144 .ah_isInterruptPending = ar5212IsInterruptPending,
145 .ah_getPendingInterrupts = ar5212GetPendingInterrupts,
146 .ah_getInterrupts = ar5212GetInterrupts,
147 .ah_setInterrupts = ar5212SetInterrupts },
148
149 .ah_getChannelEdges = ar5212GetChannelEdges,
150 .ah_getWirelessModes = ar5212GetWirelessModes,
151 .ah_eepromRead = ar5212EepromRead,
152#ifdef AH_SUPPORT_WRITE_EEPROM
153 .ah_eepromWrite = ar5212EepromWrite,
154#endif
155 .ah_gpioCfgOutput = ar5212GpioCfgOutput,
156 .ah_gpioCfgInput = ar5212GpioCfgInput,
157 .ah_gpioGet = ar5212GpioGet,
158 .ah_gpioSet = ar5212GpioSet,
159 .ah_gpioSetIntr = ar5212GpioSetIntr,
160 .ah_getChipPowerLimits = ar5212GetChipPowerLimits,
161};
162
163/*
164 * Disable PLL when in L0s as well as receiver clock when in L1.
165 * This power saving option must be enabled through the Serdes.
166 *
167 * Programming the Serdes must go through the same 288 bit serial shift
168 * register as the other analog registers. Hence the 9 writes.
169 *
170 * XXX Clean up the magic numbers.
171 */
172static void
173configurePciePowerSave(struct ath_hal *ah)
174{
175 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
176 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
177
178 /* RX shut off when elecidle is asserted */
179 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
180 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
181 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
182
183 /* Shut off PLL and CLKREQ active in L1 */
184 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
185 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
186 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
187 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
188
189 /* Load the new settings */
190 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
191}
192
193uint32_t
194ar5212GetRadioRev(struct ath_hal *ah)
195{
196 uint32_t val;
197 int i;
198
199 /* Read Radio Chip Rev Extract */
200 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
201 for (i = 0; i < 8; i++)
202 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
203 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
204 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
205 return ath_hal_reverseBits(val, 8);
206}
207
208static void
209ar5212AniSetup(struct ath_hal *ah)
210{
211 static const struct ar5212AniParams aniparams = {
212 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
213 .totalSizeDesired = { -55, -55, -55, -55, -62 },
214 .coarseHigh = { -14, -14, -14, -14, -12 },
215 .coarseLow = { -64, -64, -64, -64, -70 },
216 .firpwr = { -78, -78, -78, -78, -80 },
217 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */
218 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
219 .maxFirstepLevel = 2, /* levels 0..2 */
220 .firstep = { 0, 4, 8 },
221 .ofdmTrigHigh = 500,
222 .ofdmTrigLow = 200,
223 .cckTrigHigh = 200,
224 .cckTrigLow = 100,
225 .rssiThrHigh = 40,
226 .rssiThrLow = 7,
227 .period = 100,
228 };
229 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
230 struct ar5212AniParams tmp;
231 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
232 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */
233 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
234 } else
235 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
236}
237
238/*
239 * Attach for an AR5212 part.
240 */
241void
242ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
243 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
244{
245#define N(a) (sizeof(a)/sizeof(a[0]))
246 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
247 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
248 struct ath_hal *ah;
249
250 ah = &ahp->ah_priv.h;
251 /* set initial values */
252 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
253 ah->ah_sc = sc;
254 ah->ah_st = st;
255 ah->ah_sh = sh;
256
257 ah->ah_devid = devid; /* NB: for alq */
258 AH_PRIVATE(ah)->ah_devid = devid;
259 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */
260
261 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
262 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
263
264 ahp->ah_antControl = HAL_ANT_VARIABLE;
265 ahp->ah_diversity = AH_TRUE;
266 ahp->ah_bIQCalibration = AH_FALSE;
267 /*
268 * Enable MIC handling.
269 */
270 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
271 ahp->ah_rssiThr = INIT_RSSI_THR;
272 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */
273 ahp->ah_phyPowerOn = AH_FALSE;
274 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
275 | SM(MAX_RATE_POWER, AR_TPC_CTS)
276 | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
277 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */
278 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
279 ahp->ah_slottime = (u_int) -1;
280 ahp->ah_acktimeout = (u_int) -1;
281 ahp->ah_ctstimeout = (u_int) -1;
282 ahp->ah_sifstime = (u_int) -1;
283 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
284#undef N
285}
286
287/*
288 * Validate MAC version and revision.
289 */
290static HAL_BOOL
291ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
292{
293#define N(a) (sizeof(a)/sizeof(a[0]))
294 static const struct {
295 uint8_t version;
296 uint8_t revMin, revMax;
297 } macs[] = {
298 { AR_SREV_VERSION_VENICE,
299 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
300 { AR_SREV_VERSION_GRIFFIN,
301 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
302 { AR_SREV_5413,
303 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
304 { AR_SREV_5424,
305 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
306 { AR_SREV_2425,
307 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
308 { AR_SREV_2417,
309 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
310 };
311 int i;
312
313 for (i = 0; i < N(macs); i++)
314 if (macs[i].version == macVersion &&
315 macs[i].revMin <= macRev && macRev <= macs[i].revMax)
316 return AH_TRUE;
317 return AH_FALSE;
318#undef N
319}
320
321/*
322 * Attach for an AR5212 part.
323 */
|
337struct ath_hal *
| 324static struct ath_hal *
|
338ar5212Attach(uint16_t devid, HAL_SOFTC sc,
339 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
340{
341#define AH_EEPROM_PROTECT(ah) \
342 (IS_PCIE(ah) ? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
343 struct ath_hal_5212 *ahp;
344 struct ath_hal *ah;
| 325ar5212Attach(uint16_t devid, HAL_SOFTC sc,
326 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
327{
328#define AH_EEPROM_PROTECT(ah) \
329 (IS_PCIE(ah) ? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
330 struct ath_hal_5212 *ahp;
331 struct ath_hal *ah;
|
| 332 struct ath_hal_rf *rf;
|
345 uint32_t val;
346 uint16_t eeval;
347 HAL_STATUS ecode;
| 333 uint32_t val;
334 uint16_t eeval;
335 HAL_STATUS ecode;
|
348 HAL_BOOL rfStatus;
| |
349
350 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
351 __func__, sc, (void*) st, (void*) sh);
352
353 /* NB: memory is returned zero'd */
354 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
355 if (ahp == AH_NULL) {
356 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
357 "%s: cannot allocate memory for state block\n", __func__);
358 *status = HAL_ENOMEM;
359 return AH_NULL;
360 }
361 ar5212InitState(ahp, devid, sc, st, sh, status);
362 ah = &ahp->ah_priv.h;
363
364 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
365 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
366 __func__);
367 ecode = HAL_EIO;
368 goto bad;
369 }
370 /* Read Revisions from Chips before taking out of reset */
371 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
372 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
373 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
374
375 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
376 HALDEBUG(ah, HAL_DEBUG_ANY,
377 "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
378 __func__, AH_PRIVATE(ah)->ah_macVersion,
379 AH_PRIVATE(ah)->ah_macRev);
380 ecode = HAL_ENOTSUPP;
381 goto bad;
382 }
383
384 /* setup common ini data; rf backends handle remainder */
385 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
386 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
387
388 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */
389 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
390 ecode = HAL_EIO;
391 goto bad;
392 }
393
394 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
395
396 if (IS_PCIE(ah)) {
397 /* XXX: build flag to disable this? */
398 configurePciePowerSave(ah);
399 }
400
401 if (!ar5212ChipTest(ah)) {
402 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
403 __func__);
404 ecode = HAL_ESELFTEST;
405 goto bad;
406 }
407
408 /* Enable PCI core retry fix in software for Hainan and up */
409 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
410 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
411
412 /*
413 * Set correct Baseband to analog shift
414 * setting to access analog chips.
415 */
416 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
417
418 /* Read Radio Chip Rev Extract */
419 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
| 336
337 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
338 __func__, sc, (void*) st, (void*) sh);
339
340 /* NB: memory is returned zero'd */
341 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
342 if (ahp == AH_NULL) {
343 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
344 "%s: cannot allocate memory for state block\n", __func__);
345 *status = HAL_ENOMEM;
346 return AH_NULL;
347 }
348 ar5212InitState(ahp, devid, sc, st, sh, status);
349 ah = &ahp->ah_priv.h;
350
351 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
352 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
353 __func__);
354 ecode = HAL_EIO;
355 goto bad;
356 }
357 /* Read Revisions from Chips before taking out of reset */
358 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
359 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
360 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
361
362 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
363 HALDEBUG(ah, HAL_DEBUG_ANY,
364 "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
365 __func__, AH_PRIVATE(ah)->ah_macVersion,
366 AH_PRIVATE(ah)->ah_macRev);
367 ecode = HAL_ENOTSUPP;
368 goto bad;
369 }
370
371 /* setup common ini data; rf backends handle remainder */
372 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
373 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
374
375 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */
376 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
377 ecode = HAL_EIO;
378 goto bad;
379 }
380
381 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
382
383 if (IS_PCIE(ah)) {
384 /* XXX: build flag to disable this? */
385 configurePciePowerSave(ah);
386 }
387
388 if (!ar5212ChipTest(ah)) {
389 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
390 __func__);
391 ecode = HAL_ESELFTEST;
392 goto bad;
393 }
394
395 /* Enable PCI core retry fix in software for Hainan and up */
396 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
397 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
398
399 /*
400 * Set correct Baseband to analog shift
401 * setting to access analog chips.
402 */
403 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
404
405 /* Read Radio Chip Rev Extract */
406 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
|
| 407
408 rf = ath_hal_rfprobe(ah, &ecode);
409 if (rf == AH_NULL)
410 goto bad;
411
|
420 /* NB: silently accept anything in release code per Atheros */
421 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
422 case AR_RAD5111_SREV_MAJOR:
423 case AR_RAD5112_SREV_MAJOR:
424 case AR_RAD2112_SREV_MAJOR:
425 case AR_RAD2111_SREV_MAJOR:
426 case AR_RAD2413_SREV_MAJOR:
427 case AR_RAD5413_SREV_MAJOR:
428 case AR_RAD5424_SREV_MAJOR:
429 break;
430 default:
431 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
432 /*
433 * When RF_Silent is used, the
434 * analog chip is reset. So when the system boots
435 * up with the radio switch off we cannot determine
436 * the RF chip rev. To workaround this check the
437 * mac+phy revs and if Hainan, set the radio rev
438 * to Derby.
439 */
440 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
441 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
442 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
443 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
444 break;
445 }
446 if (IS_2413(ah)) { /* Griffin */
447 AH_PRIVATE(ah)->ah_analog5GhzRev =
448 AR_RAD2413_SREV_MAJOR | 0x1;
449 break;
450 }
451 if (IS_5413(ah)) { /* Eagle */
452 AH_PRIVATE(ah)->ah_analog5GhzRev =
453 AR_RAD5413_SREV_MAJOR | 0x2;
454 break;
455 }
456 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
457 AH_PRIVATE(ah)->ah_analog5GhzRev =
458 AR_RAD5424_SREV_MAJOR | 0x2;
459 break;
460 }
461 }
462#ifdef AH_DEBUG
463 HALDEBUG(ah, HAL_DEBUG_ANY,
464 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
465 "this driver\n",
466 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
467 ecode = HAL_ENOTSUPP;
468 goto bad;
469#endif
470 }
471 if (IS_RAD5112_REV1(ah)) {
472 HALDEBUG(ah, HAL_DEBUG_ANY,
473 "%s: 5112 Rev 1 is not supported by this "
474 "driver (analog5GhzRev 0x%x)\n", __func__,
475 AH_PRIVATE(ah)->ah_analog5GhzRev);
476 ecode = HAL_ENOTSUPP;
477 goto bad;
478 }
479
480 val = OS_REG_READ(ah, AR_PCICFG);
481 val = MS(val, AR_PCICFG_EEPROM_SIZE);
482 if (val == 0) {
483 if (!IS_PCIE(ah)) {
484 HALDEBUG(ah, HAL_DEBUG_ANY,
485 "%s: unsupported EEPROM size %u (0x%x) found\n",
486 __func__, val, val);
487 ecode = HAL_EESIZE;
488 goto bad;
489 }
490 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
491 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
492 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
493 HALDEBUG(ah, HAL_DEBUG_ANY,
494 "%s: unsupported EEPROM size %u (0x%x) found\n",
495 __func__, val, val);
496 ecode = HAL_EESIZE;
497 goto bad;
498 }
499 HALDEBUG(ah, HAL_DEBUG_ANY,
500 "%s: EEPROM size = %d. Must be %d (16k).\n",
501 __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
502 ecode = HAL_EESIZE;
503 goto bad;
504 }
505 ecode = ath_hal_legacyEepromAttach(ah);
506 if (ecode != HAL_OK) {
507 goto bad;
508 }
509 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
510
511 /*
512 * If Bmode and AR5212, verify 2.4 analog exists
513 */
514 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
515 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
516 /*
517 * Set correct Baseband to analog shift
518 * setting to access analog chips.
519 */
520 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
521 OS_DELAY(2000);
522 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
523
524 /* Set baseband for 5GHz chip */
525 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
526 OS_DELAY(2000);
527 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
528 HALDEBUG(ah, HAL_DEBUG_ANY,
529 "%s: 2G Radio Chip Rev 0x%02X is not "
530 "supported by this driver\n", __func__,
531 AH_PRIVATE(ah)->ah_analog2GhzRev);
532 ecode = HAL_ENOTSUPP;
533 goto bad;
534 }
535 }
536
537 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
538 if (ecode != HAL_OK) {
539 HALDEBUG(ah, HAL_DEBUG_ANY,
540 "%s: cannot read regulatory domain from EEPROM\n",
541 __func__);
542 goto bad;
543 }
544 AH_PRIVATE(ah)->ah_currentRD = eeval;
545 /* XXX record serial number */
546
547 /*
548 * Got everything we need now to setup the capabilities.
549 */
550 if (!ar5212FillCapabilityInfo(ah)) {
551 HALDEBUG(ah, HAL_DEBUG_ANY,
552 "%s: failed ar5212FillCapabilityInfo\n", __func__);
553 ecode = HAL_EEREAD;
554 goto bad;
555 }
556
| 412 /* NB: silently accept anything in release code per Atheros */
413 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
414 case AR_RAD5111_SREV_MAJOR:
415 case AR_RAD5112_SREV_MAJOR:
416 case AR_RAD2112_SREV_MAJOR:
417 case AR_RAD2111_SREV_MAJOR:
418 case AR_RAD2413_SREV_MAJOR:
419 case AR_RAD5413_SREV_MAJOR:
420 case AR_RAD5424_SREV_MAJOR:
421 break;
422 default:
423 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
424 /*
425 * When RF_Silent is used, the
426 * analog chip is reset. So when the system boots
427 * up with the radio switch off we cannot determine
428 * the RF chip rev. To workaround this check the
429 * mac+phy revs and if Hainan, set the radio rev
430 * to Derby.
431 */
432 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
433 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
434 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
435 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
436 break;
437 }
438 if (IS_2413(ah)) { /* Griffin */
439 AH_PRIVATE(ah)->ah_analog5GhzRev =
440 AR_RAD2413_SREV_MAJOR | 0x1;
441 break;
442 }
443 if (IS_5413(ah)) { /* Eagle */
444 AH_PRIVATE(ah)->ah_analog5GhzRev =
445 AR_RAD5413_SREV_MAJOR | 0x2;
446 break;
447 }
448 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
449 AH_PRIVATE(ah)->ah_analog5GhzRev =
450 AR_RAD5424_SREV_MAJOR | 0x2;
451 break;
452 }
453 }
454#ifdef AH_DEBUG
455 HALDEBUG(ah, HAL_DEBUG_ANY,
456 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
457 "this driver\n",
458 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
459 ecode = HAL_ENOTSUPP;
460 goto bad;
461#endif
462 }
463 if (IS_RAD5112_REV1(ah)) {
464 HALDEBUG(ah, HAL_DEBUG_ANY,
465 "%s: 5112 Rev 1 is not supported by this "
466 "driver (analog5GhzRev 0x%x)\n", __func__,
467 AH_PRIVATE(ah)->ah_analog5GhzRev);
468 ecode = HAL_ENOTSUPP;
469 goto bad;
470 }
471
472 val = OS_REG_READ(ah, AR_PCICFG);
473 val = MS(val, AR_PCICFG_EEPROM_SIZE);
474 if (val == 0) {
475 if (!IS_PCIE(ah)) {
476 HALDEBUG(ah, HAL_DEBUG_ANY,
477 "%s: unsupported EEPROM size %u (0x%x) found\n",
478 __func__, val, val);
479 ecode = HAL_EESIZE;
480 goto bad;
481 }
482 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
483 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
484 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
485 HALDEBUG(ah, HAL_DEBUG_ANY,
486 "%s: unsupported EEPROM size %u (0x%x) found\n",
487 __func__, val, val);
488 ecode = HAL_EESIZE;
489 goto bad;
490 }
491 HALDEBUG(ah, HAL_DEBUG_ANY,
492 "%s: EEPROM size = %d. Must be %d (16k).\n",
493 __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
494 ecode = HAL_EESIZE;
495 goto bad;
496 }
497 ecode = ath_hal_legacyEepromAttach(ah);
498 if (ecode != HAL_OK) {
499 goto bad;
500 }
501 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
502
503 /*
504 * If Bmode and AR5212, verify 2.4 analog exists
505 */
506 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
507 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
508 /*
509 * Set correct Baseband to analog shift
510 * setting to access analog chips.
511 */
512 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
513 OS_DELAY(2000);
514 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
515
516 /* Set baseband for 5GHz chip */
517 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
518 OS_DELAY(2000);
519 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
520 HALDEBUG(ah, HAL_DEBUG_ANY,
521 "%s: 2G Radio Chip Rev 0x%02X is not "
522 "supported by this driver\n", __func__,
523 AH_PRIVATE(ah)->ah_analog2GhzRev);
524 ecode = HAL_ENOTSUPP;
525 goto bad;
526 }
527 }
528
529 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
530 if (ecode != HAL_OK) {
531 HALDEBUG(ah, HAL_DEBUG_ANY,
532 "%s: cannot read regulatory domain from EEPROM\n",
533 __func__);
534 goto bad;
535 }
536 AH_PRIVATE(ah)->ah_currentRD = eeval;
537 /* XXX record serial number */
538
539 /*
540 * Got everything we need now to setup the capabilities.
541 */
542 if (!ar5212FillCapabilityInfo(ah)) {
543 HALDEBUG(ah, HAL_DEBUG_ANY,
544 "%s: failed ar5212FillCapabilityInfo\n", __func__);
545 ecode = HAL_EEREAD;
546 goto bad;
547 }
548
|
557 rfStatus = AH_FALSE;
558 if (IS_5413(ah)) {
559#ifdef AH_SUPPORT_5413
560 rfStatus = ar5413RfAttach(ah, &ecode);
561#else
562 ecode = HAL_ENOTSUPP;
563#endif
564 }
565 else if (IS_2413(ah))
566#ifdef AH_SUPPORT_2413
567 rfStatus = ar2413RfAttach(ah, &ecode);
568#else
569 ecode = HAL_ENOTSUPP;
570#endif
571 else if (IS_RAD5112(ah))
572#ifdef AH_SUPPORT_5112
573 rfStatus = ar5112RfAttach(ah, &ecode);
574#else
575 ecode = HAL_ENOTSUPP;
576#endif
577 else if (IS_2425(ah) || IS_2417(ah))
578#ifdef AH_SUPPORT_2425
579 rfStatus = ar2425RfAttach(ah, &ecode);
580#else
581 ecode = HAL_ENOTSUPP;
582#endif
583 else if (IS_RAD5111(ah))
584#ifdef AH_SUPPORT_5111
585 rfStatus = ar5111RfAttach(ah, &ecode);
586#else
587 ecode = HAL_ENOTSUPP;
588#endif
589 if (!rfStatus) {
| 549 if (!rf->attach(ah, &ecode)) {
|
590 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
591 __func__, ecode);
592 goto bad;
593 }
594 /*
595 * Set noise floor adjust method; we arrange a
596 * direct call instead of thunking.
597 */
598 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
599
600 /* Initialize gain ladder thermal calibration structure */
601 ar5212InitializeGainValues(ah);
602
603 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
604 if (ecode != HAL_OK) {
605 HALDEBUG(ah, HAL_DEBUG_ANY,
606 "%s: error getting mac address from EEPROM\n", __func__);
607 goto bad;
608 }
609
610 ar5212AniSetup(ah);
611 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/
612 ar5212InitNfCalHistBuffer(ah);
613
614 /* XXX EAR stuff goes here */
615
616 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
617
618 return ah;
619
620bad:
621 if (ahp)
622 ar5212Detach((struct ath_hal *) ahp);
623 if (status)
624 *status = ecode;
625 return AH_NULL;
626#undef AH_EEPROM_PROTECT
627}
628
629void
630ar5212Detach(struct ath_hal *ah)
631{
632 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
633
634 HALASSERT(ah != AH_NULL);
635 HALASSERT(ah->ah_magic == AR5212_MAGIC);
636
637 ar5212AniDetach(ah);
638 ar5212RfDetach(ah);
639 ar5212Disable(ah);
640 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
641
642 ath_hal_eepromDetach(ah);
643 ath_hal_free(ah);
644}
645
646HAL_BOOL
647ar5212ChipTest(struct ath_hal *ah)
648{
649 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
650 uint32_t regHold[2];
651 uint32_t patternData[4] =
652 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
653 int i, j;
654
655 /* Test PHY & MAC registers */
656 for (i = 0; i < 2; i++) {
657 uint32_t addr = regAddr[i];
658 uint32_t wrData, rdData;
659
660 regHold[i] = OS_REG_READ(ah, addr);
661 for (j = 0; j < 0x100; j++) {
662 wrData = (j << 16) | j;
663 OS_REG_WRITE(ah, addr, wrData);
664 rdData = OS_REG_READ(ah, addr);
665 if (rdData != wrData) {
666 HALDEBUG(ah, HAL_DEBUG_ANY,
667"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
668 __func__, addr, wrData, rdData);
669 return AH_FALSE;
670 }
671 }
672 for (j = 0; j < 4; j++) {
673 wrData = patternData[j];
674 OS_REG_WRITE(ah, addr, wrData);
675 rdData = OS_REG_READ(ah, addr);
676 if (wrData != rdData) {
677 HALDEBUG(ah, HAL_DEBUG_ANY,
678"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
679 __func__, addr, wrData, rdData);
680 return AH_FALSE;
681 }
682 }
683 OS_REG_WRITE(ah, regAddr[i], regHold[i]);
684 }
685 OS_DELAY(100);
686 return AH_TRUE;
687}
688
689/*
690 * Store the channel edges for the requested operational mode
691 */
692HAL_BOOL
693ar5212GetChannelEdges(struct ath_hal *ah,
694 uint16_t flags, uint16_t *low, uint16_t *high)
695{
696 if (flags & CHANNEL_5GHZ) {
697 *low = 4915;
698 *high = 6100;
699 return AH_TRUE;
700 }
701 if ((flags & CHANNEL_2GHZ) &&
702 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
703 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
704 *low = 2312;
705 *high = 2732;
706 return AH_TRUE;
707 }
708 return AH_FALSE;
709}
710
711/*
712 * Fill all software cached or static hardware state information.
713 * Return failure if capabilities are to come from EEPROM and
714 * cannot be read.
715 */
716HAL_BOOL
717ar5212FillCapabilityInfo(struct ath_hal *ah)
718{
719#define AR_KEYTABLE_SIZE 128
720#define IS_GRIFFIN_LITE(ah) \
721 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
722 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
723#define IS_COBRA(ah) \
724 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
725#define IS_2112(ah) \
726 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
727
728 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
729 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
730 uint16_t capField, val;
731
732 /* Read the capability EEPROM location */
733 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
734 HALDEBUG(ah, HAL_DEBUG_ANY,
735 "%s: unable to read caps from eeprom\n", __func__);
736 return AH_FALSE;
737 }
738 if (IS_2112(ah))
739 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
740 if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
741 /*
742 * For griffin-lite cards with unprogrammed capabilities.
743 */
744 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
745 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
746 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
747 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
748 HALDEBUG(ah, HAL_DEBUG_ATTACH,
749 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
750 __func__, capField);
751 }
752
753 /* Modify reg domain on newer cards that need to work with older sw */
754 if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
755 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
756 if (ahpriv->ah_currentRD == 0x64 ||
757 ahpriv->ah_currentRD == 0x65)
758 ahpriv->ah_currentRD += 5;
759 else if (ahpriv->ah_currentRD == 0x41)
760 ahpriv->ah_currentRD = 0x43;
761 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
762 __func__, ahpriv->ah_currentRD);
763 }
764
765 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
766 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
767 HALDEBUG(ah, HAL_DEBUG_ATTACH,
768 "%s: enable Bmode and disable turbo for Swan/Nala\n",
769 __func__);
770 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
771 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
772 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
773 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
774 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
775 }
776
777 /* Construct wireless mode from EEPROM */
778 pCap->halWirelessModes = 0;
779 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
780 pCap->halWirelessModes |= HAL_MODE_11A;
781 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
782 pCap->halWirelessModes |= HAL_MODE_TURBO;
783 }
784 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
785 pCap->halWirelessModes |= HAL_MODE_11B;
786 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
787 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
788 pCap->halWirelessModes |= HAL_MODE_11G;
789 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
790 pCap->halWirelessModes |= HAL_MODE_108G;
791 }
792
793 pCap->halLow2GhzChan = 2312;
794 /* XXX 2417 too? */
795 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))
796 pCap->halHigh2GhzChan = 2500;
797 else
798 pCap->halHigh2GhzChan = 2732;
799
800 pCap->halLow5GhzChan = 4915;
801 pCap->halHigh5GhzChan = 6100;
802
803 pCap->halCipherCkipSupport = AH_FALSE;
804 pCap->halCipherTkipSupport = AH_TRUE;
805 pCap->halCipherAesCcmSupport =
806 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
807 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
808 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
809 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
810
811 pCap->halMicCkipSupport = AH_FALSE;
812 pCap->halMicTkipSupport = AH_TRUE;
813 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
814 /*
815 * Starting with Griffin TX+RX mic keys can be combined
816 * in one key cache slot.
817 */
818 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
819 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
820 else
821 pCap->halTkipMicTxRxKeySupport = AH_FALSE;
822 pCap->halChanSpreadSupport = AH_TRUE;
823 pCap->halSleepAfterBeaconBroken = AH_TRUE;
824
825 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
826 pCap->halCompressSupport =
827 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
828 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
829 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
830 pCap->halFastFramesSupport =
831 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
832 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
833 pCap->halChapTuningSupport = AH_TRUE;
834 pCap->halTurboPrimeSupport = AH_TRUE;
835 }
836 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
837
838 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
839 pCap->halVEOLSupport = AH_TRUE;
840 pCap->halBssIdMaskSupport = AH_TRUE;
841 pCap->halMcastKeySrchSupport = AH_TRUE;
842 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
843 ahpriv->ah_macRev == 8) ||
844 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
845 pCap->halTsfAddSupport = AH_TRUE;
846
847 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
848 pCap->halTotalQueues = val;
849 else
850 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
851
852 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
853 pCap->halKeyCacheSize = val;
854 else
855 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
856
857 pCap->halChanHalfRate = AH_TRUE;
858 pCap->halChanQuarterRate = AH_TRUE;
859
860 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
861 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
862 /* NB: enabled by default */
863 ahpriv->ah_rfkillEnabled = AH_TRUE;
864 pCap->halRfSilentSupport = AH_TRUE;
865 }
866
867 /* NB: this is a guess, noone seems to know the answer */
868 ahpriv->ah_rxornIsFatal =
869 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
870
871 /* h/w phy counters first appeared in Hainan */
872 pCap->halHwPhyCounterSupport =
873 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
874 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
875 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE;
876
877 pCap->halTstampPrecision = 15;
878
879 return AH_TRUE;
880#undef IS_COBRA
881#undef IS_GRIFFIN_LITE
882#undef AR_KEYTABLE_SIZE
883}
| 550 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
551 __func__, ecode);
552 goto bad;
553 }
554 /*
555 * Set noise floor adjust method; we arrange a
556 * direct call instead of thunking.
557 */
558 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
559
560 /* Initialize gain ladder thermal calibration structure */
561 ar5212InitializeGainValues(ah);
562
563 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
564 if (ecode != HAL_OK) {
565 HALDEBUG(ah, HAL_DEBUG_ANY,
566 "%s: error getting mac address from EEPROM\n", __func__);
567 goto bad;
568 }
569
570 ar5212AniSetup(ah);
571 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/
572 ar5212InitNfCalHistBuffer(ah);
573
574 /* XXX EAR stuff goes here */
575
576 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
577
578 return ah;
579
580bad:
581 if (ahp)
582 ar5212Detach((struct ath_hal *) ahp);
583 if (status)
584 *status = ecode;
585 return AH_NULL;
586#undef AH_EEPROM_PROTECT
587}
588
589void
590ar5212Detach(struct ath_hal *ah)
591{
592 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
593
594 HALASSERT(ah != AH_NULL);
595 HALASSERT(ah->ah_magic == AR5212_MAGIC);
596
597 ar5212AniDetach(ah);
598 ar5212RfDetach(ah);
599 ar5212Disable(ah);
600 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
601
602 ath_hal_eepromDetach(ah);
603 ath_hal_free(ah);
604}
605
606HAL_BOOL
607ar5212ChipTest(struct ath_hal *ah)
608{
609 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
610 uint32_t regHold[2];
611 uint32_t patternData[4] =
612 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
613 int i, j;
614
615 /* Test PHY & MAC registers */
616 for (i = 0; i < 2; i++) {
617 uint32_t addr = regAddr[i];
618 uint32_t wrData, rdData;
619
620 regHold[i] = OS_REG_READ(ah, addr);
621 for (j = 0; j < 0x100; j++) {
622 wrData = (j << 16) | j;
623 OS_REG_WRITE(ah, addr, wrData);
624 rdData = OS_REG_READ(ah, addr);
625 if (rdData != wrData) {
626 HALDEBUG(ah, HAL_DEBUG_ANY,
627"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
628 __func__, addr, wrData, rdData);
629 return AH_FALSE;
630 }
631 }
632 for (j = 0; j < 4; j++) {
633 wrData = patternData[j];
634 OS_REG_WRITE(ah, addr, wrData);
635 rdData = OS_REG_READ(ah, addr);
636 if (wrData != rdData) {
637 HALDEBUG(ah, HAL_DEBUG_ANY,
638"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
639 __func__, addr, wrData, rdData);
640 return AH_FALSE;
641 }
642 }
643 OS_REG_WRITE(ah, regAddr[i], regHold[i]);
644 }
645 OS_DELAY(100);
646 return AH_TRUE;
647}
648
649/*
650 * Store the channel edges for the requested operational mode
651 */
652HAL_BOOL
653ar5212GetChannelEdges(struct ath_hal *ah,
654 uint16_t flags, uint16_t *low, uint16_t *high)
655{
656 if (flags & CHANNEL_5GHZ) {
657 *low = 4915;
658 *high = 6100;
659 return AH_TRUE;
660 }
661 if ((flags & CHANNEL_2GHZ) &&
662 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
663 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
664 *low = 2312;
665 *high = 2732;
666 return AH_TRUE;
667 }
668 return AH_FALSE;
669}
670
671/*
672 * Fill all software cached or static hardware state information.
673 * Return failure if capabilities are to come from EEPROM and
674 * cannot be read.
675 */
676HAL_BOOL
677ar5212FillCapabilityInfo(struct ath_hal *ah)
678{
679#define AR_KEYTABLE_SIZE 128
680#define IS_GRIFFIN_LITE(ah) \
681 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
682 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
683#define IS_COBRA(ah) \
684 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
685#define IS_2112(ah) \
686 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
687
688 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
689 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
690 uint16_t capField, val;
691
692 /* Read the capability EEPROM location */
693 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
694 HALDEBUG(ah, HAL_DEBUG_ANY,
695 "%s: unable to read caps from eeprom\n", __func__);
696 return AH_FALSE;
697 }
698 if (IS_2112(ah))
699 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
700 if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
701 /*
702 * For griffin-lite cards with unprogrammed capabilities.
703 */
704 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
705 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
706 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
707 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
708 HALDEBUG(ah, HAL_DEBUG_ATTACH,
709 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
710 __func__, capField);
711 }
712
713 /* Modify reg domain on newer cards that need to work with older sw */
714 if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
715 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
716 if (ahpriv->ah_currentRD == 0x64 ||
717 ahpriv->ah_currentRD == 0x65)
718 ahpriv->ah_currentRD += 5;
719 else if (ahpriv->ah_currentRD == 0x41)
720 ahpriv->ah_currentRD = 0x43;
721 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
722 __func__, ahpriv->ah_currentRD);
723 }
724
725 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
726 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
727 HALDEBUG(ah, HAL_DEBUG_ATTACH,
728 "%s: enable Bmode and disable turbo for Swan/Nala\n",
729 __func__);
730 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
731 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
732 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
733 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
734 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
735 }
736
737 /* Construct wireless mode from EEPROM */
738 pCap->halWirelessModes = 0;
739 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
740 pCap->halWirelessModes |= HAL_MODE_11A;
741 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
742 pCap->halWirelessModes |= HAL_MODE_TURBO;
743 }
744 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
745 pCap->halWirelessModes |= HAL_MODE_11B;
746 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
747 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
748 pCap->halWirelessModes |= HAL_MODE_11G;
749 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
750 pCap->halWirelessModes |= HAL_MODE_108G;
751 }
752
753 pCap->halLow2GhzChan = 2312;
754 /* XXX 2417 too? */
755 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))
756 pCap->halHigh2GhzChan = 2500;
757 else
758 pCap->halHigh2GhzChan = 2732;
759
760 pCap->halLow5GhzChan = 4915;
761 pCap->halHigh5GhzChan = 6100;
762
763 pCap->halCipherCkipSupport = AH_FALSE;
764 pCap->halCipherTkipSupport = AH_TRUE;
765 pCap->halCipherAesCcmSupport =
766 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
767 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
768 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
769 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
770
771 pCap->halMicCkipSupport = AH_FALSE;
772 pCap->halMicTkipSupport = AH_TRUE;
773 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
774 /*
775 * Starting with Griffin TX+RX mic keys can be combined
776 * in one key cache slot.
777 */
778 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
779 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
780 else
781 pCap->halTkipMicTxRxKeySupport = AH_FALSE;
782 pCap->halChanSpreadSupport = AH_TRUE;
783 pCap->halSleepAfterBeaconBroken = AH_TRUE;
784
785 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
786 pCap->halCompressSupport =
787 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
788 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
789 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
790 pCap->halFastFramesSupport =
791 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
792 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
793 pCap->halChapTuningSupport = AH_TRUE;
794 pCap->halTurboPrimeSupport = AH_TRUE;
795 }
796 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
797
798 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
799 pCap->halVEOLSupport = AH_TRUE;
800 pCap->halBssIdMaskSupport = AH_TRUE;
801 pCap->halMcastKeySrchSupport = AH_TRUE;
802 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
803 ahpriv->ah_macRev == 8) ||
804 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
805 pCap->halTsfAddSupport = AH_TRUE;
806
807 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
808 pCap->halTotalQueues = val;
809 else
810 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
811
812 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
813 pCap->halKeyCacheSize = val;
814 else
815 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
816
817 pCap->halChanHalfRate = AH_TRUE;
818 pCap->halChanQuarterRate = AH_TRUE;
819
820 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
821 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
822 /* NB: enabled by default */
823 ahpriv->ah_rfkillEnabled = AH_TRUE;
824 pCap->halRfSilentSupport = AH_TRUE;
825 }
826
827 /* NB: this is a guess, noone seems to know the answer */
828 ahpriv->ah_rxornIsFatal =
829 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
830
831 /* h/w phy counters first appeared in Hainan */
832 pCap->halHwPhyCounterSupport =
833 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
834 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
835 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE;
836
837 pCap->halTstampPrecision = 15;
838
839 return AH_TRUE;
840#undef IS_COBRA
841#undef IS_GRIFFIN_LITE
842#undef AR_KEYTABLE_SIZE
843}
|
884#endif /* AH_SUPPORT_AR5212 */
| 844
845static const char*
846ar5212Probe(uint16_t vendorid, uint16_t devid)
847{
848 if (vendorid == ATHEROS_VENDOR_ID ||
849 vendorid == ATHEROS_3COM_VENDOR_ID ||
850 vendorid == ATHEROS_3COM2_VENDOR_ID) {
851 switch (devid) {
852 case AR5212_FPGA:
853 return "Atheros 5212 (FPGA)";
854 case AR5212_DEVID:
855 case AR5212_DEVID_IBM:
856 case AR5212_DEFAULT:
857 return "Atheros 5212";
858 case AR5212_AR2413:
859 return "Atheros 2413";
860 case AR5212_AR2417:
861 return "Atheros 2417";
862 case AR5212_AR5413:
863 return "Atheros 5413";
864 case AR5212_AR5424:
865 return "Atheros 5424/2424";
866 }
867 }
868 return AH_NULL;
869}
870AH_CHIP(ar5212, ar5212Probe, ar5212Attach);
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