1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 222265 2011-05-24 18:25:40Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ar5212/ar5212.h"
26#include "ar5212/ar5212reg.h"
27#include "ar5212/ar5212phy.h"
28
29#define AH_5212_COMMON
30#include "ar5212/ar5212.ini"
31
32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
33static void ar5212DisablePCIE(struct ath_hal *ah);
34
35static const struct ath_hal_private ar5212hal = {{
36 .ah_magic = AR5212_MAGIC,
37
38 .ah_getRateTable = ar5212GetRateTable,
39 .ah_detach = ar5212Detach,
40
41 /* Reset Functions */
42 .ah_reset = ar5212Reset,
43 .ah_phyDisable = ar5212PhyDisable,
44 .ah_disable = ar5212Disable,
45 .ah_configPCIE = ar5212ConfigPCIE,
46 .ah_disablePCIE = ar5212DisablePCIE,
47 .ah_setPCUConfig = ar5212SetPCUConfig,
48 .ah_perCalibration = ar5212PerCalibration,
49 .ah_perCalibrationN = ar5212PerCalibrationN,
50 .ah_resetCalValid = ar5212ResetCalValid,
51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit,
52 .ah_getChanNoise = ath_hal_getChanNoise,
53
54 /* Transmit functions */
55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel,
56 .ah_setupTxQueue = ar5212SetupTxQueue,
57 .ah_setTxQueueProps = ar5212SetTxQueueProps,
58 .ah_getTxQueueProps = ar5212GetTxQueueProps,
59 .ah_releaseTxQueue = ar5212ReleaseTxQueue,
60 .ah_resetTxQueue = ar5212ResetTxQueue,
61 .ah_getTxDP = ar5212GetTxDP,
62 .ah_setTxDP = ar5212SetTxDP,
63 .ah_numTxPending = ar5212NumTxPending,
64 .ah_startTxDma = ar5212StartTxDma,
65 .ah_stopTxDma = ar5212StopTxDma,
66 .ah_setupTxDesc = ar5212SetupTxDesc,
67 .ah_setupXTxDesc = ar5212SetupXTxDesc,
68 .ah_fillTxDesc = ar5212FillTxDesc,
69 .ah_procTxDesc = ar5212ProcTxDesc,
70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue,
71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc,
72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates,
73
74 /* RX Functions */
75 .ah_getRxDP = ar5212GetRxDP,
76 .ah_setRxDP = ar5212SetRxDP,
77 .ah_enableReceive = ar5212EnableReceive,
78 .ah_stopDmaReceive = ar5212StopDmaReceive,
79 .ah_startPcuReceive = ar5212StartPcuReceive,
80 .ah_stopPcuReceive = ar5212StopPcuReceive,
81 .ah_setMulticastFilter = ar5212SetMulticastFilter,
82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex,
83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex,
84 .ah_getRxFilter = ar5212GetRxFilter,
85 .ah_setRxFilter = ar5212SetRxFilter,
86 .ah_setupRxDesc = ar5212SetupRxDesc,
87 .ah_procRxDesc = ar5212ProcRxDesc,
88 .ah_rxMonitor = ar5212RxMonitor,
89 .ah_aniPoll = ar5212AniPoll,
90 .ah_procMibEvent = ar5212ProcessMibIntr,
91
92 /* Misc Functions */
93 .ah_getCapability = ar5212GetCapability,
94 .ah_setCapability = ar5212SetCapability,
95 .ah_getDiagState = ar5212GetDiagState,
96 .ah_getMacAddress = ar5212GetMacAddress,
97 .ah_setMacAddress = ar5212SetMacAddress,
98 .ah_getBssIdMask = ar5212GetBssIdMask,
99 .ah_setBssIdMask = ar5212SetBssIdMask,
100 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain,
101 .ah_setLedState = ar5212SetLedState,
102 .ah_writeAssocid = ar5212WriteAssocid,
103 .ah_gpioCfgInput = ar5212GpioCfgInput,
104 .ah_gpioCfgOutput = ar5212GpioCfgOutput,
105 .ah_gpioGet = ar5212GpioGet,
106 .ah_gpioSet = ar5212GpioSet,
107 .ah_gpioSetIntr = ar5212GpioSetIntr,
108 .ah_getTsf32 = ar5212GetTsf32,
109 .ah_getTsf64 = ar5212GetTsf64,
110 .ah_resetTsf = ar5212ResetTsf,
111 .ah_detectCardPresent = ar5212DetectCardPresent,
112 .ah_updateMibCounters = ar5212UpdateMibCounters,
113 .ah_getRfGain = ar5212GetRfgain,
114 .ah_getDefAntenna = ar5212GetDefAntenna,
115 .ah_setDefAntenna = ar5212SetDefAntenna,
116 .ah_getAntennaSwitch = ar5212GetAntennaSwitch,
117 .ah_setAntennaSwitch = ar5212SetAntennaSwitch,
118 .ah_setSifsTime = ar5212SetSifsTime,
119 .ah_getSifsTime = ar5212GetSifsTime,
120 .ah_setSlotTime = ar5212SetSlotTime,
121 .ah_getSlotTime = ar5212GetSlotTime,
122 .ah_setAckTimeout = ar5212SetAckTimeout,
123 .ah_getAckTimeout = ar5212GetAckTimeout,
124 .ah_setAckCTSRate = ar5212SetAckCTSRate,
125 .ah_getAckCTSRate = ar5212GetAckCTSRate,
126 .ah_setCTSTimeout = ar5212SetCTSTimeout,
127 .ah_getCTSTimeout = ar5212GetCTSTimeout,
128 .ah_setDecompMask = ar5212SetDecompMask,
129 .ah_setCoverageClass = ar5212SetCoverageClass,
130
131 /* Key Cache Functions */
132 .ah_getKeyCacheSize = ar5212GetKeyCacheSize,
133 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry,
134 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid,
135 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry,
136 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac,
137
138 /* Power Management Functions */
139 .ah_setPowerMode = ar5212SetPowerMode,
140 .ah_getPowerMode = ar5212GetPowerMode,
141
142 /* Beacon Functions */
143 .ah_setBeaconTimers = ar5212SetBeaconTimers,
144 .ah_beaconInit = ar5212BeaconInit,
145 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers,
146 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers,
147
148 /* Interrupt Functions */
149 .ah_isInterruptPending = ar5212IsInterruptPending,
150 .ah_getPendingInterrupts = ar5212GetPendingInterrupts,
151 .ah_getInterrupts = ar5212GetInterrupts,
152 .ah_setInterrupts = ar5212SetInterrupts },
153
154 .ah_getChannelEdges = ar5212GetChannelEdges,
155 .ah_getWirelessModes = ar5212GetWirelessModes,
156 .ah_eepromRead = ar5212EepromRead,
157#ifdef AH_SUPPORT_WRITE_EEPROM
158 .ah_eepromWrite = ar5212EepromWrite,
159#endif
160 .ah_getChipPowerLimits = ar5212GetChipPowerLimits,
161};
162
163uint32_t
164ar5212GetRadioRev(struct ath_hal *ah)
165{
166 uint32_t val;
167 int i;
168
169 /* Read Radio Chip Rev Extract */
170 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
171 for (i = 0; i < 8; i++)
172 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
173 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
174 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
175 return ath_hal_reverseBits(val, 8);
176}
177
178static void
179ar5212AniSetup(struct ath_hal *ah)
180{
181 static const struct ar5212AniParams aniparams = {
182 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
183 .totalSizeDesired = { -55, -55, -55, -55, -62 },
184 .coarseHigh = { -14, -14, -14, -14, -12 },
185 .coarseLow = { -64, -64, -64, -64, -70 },
186 .firpwr = { -78, -78, -78, -78, -80 },
187 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */
188 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
189 .maxFirstepLevel = 2, /* levels 0..2 */
190 .firstep = { 0, 4, 8 },
191 .ofdmTrigHigh = 500,
192 .ofdmTrigLow = 200,
193 .cckTrigHigh = 200,
194 .cckTrigLow = 100,
195 .rssiThrHigh = 40,
196 .rssiThrLow = 7,
197 .period = 100,
198 };
199 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
200 struct ar5212AniParams tmp;
201 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
202 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */
203 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
204 } else
205 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
206
207 /* Set overridable ANI methods */
208 AH5212(ah)->ah_aniControl = ar5212AniControl;
209}
210
211/*
212 * Attach for an AR5212 part.
213 */
214void
215ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
216 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
217{
218#define N(a) (sizeof(a)/sizeof(a[0]))
219 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
220 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
221 struct ath_hal *ah;
222
223 ah = &ahp->ah_priv.h;
224 /* set initial values */
225 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
226 ah->ah_sc = sc;
227 ah->ah_st = st;
228 ah->ah_sh = sh;
229
230 ah->ah_devid = devid; /* NB: for alq */
231 AH_PRIVATE(ah)->ah_devid = devid;
232 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */
233
234 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
235 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
236
237 ahp->ah_antControl = HAL_ANT_VARIABLE;
238 ahp->ah_diversity = AH_TRUE;
239 ahp->ah_bIQCalibration = AH_FALSE;
240 /*
241 * Enable MIC handling.
242 */
243 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
244 ahp->ah_rssiThr = INIT_RSSI_THR;
245 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */
246 ahp->ah_phyPowerOn = AH_FALSE;
247 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
248 | SM(MAX_RATE_POWER, AR_TPC_CTS)
249 | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
250 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */
251 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
252 ahp->ah_slottime = (u_int) -1;
253 ahp->ah_acktimeout = (u_int) -1;
254 ahp->ah_ctstimeout = (u_int) -1;
255 ahp->ah_sifstime = (u_int) -1;
256 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD,
257 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD,
258
259 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
260#undef N
261}
262
263/*
264 * Validate MAC version and revision.
265 */
266static HAL_BOOL
267ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
268{
269#define N(a) (sizeof(a)/sizeof(a[0]))
270 static const struct {
271 uint8_t version;
272 uint8_t revMin, revMax;
273 } macs[] = {
274 { AR_SREV_VERSION_VENICE,
275 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
276 { AR_SREV_VERSION_GRIFFIN,
277 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
278 { AR_SREV_5413,
279 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
280 { AR_SREV_5424,
281 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
282 { AR_SREV_2425,
283 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
284 { AR_SREV_2417,
285 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
286 };
287 int i;
288
289 for (i = 0; i < N(macs); i++)
290 if (macs[i].version == macVersion &&
291 macs[i].revMin <= macRev && macRev <= macs[i].revMax)
292 return AH_TRUE;
293 return AH_FALSE;
294#undef N
295}
296
297/*
298 * Attach for an AR5212 part.
299 */
300static struct ath_hal *
301ar5212Attach(uint16_t devid, HAL_SOFTC sc,
302 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
303 HAL_STATUS *status)
304{
305#define AH_EEPROM_PROTECT(ah) \
306 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
307 struct ath_hal_5212 *ahp;
308 struct ath_hal *ah;
309 struct ath_hal_rf *rf;
310 uint32_t val;
311 uint16_t eeval;
312 HAL_STATUS ecode;
313
314 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
315 __func__, sc, (void*) st, (void*) sh);
316
317 /* NB: memory is returned zero'd */
318 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
319 if (ahp == AH_NULL) {
320 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
321 "%s: cannot allocate memory for state block\n", __func__);
322 *status = HAL_ENOMEM;
323 return AH_NULL;
324 }
325 ar5212InitState(ahp, devid, sc, st, sh, status);
326 ah = &ahp->ah_priv.h;
327
328 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
329 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
330 __func__);
331 ecode = HAL_EIO;
332 goto bad;
333 }
334 /* Read Revisions from Chips before taking out of reset */
335 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
336 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
337 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
338 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);
339
340 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
341 HALDEBUG(ah, HAL_DEBUG_ANY,
342 "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
343 __func__, AH_PRIVATE(ah)->ah_macVersion,
344 AH_PRIVATE(ah)->ah_macRev);
345 ecode = HAL_ENOTSUPP;
346 goto bad;
347 }
348
349 /* setup common ini data; rf backends handle remainder */
350 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
351 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
352
353 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */
354 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
355 ecode = HAL_EIO;
356 goto bad;
357 }
358
359 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
360
361 if (AH_PRIVATE(ah)->ah_ispcie) {
362 /* XXX: build flag to disable this? */
363 ath_hal_configPCIE(ah, AH_FALSE);
364 }
365
366 if (!ar5212ChipTest(ah)) {
367 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
368 __func__);
369 ecode = HAL_ESELFTEST;
370 goto bad;
371 }
372
373 /* Enable PCI core retry fix in software for Hainan and up */
374 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
375 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
376
377 /*
378 * Set correct Baseband to analog shift
379 * setting to access analog chips.
380 */
381 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
382
383 /* Read Radio Chip Rev Extract */
384 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
385
386 rf = ath_hal_rfprobe(ah, &ecode);
387 if (rf == AH_NULL)
388 goto bad;
389
390 /* NB: silently accept anything in release code per Atheros */
391 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
392 case AR_RAD5111_SREV_MAJOR:
393 case AR_RAD5112_SREV_MAJOR:
394 case AR_RAD2112_SREV_MAJOR:
395 case AR_RAD2111_SREV_MAJOR:
396 case AR_RAD2413_SREV_MAJOR:
397 case AR_RAD5413_SREV_MAJOR:
398 case AR_RAD5424_SREV_MAJOR:
399 break;
400 default:
401 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
402 /*
403 * When RF_Silent is used, the
404 * analog chip is reset. So when the system boots
405 * up with the radio switch off we cannot determine
406 * the RF chip rev. To workaround this check the
407 * mac+phy revs and if Hainan, set the radio rev
408 * to Derby.
409 */
410 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
411 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
412 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
413 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
414 break;
415 }
416 if (IS_2413(ah)) { /* Griffin */
417 AH_PRIVATE(ah)->ah_analog5GhzRev =
418 AR_RAD2413_SREV_MAJOR | 0x1;
419 break;
420 }
421 if (IS_5413(ah)) { /* Eagle */
422 AH_PRIVATE(ah)->ah_analog5GhzRev =
423 AR_RAD5413_SREV_MAJOR | 0x2;
424 break;
425 }
426 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
427 AH_PRIVATE(ah)->ah_analog5GhzRev =
428 AR_RAD5424_SREV_MAJOR | 0x2;
429 break;
430 }
431 }
432#ifdef AH_DEBUG
433 HALDEBUG(ah, HAL_DEBUG_ANY,
434 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
435 "this driver\n",
436 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
437 ecode = HAL_ENOTSUPP;
438 goto bad;
439#endif
440 }
441 if (IS_RAD5112_REV1(ah)) {
442 HALDEBUG(ah, HAL_DEBUG_ANY,
443 "%s: 5112 Rev 1 is not supported by this "
444 "driver (analog5GhzRev 0x%x)\n", __func__,
445 AH_PRIVATE(ah)->ah_analog5GhzRev);
446 ecode = HAL_ENOTSUPP;
447 goto bad;
448 }
449
450 val = OS_REG_READ(ah, AR_PCICFG);
451 val = MS(val, AR_PCICFG_EEPROM_SIZE);
452 if (val == 0) {
453 if (!AH_PRIVATE(ah)->ah_ispcie) {
454 HALDEBUG(ah, HAL_DEBUG_ANY,
455 "%s: unsupported EEPROM size %u (0x%x) found\n",
456 __func__, val, val);
457 ecode = HAL_EESIZE;
458 goto bad;
459 }
460 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
461 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
462 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
463 HALDEBUG(ah, HAL_DEBUG_ANY,
464 "%s: unsupported EEPROM size %u (0x%x) found\n",
465 __func__, val, val);
466 ecode = HAL_EESIZE;
467 goto bad;
468 }
469 HALDEBUG(ah, HAL_DEBUG_ANY,
470 "%s: EEPROM size = %d. Must be %d (16k).\n",
471 __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
472 ecode = HAL_EESIZE;
473 goto bad;
474 }
475 ecode = ath_hal_legacyEepromAttach(ah);
476 if (ecode != HAL_OK) {
477 goto bad;
478 }
479 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
480
481 /*
482 * If Bmode and AR5212, verify 2.4 analog exists
483 */
484 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
485 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
486 /*
487 * Set correct Baseband to analog shift
488 * setting to access analog chips.
489 */
490 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
491 OS_DELAY(2000);
492 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
493
494 /* Set baseband for 5GHz chip */
495 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
496 OS_DELAY(2000);
497 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
498 HALDEBUG(ah, HAL_DEBUG_ANY,
499 "%s: 2G Radio Chip Rev 0x%02X is not "
500 "supported by this driver\n", __func__,
501 AH_PRIVATE(ah)->ah_analog2GhzRev);
502 ecode = HAL_ENOTSUPP;
503 goto bad;
504 }
505 }
506
507 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
508 if (ecode != HAL_OK) {
509 HALDEBUG(ah, HAL_DEBUG_ANY,
510 "%s: cannot read regulatory domain from EEPROM\n",
511 __func__);
512 goto bad;
513 }
514 AH_PRIVATE(ah)->ah_currentRD = eeval;
515 /* XXX record serial number */
516
517 /*
518 * Got everything we need now to setup the capabilities.
519 */
520 if (!ar5212FillCapabilityInfo(ah)) {
521 HALDEBUG(ah, HAL_DEBUG_ANY,
522 "%s: failed ar5212FillCapabilityInfo\n", __func__);
523 ecode = HAL_EEREAD;
524 goto bad;
525 }
526
527 if (!rf->attach(ah, &ecode)) {
528 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
529 __func__, ecode);
530 goto bad;
531 }
532 /*
533 * Set noise floor adjust method; we arrange a
534 * direct call instead of thunking.
535 */
536 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
537
538 /* Initialize gain ladder thermal calibration structure */
539 ar5212InitializeGainValues(ah);
540
541 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
542 if (ecode != HAL_OK) {
543 HALDEBUG(ah, HAL_DEBUG_ANY,
544 "%s: error getting mac address from EEPROM\n", __func__);
545 goto bad;
546 }
547
548 ar5212AniSetup(ah);
549 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/
550 ar5212InitNfCalHistBuffer(ah);
551
552 /* XXX EAR stuff goes here */
553
554 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
555
556 return ah;
557
558bad:
559 if (ahp)
560 ar5212Detach((struct ath_hal *) ahp);
561 if (status)
562 *status = ecode;
563 return AH_NULL;
564#undef AH_EEPROM_PROTECT
565}
566
567void
568ar5212Detach(struct ath_hal *ah)
569{
570 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
571
572 HALASSERT(ah != AH_NULL);
573 HALASSERT(ah->ah_magic == AR5212_MAGIC);
574
575 ar5212AniDetach(ah);
576 ar5212RfDetach(ah);
577 ar5212Disable(ah);
578 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
579
580 ath_hal_eepromDetach(ah);
581 ath_hal_free(ah);
582}
583
584HAL_BOOL
585ar5212ChipTest(struct ath_hal *ah)
586{
587 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
588 uint32_t regHold[2];
589 uint32_t patternData[4] =
590 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
591 int i, j;
592
593 /* Test PHY & MAC registers */
594 for (i = 0; i < 2; i++) {
595 uint32_t addr = regAddr[i];
596 uint32_t wrData, rdData;
597
598 regHold[i] = OS_REG_READ(ah, addr);
599 for (j = 0; j < 0x100; j++) {
600 wrData = (j << 16) | j;
601 OS_REG_WRITE(ah, addr, wrData);
602 rdData = OS_REG_READ(ah, addr);
603 if (rdData != wrData) {
604 HALDEBUG(ah, HAL_DEBUG_ANY,
605"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
606 __func__, addr, wrData, rdData);
607 return AH_FALSE;
608 }
609 }
610 for (j = 0; j < 4; j++) {
611 wrData = patternData[j];
612 OS_REG_WRITE(ah, addr, wrData);
613 rdData = OS_REG_READ(ah, addr);
614 if (wrData != rdData) {
615 HALDEBUG(ah, HAL_DEBUG_ANY,
616"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
617 __func__, addr, wrData, rdData);
618 return AH_FALSE;
619 }
620 }
621 OS_REG_WRITE(ah, regAddr[i], regHold[i]);
622 }
623 OS_DELAY(100);
624 return AH_TRUE;
625}
626
627/*
628 * Store the channel edges for the requested operational mode
629 */
630HAL_BOOL
631ar5212GetChannelEdges(struct ath_hal *ah,
632 uint16_t flags, uint16_t *low, uint16_t *high)
633{
634 if (flags & IEEE80211_CHAN_5GHZ) {
635 *low = 4915;
636 *high = 6100;
637 return AH_TRUE;
638 }
639 if ((flags & IEEE80211_CHAN_2GHZ) &&
640 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
641 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
642 *low = 2312;
643 *high = 2732;
644 return AH_TRUE;
645 }
646 return AH_FALSE;
647}
648
649/*
650 * Disable PLL when in L0s as well as receiver clock when in L1.
651 * This power saving option must be enabled through the Serdes.
652 *
653 * Programming the Serdes must go through the same 288 bit serial shift
654 * register as the other analog registers. Hence the 9 writes.
655 *
656 * XXX Clean up the magic numbers.
657 */
658static void
659ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
660{
661 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
662 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
663
664 /* RX shut off when elecidle is asserted */
665 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
666 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
667 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
668
669 /* Shut off PLL and CLKREQ active in L1 */
670 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
671 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
672 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
673 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
674
675 /* Load the new settings */
676 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
677}
678
679static void
680ar5212DisablePCIE(struct ath_hal *ah)
681{
682 /* NB: fill in for 9100 */
683}
684
685/*
686 * Fill all software cached or static hardware state information.
687 * Return failure if capabilities are to come from EEPROM and
688 * cannot be read.
689 */
690HAL_BOOL
691ar5212FillCapabilityInfo(struct ath_hal *ah)
692{
693#define AR_KEYTABLE_SIZE 128
694#define IS_GRIFFIN_LITE(ah) \
695 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
696 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
697#define IS_COBRA(ah) \
698 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
699#define IS_2112(ah) \
700 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
701
702 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
703 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
704 uint16_t capField, val;
705
706 /* Read the capability EEPROM location */
707 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
708 HALDEBUG(ah, HAL_DEBUG_ANY,
709 "%s: unable to read caps from eeprom\n", __func__);
710 return AH_FALSE;
711 }
712 if (IS_2112(ah))
713 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
714 if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
715 /*
716 * For griffin-lite cards with unprogrammed capabilities.
717 */
718 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
719 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
720 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
721 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
722 HALDEBUG(ah, HAL_DEBUG_ATTACH,
723 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
724 __func__, capField);
725 }
726
727 /* Modify reg domain on newer cards that need to work with older sw */
728 if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
729 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
730 if (ahpriv->ah_currentRD == 0x64 ||
731 ahpriv->ah_currentRD == 0x65)
732 ahpriv->ah_currentRD += 5;
733 else if (ahpriv->ah_currentRD == 0x41)
734 ahpriv->ah_currentRD = 0x43;
735 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
736 __func__, ahpriv->ah_currentRD);
737 }
738
739 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
740 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
741 HALDEBUG(ah, HAL_DEBUG_ATTACH,
742 "%s: enable Bmode and disable turbo for Swan/Nala\n",
743 __func__);
744 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
745 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
746 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
747 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
748 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
749 }
750
751 /* Construct wireless mode from EEPROM */
752 pCap->halWirelessModes = 0;
753 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
754 pCap->halWirelessModes |= HAL_MODE_11A;
755 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
756 pCap->halWirelessModes |= HAL_MODE_TURBO;
757 }
758 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
759 pCap->halWirelessModes |= HAL_MODE_11B;
760 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
761 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
762 pCap->halWirelessModes |= HAL_MODE_11G;
763 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
764 pCap->halWirelessModes |= HAL_MODE_108G;
765 }
766
767 pCap->halLow2GhzChan = 2312;
768 /* XXX 2417 too? */
769 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))
770 pCap->halHigh2GhzChan = 2500;
771 else
772 pCap->halHigh2GhzChan = 2732;
773
774 pCap->halLow5GhzChan = 4915;
775 pCap->halHigh5GhzChan = 6100;
776
777 pCap->halCipherCkipSupport = AH_FALSE;
778 pCap->halCipherTkipSupport = AH_TRUE;
779 pCap->halCipherAesCcmSupport =
780 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
781 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
782 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
783 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
784
785 pCap->halMicCkipSupport = AH_FALSE;
786 pCap->halMicTkipSupport = AH_TRUE;
787 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
788 /*
789 * Starting with Griffin TX+RX mic keys can be combined
790 * in one key cache slot.
791 */
792 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
793 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
794 else
795 pCap->halTkipMicTxRxKeySupport = AH_FALSE;
796 pCap->halChanSpreadSupport = AH_TRUE;
797 pCap->halSleepAfterBeaconBroken = AH_TRUE;
798
799 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
800 pCap->halCompressSupport =
801 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
802 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
803 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
804 pCap->halFastFramesSupport =
805 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
806 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
807 pCap->halChapTuningSupport = AH_TRUE;
808 pCap->halTurboPrimeSupport = AH_TRUE;
809 }
810 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
811
812 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
813 pCap->halVEOLSupport = AH_TRUE;
814 pCap->halBssIdMaskSupport = AH_TRUE;
815 pCap->halMcastKeySrchSupport = AH_TRUE;
816 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
817 ahpriv->ah_macRev == 8) ||
818 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
819 pCap->halTsfAddSupport = AH_TRUE;
820
821 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
822 pCap->halTotalQueues = val;
823 else
824 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
825
826 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
827 pCap->halKeyCacheSize = val;
828 else
829 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
830
831 pCap->halChanHalfRate = AH_TRUE;
832 pCap->halChanQuarterRate = AH_TRUE;
833
834 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
835 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
836 /* NB: enabled by default */
837 ahpriv->ah_rfkillEnabled = AH_TRUE;
838 pCap->halRfSilentSupport = AH_TRUE;
839 }
840
841 /* NB: this is a guess, noone seems to know the answer */
842 ahpriv->ah_rxornIsFatal =
843 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
844
845 /* enable features that first appeared in Hainan */
846 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
847 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
848 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
849 /* h/w phy counters */
850 pCap->halHwPhyCounterSupport = AH_TRUE;
851 /* bssid match disable */
852 pCap->halBssidMatchSupport = AH_TRUE;
853 }
854
855 pCap->halTstampPrecision = 15;
856 pCap->halIntrMask = HAL_INT_COMMON
857 | HAL_INT_RX
858 | HAL_INT_TX
859 | HAL_INT_FATAL
860 | HAL_INT_BNR
861 | HAL_INT_BMISC
862 ;
863 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
864 pCap->halIntrMask &= ~HAL_INT_TBTT;
865
866 pCap->hal4kbSplitTransSupport = AH_TRUE;
867 pCap->halHasRxSelfLinkedTail = AH_TRUE;
868
869 return AH_TRUE;
870#undef IS_COBRA
871#undef IS_GRIFFIN_LITE
872#undef AR_KEYTABLE_SIZE
873}
874
875static const char*
876ar5212Probe(uint16_t vendorid, uint16_t devid)
877{
878 if (vendorid == ATHEROS_VENDOR_ID ||
879 vendorid == ATHEROS_3COM_VENDOR_ID ||
880 vendorid == ATHEROS_3COM2_VENDOR_ID) {
881 switch (devid) {
882 case AR5212_FPGA:
883 return "Atheros 5212 (FPGA)";
884 case AR5212_DEVID:
885 case AR5212_DEVID_IBM:
886 case AR5212_DEFAULT:
887 return "Atheros 5212";
888 case AR5212_AR2413:
889 return "Atheros 2413";
890 case AR5212_AR2417:
891 return "Atheros 2417";
892 case AR5212_AR5413:
893 return "Atheros 5413";
894 case AR5212_AR5424:
895 return "Atheros 5424/2424";
896 }
897 }
898 return AH_NULL;
899}
900AH_CHIP(AR5212, ar5212Probe, ar5212Attach);
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 222265 2011-05-24 18:25:40Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ar5212/ar5212.h"
26#include "ar5212/ar5212reg.h"
27#include "ar5212/ar5212phy.h"
28
29#define AH_5212_COMMON
30#include "ar5212/ar5212.ini"
31
32static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
33static void ar5212DisablePCIE(struct ath_hal *ah);
34
35static const struct ath_hal_private ar5212hal = {{
36 .ah_magic = AR5212_MAGIC,
37
38 .ah_getRateTable = ar5212GetRateTable,
39 .ah_detach = ar5212Detach,
40
41 /* Reset Functions */
42 .ah_reset = ar5212Reset,
43 .ah_phyDisable = ar5212PhyDisable,
44 .ah_disable = ar5212Disable,
45 .ah_configPCIE = ar5212ConfigPCIE,
46 .ah_disablePCIE = ar5212DisablePCIE,
47 .ah_setPCUConfig = ar5212SetPCUConfig,
48 .ah_perCalibration = ar5212PerCalibration,
49 .ah_perCalibrationN = ar5212PerCalibrationN,
50 .ah_resetCalValid = ar5212ResetCalValid,
51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit,
52 .ah_getChanNoise = ath_hal_getChanNoise,
53
54 /* Transmit functions */
55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel,
56 .ah_setupTxQueue = ar5212SetupTxQueue,
57 .ah_setTxQueueProps = ar5212SetTxQueueProps,
58 .ah_getTxQueueProps = ar5212GetTxQueueProps,
59 .ah_releaseTxQueue = ar5212ReleaseTxQueue,
60 .ah_resetTxQueue = ar5212ResetTxQueue,
61 .ah_getTxDP = ar5212GetTxDP,
62 .ah_setTxDP = ar5212SetTxDP,
63 .ah_numTxPending = ar5212NumTxPending,
64 .ah_startTxDma = ar5212StartTxDma,
65 .ah_stopTxDma = ar5212StopTxDma,
66 .ah_setupTxDesc = ar5212SetupTxDesc,
67 .ah_setupXTxDesc = ar5212SetupXTxDesc,
68 .ah_fillTxDesc = ar5212FillTxDesc,
69 .ah_procTxDesc = ar5212ProcTxDesc,
70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue,
71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc,
72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates,
73
74 /* RX Functions */
75 .ah_getRxDP = ar5212GetRxDP,
76 .ah_setRxDP = ar5212SetRxDP,
77 .ah_enableReceive = ar5212EnableReceive,
78 .ah_stopDmaReceive = ar5212StopDmaReceive,
79 .ah_startPcuReceive = ar5212StartPcuReceive,
80 .ah_stopPcuReceive = ar5212StopPcuReceive,
81 .ah_setMulticastFilter = ar5212SetMulticastFilter,
82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex,
83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex,
84 .ah_getRxFilter = ar5212GetRxFilter,
85 .ah_setRxFilter = ar5212SetRxFilter,
86 .ah_setupRxDesc = ar5212SetupRxDesc,
87 .ah_procRxDesc = ar5212ProcRxDesc,
88 .ah_rxMonitor = ar5212RxMonitor,
89 .ah_aniPoll = ar5212AniPoll,
90 .ah_procMibEvent = ar5212ProcessMibIntr,
91
92 /* Misc Functions */
93 .ah_getCapability = ar5212GetCapability,
94 .ah_setCapability = ar5212SetCapability,
95 .ah_getDiagState = ar5212GetDiagState,
96 .ah_getMacAddress = ar5212GetMacAddress,
97 .ah_setMacAddress = ar5212SetMacAddress,
98 .ah_getBssIdMask = ar5212GetBssIdMask,
99 .ah_setBssIdMask = ar5212SetBssIdMask,
100 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain,
101 .ah_setLedState = ar5212SetLedState,
102 .ah_writeAssocid = ar5212WriteAssocid,
103 .ah_gpioCfgInput = ar5212GpioCfgInput,
104 .ah_gpioCfgOutput = ar5212GpioCfgOutput,
105 .ah_gpioGet = ar5212GpioGet,
106 .ah_gpioSet = ar5212GpioSet,
107 .ah_gpioSetIntr = ar5212GpioSetIntr,
108 .ah_getTsf32 = ar5212GetTsf32,
109 .ah_getTsf64 = ar5212GetTsf64,
110 .ah_resetTsf = ar5212ResetTsf,
111 .ah_detectCardPresent = ar5212DetectCardPresent,
112 .ah_updateMibCounters = ar5212UpdateMibCounters,
113 .ah_getRfGain = ar5212GetRfgain,
114 .ah_getDefAntenna = ar5212GetDefAntenna,
115 .ah_setDefAntenna = ar5212SetDefAntenna,
116 .ah_getAntennaSwitch = ar5212GetAntennaSwitch,
117 .ah_setAntennaSwitch = ar5212SetAntennaSwitch,
118 .ah_setSifsTime = ar5212SetSifsTime,
119 .ah_getSifsTime = ar5212GetSifsTime,
120 .ah_setSlotTime = ar5212SetSlotTime,
121 .ah_getSlotTime = ar5212GetSlotTime,
122 .ah_setAckTimeout = ar5212SetAckTimeout,
123 .ah_getAckTimeout = ar5212GetAckTimeout,
124 .ah_setAckCTSRate = ar5212SetAckCTSRate,
125 .ah_getAckCTSRate = ar5212GetAckCTSRate,
126 .ah_setCTSTimeout = ar5212SetCTSTimeout,
127 .ah_getCTSTimeout = ar5212GetCTSTimeout,
128 .ah_setDecompMask = ar5212SetDecompMask,
129 .ah_setCoverageClass = ar5212SetCoverageClass,
130
131 /* Key Cache Functions */
132 .ah_getKeyCacheSize = ar5212GetKeyCacheSize,
133 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry,
134 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid,
135 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry,
136 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac,
137
138 /* Power Management Functions */
139 .ah_setPowerMode = ar5212SetPowerMode,
140 .ah_getPowerMode = ar5212GetPowerMode,
141
142 /* Beacon Functions */
143 .ah_setBeaconTimers = ar5212SetBeaconTimers,
144 .ah_beaconInit = ar5212BeaconInit,
145 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers,
146 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers,
147
148 /* Interrupt Functions */
149 .ah_isInterruptPending = ar5212IsInterruptPending,
150 .ah_getPendingInterrupts = ar5212GetPendingInterrupts,
151 .ah_getInterrupts = ar5212GetInterrupts,
152 .ah_setInterrupts = ar5212SetInterrupts },
153
154 .ah_getChannelEdges = ar5212GetChannelEdges,
155 .ah_getWirelessModes = ar5212GetWirelessModes,
156 .ah_eepromRead = ar5212EepromRead,
157#ifdef AH_SUPPORT_WRITE_EEPROM
158 .ah_eepromWrite = ar5212EepromWrite,
159#endif
160 .ah_getChipPowerLimits = ar5212GetChipPowerLimits,
161};
162
163uint32_t
164ar5212GetRadioRev(struct ath_hal *ah)
165{
166 uint32_t val;
167 int i;
168
169 /* Read Radio Chip Rev Extract */
170 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
171 for (i = 0; i < 8; i++)
172 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
173 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
174 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
175 return ath_hal_reverseBits(val, 8);
176}
177
178static void
179ar5212AniSetup(struct ath_hal *ah)
180{
181 static const struct ar5212AniParams aniparams = {
182 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
183 .totalSizeDesired = { -55, -55, -55, -55, -62 },
184 .coarseHigh = { -14, -14, -14, -14, -12 },
185 .coarseLow = { -64, -64, -64, -64, -70 },
186 .firpwr = { -78, -78, -78, -78, -80 },
187 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */
188 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
189 .maxFirstepLevel = 2, /* levels 0..2 */
190 .firstep = { 0, 4, 8 },
191 .ofdmTrigHigh = 500,
192 .ofdmTrigLow = 200,
193 .cckTrigHigh = 200,
194 .cckTrigLow = 100,
195 .rssiThrHigh = 40,
196 .rssiThrLow = 7,
197 .period = 100,
198 };
199 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
200 struct ar5212AniParams tmp;
201 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
202 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */
203 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
204 } else
205 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
206
207 /* Set overridable ANI methods */
208 AH5212(ah)->ah_aniControl = ar5212AniControl;
209}
210
211/*
212 * Attach for an AR5212 part.
213 */
214void
215ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
216 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
217{
218#define N(a) (sizeof(a)/sizeof(a[0]))
219 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
220 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
221 struct ath_hal *ah;
222
223 ah = &ahp->ah_priv.h;
224 /* set initial values */
225 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
226 ah->ah_sc = sc;
227 ah->ah_st = st;
228 ah->ah_sh = sh;
229
230 ah->ah_devid = devid; /* NB: for alq */
231 AH_PRIVATE(ah)->ah_devid = devid;
232 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */
233
234 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
235 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
236
237 ahp->ah_antControl = HAL_ANT_VARIABLE;
238 ahp->ah_diversity = AH_TRUE;
239 ahp->ah_bIQCalibration = AH_FALSE;
240 /*
241 * Enable MIC handling.
242 */
243 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
244 ahp->ah_rssiThr = INIT_RSSI_THR;
245 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */
246 ahp->ah_phyPowerOn = AH_FALSE;
247 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
248 | SM(MAX_RATE_POWER, AR_TPC_CTS)
249 | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
250 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */
251 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
252 ahp->ah_slottime = (u_int) -1;
253 ahp->ah_acktimeout = (u_int) -1;
254 ahp->ah_ctstimeout = (u_int) -1;
255 ahp->ah_sifstime = (u_int) -1;
256 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD,
257 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD,
258
259 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
260#undef N
261}
262
263/*
264 * Validate MAC version and revision.
265 */
266static HAL_BOOL
267ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
268{
269#define N(a) (sizeof(a)/sizeof(a[0]))
270 static const struct {
271 uint8_t version;
272 uint8_t revMin, revMax;
273 } macs[] = {
274 { AR_SREV_VERSION_VENICE,
275 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
276 { AR_SREV_VERSION_GRIFFIN,
277 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX },
278 { AR_SREV_5413,
279 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
280 { AR_SREV_5424,
281 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
282 { AR_SREV_2425,
283 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
284 { AR_SREV_2417,
285 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX },
286 };
287 int i;
288
289 for (i = 0; i < N(macs); i++)
290 if (macs[i].version == macVersion &&
291 macs[i].revMin <= macRev && macRev <= macs[i].revMax)
292 return AH_TRUE;
293 return AH_FALSE;
294#undef N
295}
296
297/*
298 * Attach for an AR5212 part.
299 */
300static struct ath_hal *
301ar5212Attach(uint16_t devid, HAL_SOFTC sc,
302 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
303 HAL_STATUS *status)
304{
305#define AH_EEPROM_PROTECT(ah) \
306 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
307 struct ath_hal_5212 *ahp;
308 struct ath_hal *ah;
309 struct ath_hal_rf *rf;
310 uint32_t val;
311 uint16_t eeval;
312 HAL_STATUS ecode;
313
314 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
315 __func__, sc, (void*) st, (void*) sh);
316
317 /* NB: memory is returned zero'd */
318 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
319 if (ahp == AH_NULL) {
320 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
321 "%s: cannot allocate memory for state block\n", __func__);
322 *status = HAL_ENOMEM;
323 return AH_NULL;
324 }
325 ar5212InitState(ahp, devid, sc, st, sh, status);
326 ah = &ahp->ah_priv.h;
327
328 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
329 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
330 __func__);
331 ecode = HAL_EIO;
332 goto bad;
333 }
334 /* Read Revisions from Chips before taking out of reset */
335 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
336 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
337 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
338 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah);
339
340 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
341 HALDEBUG(ah, HAL_DEBUG_ANY,
342 "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
343 __func__, AH_PRIVATE(ah)->ah_macVersion,
344 AH_PRIVATE(ah)->ah_macRev);
345 ecode = HAL_ENOTSUPP;
346 goto bad;
347 }
348
349 /* setup common ini data; rf backends handle remainder */
350 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
351 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
352
353 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */
354 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
355 ecode = HAL_EIO;
356 goto bad;
357 }
358
359 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
360
361 if (AH_PRIVATE(ah)->ah_ispcie) {
362 /* XXX: build flag to disable this? */
363 ath_hal_configPCIE(ah, AH_FALSE);
364 }
365
366 if (!ar5212ChipTest(ah)) {
367 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
368 __func__);
369 ecode = HAL_ESELFTEST;
370 goto bad;
371 }
372
373 /* Enable PCI core retry fix in software for Hainan and up */
374 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
375 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
376
377 /*
378 * Set correct Baseband to analog shift
379 * setting to access analog chips.
380 */
381 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
382
383 /* Read Radio Chip Rev Extract */
384 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
385
386 rf = ath_hal_rfprobe(ah, &ecode);
387 if (rf == AH_NULL)
388 goto bad;
389
390 /* NB: silently accept anything in release code per Atheros */
391 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
392 case AR_RAD5111_SREV_MAJOR:
393 case AR_RAD5112_SREV_MAJOR:
394 case AR_RAD2112_SREV_MAJOR:
395 case AR_RAD2111_SREV_MAJOR:
396 case AR_RAD2413_SREV_MAJOR:
397 case AR_RAD5413_SREV_MAJOR:
398 case AR_RAD5424_SREV_MAJOR:
399 break;
400 default:
401 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
402 /*
403 * When RF_Silent is used, the
404 * analog chip is reset. So when the system boots
405 * up with the radio switch off we cannot determine
406 * the RF chip rev. To workaround this check the
407 * mac+phy revs and if Hainan, set the radio rev
408 * to Derby.
409 */
410 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
411 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
412 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
413 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
414 break;
415 }
416 if (IS_2413(ah)) { /* Griffin */
417 AH_PRIVATE(ah)->ah_analog5GhzRev =
418 AR_RAD2413_SREV_MAJOR | 0x1;
419 break;
420 }
421 if (IS_5413(ah)) { /* Eagle */
422 AH_PRIVATE(ah)->ah_analog5GhzRev =
423 AR_RAD5413_SREV_MAJOR | 0x2;
424 break;
425 }
426 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */
427 AH_PRIVATE(ah)->ah_analog5GhzRev =
428 AR_RAD5424_SREV_MAJOR | 0x2;
429 break;
430 }
431 }
432#ifdef AH_DEBUG
433 HALDEBUG(ah, HAL_DEBUG_ANY,
434 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
435 "this driver\n",
436 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
437 ecode = HAL_ENOTSUPP;
438 goto bad;
439#endif
440 }
441 if (IS_RAD5112_REV1(ah)) {
442 HALDEBUG(ah, HAL_DEBUG_ANY,
443 "%s: 5112 Rev 1 is not supported by this "
444 "driver (analog5GhzRev 0x%x)\n", __func__,
445 AH_PRIVATE(ah)->ah_analog5GhzRev);
446 ecode = HAL_ENOTSUPP;
447 goto bad;
448 }
449
450 val = OS_REG_READ(ah, AR_PCICFG);
451 val = MS(val, AR_PCICFG_EEPROM_SIZE);
452 if (val == 0) {
453 if (!AH_PRIVATE(ah)->ah_ispcie) {
454 HALDEBUG(ah, HAL_DEBUG_ANY,
455 "%s: unsupported EEPROM size %u (0x%x) found\n",
456 __func__, val, val);
457 ecode = HAL_EESIZE;
458 goto bad;
459 }
460 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
461 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
462 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
463 HALDEBUG(ah, HAL_DEBUG_ANY,
464 "%s: unsupported EEPROM size %u (0x%x) found\n",
465 __func__, val, val);
466 ecode = HAL_EESIZE;
467 goto bad;
468 }
469 HALDEBUG(ah, HAL_DEBUG_ANY,
470 "%s: EEPROM size = %d. Must be %d (16k).\n",
471 __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
472 ecode = HAL_EESIZE;
473 goto bad;
474 }
475 ecode = ath_hal_legacyEepromAttach(ah);
476 if (ecode != HAL_OK) {
477 goto bad;
478 }
479 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
480
481 /*
482 * If Bmode and AR5212, verify 2.4 analog exists
483 */
484 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
485 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
486 /*
487 * Set correct Baseband to analog shift
488 * setting to access analog chips.
489 */
490 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
491 OS_DELAY(2000);
492 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
493
494 /* Set baseband for 5GHz chip */
495 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
496 OS_DELAY(2000);
497 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
498 HALDEBUG(ah, HAL_DEBUG_ANY,
499 "%s: 2G Radio Chip Rev 0x%02X is not "
500 "supported by this driver\n", __func__,
501 AH_PRIVATE(ah)->ah_analog2GhzRev);
502 ecode = HAL_ENOTSUPP;
503 goto bad;
504 }
505 }
506
507 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
508 if (ecode != HAL_OK) {
509 HALDEBUG(ah, HAL_DEBUG_ANY,
510 "%s: cannot read regulatory domain from EEPROM\n",
511 __func__);
512 goto bad;
513 }
514 AH_PRIVATE(ah)->ah_currentRD = eeval;
515 /* XXX record serial number */
516
517 /*
518 * Got everything we need now to setup the capabilities.
519 */
520 if (!ar5212FillCapabilityInfo(ah)) {
521 HALDEBUG(ah, HAL_DEBUG_ANY,
522 "%s: failed ar5212FillCapabilityInfo\n", __func__);
523 ecode = HAL_EEREAD;
524 goto bad;
525 }
526
527 if (!rf->attach(ah, &ecode)) {
528 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
529 __func__, ecode);
530 goto bad;
531 }
532 /*
533 * Set noise floor adjust method; we arrange a
534 * direct call instead of thunking.
535 */
536 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
537
538 /* Initialize gain ladder thermal calibration structure */
539 ar5212InitializeGainValues(ah);
540
541 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
542 if (ecode != HAL_OK) {
543 HALDEBUG(ah, HAL_DEBUG_ANY,
544 "%s: error getting mac address from EEPROM\n", __func__);
545 goto bad;
546 }
547
548 ar5212AniSetup(ah);
549 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/
550 ar5212InitNfCalHistBuffer(ah);
551
552 /* XXX EAR stuff goes here */
553
554 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
555
556 return ah;
557
558bad:
559 if (ahp)
560 ar5212Detach((struct ath_hal *) ahp);
561 if (status)
562 *status = ecode;
563 return AH_NULL;
564#undef AH_EEPROM_PROTECT
565}
566
567void
568ar5212Detach(struct ath_hal *ah)
569{
570 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
571
572 HALASSERT(ah != AH_NULL);
573 HALASSERT(ah->ah_magic == AR5212_MAGIC);
574
575 ar5212AniDetach(ah);
576 ar5212RfDetach(ah);
577 ar5212Disable(ah);
578 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
579
580 ath_hal_eepromDetach(ah);
581 ath_hal_free(ah);
582}
583
584HAL_BOOL
585ar5212ChipTest(struct ath_hal *ah)
586{
587 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
588 uint32_t regHold[2];
589 uint32_t patternData[4] =
590 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
591 int i, j;
592
593 /* Test PHY & MAC registers */
594 for (i = 0; i < 2; i++) {
595 uint32_t addr = regAddr[i];
596 uint32_t wrData, rdData;
597
598 regHold[i] = OS_REG_READ(ah, addr);
599 for (j = 0; j < 0x100; j++) {
600 wrData = (j << 16) | j;
601 OS_REG_WRITE(ah, addr, wrData);
602 rdData = OS_REG_READ(ah, addr);
603 if (rdData != wrData) {
604 HALDEBUG(ah, HAL_DEBUG_ANY,
605"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
606 __func__, addr, wrData, rdData);
607 return AH_FALSE;
608 }
609 }
610 for (j = 0; j < 4; j++) {
611 wrData = patternData[j];
612 OS_REG_WRITE(ah, addr, wrData);
613 rdData = OS_REG_READ(ah, addr);
614 if (wrData != rdData) {
615 HALDEBUG(ah, HAL_DEBUG_ANY,
616"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
617 __func__, addr, wrData, rdData);
618 return AH_FALSE;
619 }
620 }
621 OS_REG_WRITE(ah, regAddr[i], regHold[i]);
622 }
623 OS_DELAY(100);
624 return AH_TRUE;
625}
626
627/*
628 * Store the channel edges for the requested operational mode
629 */
630HAL_BOOL
631ar5212GetChannelEdges(struct ath_hal *ah,
632 uint16_t flags, uint16_t *low, uint16_t *high)
633{
634 if (flags & IEEE80211_CHAN_5GHZ) {
635 *low = 4915;
636 *high = 6100;
637 return AH_TRUE;
638 }
639 if ((flags & IEEE80211_CHAN_2GHZ) &&
640 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
641 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
642 *low = 2312;
643 *high = 2732;
644 return AH_TRUE;
645 }
646 return AH_FALSE;
647}
648
649/*
650 * Disable PLL when in L0s as well as receiver clock when in L1.
651 * This power saving option must be enabled through the Serdes.
652 *
653 * Programming the Serdes must go through the same 288 bit serial shift
654 * register as the other analog registers. Hence the 9 writes.
655 *
656 * XXX Clean up the magic numbers.
657 */
658static void
659ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
660{
661 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
662 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
663
664 /* RX shut off when elecidle is asserted */
665 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
666 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
667 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
668
669 /* Shut off PLL and CLKREQ active in L1 */
670 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
671 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
672 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
673 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
674
675 /* Load the new settings */
676 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
677}
678
679static void
680ar5212DisablePCIE(struct ath_hal *ah)
681{
682 /* NB: fill in for 9100 */
683}
684
685/*
686 * Fill all software cached or static hardware state information.
687 * Return failure if capabilities are to come from EEPROM and
688 * cannot be read.
689 */
690HAL_BOOL
691ar5212FillCapabilityInfo(struct ath_hal *ah)
692{
693#define AR_KEYTABLE_SIZE 128
694#define IS_GRIFFIN_LITE(ah) \
695 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
696 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
697#define IS_COBRA(ah) \
698 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
699#define IS_2112(ah) \
700 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
701
702 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
703 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
704 uint16_t capField, val;
705
706 /* Read the capability EEPROM location */
707 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
708 HALDEBUG(ah, HAL_DEBUG_ANY,
709 "%s: unable to read caps from eeprom\n", __func__);
710 return AH_FALSE;
711 }
712 if (IS_2112(ah))
713 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
714 if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
715 /*
716 * For griffin-lite cards with unprogrammed capabilities.
717 */
718 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
719 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
720 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
721 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
722 HALDEBUG(ah, HAL_DEBUG_ATTACH,
723 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
724 __func__, capField);
725 }
726
727 /* Modify reg domain on newer cards that need to work with older sw */
728 if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
729 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
730 if (ahpriv->ah_currentRD == 0x64 ||
731 ahpriv->ah_currentRD == 0x65)
732 ahpriv->ah_currentRD += 5;
733 else if (ahpriv->ah_currentRD == 0x41)
734 ahpriv->ah_currentRD = 0x43;
735 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
736 __func__, ahpriv->ah_currentRD);
737 }
738
739 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
740 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
741 HALDEBUG(ah, HAL_DEBUG_ATTACH,
742 "%s: enable Bmode and disable turbo for Swan/Nala\n",
743 __func__);
744 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
745 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
746 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
747 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
748 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
749 }
750
751 /* Construct wireless mode from EEPROM */
752 pCap->halWirelessModes = 0;
753 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
754 pCap->halWirelessModes |= HAL_MODE_11A;
755 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
756 pCap->halWirelessModes |= HAL_MODE_TURBO;
757 }
758 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
759 pCap->halWirelessModes |= HAL_MODE_11B;
760 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
761 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
762 pCap->halWirelessModes |= HAL_MODE_11G;
763 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
764 pCap->halWirelessModes |= HAL_MODE_108G;
765 }
766
767 pCap->halLow2GhzChan = 2312;
768 /* XXX 2417 too? */
769 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))
770 pCap->halHigh2GhzChan = 2500;
771 else
772 pCap->halHigh2GhzChan = 2732;
773
774 pCap->halLow5GhzChan = 4915;
775 pCap->halHigh5GhzChan = 6100;
776
777 pCap->halCipherCkipSupport = AH_FALSE;
778 pCap->halCipherTkipSupport = AH_TRUE;
779 pCap->halCipherAesCcmSupport =
780 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
781 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
782 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
783 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
784
785 pCap->halMicCkipSupport = AH_FALSE;
786 pCap->halMicTkipSupport = AH_TRUE;
787 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
788 /*
789 * Starting with Griffin TX+RX mic keys can be combined
790 * in one key cache slot.
791 */
792 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
793 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
794 else
795 pCap->halTkipMicTxRxKeySupport = AH_FALSE;
796 pCap->halChanSpreadSupport = AH_TRUE;
797 pCap->halSleepAfterBeaconBroken = AH_TRUE;
798
799 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
800 pCap->halCompressSupport =
801 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
802 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
803 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
804 pCap->halFastFramesSupport =
805 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
806 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
807 pCap->halChapTuningSupport = AH_TRUE;
808 pCap->halTurboPrimeSupport = AH_TRUE;
809 }
810 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
811
812 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
813 pCap->halVEOLSupport = AH_TRUE;
814 pCap->halBssIdMaskSupport = AH_TRUE;
815 pCap->halMcastKeySrchSupport = AH_TRUE;
816 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
817 ahpriv->ah_macRev == 8) ||
818 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
819 pCap->halTsfAddSupport = AH_TRUE;
820
821 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
822 pCap->halTotalQueues = val;
823 else
824 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
825
826 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
827 pCap->halKeyCacheSize = val;
828 else
829 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
830
831 pCap->halChanHalfRate = AH_TRUE;
832 pCap->halChanQuarterRate = AH_TRUE;
833
834 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
835 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
836 /* NB: enabled by default */
837 ahpriv->ah_rfkillEnabled = AH_TRUE;
838 pCap->halRfSilentSupport = AH_TRUE;
839 }
840
841 /* NB: this is a guess, noone seems to know the answer */
842 ahpriv->ah_rxornIsFatal =
843 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
844
845 /* enable features that first appeared in Hainan */
846 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
847 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
848 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
849 /* h/w phy counters */
850 pCap->halHwPhyCounterSupport = AH_TRUE;
851 /* bssid match disable */
852 pCap->halBssidMatchSupport = AH_TRUE;
853 }
854
855 pCap->halTstampPrecision = 15;
856 pCap->halIntrMask = HAL_INT_COMMON
857 | HAL_INT_RX
858 | HAL_INT_TX
859 | HAL_INT_FATAL
860 | HAL_INT_BNR
861 | HAL_INT_BMISC
862 ;
863 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
864 pCap->halIntrMask &= ~HAL_INT_TBTT;
865
866 pCap->hal4kbSplitTransSupport = AH_TRUE;
867 pCap->halHasRxSelfLinkedTail = AH_TRUE;
868
869 return AH_TRUE;
870#undef IS_COBRA
871#undef IS_GRIFFIN_LITE
872#undef AR_KEYTABLE_SIZE
873}
874
875static const char*
876ar5212Probe(uint16_t vendorid, uint16_t devid)
877{
878 if (vendorid == ATHEROS_VENDOR_ID ||
879 vendorid == ATHEROS_3COM_VENDOR_ID ||
880 vendorid == ATHEROS_3COM2_VENDOR_ID) {
881 switch (devid) {
882 case AR5212_FPGA:
883 return "Atheros 5212 (FPGA)";
884 case AR5212_DEVID:
885 case AR5212_DEVID_IBM:
886 case AR5212_DEFAULT:
887 return "Atheros 5212";
888 case AR5212_AR2413:
889 return "Atheros 2413";
890 case AR5212_AR2417:
891 return "Atheros 2417";
892 case AR5212_AR5413:
893 return "Atheros 5413";
894 case AR5212_AR5424:
895 return "Atheros 5424/2424";
896 }
897 }
898 return AH_NULL;
899}
900AH_CHIP(AR5212, ar5212Probe, ar5212Attach);