18 */
19#ifndef _ATH_AR5212_H_
20#define _ATH_AR5212_H_
21
22#include "ah_eeprom.h"
23
24#define AR5212_MAGIC 0x19541014
25
26/* DCU Transmit Filter macros */
27#define CALC_MMR(dcu, idx) \
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
29#define TXBLK_FROM_MMR(mmr) \
30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
31#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
32#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
33
34/* MAC register values */
35
36#define INIT_INTERRUPT_MASK \
37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \
38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \
39 AR_IMR_HIUERR )
40#define INIT_BEACON_CONTROL \
41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
43
44#define INIT_CONFIG_STATUS 0x00000000
45#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
46#define INIT_IQCAL_LOG_COUNT_MAX 0xF
47#define INIT_BCON_CNTRL_REG 0x00000000
48
49#define INIT_USEC 40
50#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */
51#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */
52
53#define RX_NON_FULL_RATE_LATENCY 63
54#define TX_HALF_RATE_LATENCY 108
55#define TX_QUARTER_RATE_LATENCY 216
56
57#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */
58#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */
59#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
60#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
61#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
62#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
63
64#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */
65
66/* Tx frame start to tx data start delay */
67#define TX_FRAME_D_START_HALF_RATE 0xc
68#define TX_FRAME_D_START_QUARTER_RATE 0xd
69
70/*
71 * Various fifo fill before Tx start, in 64-byte units
72 * i.e. put the frame in the air while still DMAing
73 */
74#define MIN_TX_FIFO_THRESHOLD 0x1
75#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
76#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
77
78#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */
79
80/*
81 * Gain support.
82 */
83#define NUM_CORNER_FIX_BITS 4
84#define NUM_CORNER_FIX_BITS_5112 7
85#define DYN_ADJ_UP_MARGIN 15
86#define DYN_ADJ_LO_MARGIN 20
87#define PHY_PROBE_CCK_CORRECTION 5
88#define CCK_OFDM_GAIN_DELTA 15
89
90enum GAIN_PARAMS {
91 GP_TXCLIP,
92 GP_PD90,
93 GP_PD84,
94 GP_GSEL,
95};
96
97enum GAIN_PARAMS_5112 {
98 GP_MIXGAIN_OVR,
99 GP_PWD_138,
100 GP_PWD_137,
101 GP_PWD_136,
102 GP_PWD_132,
103 GP_PWD_131,
104 GP_PWD_130,
105};
106
107typedef struct _gainOptStep {
108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112];
109 int32_t stepGain;
110 int8_t stepName[16];
111} GAIN_OPTIMIZATION_STEP;
112
113typedef struct {
114 uint32_t numStepsInLadder;
115 uint32_t defaultStepNum;
116 GAIN_OPTIMIZATION_STEP optStep[10];
117} GAIN_OPTIMIZATION_LADDER;
118
119typedef struct {
120 uint32_t currStepNum;
121 uint32_t currGain;
122 uint32_t targetGain;
123 uint32_t loTrig;
124 uint32_t hiTrig;
125 uint32_t active;
126 const GAIN_OPTIMIZATION_STEP *currStep;
127} GAIN_VALUES;
128
129/* RF HAL structures */
130typedef struct RfHalFuncs {
131 void *priv; /* private state */
132
133 void (*rfDetach)(struct ath_hal *ah);
134 void (*writeRegs)(struct ath_hal *,
135 u_int modeIndex, u_int freqIndex, int regWrites);
136 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
137 HAL_BOOL (*setChannel)(struct ath_hal *,
138 const struct ieee80211_channel *);
139 HAL_BOOL (*setRfRegs)(struct ath_hal *,
140 const struct ieee80211_channel *, uint16_t modesIndex,
141 uint16_t *rfXpdGain);
142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
143 int16_t *minPower, int16_t *maxPower,
144 const struct ieee80211_channel *, uint16_t *rfXpdGain);
145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah,
146 const const struct ieee80211_channel *,
147 int16_t *maxPow, int16_t *minPow);
148 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
149} RF_HAL_FUNCS;
150
151struct ar5212AniParams {
152 int maxNoiseImmunityLevel; /* [0..4] */
153 int totalSizeDesired[5];
154 int coarseHigh[5];
155 int coarseLow[5];
156 int firpwr[5];
157
158 int maxSpurImmunityLevel; /* [0..7] */
159 int cycPwrThr1[8];
160
161 int maxFirstepLevel; /* [0..2] */
162 int firstep[3];
163
164 uint32_t ofdmTrigHigh;
165 uint32_t ofdmTrigLow;
166 uint32_t cckTrigHigh;
167 uint32_t cckTrigLow;
168 int32_t rssiThrLow;
169 uint32_t rssiThrHigh;
170
171 int period; /* update listen period */
172
173 /* NB: intentionally ordered so data exported to user space is first */
174 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */
175 uint32_t cckPhyErrBase; /* Base value for cck err counters */
176};
177
178/*
179 * Per-channel ANI state private to the driver.
180 */
181struct ar5212AniState {
182 uint8_t noiseImmunityLevel;
183 uint8_t spurImmunityLevel;
184 uint8_t firstepLevel;
185 uint8_t ofdmWeakSigDetectOff;
186 uint8_t cckWeakSigThreshold;
187 uint32_t listenTime;
188
189 /* NB: intentionally ordered so data exported to user space is first */
190 uint32_t txFrameCount; /* Last txFrameCount */
191 uint32_t rxFrameCount; /* Last rx Frame count */
192 uint32_t cycleCount; /* Last cycleCount
193 (to detect wrap-around) */
194 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
195 uint32_t cckPhyErrCount; /* CCK err count since last reset */
196
197 const struct ar5212AniParams *params;
198};
199
200#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
201#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
202
203struct ar5212Stats {
204 uint32_t ast_ani_niup; /* ANI increased noise immunity */
205 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
206 uint32_t ast_ani_spurup; /* ANI increased spur immunity */
207 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
208 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
209 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
210 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
211 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
212 uint32_t ast_ani_stepup; /* ANI increased first step level */
213 uint32_t ast_ani_stepdown;/* ANI decreased first step level */
214 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
215 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
216 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
217 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
218 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
219 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
220 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
221};
222
223/*
224 * NF Cal history buffer
225 */
226#define AR5212_CCA_MAX_GOOD_VALUE -95
227#define AR5212_CCA_MAX_HIGH_VALUE -62
228#define AR5212_CCA_MIN_BAD_VALUE -125
229
230#define AR512_NF_CAL_HIST_MAX 5
231
232struct ar5212NfCalHist {
233 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX];
234 int16_t privNF;
235 uint8_t currIndex;
236 uint8_t first_run;
237 uint8_t invalidNFcount;
238};
239
240struct ath_hal_5212 {
241 struct ath_hal_private ah_priv; /* base class */
242
243 /*
244 * Per-chip common Initialization data.
245 * NB: RF backends have their own ini data.
246 */
247 HAL_INI_ARRAY ah_ini_modes;
248 HAL_INI_ARRAY ah_ini_common;
249
250 GAIN_VALUES ah_gainValues;
251
252 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
253 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
254 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
255 uint16_t ah_assocId;
256
257 /*
258 * Runtime state.
259 */
260 uint32_t ah_maskReg; /* copy of AR_IMR */
261 struct ar5212Stats ah_stats; /* various statistics */
262 RF_HAL_FUNCS *ah_rfHal;
263 uint32_t ah_txDescMask; /* mask for TXDESC */
264 uint32_t ah_txOkInterruptMask;
265 uint32_t ah_txErrInterruptMask;
266 uint32_t ah_txDescInterruptMask;
267 uint32_t ah_txEolInterruptMask;
268 uint32_t ah_txUrnInterruptMask;
269 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
270 uint32_t ah_intrTxqs; /* tx q interrupt state */
271 /* decomp mask array */
272 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
273 HAL_POWER_MODE ah_powerMode;
274 HAL_ANT_SETTING ah_antControl; /* antenna setting */
275 HAL_BOOL ah_diversity; /* fast diversity setting */
276 enum {
277 IQ_CAL_INACTIVE,
278 IQ_CAL_RUNNING,
279 IQ_CAL_DONE
280 } ah_bIQCalibration; /* IQ calibrate state */
281 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */
282 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
283 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
284 uint32_t ah_miscMode; /* MISC_MODE settings */
285 uint32_t ah_rssiThr; /* RSSI_THR settings */
286 HAL_BOOL ah_cwCalRequire; /* for ap51 */
287 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */
288 HAL_BOOL ah_phyPowerOn; /* PHY power state */
289 HAL_BOOL ah_isHb63; /* cached HB63 check */
290 uint32_t ah_macTPC; /* tpc register */
291 uint32_t ah_beaconInterval; /* XXX */
292 enum {
293 AUTO_32KHZ, /* use it if 32kHz crystal present */
294 USE_32KHZ, /* do it regardless */
295 DONT_USE_32KHZ, /* don't use it regardless */
296 } ah_enable32kHzClock; /* whether to sleep at 32kHz */
297 uint32_t ah_ofdmTxPower;
298 int16_t ah_txPowerIndexOffset;
299 /*
300 * Noise floor cal histogram support.
301 */
302 struct ar5212NfCalHist ah_nfCalHist;
303
304 u_int ah_slottime; /* user-specified slot time */
305 u_int ah_acktimeout; /* user-specified ack timeout */
306 u_int ah_ctstimeout; /* user-specified cts timeout */
307 u_int ah_sifstime; /* user-specified sifs time */
308 /*
309 * RF Silent handling; setup according to the EEPROM.
310 */
311 uint32_t ah_gpioSelect; /* GPIO pin to use */
312 uint32_t ah_polarity; /* polarity to disable RF */
313 uint32_t ah_gpioBit; /* after init, prev value */
314 /*
315 * ANI support.
316 */
317 uint32_t ah_procPhyErr; /* Process Phy errs */
318 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */
319 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
320 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
321 struct ar5212AniState *ah_curani; /* cached last reference */
322 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */
323 HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */
324
325 /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */
326 HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param);
327
328 /*
329 * Transmit power state. Note these are maintained
330 * here so they can be retrieved by diagnostic tools.
331 */
332 uint16_t *ah_pcdacTable;
333 u_int ah_pcdacTableSize;
334 uint16_t ah_ratesArray[37];
335
336 uint8_t ah_txTrigLev; /* current Tx trigger level */
337 uint8_t ah_maxTxTrigLev; /* max tx trigger level */
338};
339#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
340
341/*
342 * IS_XXXX macros test the MAC version
343 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G)
344 *
345 * Some single chip radios have equivalent radio/RF (e.g. 5112)
346 * for those use IS_RADXXX_ANY macros.
347 */
348#define IS_2317(ah) \
349 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
350 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
351#define IS_2316(ah) \
352 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
353#define IS_2413(ah) \
354 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
355#define IS_5424(ah) \
356 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
357 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
358 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
359#define IS_5413(ah) \
360 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
361#define IS_2425(ah) \
362 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
363#define IS_2417(ah) \
364 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
365#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)
366
367#define AH_RADIO_MAJOR(ah) \
368 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
369#define AH_RADIO_MINOR(ah) \
370 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)
371#define IS_RAD5111(ah) \
372 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \
373 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)
374#define IS_RAD5112(ah) \
375 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \
376 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)
377/* NB: does not include 5413 as Atheros' IS_5112 macro does */
378#define IS_RAD5112_ANY(ah) \
379 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \
380 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)
381#define IS_RAD5112_REV1(ah) \
382 (IS_RAD5112(ah) && \
383 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))
384#define IS_RADX112_REV2(ah) \
385 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \
386 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \
387 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \
388 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)
389
390#define ar5212RfDetach(ah) do { \
391 if (AH5212(ah)->ah_rfHal != AH_NULL) \
392 AH5212(ah)->ah_rfHal->rfDetach(ah); \
393} while (0)
394#define ar5212GetRfBank(ah, b) \
395 AH5212(ah)->ah_rfHal->getRfBank(ah, b)
396
397/*
398 * Hack macros for Nala/San: 11b is handled
399 * using 11g; flip the channel flags to accomplish this.
400 */
401#define SAVE_CCK(_ah, _chan, _flag) do { \
402 if ((IS_2425(_ah) || IS_2417(_ah)) && \
403 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \
404 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \
405 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \
406 (_flag) = AH_TRUE; \
407 } else \
408 (_flag) = AH_FALSE; \
409} while (0)
410#define RESTORE_CCK(_ah, _chan, _flag) do { \
411 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \
412 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \
413 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \
414 } \
415} while (0)
416
417struct ath_hal;
418
419extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);
420extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
421 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
422extern void ar5212Detach(struct ath_hal *ah);
423extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
424extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
425 uint16_t flags, uint16_t *low, uint16_t *high);
426extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
427
428extern void ar5212SetBeaconTimers(struct ath_hal *ah,
429 const HAL_BEACON_TIMERS *);
430extern void ar5212BeaconInit(struct ath_hal *ah,
431 uint32_t next_beacon, uint32_t beacon_period);
432extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
433extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,
434 const HAL_BEACON_STATE *);
435extern uint64_t ar5212GetNextTBTT(struct ath_hal *);
436
437extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
438extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
439extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
440extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
441
442extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
443extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
444extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
445extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
446 uint16_t entry, const uint8_t *mac);
447extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
448 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
449
450extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
451extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
452extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
453extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
454extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
455extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
456extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
457 uint16_t regDomain, HAL_STATUS *stats);
458extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
459extern void ar5212EnableRfKill(struct ath_hal *);
460extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio,
461 HAL_GPIO_MUX_TYPE);
462extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
463extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
464extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
465extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
466extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
467extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
468 uint16_t assocId);
469extern uint32_t ar5212GetTsf32(struct ath_hal *ah);
470extern uint64_t ar5212GetTsf64(struct ath_hal *ah);
471extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64);
472extern void ar5212ResetTsf(struct ath_hal *ah);
473extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
474extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
475extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
476extern void ar5212EnableMibCounters(struct ath_hal *);
477extern void ar5212DisableMibCounters(struct ath_hal *);
478extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
479extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
480extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);
481extern u_int ar5212GetDefAntenna(struct ath_hal *ah);
482extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
483extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
484extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
485extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
486extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
487extern u_int ar5212GetSifsTime(struct ath_hal *);
488extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
489extern u_int ar5212GetSlotTime(struct ath_hal *);
490extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
491extern u_int ar5212GetAckTimeout(struct ath_hal *);
492extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
493extern u_int ar5212GetAckCTSRate(struct ath_hal *);
494extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
495extern u_int ar5212GetCTSTimeout(struct ath_hal *);
496extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
497void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
498extern void ar5212SetPCUConfig(struct ath_hal *);
499extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
500extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
501extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
502extern int16_t ar5212GetNfAdjust(struct ath_hal *,
503 const HAL_CHANNEL_INTERNAL *);
504extern void ar5212SetCompRegs(struct ath_hal *ah);
505extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
506 uint32_t, uint32_t *);
507extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
508 uint32_t, uint32_t, HAL_STATUS *);
509extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
510 const void *args, uint32_t argsize,
511 void **result, uint32_t *resultsize);
512extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period,
513 uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag);
514extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *,
515 HAL_SURVEY_SAMPLE *);
516
517extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
518 int setChip);
519extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
520extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
521
522extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE);
523extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE);
524extern void ar5212EnableReceive(struct ath_hal *ah);
525extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
526extern void ar5212StartPcuReceive(struct ath_hal *ah);
527extern void ar5212StopPcuReceive(struct ath_hal *ah);
528extern void ar5212SetMulticastFilter(struct ath_hal *ah,
529 uint32_t filter0, uint32_t filter1);
530extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
531extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
532extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);
533extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
534extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
535 struct ath_desc *, uint32_t size, u_int flags);
536extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
537 uint32_t, struct ath_desc *, uint64_t,
538 struct ath_rx_status *);
539
540extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
541 struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
542 HAL_STATUS *status);
543extern HAL_BOOL ar5212SetChannel(struct ath_hal *,
544 const struct ieee80211_channel *);
545extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
546extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
547extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
548extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah,
549 const struct ieee80211_channel *);
550extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah,
551 struct ieee80211_channel *chan, HAL_BOOL *isIQdone);
552extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah,
553 struct ieee80211_channel *chan, u_int chainMask,
554 HAL_BOOL longCal, HAL_BOOL *isCalDone);
555extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah,
556 const struct ieee80211_channel *);
557extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
558extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
559extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
560extern void ar5212SetSpurMitigation(struct ath_hal *,
561 const struct ieee80211_channel *);
562extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
563 HAL_ANT_SETTING settings, const struct ieee80211_channel *);
564extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
565extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
566 struct ieee80211_channel *chan);
567extern void ar5212InitializeGainValues(struct ath_hal *);
568extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
569extern void ar5212RequestRfgain(struct ath_hal *);
570
571extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
572 HAL_BOOL IncTrigLevel);
573extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
574 const HAL_TXQ_INFO *qInfo);
575extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
576 HAL_TXQ_INFO *qInfo);
577extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
578 const HAL_TXQ_INFO *qInfo);
579extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
580extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
581extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
582extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
583extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
584extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
585extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
586extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
587 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
588 u_int txRate0, u_int txTries0,
589 u_int keyIx, u_int antMode, u_int flags,
590 u_int rtsctsRate, u_int rtsctsDuration,
591 u_int compicvLen, u_int compivLen, u_int comp);
592extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
593 u_int txRate1, u_int txRetries1,
594 u_int txRate2, u_int txRetries2,
595 u_int txRate3, u_int txRetries3);
596extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
597 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
598 const struct ath_desc *ds0);
599extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
600 struct ath_desc *, struct ath_tx_status *);
601extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
602extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
603extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah,
604 const struct ath_desc *ds0, int *rates, int *tries);
| 18 */
19#ifndef _ATH_AR5212_H_
20#define _ATH_AR5212_H_
21
22#include "ah_eeprom.h"
23
24#define AR5212_MAGIC 0x19541014
25
26/* DCU Transmit Filter macros */
27#define CALC_MMR(dcu, idx) \
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
29#define TXBLK_FROM_MMR(mmr) \
30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
31#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
32#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
33
34/* MAC register values */
35
36#define INIT_INTERRUPT_MASK \
37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \
38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \
39 AR_IMR_HIUERR )
40#define INIT_BEACON_CONTROL \
41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
43
44#define INIT_CONFIG_STATUS 0x00000000
45#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
46#define INIT_IQCAL_LOG_COUNT_MAX 0xF
47#define INIT_BCON_CNTRL_REG 0x00000000
48
49#define INIT_USEC 40
50#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */
51#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */
52
53#define RX_NON_FULL_RATE_LATENCY 63
54#define TX_HALF_RATE_LATENCY 108
55#define TX_QUARTER_RATE_LATENCY 216
56
57#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */
58#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */
59#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
60#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
61#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
62#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
63
64#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */
65
66/* Tx frame start to tx data start delay */
67#define TX_FRAME_D_START_HALF_RATE 0xc
68#define TX_FRAME_D_START_QUARTER_RATE 0xd
69
70/*
71 * Various fifo fill before Tx start, in 64-byte units
72 * i.e. put the frame in the air while still DMAing
73 */
74#define MIN_TX_FIFO_THRESHOLD 0x1
75#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
76#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
77
78#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */
79
80/*
81 * Gain support.
82 */
83#define NUM_CORNER_FIX_BITS 4
84#define NUM_CORNER_FIX_BITS_5112 7
85#define DYN_ADJ_UP_MARGIN 15
86#define DYN_ADJ_LO_MARGIN 20
87#define PHY_PROBE_CCK_CORRECTION 5
88#define CCK_OFDM_GAIN_DELTA 15
89
90enum GAIN_PARAMS {
91 GP_TXCLIP,
92 GP_PD90,
93 GP_PD84,
94 GP_GSEL,
95};
96
97enum GAIN_PARAMS_5112 {
98 GP_MIXGAIN_OVR,
99 GP_PWD_138,
100 GP_PWD_137,
101 GP_PWD_136,
102 GP_PWD_132,
103 GP_PWD_131,
104 GP_PWD_130,
105};
106
107typedef struct _gainOptStep {
108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112];
109 int32_t stepGain;
110 int8_t stepName[16];
111} GAIN_OPTIMIZATION_STEP;
112
113typedef struct {
114 uint32_t numStepsInLadder;
115 uint32_t defaultStepNum;
116 GAIN_OPTIMIZATION_STEP optStep[10];
117} GAIN_OPTIMIZATION_LADDER;
118
119typedef struct {
120 uint32_t currStepNum;
121 uint32_t currGain;
122 uint32_t targetGain;
123 uint32_t loTrig;
124 uint32_t hiTrig;
125 uint32_t active;
126 const GAIN_OPTIMIZATION_STEP *currStep;
127} GAIN_VALUES;
128
129/* RF HAL structures */
130typedef struct RfHalFuncs {
131 void *priv; /* private state */
132
133 void (*rfDetach)(struct ath_hal *ah);
134 void (*writeRegs)(struct ath_hal *,
135 u_int modeIndex, u_int freqIndex, int regWrites);
136 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
137 HAL_BOOL (*setChannel)(struct ath_hal *,
138 const struct ieee80211_channel *);
139 HAL_BOOL (*setRfRegs)(struct ath_hal *,
140 const struct ieee80211_channel *, uint16_t modesIndex,
141 uint16_t *rfXpdGain);
142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
143 int16_t *minPower, int16_t *maxPower,
144 const struct ieee80211_channel *, uint16_t *rfXpdGain);
145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah,
146 const const struct ieee80211_channel *,
147 int16_t *maxPow, int16_t *minPow);
148 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
149} RF_HAL_FUNCS;
150
151struct ar5212AniParams {
152 int maxNoiseImmunityLevel; /* [0..4] */
153 int totalSizeDesired[5];
154 int coarseHigh[5];
155 int coarseLow[5];
156 int firpwr[5];
157
158 int maxSpurImmunityLevel; /* [0..7] */
159 int cycPwrThr1[8];
160
161 int maxFirstepLevel; /* [0..2] */
162 int firstep[3];
163
164 uint32_t ofdmTrigHigh;
165 uint32_t ofdmTrigLow;
166 uint32_t cckTrigHigh;
167 uint32_t cckTrigLow;
168 int32_t rssiThrLow;
169 uint32_t rssiThrHigh;
170
171 int period; /* update listen period */
172
173 /* NB: intentionally ordered so data exported to user space is first */
174 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */
175 uint32_t cckPhyErrBase; /* Base value for cck err counters */
176};
177
178/*
179 * Per-channel ANI state private to the driver.
180 */
181struct ar5212AniState {
182 uint8_t noiseImmunityLevel;
183 uint8_t spurImmunityLevel;
184 uint8_t firstepLevel;
185 uint8_t ofdmWeakSigDetectOff;
186 uint8_t cckWeakSigThreshold;
187 uint32_t listenTime;
188
189 /* NB: intentionally ordered so data exported to user space is first */
190 uint32_t txFrameCount; /* Last txFrameCount */
191 uint32_t rxFrameCount; /* Last rx Frame count */
192 uint32_t cycleCount; /* Last cycleCount
193 (to detect wrap-around) */
194 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
195 uint32_t cckPhyErrCount; /* CCK err count since last reset */
196
197 const struct ar5212AniParams *params;
198};
199
200#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
201#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
202
203struct ar5212Stats {
204 uint32_t ast_ani_niup; /* ANI increased noise immunity */
205 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
206 uint32_t ast_ani_spurup; /* ANI increased spur immunity */
207 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
208 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
209 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
210 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
211 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
212 uint32_t ast_ani_stepup; /* ANI increased first step level */
213 uint32_t ast_ani_stepdown;/* ANI decreased first step level */
214 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
215 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
216 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
217 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
218 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
219 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
220 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
221};
222
223/*
224 * NF Cal history buffer
225 */
226#define AR5212_CCA_MAX_GOOD_VALUE -95
227#define AR5212_CCA_MAX_HIGH_VALUE -62
228#define AR5212_CCA_MIN_BAD_VALUE -125
229
230#define AR512_NF_CAL_HIST_MAX 5
231
232struct ar5212NfCalHist {
233 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX];
234 int16_t privNF;
235 uint8_t currIndex;
236 uint8_t first_run;
237 uint8_t invalidNFcount;
238};
239
240struct ath_hal_5212 {
241 struct ath_hal_private ah_priv; /* base class */
242
243 /*
244 * Per-chip common Initialization data.
245 * NB: RF backends have their own ini data.
246 */
247 HAL_INI_ARRAY ah_ini_modes;
248 HAL_INI_ARRAY ah_ini_common;
249
250 GAIN_VALUES ah_gainValues;
251
252 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
253 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
254 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
255 uint16_t ah_assocId;
256
257 /*
258 * Runtime state.
259 */
260 uint32_t ah_maskReg; /* copy of AR_IMR */
261 struct ar5212Stats ah_stats; /* various statistics */
262 RF_HAL_FUNCS *ah_rfHal;
263 uint32_t ah_txDescMask; /* mask for TXDESC */
264 uint32_t ah_txOkInterruptMask;
265 uint32_t ah_txErrInterruptMask;
266 uint32_t ah_txDescInterruptMask;
267 uint32_t ah_txEolInterruptMask;
268 uint32_t ah_txUrnInterruptMask;
269 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
270 uint32_t ah_intrTxqs; /* tx q interrupt state */
271 /* decomp mask array */
272 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
273 HAL_POWER_MODE ah_powerMode;
274 HAL_ANT_SETTING ah_antControl; /* antenna setting */
275 HAL_BOOL ah_diversity; /* fast diversity setting */
276 enum {
277 IQ_CAL_INACTIVE,
278 IQ_CAL_RUNNING,
279 IQ_CAL_DONE
280 } ah_bIQCalibration; /* IQ calibrate state */
281 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */
282 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
283 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
284 uint32_t ah_miscMode; /* MISC_MODE settings */
285 uint32_t ah_rssiThr; /* RSSI_THR settings */
286 HAL_BOOL ah_cwCalRequire; /* for ap51 */
287 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */
288 HAL_BOOL ah_phyPowerOn; /* PHY power state */
289 HAL_BOOL ah_isHb63; /* cached HB63 check */
290 uint32_t ah_macTPC; /* tpc register */
291 uint32_t ah_beaconInterval; /* XXX */
292 enum {
293 AUTO_32KHZ, /* use it if 32kHz crystal present */
294 USE_32KHZ, /* do it regardless */
295 DONT_USE_32KHZ, /* don't use it regardless */
296 } ah_enable32kHzClock; /* whether to sleep at 32kHz */
297 uint32_t ah_ofdmTxPower;
298 int16_t ah_txPowerIndexOffset;
299 /*
300 * Noise floor cal histogram support.
301 */
302 struct ar5212NfCalHist ah_nfCalHist;
303
304 u_int ah_slottime; /* user-specified slot time */
305 u_int ah_acktimeout; /* user-specified ack timeout */
306 u_int ah_ctstimeout; /* user-specified cts timeout */
307 u_int ah_sifstime; /* user-specified sifs time */
308 /*
309 * RF Silent handling; setup according to the EEPROM.
310 */
311 uint32_t ah_gpioSelect; /* GPIO pin to use */
312 uint32_t ah_polarity; /* polarity to disable RF */
313 uint32_t ah_gpioBit; /* after init, prev value */
314 /*
315 * ANI support.
316 */
317 uint32_t ah_procPhyErr; /* Process Phy errs */
318 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */
319 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
320 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
321 struct ar5212AniState *ah_curani; /* cached last reference */
322 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */
323 HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */
324
325 /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */
326 HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param);
327
328 /*
329 * Transmit power state. Note these are maintained
330 * here so they can be retrieved by diagnostic tools.
331 */
332 uint16_t *ah_pcdacTable;
333 u_int ah_pcdacTableSize;
334 uint16_t ah_ratesArray[37];
335
336 uint8_t ah_txTrigLev; /* current Tx trigger level */
337 uint8_t ah_maxTxTrigLev; /* max tx trigger level */
338};
339#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
340
341/*
342 * IS_XXXX macros test the MAC version
343 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G)
344 *
345 * Some single chip radios have equivalent radio/RF (e.g. 5112)
346 * for those use IS_RADXXX_ANY macros.
347 */
348#define IS_2317(ah) \
349 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
350 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
351#define IS_2316(ah) \
352 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
353#define IS_2413(ah) \
354 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
355#define IS_5424(ah) \
356 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
357 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
358 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
359#define IS_5413(ah) \
360 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
361#define IS_2425(ah) \
362 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
363#define IS_2417(ah) \
364 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
365#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)
366
367#define AH_RADIO_MAJOR(ah) \
368 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
369#define AH_RADIO_MINOR(ah) \
370 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)
371#define IS_RAD5111(ah) \
372 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \
373 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)
374#define IS_RAD5112(ah) \
375 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \
376 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)
377/* NB: does not include 5413 as Atheros' IS_5112 macro does */
378#define IS_RAD5112_ANY(ah) \
379 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \
380 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)
381#define IS_RAD5112_REV1(ah) \
382 (IS_RAD5112(ah) && \
383 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))
384#define IS_RADX112_REV2(ah) \
385 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \
386 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \
387 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \
388 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)
389
390#define ar5212RfDetach(ah) do { \
391 if (AH5212(ah)->ah_rfHal != AH_NULL) \
392 AH5212(ah)->ah_rfHal->rfDetach(ah); \
393} while (0)
394#define ar5212GetRfBank(ah, b) \
395 AH5212(ah)->ah_rfHal->getRfBank(ah, b)
396
397/*
398 * Hack macros for Nala/San: 11b is handled
399 * using 11g; flip the channel flags to accomplish this.
400 */
401#define SAVE_CCK(_ah, _chan, _flag) do { \
402 if ((IS_2425(_ah) || IS_2417(_ah)) && \
403 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \
404 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \
405 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \
406 (_flag) = AH_TRUE; \
407 } else \
408 (_flag) = AH_FALSE; \
409} while (0)
410#define RESTORE_CCK(_ah, _chan, _flag) do { \
411 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \
412 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \
413 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \
414 } \
415} while (0)
416
417struct ath_hal;
418
419extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);
420extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
421 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
422extern void ar5212Detach(struct ath_hal *ah);
423extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
424extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
425 uint16_t flags, uint16_t *low, uint16_t *high);
426extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
427
428extern void ar5212SetBeaconTimers(struct ath_hal *ah,
429 const HAL_BEACON_TIMERS *);
430extern void ar5212BeaconInit(struct ath_hal *ah,
431 uint32_t next_beacon, uint32_t beacon_period);
432extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
433extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,
434 const HAL_BEACON_STATE *);
435extern uint64_t ar5212GetNextTBTT(struct ath_hal *);
436
437extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
438extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
439extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
440extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
441
442extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
443extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
444extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
445extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
446 uint16_t entry, const uint8_t *mac);
447extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
448 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
449
450extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
451extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
452extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
453extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
454extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
455extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
456extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
457 uint16_t regDomain, HAL_STATUS *stats);
458extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
459extern void ar5212EnableRfKill(struct ath_hal *);
460extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio,
461 HAL_GPIO_MUX_TYPE);
462extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
463extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
464extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
465extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
466extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
467extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
468 uint16_t assocId);
469extern uint32_t ar5212GetTsf32(struct ath_hal *ah);
470extern uint64_t ar5212GetTsf64(struct ath_hal *ah);
471extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64);
472extern void ar5212ResetTsf(struct ath_hal *ah);
473extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
474extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
475extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
476extern void ar5212EnableMibCounters(struct ath_hal *);
477extern void ar5212DisableMibCounters(struct ath_hal *);
478extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
479extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
480extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);
481extern u_int ar5212GetDefAntenna(struct ath_hal *ah);
482extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
483extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
484extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
485extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
486extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
487extern u_int ar5212GetSifsTime(struct ath_hal *);
488extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
489extern u_int ar5212GetSlotTime(struct ath_hal *);
490extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
491extern u_int ar5212GetAckTimeout(struct ath_hal *);
492extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
493extern u_int ar5212GetAckCTSRate(struct ath_hal *);
494extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
495extern u_int ar5212GetCTSTimeout(struct ath_hal *);
496extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
497void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
498extern void ar5212SetPCUConfig(struct ath_hal *);
499extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
500extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
501extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
502extern int16_t ar5212GetNfAdjust(struct ath_hal *,
503 const HAL_CHANNEL_INTERNAL *);
504extern void ar5212SetCompRegs(struct ath_hal *ah);
505extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
506 uint32_t, uint32_t *);
507extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
508 uint32_t, uint32_t, HAL_STATUS *);
509extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
510 const void *args, uint32_t argsize,
511 void **result, uint32_t *resultsize);
512extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period,
513 uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag);
514extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *,
515 HAL_SURVEY_SAMPLE *);
516
517extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
518 int setChip);
519extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
520extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
521
522extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE);
523extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE);
524extern void ar5212EnableReceive(struct ath_hal *ah);
525extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
526extern void ar5212StartPcuReceive(struct ath_hal *ah);
527extern void ar5212StopPcuReceive(struct ath_hal *ah);
528extern void ar5212SetMulticastFilter(struct ath_hal *ah,
529 uint32_t filter0, uint32_t filter1);
530extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
531extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
532extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);
533extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
534extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
535 struct ath_desc *, uint32_t size, u_int flags);
536extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
537 uint32_t, struct ath_desc *, uint64_t,
538 struct ath_rx_status *);
539
540extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
541 struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
542 HAL_STATUS *status);
543extern HAL_BOOL ar5212SetChannel(struct ath_hal *,
544 const struct ieee80211_channel *);
545extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
546extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
547extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
548extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah,
549 const struct ieee80211_channel *);
550extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah,
551 struct ieee80211_channel *chan, HAL_BOOL *isIQdone);
552extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah,
553 struct ieee80211_channel *chan, u_int chainMask,
554 HAL_BOOL longCal, HAL_BOOL *isCalDone);
555extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah,
556 const struct ieee80211_channel *);
557extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
558extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
559extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
560extern void ar5212SetSpurMitigation(struct ath_hal *,
561 const struct ieee80211_channel *);
562extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
563 HAL_ANT_SETTING settings, const struct ieee80211_channel *);
564extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
565extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
566 struct ieee80211_channel *chan);
567extern void ar5212InitializeGainValues(struct ath_hal *);
568extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
569extern void ar5212RequestRfgain(struct ath_hal *);
570
571extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
572 HAL_BOOL IncTrigLevel);
573extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
574 const HAL_TXQ_INFO *qInfo);
575extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
576 HAL_TXQ_INFO *qInfo);
577extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
578 const HAL_TXQ_INFO *qInfo);
579extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
580extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
581extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
582extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
583extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
584extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
585extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
586extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
587 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
588 u_int txRate0, u_int txTries0,
589 u_int keyIx, u_int antMode, u_int flags,
590 u_int rtsctsRate, u_int rtsctsDuration,
591 u_int compicvLen, u_int compivLen, u_int comp);
592extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
593 u_int txRate1, u_int txRetries1,
594 u_int txRate2, u_int txRetries2,
595 u_int txRate3, u_int txRetries3);
596extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
597 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
598 const struct ath_desc *ds0);
599extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
600 struct ath_desc *, struct ath_tx_status *);
601extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
602extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
603extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah,
604 const struct ath_desc *ds0, int *rates, int *tries);
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