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1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5210/ar5210.h 225444 2011-09-08 01:23:05Z adrian $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5210/ar5210.h 234873 2012-05-01 14:48:51Z adrian $
18 */
19#ifndef _ATH_AR5210_H_
20#define _ATH_AR5210_H_
21
22#define AR5210_MAGIC 0x19980124
23
24#if 0
25/*
26 * RTS_ENABLE includes LONG_PKT because they essentially
27 * imply the same thing, and are set or not set together
28 * for this chip
29 */
30#define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31#define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
32#define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)
33#define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34#define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35#define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)
36#define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)
37#define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)
38#define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f)
39#define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0)
40#endif
41
42#define INIT_CONFIG_STATUS 0x00000000
43#define INIT_ACKTOPS 0x00000008
44#define INIT_BCON_CNTRL_REG 0x00000000
45#define INIT_SLOT_TIME 0x00000168
46#define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */
47#define INIT_ACK_CTS_TIMEOUT 0x04000400
48#define INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
49
50#define INIT_USEC 0x27
51#define INIT_USEC_TURBO 0x4f
52#define INIT_USEC_32 0x1f
53#define INIT_TX_LATENCY 0x36
54#define INIT_RX_LATENCY 0x1D
55#define INIT_TRANSMIT_LATENCY \
56 ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
57 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
58 (INIT_USEC_32 << 7) | INIT_USEC )
59#define INIT_TRANSMIT_LATENCY_TURBO \
60 ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
61 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
62 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
63
64#define INIT_SIFS 0x230 /* = 16 us - 2 us */
65#define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
66
67/*
68 * Various fifo fill before Tx start, in 64-byte units
69 * i.e. put the frame in the air while still DMAing
70 */
71#define MIN_TX_FIFO_THRESHOLD 0x1
72#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
73
74#define INIT_NEXT_CFP_START 0xffffffff
75
76#define INIT_BEACON_PERIOD 0xffff
77#define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */
78#define INIT_BEACON_CONTROL \
79 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
80 (INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD)
81
82#define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */
83#define INIT_ProgIFS 0x398 /* PIFS - 2us */
84#define INIT_ProgIFS_TURBO 0x3C0
85#define INIT_EIFS 0xd70
86#define INIT_EIFS_TURBO 0x1ae0
87#define INIT_CARR_SENSE_EN 1
88#define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
89 (INIT_ProgIFS) )
90#define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
91 (INIT_ProgIFS_TURBO) )
92
93#define AR5210_MAX_RATE_POWER 60
94
95#undef HAL_NUM_TX_QUEUES /* from ah.h */
96#define HAL_NUM_TX_QUEUES 3
97
98struct ath_hal_5210 {
99 struct ath_hal_private ah_priv; /* base definitions */
100
101 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
102 /*
103 * Runtime state.
104 */
105 uint32_t ah_maskReg; /* shadow of IMR+IER regs */
106 uint32_t ah_txOkInterruptMask;
107 uint32_t ah_txErrInterruptMask;
108 uint32_t ah_txDescInterruptMask;
109 uint32_t ah_txEolInterruptMask;
110 uint32_t ah_txUrnInterruptMask;
111 HAL_POWER_MODE ah_powerMode;
112 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
113 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
114 /*
115 * Station mode support.
116 */
117 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
118 uint32_t ah_rssiThr; /* RSSI_THR settings */
119
120 u_int ah_sifstime; /* user-specified sifs time */
121 u_int ah_slottime; /* user-specified slot time */
122 u_int ah_acktimeout; /* user-specified ack timeout */
123 u_int ah_ctstimeout; /* user-specified cts timeout */
124};
125#define AH5210(ah) ((struct ath_hal_5210 *)(ah))
126
127struct ath_hal;
128
129extern void ar5210Detach(struct ath_hal *ah);
130extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
131 struct ieee80211_channel *, HAL_BOOL bChannelChange, HAL_STATUS *);
132extern void ar5210SetPCUConfig(struct ath_hal *);
133extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);
134extern HAL_BOOL ar5210Disable(struct ath_hal *);
135extern HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *);
136extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);
137extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
138 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
139extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);
140extern int16_t ar5210GetNoiseFloor(struct ath_hal *);
141extern int16_t ar5210GetNfAdjust(struct ath_hal *,
142 const HAL_CHANNEL_INTERNAL *);
143extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
144extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *,
145 const struct ieee80211_channel *);
146extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
147extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
148
149extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
150 const HAL_TXQ_INFO *qInfo);
151extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
152 HAL_TXQ_INFO *qInfo);
153extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
154 const HAL_TXQ_INFO *qInfo);
155extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
156extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
157extern uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
158extern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
159extern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
160extern uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
161extern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
162extern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
163extern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
164 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
165 u_int txRate0, u_int txRetries0,
166 u_int keyIx, u_int antMode, u_int flags,
167 u_int rtsctsRate, u_int rtsctsDuration,
168 u_int compicvLen, u_int compivLen, u_int comp);
169extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
170 u_int txRate1, u_int txRetries1,
171 u_int txRate2, u_int txRetries2,
172 u_int txRate3, u_int txRetries3);
173extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
174 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
175 const struct ath_desc *ds0);
176extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
177 struct ath_desc *, struct ath_tx_status *);
178extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
179extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
180extern HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,
181 const struct ath_desc *, int *rates, int *tries);
182
183extern uint32_t ar5210GetRxDP(struct ath_hal *);
184extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp);
185extern void ar5210EnableReceive(struct ath_hal *);
186extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
187extern void ar5210StartPcuReceive(struct ath_hal *);
188extern void ar5210StopPcuReceive(struct ath_hal *);
189extern void ar5210SetMulticastFilter(struct ath_hal *,
190 uint32_t filter0, uint32_t filter1);
191extern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
192extern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
193extern uint32_t ar5210GetRxFilter(struct ath_hal *);
194extern void ar5210SetRxFilter(struct ath_hal *, uint32_t);
195extern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
196 uint32_t, u_int flags);
197extern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
198 uint32_t, struct ath_desc *, uint64_t,
199 struct ath_rx_status *);
200
201extern void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
202extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
203extern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
204extern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
205extern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
206extern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
207extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
208 uint16_t, HAL_STATUS *);
209extern u_int ar5210GetWirelessModes(struct ath_hal *ah);
210extern void ar5210EnableRfKill(struct ath_hal *);
211extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
212extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,
213 HAL_GPIO_MUX_TYPE);
214extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
215extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
216extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
217extern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
218extern u_int ar5210GetDefAntenna(struct ath_hal *);
219extern void ar5210SetDefAntenna(struct ath_hal *, u_int);
220extern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
221extern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
222extern void ar5210WriteAssocid(struct ath_hal *,
223 const uint8_t *bssid, uint16_t assocId);
224extern uint32_t ar5210GetTsf32(struct ath_hal *);
225extern uint64_t ar5210GetTsf64(struct ath_hal *);
226extern void ar5210ResetTsf(struct ath_hal *);
227extern uint32_t ar5210GetRandomSeed(struct ath_hal *);
228extern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
229extern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
230extern void ar5210EnableHwEncryption(struct ath_hal *);
231extern void ar5210DisableHwEncryption(struct ath_hal *);
232extern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
233extern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
234extern u_int ar5210GetSifsTime(struct ath_hal *);
235extern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
236extern u_int ar5210GetSlotTime(struct ath_hal *);
237extern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
238extern u_int ar5210GetAckTimeout(struct ath_hal *);
239extern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
240extern u_int ar5210GetAckCTSRate(struct ath_hal *);
241extern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
242extern u_int ar5210GetCTSTimeout(struct ath_hal *);
243extern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
244void ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
245extern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
246 uint32_t, uint32_t *);
247extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
248 uint32_t, uint32_t, HAL_STATUS *);
249extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
250 const void *args, uint32_t argsize,
251 void **result, uint32_t *resultsize);
252extern uint32_t ar5210Get11nExtBusy(struct ath_hal *);
253extern HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *,
254 HAL_SURVEY_SAMPLE *);
255
256extern u_int ar5210GetKeyCacheSize(struct ath_hal *);
257extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
258extern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
259extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
260 const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
261extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
262 uint16_t, const uint8_t *);
263
264extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
265 int setChip);
266extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
267
268extern void ar5210SetBeaconTimers(struct ath_hal *,
269 const HAL_BEACON_TIMERS *);
270extern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
271extern void ar5210SetStaBeaconTimers(struct ath_hal *,
272 const HAL_BEACON_STATE *);
273extern void ar5210ResetStaBeaconTimers(struct ath_hal *);
274extern uint64_t ar5210GetNextTBTT(struct ath_hal *);
275
276extern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
277extern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
278extern HAL_INT ar5210GetInterrupts(struct ath_hal *);
279extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
280
281extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
282
283extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
284extern void ar5210AniPoll(struct ath_hal *, const struct ieee80211_channel *);
285extern void ar5210RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,
286 const struct ieee80211_channel *);
287extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
288#endif /* _ATH_AR5210_H_ */