1/*
2 * Copyright (c) 2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
| 1/*
2 * Copyright (c) 2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
|
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_eeprom_v14.h 220947 2011-04-22 10:59:20Z adrian $
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_eeprom_v14.h 221622 2011-05-08 08:18:30Z adrian $
|
18 */
19#ifndef _AH_EEPROM_V14_H_
20#define _AH_EEPROM_V14_H_
21
22#include "ah_eeprom.h"
23
24/* reg_off = 4 * (eep_off) */
25#define AR5416_EEPROM_S 2
26#define AR5416_EEPROM_OFFSET 0x2000
27#define AR5416_EEPROM_START_ADDR 0x503f1200
28#define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */
29#define AR5416_EEPROM_MAGIC 0xa55a
30#define AR5416_EEPROM_MAGIC_OFFSET 0x0
31
32#define owl_get_ntxchains(_txchainmask) \
33 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
34
35#ifdef __LINUX_ARM_ARCH__ /* AP71 */
36#define owl_eep_start_loc 0
37#else
38#define owl_eep_start_loc 256
39#endif
40
41/* End temp defines */
42
43#define AR5416_EEP_NO_BACK_VER 0x1
44#define AR5416_EEP_VER 0xE
45#define AR5416_EEP_VER_MINOR_MASK 0xFFF
46// Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc
47#define AR5416_EEP_MINOR_VER_2 0x2
48// Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable
49#define AR5416_EEP_MINOR_VER_3 0x3
50#define AR5416_EEP_MINOR_VER_7 0x7
51#define AR5416_EEP_MINOR_VER_9 0x9
52#define AR5416_EEP_MINOR_VER_10 0xa
53#define AR5416_EEP_MINOR_VER_16 0x10
54#define AR5416_EEP_MINOR_VER_17 0x11
55#define AR5416_EEP_MINOR_VER_19 0x13
56#define AR5416_EEP_MINOR_VER_20 0x14
57#define AR5416_EEP_MINOR_VER_21 0x15
58#define AR5416_EEP_MINOR_VER_22 0x16
59
60// 16-bit offset location start of calibration struct
61#define AR5416_EEP_START_LOC 256
62#define AR5416_NUM_5G_CAL_PIERS 8
63#define AR5416_NUM_2G_CAL_PIERS 4
64#define AR5416_NUM_5G_20_TARGET_POWERS 8
65#define AR5416_NUM_5G_40_TARGET_POWERS 8
66#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
67#define AR5416_NUM_2G_20_TARGET_POWERS 4
68#define AR5416_NUM_2G_40_TARGET_POWERS 4
69#define AR5416_NUM_CTLS 24
70#define AR5416_NUM_BAND_EDGES 8
71#define AR5416_NUM_PD_GAINS 4
72#define AR5416_PD_GAINS_IN_MASK 4
73#define AR5416_PD_GAIN_ICEPTS 5
74#define AR5416_EEPROM_MODAL_SPURS 5
75#define AR5416_MAX_RATE_POWER 63
76#define AR5416_NUM_PDADC_VALUES 128
77#define AR5416_NUM_RATES 16
78#define AR5416_BCHAN_UNUSED 0xFF
79#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
80#define AR5416_EEPMISC_BIG_ENDIAN 0x01
81#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
82#define AR5416_MAX_CHAINS 3
83#define AR5416_PWR_TABLE_OFFSET_DB -5
84#define AR5416_ANT_16S 25
85
86#define AR5416_NUM_ANT_CHAIN_FIELDS 7
87#define AR5416_NUM_ANT_COMMON_FIELDS 4
88#define AR5416_SIZE_ANT_CHAIN_FIELD 3
89#define AR5416_SIZE_ANT_COMMON_FIELD 4
90#define AR5416_ANT_CHAIN_MASK 0x7
91#define AR5416_ANT_COMMON_MASK 0xf
92#define AR5416_CHAIN_0_IDX 0
93#define AR5416_CHAIN_1_IDX 1
94#define AR5416_CHAIN_2_IDX 2
95
96#define AR5416_OPFLAGS_11A 0x01
97#define AR5416_OPFLAGS_11G 0x02
| 18 */
19#ifndef _AH_EEPROM_V14_H_
20#define _AH_EEPROM_V14_H_
21
22#include "ah_eeprom.h"
23
24/* reg_off = 4 * (eep_off) */
25#define AR5416_EEPROM_S 2
26#define AR5416_EEPROM_OFFSET 0x2000
27#define AR5416_EEPROM_START_ADDR 0x503f1200
28#define AR5416_EEPROM_MAX 0xae0 /* Ignore for the moment used only on the flash implementations */
29#define AR5416_EEPROM_MAGIC 0xa55a
30#define AR5416_EEPROM_MAGIC_OFFSET 0x0
31
32#define owl_get_ntxchains(_txchainmask) \
33 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
34
35#ifdef __LINUX_ARM_ARCH__ /* AP71 */
36#define owl_eep_start_loc 0
37#else
38#define owl_eep_start_loc 256
39#endif
40
41/* End temp defines */
42
43#define AR5416_EEP_NO_BACK_VER 0x1
44#define AR5416_EEP_VER 0xE
45#define AR5416_EEP_VER_MINOR_MASK 0xFFF
46// Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc
47#define AR5416_EEP_MINOR_VER_2 0x2
48// Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable
49#define AR5416_EEP_MINOR_VER_3 0x3
50#define AR5416_EEP_MINOR_VER_7 0x7
51#define AR5416_EEP_MINOR_VER_9 0x9
52#define AR5416_EEP_MINOR_VER_10 0xa
53#define AR5416_EEP_MINOR_VER_16 0x10
54#define AR5416_EEP_MINOR_VER_17 0x11
55#define AR5416_EEP_MINOR_VER_19 0x13
56#define AR5416_EEP_MINOR_VER_20 0x14
57#define AR5416_EEP_MINOR_VER_21 0x15
58#define AR5416_EEP_MINOR_VER_22 0x16
59
60// 16-bit offset location start of calibration struct
61#define AR5416_EEP_START_LOC 256
62#define AR5416_NUM_5G_CAL_PIERS 8
63#define AR5416_NUM_2G_CAL_PIERS 4
64#define AR5416_NUM_5G_20_TARGET_POWERS 8
65#define AR5416_NUM_5G_40_TARGET_POWERS 8
66#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
67#define AR5416_NUM_2G_20_TARGET_POWERS 4
68#define AR5416_NUM_2G_40_TARGET_POWERS 4
69#define AR5416_NUM_CTLS 24
70#define AR5416_NUM_BAND_EDGES 8
71#define AR5416_NUM_PD_GAINS 4
72#define AR5416_PD_GAINS_IN_MASK 4
73#define AR5416_PD_GAIN_ICEPTS 5
74#define AR5416_EEPROM_MODAL_SPURS 5
75#define AR5416_MAX_RATE_POWER 63
76#define AR5416_NUM_PDADC_VALUES 128
77#define AR5416_NUM_RATES 16
78#define AR5416_BCHAN_UNUSED 0xFF
79#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
80#define AR5416_EEPMISC_BIG_ENDIAN 0x01
81#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
82#define AR5416_MAX_CHAINS 3
83#define AR5416_PWR_TABLE_OFFSET_DB -5
84#define AR5416_ANT_16S 25
85
86#define AR5416_NUM_ANT_CHAIN_FIELDS 7
87#define AR5416_NUM_ANT_COMMON_FIELDS 4
88#define AR5416_SIZE_ANT_CHAIN_FIELD 3
89#define AR5416_SIZE_ANT_COMMON_FIELD 4
90#define AR5416_ANT_CHAIN_MASK 0x7
91#define AR5416_ANT_COMMON_MASK 0xf
92#define AR5416_CHAIN_0_IDX 0
93#define AR5416_CHAIN_1_IDX 1
94#define AR5416_CHAIN_2_IDX 2
95
96#define AR5416_OPFLAGS_11A 0x01
97#define AR5416_OPFLAGS_11G 0x02
|
98#define AR5416_OPFLAGS_5G_HT40 0x04
99#define AR5416_OPFLAGS_2G_HT40 0x08
100#define AR5416_OPFLAGS_5G_HT20 0x10
101#define AR5416_OPFLAGS_2G_HT20 0x20
| 98#define AR5416_OPFLAGS_N_5G_HT40 0x04 /* If set, disable 5G HT40 */
99#define AR5416_OPFLAGS_N_2G_HT40 0x08
100#define AR5416_OPFLAGS_N_5G_HT20 0x10
101#define AR5416_OPFLAGS_N_2G_HT20 0x20
|
102
103/* RF silent fields in EEPROM */
104#define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */
105#define EEP_RFSILENT_ENABLED_S 0
106#define EEP_RFSILENT_POLARITY 0x0002 /* polarity */
107#define EEP_RFSILENT_POLARITY_S 1
108#define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */
109#define EEP_RFSILENT_GPIO_SEL_S 2
110
111/* Rx gain type values */
112#define AR5416_EEP_RXGAIN_23dB_BACKOFF 0
113#define AR5416_EEP_RXGAIN_13dB_BACKOFF 1
114#define AR5416_EEP_RXGAIN_ORIG 2
115
116/* Tx gain type values */
117#define AR5416_EEP_TXGAIN_ORIG 0
118#define AR5416_EEP_TXGAIN_HIGH_POWER 1
119
120typedef struct spurChanStruct {
121 uint16_t spurChan;
122 uint8_t spurRangeLow;
123 uint8_t spurRangeHigh;
124} __packed SPUR_CHAN;
125
126typedef struct CalTargetPowerLegacy {
127 uint8_t bChannel;
128 uint8_t tPow2x[4];
129} __packed CAL_TARGET_POWER_LEG;
130
131typedef struct CalTargetPowerHt {
132 uint8_t bChannel;
133 uint8_t tPow2x[8];
134} __packed CAL_TARGET_POWER_HT;
135
136typedef struct CalCtlEdges {
137 uint8_t bChannel;
138 uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */
139#define CAL_CTL_EDGES_POWER 0x3f
140#define CAL_CTL_EDGES_POWER_S 0
141#define CAL_CTL_EDGES_FLAG 0xc0
142#define CAL_CTL_EDGES_FLAG_S 6
143} __packed CAL_CTL_EDGES;
144
145/*
146 * These are the secondary regulatory domain flags
147 * for regDmn[1].
148 */
149#define AR5416_REGDMN_EN_FCC_MID 0x01 /* 5.47 - 5.7GHz operation */
150#define AR5416_REGDMN_EN_JAP_MID 0x02 /* 5.47 - 5.7GHz operation */
151#define AR5416_REGDMN_EN_FCC_DFS_HT40 0x04 /* FCC HT40 + DFS operation */
152#define AR5416_REGDMN_EN_JAP_HT40 0x08 /* JP HT40 operation */
153#define AR5416_REGDMN_EN_JAP_DFS_HT40 0x10 /* JP HT40 + DFS operation */
154
155/*
156 * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
157 * and length are swapped). We reverse their position after reading
158 * the data into host memory so the version field is at the same
159 * offset as in previous EEPROM layouts. This makes utilities that
160 * inspect the EEPROM contents work without looking at the PCI device
161 * id which may or may not be reliable.
162 */
163typedef struct BaseEepHeader {
164 uint16_t version; /* NB: length in EEPROM */
165 uint16_t checksum;
166 uint16_t length; /* NB: version in EEPROM */
167 uint8_t opCapFlags;
168 uint8_t eepMisc;
169 uint16_t regDmn[2];
170 uint8_t macAddr[6];
171 uint8_t rxMask;
172 uint8_t txMask;
173 uint16_t rfSilent;
174 uint16_t blueToothOptions;
175 uint16_t deviceCap;
176 uint32_t binBuildNumber;
177 uint8_t deviceType;
178 uint8_t pwdclkind;
179 uint8_t fastClk5g;
180 uint8_t divChain;
181 uint8_t rxGainType;
182 uint8_t dacHiPwrMode_5G;/* use the DAC high power mode (MB91) */
183 uint8_t openLoopPwrCntl;/* 1: use open loop power control,
184 0: use closed loop power control */
185 uint8_t dacLpMode;
186 uint8_t txGainType; /* high power tx gain table support */
187 uint8_t rcChainMask; /* "1" if the card is an HB93 1x2 */
188 uint8_t desiredScaleCCK;
189 uint8_t pwr_table_offset;
190 uint8_t frac_n_5g;
191 uint8_t futureBase[21];
192} __packed BASE_EEP_HEADER; // 64 B
193
194typedef struct ModalEepHeader {
195 uint32_t antCtrlChain[AR5416_MAX_CHAINS]; // 12
196 uint32_t antCtrlCommon; // 4
197 int8_t antennaGainCh[AR5416_MAX_CHAINS]; // 3
198 uint8_t switchSettling; // 1
199 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; // 3
200 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; // 3
201 uint8_t adcDesiredSize; // 1
202 int8_t pgaDesiredSize; // 1
203 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; // 3
204 uint8_t txEndToXpaOff; // 1
205 uint8_t txEndToRxOn; // 1
206 uint8_t txFrameToXpaOn; // 1
207 uint8_t thresh62; // 1
208 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3
209 uint8_t xpdGain; // 1
210 uint8_t xpd; // 1
211 int8_t iqCalICh[AR5416_MAX_CHAINS]; // 1
212 int8_t iqCalQCh[AR5416_MAX_CHAINS]; // 1
213 uint8_t pdGainOverlap; // 1
214 uint8_t ob; // 1
215 uint8_t db; // 1
216 uint8_t xpaBiasLvl; // 1
217 uint8_t pwrDecreaseFor2Chain; // 1
218 uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
219 uint8_t txFrameToDataStart; // 1
220 uint8_t txFrameToPaOn; // 1
221 uint8_t ht40PowerIncForPdadc; // 1
222 uint8_t bswAtten[AR5416_MAX_CHAINS]; // 3
223 uint8_t bswMargin[AR5416_MAX_CHAINS]; // 3
224 uint8_t swSettleHt40; // 1
225 uint8_t xatten2Db[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6)
226 uint8_t xatten2Margin[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17)
227 uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
228 uint8_t db_ch1; // 1
229 uint8_t flagBits; // 1
230#define AR5416_EEP_FLAG_USEANT1 0x80 /* +1 configured antenna */
231#define AR5416_EEP_FLAG_FORCEXPAON 0x40 /* force XPA bit for 5G */
232#define AR5416_EEP_FLAG_LOCALBIAS 0x20 /* enable local bias */
233#define AR5416_EEP_FLAG_FEMBANDSELECT 0x10 /* FEM band select used */
234#define AR5416_EEP_FLAG_XLNABUFIN 0x08
235#define AR5416_EEP_FLAG_XLNAISEL1 0x04
236#define AR5416_EEP_FLAG_XLNAISEL2 0x02
237#define AR5416_EEP_FLAG_XLNABUFMODE 0x01
238 uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
239 uint16_t xpaBiasLvlFreq[3]; // 3
240 uint8_t futureModal[6]; // 6
241
242 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
243} __packed MODAL_EEP_HEADER; // == 100 B
244
245typedef struct calDataPerFreqOpLoop {
246 uint8_t pwrPdg[2][5]; /* power measurement */
247 uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */
248 uint8_t pcdac[2][5]; /* pcdac used for power measurement */
249 uint8_t empty[2][5]; /* future use */
250} __packed CAL_DATA_PER_FREQ_OP_LOOP;
251
252typedef struct CalCtlData {
253 CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
254} __packed CAL_CTL_DATA;
255
256typedef struct calDataPerFreq {
257 uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
258 uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
259} __packed CAL_DATA_PER_FREQ;
260
261struct ar5416eeprom {
262 BASE_EEP_HEADER baseEepHeader; // 64 B
263 uint8_t custData[64]; // 64 B
264 MODAL_EEP_HEADER modalHeader[2]; // 200 B
265 uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
266 uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
267 CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
268 CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
269 CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
270 CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
271 CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
272 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
273 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
274 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
275 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
276 uint8_t ctlIndex[AR5416_NUM_CTLS];
277 CAL_CTL_DATA ctlData[AR5416_NUM_CTLS];
278 uint8_t padding;
279} __packed;
280
281typedef struct {
282 struct ar5416eeprom ee_base;
283#define NUM_EDGES 8
284 uint16_t ee_numCtls;
285 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS];
286 /* XXX these are dynamically calculated for use by shared code */
287 int8_t ee_antennaGainMax[2];
288} HAL_EEPROM_v14;
289#endif /* _AH_EEPROM_V14_H_ */
| 102
103/* RF silent fields in EEPROM */
104#define EEP_RFSILENT_ENABLED 0x0001 /* enabled/disabled */
105#define EEP_RFSILENT_ENABLED_S 0
106#define EEP_RFSILENT_POLARITY 0x0002 /* polarity */
107#define EEP_RFSILENT_POLARITY_S 1
108#define EEP_RFSILENT_GPIO_SEL 0x001c /* gpio PIN */
109#define EEP_RFSILENT_GPIO_SEL_S 2
110
111/* Rx gain type values */
112#define AR5416_EEP_RXGAIN_23dB_BACKOFF 0
113#define AR5416_EEP_RXGAIN_13dB_BACKOFF 1
114#define AR5416_EEP_RXGAIN_ORIG 2
115
116/* Tx gain type values */
117#define AR5416_EEP_TXGAIN_ORIG 0
118#define AR5416_EEP_TXGAIN_HIGH_POWER 1
119
120typedef struct spurChanStruct {
121 uint16_t spurChan;
122 uint8_t spurRangeLow;
123 uint8_t spurRangeHigh;
124} __packed SPUR_CHAN;
125
126typedef struct CalTargetPowerLegacy {
127 uint8_t bChannel;
128 uint8_t tPow2x[4];
129} __packed CAL_TARGET_POWER_LEG;
130
131typedef struct CalTargetPowerHt {
132 uint8_t bChannel;
133 uint8_t tPow2x[8];
134} __packed CAL_TARGET_POWER_HT;
135
136typedef struct CalCtlEdges {
137 uint8_t bChannel;
138 uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */
139#define CAL_CTL_EDGES_POWER 0x3f
140#define CAL_CTL_EDGES_POWER_S 0
141#define CAL_CTL_EDGES_FLAG 0xc0
142#define CAL_CTL_EDGES_FLAG_S 6
143} __packed CAL_CTL_EDGES;
144
145/*
146 * These are the secondary regulatory domain flags
147 * for regDmn[1].
148 */
149#define AR5416_REGDMN_EN_FCC_MID 0x01 /* 5.47 - 5.7GHz operation */
150#define AR5416_REGDMN_EN_JAP_MID 0x02 /* 5.47 - 5.7GHz operation */
151#define AR5416_REGDMN_EN_FCC_DFS_HT40 0x04 /* FCC HT40 + DFS operation */
152#define AR5416_REGDMN_EN_JAP_HT40 0x08 /* JP HT40 operation */
153#define AR5416_REGDMN_EN_JAP_DFS_HT40 0x10 /* JP HT40 + DFS operation */
154
155/*
156 * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
157 * and length are swapped). We reverse their position after reading
158 * the data into host memory so the version field is at the same
159 * offset as in previous EEPROM layouts. This makes utilities that
160 * inspect the EEPROM contents work without looking at the PCI device
161 * id which may or may not be reliable.
162 */
163typedef struct BaseEepHeader {
164 uint16_t version; /* NB: length in EEPROM */
165 uint16_t checksum;
166 uint16_t length; /* NB: version in EEPROM */
167 uint8_t opCapFlags;
168 uint8_t eepMisc;
169 uint16_t regDmn[2];
170 uint8_t macAddr[6];
171 uint8_t rxMask;
172 uint8_t txMask;
173 uint16_t rfSilent;
174 uint16_t blueToothOptions;
175 uint16_t deviceCap;
176 uint32_t binBuildNumber;
177 uint8_t deviceType;
178 uint8_t pwdclkind;
179 uint8_t fastClk5g;
180 uint8_t divChain;
181 uint8_t rxGainType;
182 uint8_t dacHiPwrMode_5G;/* use the DAC high power mode (MB91) */
183 uint8_t openLoopPwrCntl;/* 1: use open loop power control,
184 0: use closed loop power control */
185 uint8_t dacLpMode;
186 uint8_t txGainType; /* high power tx gain table support */
187 uint8_t rcChainMask; /* "1" if the card is an HB93 1x2 */
188 uint8_t desiredScaleCCK;
189 uint8_t pwr_table_offset;
190 uint8_t frac_n_5g;
191 uint8_t futureBase[21];
192} __packed BASE_EEP_HEADER; // 64 B
193
194typedef struct ModalEepHeader {
195 uint32_t antCtrlChain[AR5416_MAX_CHAINS]; // 12
196 uint32_t antCtrlCommon; // 4
197 int8_t antennaGainCh[AR5416_MAX_CHAINS]; // 3
198 uint8_t switchSettling; // 1
199 uint8_t txRxAttenCh[AR5416_MAX_CHAINS]; // 3
200 uint8_t rxTxMarginCh[AR5416_MAX_CHAINS]; // 3
201 uint8_t adcDesiredSize; // 1
202 int8_t pgaDesiredSize; // 1
203 uint8_t xlnaGainCh[AR5416_MAX_CHAINS]; // 3
204 uint8_t txEndToXpaOff; // 1
205 uint8_t txEndToRxOn; // 1
206 uint8_t txFrameToXpaOn; // 1
207 uint8_t thresh62; // 1
208 uint8_t noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3
209 uint8_t xpdGain; // 1
210 uint8_t xpd; // 1
211 int8_t iqCalICh[AR5416_MAX_CHAINS]; // 1
212 int8_t iqCalQCh[AR5416_MAX_CHAINS]; // 1
213 uint8_t pdGainOverlap; // 1
214 uint8_t ob; // 1
215 uint8_t db; // 1
216 uint8_t xpaBiasLvl; // 1
217 uint8_t pwrDecreaseFor2Chain; // 1
218 uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
219 uint8_t txFrameToDataStart; // 1
220 uint8_t txFrameToPaOn; // 1
221 uint8_t ht40PowerIncForPdadc; // 1
222 uint8_t bswAtten[AR5416_MAX_CHAINS]; // 3
223 uint8_t bswMargin[AR5416_MAX_CHAINS]; // 3
224 uint8_t swSettleHt40; // 1
225 uint8_t xatten2Db[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 11:6)
226 uint8_t xatten2Margin[AR5416_MAX_CHAINS]; // 3 -> New for AR9280 (0xa20c/b20c 21:17)
227 uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
228 uint8_t db_ch1; // 1
229 uint8_t flagBits; // 1
230#define AR5416_EEP_FLAG_USEANT1 0x80 /* +1 configured antenna */
231#define AR5416_EEP_FLAG_FORCEXPAON 0x40 /* force XPA bit for 5G */
232#define AR5416_EEP_FLAG_LOCALBIAS 0x20 /* enable local bias */
233#define AR5416_EEP_FLAG_FEMBANDSELECT 0x10 /* FEM band select used */
234#define AR5416_EEP_FLAG_XLNABUFIN 0x08
235#define AR5416_EEP_FLAG_XLNAISEL1 0x04
236#define AR5416_EEP_FLAG_XLNAISEL2 0x02
237#define AR5416_EEP_FLAG_XLNABUFMODE 0x01
238 uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
239 uint16_t xpaBiasLvlFreq[3]; // 3
240 uint8_t futureModal[6]; // 6
241
242 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
243} __packed MODAL_EEP_HEADER; // == 100 B
244
245typedef struct calDataPerFreqOpLoop {
246 uint8_t pwrPdg[2][5]; /* power measurement */
247 uint8_t vpdPdg[2][5]; /* pdadc voltage at power measurement */
248 uint8_t pcdac[2][5]; /* pcdac used for power measurement */
249 uint8_t empty[2][5]; /* future use */
250} __packed CAL_DATA_PER_FREQ_OP_LOOP;
251
252typedef struct CalCtlData {
253 CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
254} __packed CAL_CTL_DATA;
255
256typedef struct calDataPerFreq {
257 uint8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
258 uint8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
259} __packed CAL_DATA_PER_FREQ;
260
261struct ar5416eeprom {
262 BASE_EEP_HEADER baseEepHeader; // 64 B
263 uint8_t custData[64]; // 64 B
264 MODAL_EEP_HEADER modalHeader[2]; // 200 B
265 uint8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
266 uint8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
267 CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
268 CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
269 CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
270 CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
271 CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
272 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
273 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
274 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
275 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
276 uint8_t ctlIndex[AR5416_NUM_CTLS];
277 CAL_CTL_DATA ctlData[AR5416_NUM_CTLS];
278 uint8_t padding;
279} __packed;
280
281typedef struct {
282 struct ar5416eeprom ee_base;
283#define NUM_EDGES 8
284 uint16_t ee_numCtls;
285 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS];
286 /* XXX these are dynamically calculated for use by shared code */
287 int8_t ee_antennaGainMax[2];
288} HAL_EEPROM_v14;
289#endif /* _AH_EEPROM_V14_H_ */
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