1/*-
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-serverworks.c 249083 2013-04-04 07:12:24Z mav $");
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_serverworks_chipinit(device_t dev);
56static int ata_serverworks_ch_attach(device_t dev);
57static int ata_serverworks_ch_detach(device_t dev);
58static void ata_serverworks_tf_read(struct ata_request *request);
59static void ata_serverworks_tf_write(struct ata_request *request);
60static int ata_serverworks_setmode(device_t dev, int target, int mode);
61static void ata_serverworks_sata_reset(device_t dev);
62static int ata_serverworks_status(device_t dev);
63
64/* misc defines */
65#define SWKS_33 0
66#define SWKS_66 1
67#define SWKS_100 2
68#define SWKS_MIO 3
69
70
71/*
72 * ServerWorks chipset support functions
73 */
74static int
75ata_serverworks_probe(device_t dev)
76{
77 struct ata_pci_controller *ctlr = device_get_softc(dev);
78 static const struct ata_chip_id ids[] =
79 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" },
80 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
81 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
82 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
83 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
84 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
85 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
86 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
87 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
88 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
89 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
90 { 0, 0, 0, 0, 0, 0}};
91
92 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
93 return ENXIO;
94
95 if (!(ctlr->chip = ata_match_chip(dev, ids)))
96 return ENXIO;
97
98 ata_set_desc(dev);
99 ctlr->chipinit = ata_serverworks_chipinit;
100 return (BUS_PROBE_DEFAULT);
101}
102
103static int
104ata_serverworks_status(device_t dev)
105{
106 struct ata_channel *ch = device_get_softc(dev);
107 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
108
109 /*
110 * Check if this interrupt belongs to our channel.
111 */
112 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
113 return (0);
114
115 /*
116 * We need to do a 4-byte read on the status reg before the values
117 * will report correctly
118 */
119
120 ATA_IDX_INL(ch,ATA_STATUS);
121
122 return ata_pci_status(dev);
123}
124
125static int
126ata_serverworks_chipinit(device_t dev)
127{
128 struct ata_pci_controller *ctlr = device_get_softc(dev);
129
130 if (ata_setup_interrupt(dev, ata_generic_intr))
131 return ENXIO;
132
133 if (ctlr->chip->cfg1 == SWKS_MIO) {
134 ctlr->r_type2 = SYS_RES_MEMORY;
135 ctlr->r_rid2 = PCIR_BAR(5);
136 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
137 &ctlr->r_rid2, RF_ACTIVE)))
138 return ENXIO;
139
140 ctlr->channels = ctlr->chip->cfg2;
141 ctlr->ch_attach = ata_serverworks_ch_attach;
142 ctlr->ch_detach = ata_serverworks_ch_detach;
143 ctlr->setmode = ata_sata_setmode;
144 ctlr->getrev = ata_sata_getrev;
145 ctlr->reset = ata_serverworks_sata_reset;
146 return 0;
147 }
148 else if (ctlr->chip->cfg1 == SWKS_33) {
149 device_t *children;
150 int nchildren, i;
151
152 /* locate the ISA part in the southbridge and enable UDMA33 */
153 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
154 for (i = 0; i < nchildren; i++) {
155 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
156 pci_write_config(children[i], 0x64,
157 (pci_read_config(children[i], 0x64, 4) &
158 ~0x00002000) | 0x00004000, 4);
159 break;
160 }
161 }
162 free(children, M_TEMP);
163 }
164 }
165 else {
166 pci_write_config(dev, 0x5a,
167 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
168 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1);
169 }
170 ctlr->setmode = ata_serverworks_setmode;
171 return 0;
172}
173
174static int
175ata_serverworks_ch_attach(device_t dev)
176{
177 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
178 struct ata_channel *ch = device_get_softc(dev);
179 int ch_offset;
180 int i;
181
182 ch_offset = ch->unit * 0x100;
183
184 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
185 ch->r_io[i].res = ctlr->r_res2;
186
187 /* setup ATA registers */
188 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
189 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
190 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
191 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
192 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
193 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
194 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
195 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
196 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
197 ata_default_registers(dev);
198
199 /* setup DMA registers */
200 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
201 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
202 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
203
204 /* setup SATA registers */
205 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
206 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
207 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
208
209 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE;
210 ata_pci_hw(dev);
211 ch->hw.tf_read = ata_serverworks_tf_read;
212 ch->hw.tf_write = ata_serverworks_tf_write;
213
214 if (ctlr->chip->chipid == ATA_K2) {
215 /*
216 * Set SICR registers to turn off waiting for a status message
217 * before sending FIS. Values obtained from the Darwin driver.
218 */
219
220 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
221 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
222 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
223
224 /*
225 * Some controllers have a bug where they will send the command
226 * to the drive before seeing a DMA start, and then can begin
227 * receiving data before the DMA start arrives. The controller
228 * will then become confused and either corrupt the data or crash.
229 * Remedy this by starting DMA before sending the drive command.
230 */
231
232 ch->flags |= ATA_DMA_BEFORE_CMD;
233
234 /*
235 * The status register must be read as a long to fill the other
236 * registers.
237 */
238
239 ch->hw.status = ata_serverworks_status;
240 ch->flags |= ATA_STATUS_IS_LONG;
241 }
242
243 /* chip does not reliably do 64K DMA transfers */
244 ch->dma.max_iosize = 64 * DEV_BSIZE;
245
246 ata_pci_dmainit(dev);
247
248 return 0;
249}
250
251static int
252ata_serverworks_ch_detach(device_t dev)
253{
254
255 ata_pci_dmafini(dev);
256 return (0);
257}
258
259static void
260ata_serverworks_tf_read(struct ata_request *request)
261{
262 struct ata_channel *ch = device_get_softc(request->parent);
263
264 if (request->flags & ATA_R_48BIT) {
265 u_int16_t temp;
266
267 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
268 temp = ATA_IDX_INW(ch, ATA_SECTOR);
269 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
270 ((u_int64_t)(temp & 0xff00) << 24);
271 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
272 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
273 ((u_int64_t)(temp & 0xff00) << 32);
274 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
275 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
276 ((u_int64_t)(temp & 0xff00) << 40);
277 }
278 else {
279 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
280 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
281 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
282 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
283 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
284 }
285}
286
287static void
288ata_serverworks_tf_write(struct ata_request *request)
289{
290 struct ata_channel *ch = device_get_softc(request->parent);
291
292 if (request->flags & ATA_R_48BIT) {
293 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
294 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
295 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
296 (request->u.ata.lba & 0x00ff));
297 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
298 ((request->u.ata.lba >> 8) & 0x00ff));
299 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
300 ((request->u.ata.lba >> 16) & 0x00ff));
301 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
302 }
303 else {
304 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
305 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
306 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
307 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
308 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
309 ATA_IDX_OUTW(ch, ATA_DRIVE,
310 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
311 ((request->u.ata.lba >> 24) & 0x0f));
312 }
313}
314
315static int
316ata_serverworks_setmode(device_t dev, int target, int mode)
317{
318 device_t parent = device_get_parent(dev);
319 struct ata_pci_controller *ctlr = device_get_softc(parent);
320 struct ata_channel *ch = device_get_softc(dev);
321 int devno = (ch->unit << 1) + target;
322 int offset = (devno ^ 0x01) << 3;
323 int piomode;
324 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
325 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
326
327 mode = min(mode, ctlr->chip->max_dma);
328 if (mode >= ATA_UDMA0) {
329 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
330 pci_write_config(parent, 0x56,
331 (pci_read_config(parent, 0x56, 2) &
332 ~(0xf << (devno << 2))) |
333 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
334 pci_write_config(parent, 0x54,
335 pci_read_config(parent, 0x54, 1) |
336 (0x01 << devno), 1);
337 pci_write_config(parent, 0x44,
338 (pci_read_config(parent, 0x44, 4) &
339 ~(0xff << offset)) |
340 (dmatimings[2] << offset), 4);
341 piomode = ATA_PIO4;
342 } else if (mode >= ATA_WDMA0) {
343 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
344 pci_write_config(parent, 0x54,
345 pci_read_config(parent, 0x54, 1) &
346 ~(0x01 << devno), 1);
347 pci_write_config(parent, 0x44,
348 (pci_read_config(parent, 0x44, 4) &
349 ~(0xff << offset)) |
350 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
351 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
352 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
353 } else {
354 /* Disable UDMA, set requested PIO. */
355 pci_write_config(parent, 0x54,
356 pci_read_config(parent, 0x54, 1) &
357 ~(0x01 << devno), 1);
358 piomode = mode;
359 }
360 /* Set PIO mode and timings, calculated above. */
361 if (ctlr->chip->cfg1 != SWKS_33) {
362 pci_write_config(parent, 0x4a,
363 (pci_read_config(parent, 0x4a, 2) &
364 ~(0xf << (devno << 2))) |
365 ((piomode - ATA_PIO0) << (devno<<2)),2);
366 }
367 pci_write_config(parent, 0x40,
368 (pci_read_config(parent, 0x40, 4) &
369 ~(0xff << offset)) |
370 (piotimings[ata_mode2idx(piomode)] << offset), 4);
371 return (mode);
372}
373
374static void
375ata_serverworks_sata_reset(device_t dev)
376{
377 struct ata_channel *ch = device_get_softc(dev);
378
379 if (ata_sata_phy_reset(dev, -1, 0))
380 ata_generic_reset(dev);
381 else
382 ch->devices = 0;
383}
384
385ATA_DECLARE_DRIVER(ata_serverworks);
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-serverworks.c 249083 2013-04-04 07:12:24Z mav $");
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_serverworks_chipinit(device_t dev);
56static int ata_serverworks_ch_attach(device_t dev);
57static int ata_serverworks_ch_detach(device_t dev);
58static void ata_serverworks_tf_read(struct ata_request *request);
59static void ata_serverworks_tf_write(struct ata_request *request);
60static int ata_serverworks_setmode(device_t dev, int target, int mode);
61static void ata_serverworks_sata_reset(device_t dev);
62static int ata_serverworks_status(device_t dev);
63
64/* misc defines */
65#define SWKS_33 0
66#define SWKS_66 1
67#define SWKS_100 2
68#define SWKS_MIO 3
69
70
71/*
72 * ServerWorks chipset support functions
73 */
74static int
75ata_serverworks_probe(device_t dev)
76{
77 struct ata_pci_controller *ctlr = device_get_softc(dev);
78 static const struct ata_chip_id ids[] =
79 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" },
80 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
81 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
82 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
83 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
84 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
85 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
86 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
87 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
88 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
89 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
90 { 0, 0, 0, 0, 0, 0}};
91
92 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
93 return ENXIO;
94
95 if (!(ctlr->chip = ata_match_chip(dev, ids)))
96 return ENXIO;
97
98 ata_set_desc(dev);
99 ctlr->chipinit = ata_serverworks_chipinit;
100 return (BUS_PROBE_DEFAULT);
101}
102
103static int
104ata_serverworks_status(device_t dev)
105{
106 struct ata_channel *ch = device_get_softc(dev);
107 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
108
109 /*
110 * Check if this interrupt belongs to our channel.
111 */
112 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
113 return (0);
114
115 /*
116 * We need to do a 4-byte read on the status reg before the values
117 * will report correctly
118 */
119
120 ATA_IDX_INL(ch,ATA_STATUS);
121
122 return ata_pci_status(dev);
123}
124
125static int
126ata_serverworks_chipinit(device_t dev)
127{
128 struct ata_pci_controller *ctlr = device_get_softc(dev);
129
130 if (ata_setup_interrupt(dev, ata_generic_intr))
131 return ENXIO;
132
133 if (ctlr->chip->cfg1 == SWKS_MIO) {
134 ctlr->r_type2 = SYS_RES_MEMORY;
135 ctlr->r_rid2 = PCIR_BAR(5);
136 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
137 &ctlr->r_rid2, RF_ACTIVE)))
138 return ENXIO;
139
140 ctlr->channels = ctlr->chip->cfg2;
141 ctlr->ch_attach = ata_serverworks_ch_attach;
142 ctlr->ch_detach = ata_serverworks_ch_detach;
143 ctlr->setmode = ata_sata_setmode;
144 ctlr->getrev = ata_sata_getrev;
145 ctlr->reset = ata_serverworks_sata_reset;
146 return 0;
147 }
148 else if (ctlr->chip->cfg1 == SWKS_33) {
149 device_t *children;
150 int nchildren, i;
151
152 /* locate the ISA part in the southbridge and enable UDMA33 */
153 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
154 for (i = 0; i < nchildren; i++) {
155 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
156 pci_write_config(children[i], 0x64,
157 (pci_read_config(children[i], 0x64, 4) &
158 ~0x00002000) | 0x00004000, 4);
159 break;
160 }
161 }
162 free(children, M_TEMP);
163 }
164 }
165 else {
166 pci_write_config(dev, 0x5a,
167 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
168 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1);
169 }
170 ctlr->setmode = ata_serverworks_setmode;
171 return 0;
172}
173
174static int
175ata_serverworks_ch_attach(device_t dev)
176{
177 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
178 struct ata_channel *ch = device_get_softc(dev);
179 int ch_offset;
180 int i;
181
182 ch_offset = ch->unit * 0x100;
183
184 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
185 ch->r_io[i].res = ctlr->r_res2;
186
187 /* setup ATA registers */
188 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
189 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
190 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
191 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
192 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
193 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
194 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
195 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
196 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
197 ata_default_registers(dev);
198
199 /* setup DMA registers */
200 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
201 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
202 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
203
204 /* setup SATA registers */
205 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
206 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
207 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
208
209 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE;
210 ata_pci_hw(dev);
211 ch->hw.tf_read = ata_serverworks_tf_read;
212 ch->hw.tf_write = ata_serverworks_tf_write;
213
214 if (ctlr->chip->chipid == ATA_K2) {
215 /*
216 * Set SICR registers to turn off waiting for a status message
217 * before sending FIS. Values obtained from the Darwin driver.
218 */
219
220 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
221 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
222 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
223
224 /*
225 * Some controllers have a bug where they will send the command
226 * to the drive before seeing a DMA start, and then can begin
227 * receiving data before the DMA start arrives. The controller
228 * will then become confused and either corrupt the data or crash.
229 * Remedy this by starting DMA before sending the drive command.
230 */
231
232 ch->flags |= ATA_DMA_BEFORE_CMD;
233
234 /*
235 * The status register must be read as a long to fill the other
236 * registers.
237 */
238
239 ch->hw.status = ata_serverworks_status;
240 ch->flags |= ATA_STATUS_IS_LONG;
241 }
242
243 /* chip does not reliably do 64K DMA transfers */
244 ch->dma.max_iosize = 64 * DEV_BSIZE;
245
246 ata_pci_dmainit(dev);
247
248 return 0;
249}
250
251static int
252ata_serverworks_ch_detach(device_t dev)
253{
254
255 ata_pci_dmafini(dev);
256 return (0);
257}
258
259static void
260ata_serverworks_tf_read(struct ata_request *request)
261{
262 struct ata_channel *ch = device_get_softc(request->parent);
263
264 if (request->flags & ATA_R_48BIT) {
265 u_int16_t temp;
266
267 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
268 temp = ATA_IDX_INW(ch, ATA_SECTOR);
269 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
270 ((u_int64_t)(temp & 0xff00) << 24);
271 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
272 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
273 ((u_int64_t)(temp & 0xff00) << 32);
274 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
275 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
276 ((u_int64_t)(temp & 0xff00) << 40);
277 }
278 else {
279 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
280 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
281 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
282 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
283 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
284 }
285}
286
287static void
288ata_serverworks_tf_write(struct ata_request *request)
289{
290 struct ata_channel *ch = device_get_softc(request->parent);
291
292 if (request->flags & ATA_R_48BIT) {
293 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
294 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
295 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
296 (request->u.ata.lba & 0x00ff));
297 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
298 ((request->u.ata.lba >> 8) & 0x00ff));
299 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
300 ((request->u.ata.lba >> 16) & 0x00ff));
301 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
302 }
303 else {
304 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
305 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
306 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
307 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
308 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
309 ATA_IDX_OUTW(ch, ATA_DRIVE,
310 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
311 ((request->u.ata.lba >> 24) & 0x0f));
312 }
313}
314
315static int
316ata_serverworks_setmode(device_t dev, int target, int mode)
317{
318 device_t parent = device_get_parent(dev);
319 struct ata_pci_controller *ctlr = device_get_softc(parent);
320 struct ata_channel *ch = device_get_softc(dev);
321 int devno = (ch->unit << 1) + target;
322 int offset = (devno ^ 0x01) << 3;
323 int piomode;
324 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
325 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
326
327 mode = min(mode, ctlr->chip->max_dma);
328 if (mode >= ATA_UDMA0) {
329 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
330 pci_write_config(parent, 0x56,
331 (pci_read_config(parent, 0x56, 2) &
332 ~(0xf << (devno << 2))) |
333 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
334 pci_write_config(parent, 0x54,
335 pci_read_config(parent, 0x54, 1) |
336 (0x01 << devno), 1);
337 pci_write_config(parent, 0x44,
338 (pci_read_config(parent, 0x44, 4) &
339 ~(0xff << offset)) |
340 (dmatimings[2] << offset), 4);
341 piomode = ATA_PIO4;
342 } else if (mode >= ATA_WDMA0) {
343 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
344 pci_write_config(parent, 0x54,
345 pci_read_config(parent, 0x54, 1) &
346 ~(0x01 << devno), 1);
347 pci_write_config(parent, 0x44,
348 (pci_read_config(parent, 0x44, 4) &
349 ~(0xff << offset)) |
350 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
351 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
352 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
353 } else {
354 /* Disable UDMA, set requested PIO. */
355 pci_write_config(parent, 0x54,
356 pci_read_config(parent, 0x54, 1) &
357 ~(0x01 << devno), 1);
358 piomode = mode;
359 }
360 /* Set PIO mode and timings, calculated above. */
361 if (ctlr->chip->cfg1 != SWKS_33) {
362 pci_write_config(parent, 0x4a,
363 (pci_read_config(parent, 0x4a, 2) &
364 ~(0xf << (devno << 2))) |
365 ((piomode - ATA_PIO0) << (devno<<2)),2);
366 }
367 pci_write_config(parent, 0x40,
368 (pci_read_config(parent, 0x40, 4) &
369 ~(0xff << offset)) |
370 (piotimings[ata_mode2idx(piomode)] << offset), 4);
371 return (mode);
372}
373
374static void
375ata_serverworks_sata_reset(device_t dev)
376{
377 struct ata_channel *ch = device_get_softc(dev);
378
379 if (ata_sata_phy_reset(dev, -1, 0))
380 ata_generic_reset(dev);
381 else
382 ch->devices = 0;
383}
384
385ATA_DECLARE_DRIVER(ata_serverworks);