29 */
30
31#include "opt_ata.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/disk.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/bio.h>
39#include <sys/malloc.h>
40#include <sys/devicestat.h>
41#include <sys/sysctl.h>
42#include <machine/stdarg.h>
43#include <machine/resource.h>
44#include <machine/bus.h>
45#ifdef __alpha__
46#include <machine/md_var.h>
47#endif
48#include <sys/rman.h>
49#include <pci/pcivar.h>
50#include <pci/pcireg.h>
51#include <dev/ata/ata-all.h>
52
53/* device structures */
54struct ata_pci_controller {
55 struct resource *bmio;
56 int bmaddr;
57 struct resource *irq;
58 int irqcnt;
59};
60
61/* misc defines */
62#define IOMASK 0xfffffffc
63#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
64#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
65 (pci_get_progif(dev) & 0x05) != 0x05)
66
67int
68ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
69{
70 device_t *children;
71 int nchildren, i;
72
73 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 return 0;
75
76 for (i = 0; i < nchildren; i++) {
77 if (pci_get_devid(children[i]) == devid &&
78 pci_get_revid(children[i]) >= revid) {
79 free(children, M_TEMP);
80 return 1;
81 }
82 }
83 free(children, M_TEMP);
84 return 0;
85}
86
87static void
88ata_via_southbridge_fixup(device_t dev)
89{
90 device_t *children;
91 int nchildren, i;
92
93 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 return;
95
96 for (i = 0; i < nchildren; i++) {
97 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
98 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
99 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
100 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
101 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
102
103 if ((reg76 & 0xf0) != 0xd0) {
104 device_printf(dev,
105 "Correcting VIA config for southbridge data corruption bug\n");
106 pci_write_config(children[i], 0x75, 0x80, 1);
107 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
108 }
109 break;
110 }
111 }
112 free(children, M_TEMP);
113}
114
115static const char *
116ata_pci_match(device_t dev)
117{
118 if (pci_get_class(dev) != PCIC_STORAGE)
119 return NULL;
120
121 switch (pci_get_devid(dev)) {
122 /* supported chipsets */
123 case 0x12308086:
124 return "Intel PIIX ATA controller";
125
126 case 0x70108086:
127 return "Intel PIIX3 ATA controller";
128
129 case 0x71118086:
130 case 0x71998086:
131 case 0x84ca8086:
132 return "Intel PIIX4 ATA33 controller";
133
134 case 0x24218086:
135 return "Intel ICH0 ATA33 controller";
136
137 case 0x24118086:
138 case 0x76018086:
139 return "Intel ICH ATA66 controller";
140
141 case 0x244a8086:
142 case 0x244b8086:
143 return "Intel ICH2 ATA100 controller";
144
145 case 0x248a8086:
146 case 0x248b8086:
147 return "Intel ICH3 ATA100 controller";
148
149 case 0x522910b9:
150 if (pci_get_revid(dev) >= 0xc4)
151 return "AcerLabs Aladdin ATA100 controller";
152 else if (pci_get_revid(dev) >= 0xc2)
153 return "AcerLabs Aladdin ATA66 controller";
154 else if (pci_get_revid(dev) >= 0x20)
155 return "AcerLabs Aladdin ATA33 controller";
156 else
157 return "AcerLabs Aladdin ATA controller";
158
159 case 0x05711106:
160 if (ata_find_dev(dev, 0x05861106, 0x02))
161 return "VIA 82C586 ATA33 controller";
162 if (ata_find_dev(dev, 0x05861106, 0))
163 return "VIA 82C586 ATA controller";
164 if (ata_find_dev(dev, 0x05961106, 0x12))
165 return "VIA 82C596 ATA66 controller";
166 if (ata_find_dev(dev, 0x05961106, 0))
167 return "VIA 82C596 ATA33 controller";
168 if (ata_find_dev(dev, 0x06861106, 0x40))
169 return "VIA 82C686 ATA100 controller";
170 if (ata_find_dev(dev, 0x06861106, 0x10))
171 return "VIA 82C686 ATA66 controller";
172 if (ata_find_dev(dev, 0x06861106, 0))
173 return "VIA 82C686 ATA33 controller";
174 if (ata_find_dev(dev, 0x82311106, 0))
175 return "VIA 8231 ATA100 controller";
176 if (ata_find_dev(dev, 0x30741106, 0) ||
177 ata_find_dev(dev, 0x31091106, 0))
178 return "VIA 8233 ATA100 controller";
179 if (ata_find_dev(dev, 0x31471106, 0))
180 return "VIA 8233 ATA133 controller";
181 return "VIA Apollo ATA controller";
182
183 case 0x55131039:
184 if (ata_find_dev(dev, 0x06301039, 0x30) ||
185 ata_find_dev(dev, 0x06331039, 0) ||
186 ata_find_dev(dev, 0x06351039, 0) ||
187 ata_find_dev(dev, 0x06401039, 0) ||
188 ata_find_dev(dev, 0x06451039, 0) ||
189 ata_find_dev(dev, 0x06501039, 0) ||
190 ata_find_dev(dev, 0x07301039, 0) ||
191 ata_find_dev(dev, 0x07331039, 0) ||
192 ata_find_dev(dev, 0x07351039, 0) ||
193 ata_find_dev(dev, 0x07401039, 0) ||
194 ata_find_dev(dev, 0x07451039, 0) ||
195 ata_find_dev(dev, 0x07501039, 0))
196 return "SiS 5591 ATA100 controller";
197 else if (ata_find_dev(dev, 0x05301039, 0) ||
198 ata_find_dev(dev, 0x05401039, 0) ||
199 ata_find_dev(dev, 0x06201039, 0) ||
200 ata_find_dev(dev, 0x06301039, 0))
201 return "SiS 5591 ATA66 controller";
202 else
203 return "SiS 5591 ATA33 controller";
204
205 case 0x06491095:
206 return "CMD 649 ATA100 controller";
207
208 case 0x06481095:
209 return "CMD 648 ATA66 controller";
210
211 case 0x06461095:
212 return "CMD 646 ATA controller";
213
214 case 0xc6931080:
215 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
216 return "Cypress 82C693 ATA controller";
217 return NULL;
218
219 case 0x01021078:
220 return "Cyrix 5530 ATA33 controller";
221
222 case 0x74091022:
223 return "AMD 756 ATA66 controller";
224
225 case 0x74111022:
226 return "AMD 766 ATA100 controller";
227
228 case 0x74411022:
229 return "AMD 768 ATA100 controller";
230
| 29 */
30
31#include "opt_ata.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/disk.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/bio.h>
39#include <sys/malloc.h>
40#include <sys/devicestat.h>
41#include <sys/sysctl.h>
42#include <machine/stdarg.h>
43#include <machine/resource.h>
44#include <machine/bus.h>
45#ifdef __alpha__
46#include <machine/md_var.h>
47#endif
48#include <sys/rman.h>
49#include <pci/pcivar.h>
50#include <pci/pcireg.h>
51#include <dev/ata/ata-all.h>
52
53/* device structures */
54struct ata_pci_controller {
55 struct resource *bmio;
56 int bmaddr;
57 struct resource *irq;
58 int irqcnt;
59};
60
61/* misc defines */
62#define IOMASK 0xfffffffc
63#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
64#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
65 (pci_get_progif(dev) & 0x05) != 0x05)
66
67int
68ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
69{
70 device_t *children;
71 int nchildren, i;
72
73 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 return 0;
75
76 for (i = 0; i < nchildren; i++) {
77 if (pci_get_devid(children[i]) == devid &&
78 pci_get_revid(children[i]) >= revid) {
79 free(children, M_TEMP);
80 return 1;
81 }
82 }
83 free(children, M_TEMP);
84 return 0;
85}
86
87static void
88ata_via_southbridge_fixup(device_t dev)
89{
90 device_t *children;
91 int nchildren, i;
92
93 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 return;
95
96 for (i = 0; i < nchildren; i++) {
97 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
98 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
99 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
100 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
101 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
102
103 if ((reg76 & 0xf0) != 0xd0) {
104 device_printf(dev,
105 "Correcting VIA config for southbridge data corruption bug\n");
106 pci_write_config(children[i], 0x75, 0x80, 1);
107 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
108 }
109 break;
110 }
111 }
112 free(children, M_TEMP);
113}
114
115static const char *
116ata_pci_match(device_t dev)
117{
118 if (pci_get_class(dev) != PCIC_STORAGE)
119 return NULL;
120
121 switch (pci_get_devid(dev)) {
122 /* supported chipsets */
123 case 0x12308086:
124 return "Intel PIIX ATA controller";
125
126 case 0x70108086:
127 return "Intel PIIX3 ATA controller";
128
129 case 0x71118086:
130 case 0x71998086:
131 case 0x84ca8086:
132 return "Intel PIIX4 ATA33 controller";
133
134 case 0x24218086:
135 return "Intel ICH0 ATA33 controller";
136
137 case 0x24118086:
138 case 0x76018086:
139 return "Intel ICH ATA66 controller";
140
141 case 0x244a8086:
142 case 0x244b8086:
143 return "Intel ICH2 ATA100 controller";
144
145 case 0x248a8086:
146 case 0x248b8086:
147 return "Intel ICH3 ATA100 controller";
148
149 case 0x522910b9:
150 if (pci_get_revid(dev) >= 0xc4)
151 return "AcerLabs Aladdin ATA100 controller";
152 else if (pci_get_revid(dev) >= 0xc2)
153 return "AcerLabs Aladdin ATA66 controller";
154 else if (pci_get_revid(dev) >= 0x20)
155 return "AcerLabs Aladdin ATA33 controller";
156 else
157 return "AcerLabs Aladdin ATA controller";
158
159 case 0x05711106:
160 if (ata_find_dev(dev, 0x05861106, 0x02))
161 return "VIA 82C586 ATA33 controller";
162 if (ata_find_dev(dev, 0x05861106, 0))
163 return "VIA 82C586 ATA controller";
164 if (ata_find_dev(dev, 0x05961106, 0x12))
165 return "VIA 82C596 ATA66 controller";
166 if (ata_find_dev(dev, 0x05961106, 0))
167 return "VIA 82C596 ATA33 controller";
168 if (ata_find_dev(dev, 0x06861106, 0x40))
169 return "VIA 82C686 ATA100 controller";
170 if (ata_find_dev(dev, 0x06861106, 0x10))
171 return "VIA 82C686 ATA66 controller";
172 if (ata_find_dev(dev, 0x06861106, 0))
173 return "VIA 82C686 ATA33 controller";
174 if (ata_find_dev(dev, 0x82311106, 0))
175 return "VIA 8231 ATA100 controller";
176 if (ata_find_dev(dev, 0x30741106, 0) ||
177 ata_find_dev(dev, 0x31091106, 0))
178 return "VIA 8233 ATA100 controller";
179 if (ata_find_dev(dev, 0x31471106, 0))
180 return "VIA 8233 ATA133 controller";
181 return "VIA Apollo ATA controller";
182
183 case 0x55131039:
184 if (ata_find_dev(dev, 0x06301039, 0x30) ||
185 ata_find_dev(dev, 0x06331039, 0) ||
186 ata_find_dev(dev, 0x06351039, 0) ||
187 ata_find_dev(dev, 0x06401039, 0) ||
188 ata_find_dev(dev, 0x06451039, 0) ||
189 ata_find_dev(dev, 0x06501039, 0) ||
190 ata_find_dev(dev, 0x07301039, 0) ||
191 ata_find_dev(dev, 0x07331039, 0) ||
192 ata_find_dev(dev, 0x07351039, 0) ||
193 ata_find_dev(dev, 0x07401039, 0) ||
194 ata_find_dev(dev, 0x07451039, 0) ||
195 ata_find_dev(dev, 0x07501039, 0))
196 return "SiS 5591 ATA100 controller";
197 else if (ata_find_dev(dev, 0x05301039, 0) ||
198 ata_find_dev(dev, 0x05401039, 0) ||
199 ata_find_dev(dev, 0x06201039, 0) ||
200 ata_find_dev(dev, 0x06301039, 0))
201 return "SiS 5591 ATA66 controller";
202 else
203 return "SiS 5591 ATA33 controller";
204
205 case 0x06491095:
206 return "CMD 649 ATA100 controller";
207
208 case 0x06481095:
209 return "CMD 648 ATA66 controller";
210
211 case 0x06461095:
212 return "CMD 646 ATA controller";
213
214 case 0xc6931080:
215 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
216 return "Cypress 82C693 ATA controller";
217 return NULL;
218
219 case 0x01021078:
220 return "Cyrix 5530 ATA33 controller";
221
222 case 0x74091022:
223 return "AMD 756 ATA66 controller";
224
225 case 0x74111022:
226 return "AMD 766 ATA100 controller";
227
228 case 0x74411022:
229 return "AMD 768 ATA100 controller";
230
|
231 case 0x02111166:
232 return "ServerWorks ROSB4 ATA33 controller";
233
234 case 0x02121166:
235 if (pci_get_revid(dev) >= 0x92)
236 return "ServerWorks CSB5 ATA100 controller";
237 else
238 return "ServerWorks CSB5 ATA66 controller";
239
240 case 0x4d33105a:
241 return "Promise ATA33 controller";
242
243 case 0x4d38105a:
244 return "Promise ATA66 controller";
245
246 case 0x0d30105a:
247 case 0x4d30105a:
248 return "Promise ATA100 controller";
249
250 case 0x4d68105a:
251 case 0x6268105a:
252 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
253 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
254 static long start = 0, end = 0;
255
256 /* we belive we are on a TX4, now do our (simple) magic */
257 if (pci_get_slot(dev) == 1) {
258 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
259 return "Promise TX4 ATA100 controller (channel 0+1)";
260 }
261 else if (pci_get_slot(dev) == 2 && start && end) {
262 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
263 start = end = 0;
264 return "Promise TX4 ATA100 controller (channel 2+3)";
265 }
266 else
267 start = end = 0;
268 }
269 return "Promise TX2 ATA100 controller";
270
271 case 0x4d69105a:
272 case 0x5275105a:
273 case 0x6269105a:
274 return "Promise TX2 ATA133 controller";
275
276 case 0x00041103:
277 switch (pci_get_revid(dev)) {
278 case 0x00:
279 case 0x01:
280 return "HighPoint HPT366 ATA66 controller";
281 case 0x02:
282 return "HighPoint HPT368 ATA66 controller";
283 case 0x03:
284 case 0x04:
285 return "HighPoint HPT370 ATA100 controller";
286 case 0x05:
287 return "HighPoint HPT372 ATA133 controller";
288 }
289 return NULL;
290
291 case 0x00051103:
292 switch (pci_get_revid(dev)) {
293 case 0x01:
294 return "HighPoint HPT372 ATA133 controller";
295 }
296 return NULL;
297
298 case 0x00081103:
299 switch (pci_get_revid(dev)) {
300 case 0x07:
301 return "HighPoint HPT374 ATA133 controller";
302 }
303 return NULL;
304
305 case 0x000116ca:
306 return "Cenatek Rocket Drive controller";
307
308 /* unsupported but known chipsets, generic DMA only */
309 case 0x10001042:
310 case 0x10011042:
311 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
312
313 case 0x06401095:
314 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
315
316 /* unknown chipsets, try generic DMA if it seems possible */
317 default:
318 if (pci_get_class(dev) == PCIC_STORAGE &&
319 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
320 return "Generic PCI ATA controller";
321 }
322 return NULL;
323}
324
325static int
326ata_pci_probe(device_t dev)
327{
328 const char *desc = ata_pci_match(dev);
329
330 if (desc) {
331 device_set_desc(dev, desc);
332 return 0;
333 }
334 else
335 return ENXIO;
336}
337
338static int
339ata_pci_add_child(device_t dev, int unit)
340{
341 device_t child;
342
343 /* check if this is located at one of the std addresses */
344 if (ATA_MASTERDEV(dev)) {
345 if (!(child = device_add_child(dev, "ata", unit)))
346 return ENOMEM;
347 }
348 else {
349 if (!(child =
350 device_add_child(dev, "ata",
351 devclass_find_free_unit(ata_devclass, 2))))
352 return ENOMEM;
353 }
354 return 0;
355}
356
357static int
358ata_pci_attach(device_t dev)
359{
360 struct ata_pci_controller *controller = device_get_softc(dev);
361 u_int8_t class, subclass;
362 u_int32_t type, cmd;
363 int rid;
364
365 /* set up vendor-specific stuff */
366 type = pci_get_devid(dev);
367 class = pci_get_class(dev);
368 subclass = pci_get_subclass(dev);
369 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
370
371 if (!(cmd & PCIM_CMD_PORTEN)) {
372 device_printf(dev, "ATA channel disabled by BIOS\n");
373 return 0;
374 }
375
376#ifdef __sparc64__
377 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
378 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
379 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
380 }
381#endif
382 /* is busmastering supported ? */
383 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
384 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
385
386 /* is there a valid port range to connect to ? */
387 rid = 0x20;
388 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
389 0, ~0, 1, RF_ACTIVE);
390 if (!controller->bmio)
391 device_printf(dev, "Busmastering DMA not configured\n");
392 }
393 else
394 device_printf(dev, "Busmastering DMA not supported\n");
395
396 /* do extra chipset specific setups */
397 switch (type) {
398
399 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */
400 pci_write_config(dev, 0x53,
401 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
402 break;
403
404 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
405 case 0x4d30105a:
406 case 0x0d30105a:
407 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
408 /* FALLTHROUGH */
409
410 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
411 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
412 break;
413
414 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */
415 if (pci_get_revid(dev) < 2) { /* HPT366 */
416 /* turn off interrupt prediction */
417 pci_write_config(dev, 0x51,
418 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
419 break;
420 }
421 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
422 /* turn off interrupt prediction */
423 pci_write_config(dev, 0x51,
424 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
425 pci_write_config(dev, 0x55,
426 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
427
428 /* turn on interrupts */
429 pci_write_config(dev, 0x5a,
430 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
431
432 /* set clocks etc */
433 pci_write_config(dev, 0x5b, 0x22, 1);
434 break;
435 }
436 /* FALLTHROUGH */
437
438 case 0x00051103: /* HighPoint HPT372 default setup */
439 case 0x00081103: /* HighPoint HPT374 default setup */
440 /* turn off interrupt prediction */
441 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
442 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
443
444 /* turn on interrupts */
445 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
446
447 /* set clocks etc */
448 pci_write_config(dev, 0x5b,
449 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
450 break;
451
452 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
453 /* prepare for ATA-66 on the 82C686a and 82C596b */
454 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
455 !ata_find_dev(dev, 0x06861106, 0x40)) ||
456 ata_find_dev(dev, 0x05961106, 0x12))
457 pci_write_config(dev, 0x50, 0x030b030b, 4);
458
459 /* the southbridge might need the data corruption fix */
460 if (ata_find_dev(dev, 0x06861106, 0x40) ||
461 ata_find_dev(dev, 0x82311106, 0x10))
462 ata_via_southbridge_fixup(dev);
463 /* FALLTHROUGH */
464
465 case 0x74091022: /* AMD 756 default setup */
466 case 0x74111022: /* AMD 766 default setup */
467 case 0x74411022: /* AMD 768 default setup */
| 234 case 0x02111166:
235 return "ServerWorks ROSB4 ATA33 controller";
236
237 case 0x02121166:
238 if (pci_get_revid(dev) >= 0x92)
239 return "ServerWorks CSB5 ATA100 controller";
240 else
241 return "ServerWorks CSB5 ATA66 controller";
242
243 case 0x4d33105a:
244 return "Promise ATA33 controller";
245
246 case 0x4d38105a:
247 return "Promise ATA66 controller";
248
249 case 0x0d30105a:
250 case 0x4d30105a:
251 return "Promise ATA100 controller";
252
253 case 0x4d68105a:
254 case 0x6268105a:
255 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
256 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
257 static long start = 0, end = 0;
258
259 /* we belive we are on a TX4, now do our (simple) magic */
260 if (pci_get_slot(dev) == 1) {
261 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
262 return "Promise TX4 ATA100 controller (channel 0+1)";
263 }
264 else if (pci_get_slot(dev) == 2 && start && end) {
265 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
266 start = end = 0;
267 return "Promise TX4 ATA100 controller (channel 2+3)";
268 }
269 else
270 start = end = 0;
271 }
272 return "Promise TX2 ATA100 controller";
273
274 case 0x4d69105a:
275 case 0x5275105a:
276 case 0x6269105a:
277 return "Promise TX2 ATA133 controller";
278
279 case 0x00041103:
280 switch (pci_get_revid(dev)) {
281 case 0x00:
282 case 0x01:
283 return "HighPoint HPT366 ATA66 controller";
284 case 0x02:
285 return "HighPoint HPT368 ATA66 controller";
286 case 0x03:
287 case 0x04:
288 return "HighPoint HPT370 ATA100 controller";
289 case 0x05:
290 return "HighPoint HPT372 ATA133 controller";
291 }
292 return NULL;
293
294 case 0x00051103:
295 switch (pci_get_revid(dev)) {
296 case 0x01:
297 return "HighPoint HPT372 ATA133 controller";
298 }
299 return NULL;
300
301 case 0x00081103:
302 switch (pci_get_revid(dev)) {
303 case 0x07:
304 return "HighPoint HPT374 ATA133 controller";
305 }
306 return NULL;
307
308 case 0x000116ca:
309 return "Cenatek Rocket Drive controller";
310
311 /* unsupported but known chipsets, generic DMA only */
312 case 0x10001042:
313 case 0x10011042:
314 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
315
316 case 0x06401095:
317 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
318
319 /* unknown chipsets, try generic DMA if it seems possible */
320 default:
321 if (pci_get_class(dev) == PCIC_STORAGE &&
322 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
323 return "Generic PCI ATA controller";
324 }
325 return NULL;
326}
327
328static int
329ata_pci_probe(device_t dev)
330{
331 const char *desc = ata_pci_match(dev);
332
333 if (desc) {
334 device_set_desc(dev, desc);
335 return 0;
336 }
337 else
338 return ENXIO;
339}
340
341static int
342ata_pci_add_child(device_t dev, int unit)
343{
344 device_t child;
345
346 /* check if this is located at one of the std addresses */
347 if (ATA_MASTERDEV(dev)) {
348 if (!(child = device_add_child(dev, "ata", unit)))
349 return ENOMEM;
350 }
351 else {
352 if (!(child =
353 device_add_child(dev, "ata",
354 devclass_find_free_unit(ata_devclass, 2))))
355 return ENOMEM;
356 }
357 return 0;
358}
359
360static int
361ata_pci_attach(device_t dev)
362{
363 struct ata_pci_controller *controller = device_get_softc(dev);
364 u_int8_t class, subclass;
365 u_int32_t type, cmd;
366 int rid;
367
368 /* set up vendor-specific stuff */
369 type = pci_get_devid(dev);
370 class = pci_get_class(dev);
371 subclass = pci_get_subclass(dev);
372 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
373
374 if (!(cmd & PCIM_CMD_PORTEN)) {
375 device_printf(dev, "ATA channel disabled by BIOS\n");
376 return 0;
377 }
378
379#ifdef __sparc64__
380 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
381 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
382 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
383 }
384#endif
385 /* is busmastering supported ? */
386 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
387 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
388
389 /* is there a valid port range to connect to ? */
390 rid = 0x20;
391 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
392 0, ~0, 1, RF_ACTIVE);
393 if (!controller->bmio)
394 device_printf(dev, "Busmastering DMA not configured\n");
395 }
396 else
397 device_printf(dev, "Busmastering DMA not supported\n");
398
399 /* do extra chipset specific setups */
400 switch (type) {
401
402 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */
403 pci_write_config(dev, 0x53,
404 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
405 break;
406
407 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
408 case 0x4d30105a:
409 case 0x0d30105a:
410 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
411 /* FALLTHROUGH */
412
413 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
414 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
415 break;
416
417 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */
418 if (pci_get_revid(dev) < 2) { /* HPT366 */
419 /* turn off interrupt prediction */
420 pci_write_config(dev, 0x51,
421 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
422 break;
423 }
424 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
425 /* turn off interrupt prediction */
426 pci_write_config(dev, 0x51,
427 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
428 pci_write_config(dev, 0x55,
429 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
430
431 /* turn on interrupts */
432 pci_write_config(dev, 0x5a,
433 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
434
435 /* set clocks etc */
436 pci_write_config(dev, 0x5b, 0x22, 1);
437 break;
438 }
439 /* FALLTHROUGH */
440
441 case 0x00051103: /* HighPoint HPT372 default setup */
442 case 0x00081103: /* HighPoint HPT374 default setup */
443 /* turn off interrupt prediction */
444 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
445 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
446
447 /* turn on interrupts */
448 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
449
450 /* set clocks etc */
451 pci_write_config(dev, 0x5b,
452 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
453 break;
454
455 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
456 /* prepare for ATA-66 on the 82C686a and 82C596b */
457 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
458 !ata_find_dev(dev, 0x06861106, 0x40)) ||
459 ata_find_dev(dev, 0x05961106, 0x12))
460 pci_write_config(dev, 0x50, 0x030b030b, 4);
461
462 /* the southbridge might need the data corruption fix */
463 if (ata_find_dev(dev, 0x06861106, 0x40) ||
464 ata_find_dev(dev, 0x82311106, 0x10))
465 ata_via_southbridge_fixup(dev);
466 /* FALLTHROUGH */
467
468 case 0x74091022: /* AMD 756 default setup */
469 case 0x74111022: /* AMD 766 default setup */
470 case 0x74411022: /* AMD 768 default setup */
|
468 /* set prefetch, postwrite */
469 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
470
471 /* set fifo configuration half'n'half */
472 pci_write_config(dev, 0x43,
473 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
474
475 /* set status register read retry */
476 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
477
478 /* set DMA read & end-of-sector fifo flush */
479 pci_write_config(dev, 0x46,
480 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
481
482 /* set sector size */
483 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
484 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
485 break;
486
487 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
488 pci_write_config(dev, 0x64,
489 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
490 0x00004000, 4);
491 break;
492
493 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
494 pci_write_config(dev, 0x5a,
495 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
496 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
497 break;
498
499 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
500 pci_write_config(dev, 0x71, 0x01, 1);
501 break;
502
503 case 0x10001042: /* RZ 100? known bad, no DMA */
504 case 0x10011042:
505 case 0x06401095: /* CMD 640 known bad, no DMA */
506 controller->bmio = NULL;
507 device_printf(dev, "Busmastering DMA disabled\n");
508 }
509
510 if (controller->bmio) {
511 controller->bmaddr = rman_get_start(controller->bmio);
512 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
513 SYS_RES_IOPORT, rid, controller->bmio);
514 controller->bmio = NULL;
515 }
516
517 /*
518 * the Cypress chip is a mess, it contains two ATA functions, but
519 * both channels are visible on the first one.
520 * simply ignore the second function for now, as the right
521 * solution (ignoring the second channel on the first function)
522 * doesn't work with the crappy ATA interrupt setup on the alpha.
523 */
524 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
525 return 0;
526
527 ata_pci_add_child(dev, 0);
528
529 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
530 ata_pci_add_child(dev, 1);
531
532 return bus_generic_attach(dev);
533}
534
535static int
536ata_pci_intr(struct ata_channel *ch)
537{
538 u_int8_t dmastat;
539
540 /*
541 * since we might share the IRQ with another device, and in some
542 * cases with our twin channel, we only want to process interrupts
543 * that we know this channel generated.
544 */
545 switch (ch->chiptype) {
546 case 0x00041103: /* HighPoint HPT366/368/370/372 */
547 case 0x00051103: /* HighPoint HPT372 */
548 case 0x00081103: /* HighPoint HPT374 */
549 if (((dmastat = ata_dmastatus(ch)) &
550 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
551 return 1;
552 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
553 DELAY(1);
554 return 0;
555
556 case 0x06481095: /* CMD 648 */
557 case 0x06491095: /* CMD 649 */
558 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
559 (ch->unit ? 0x08 : 0x04)))
560 return 1;
561 break;
562
563 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
564 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
565 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
566 case 0x0d30105a: /* Promise OEM ATA100 */
567 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
568 (ch->unit ? 0x00004000 : 0x00000400)))
569 return 1;
570 break;
571
572 case 0x4d68105a: /* Promise TX2 ATA100 */
573 case 0x6268105a: /* Promise TX2 ATA100 */
574 case 0x4d69105a: /* Promise TX2 ATA133 */
575 case 0x5275105a: /* Promise TX2 ATA133 */
576 case 0x6269105a: /* Promise TX2 ATA133 */
577 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
578 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
579 return 1;
580 break;
581 }
582
583 if (ch->flags & ATA_DMA_ACTIVE) {
584 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
585 return 1;
586 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
587 DELAY(1);
588 }
589 return 0;
590}
591
592static int
593ata_pci_print_child(device_t dev, device_t child)
594{
595 struct ata_channel *ch = device_get_softc(child);
596 int retval = 0;
597
598 retval += bus_print_child_header(dev, child);
599 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
600
601 if (ATA_MASTERDEV(dev))
602 retval += printf(" irq %d", 14 + ch->unit);
603
604 retval += bus_print_child_footer(dev, child);
605
606 return retval;
607}
608
609static struct resource *
610ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
611 u_long start, u_long end, u_long count, u_int flags)
612{
613 struct ata_pci_controller *controller = device_get_softc(dev);
614 struct resource *res = NULL;
615 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
616 int myrid;
617
618 if (type == SYS_RES_IOPORT) {
619 switch (*rid) {
620 case ATA_IOADDR_RID:
621 if (ATA_MASTERDEV(dev)) {
622 myrid = 0;
623 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
624 end = start + ATA_IOSIZE - 1;
625 count = ATA_IOSIZE;
626 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
627 SYS_RES_IOPORT, &myrid,
628 start, end, count, flags);
629 }
630 else {
631 myrid = 0x10 + 8 * unit;
632 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
633 SYS_RES_IOPORT, &myrid,
634 start, end, count, flags);
635 }
636 break;
637
638 case ATA_ALTADDR_RID:
639 if (ATA_MASTERDEV(dev)) {
640 myrid = 0;
641 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
642 end = start + ATA_ALTIOSIZE - 1;
643 count = ATA_ALTIOSIZE;
644 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
645 SYS_RES_IOPORT, &myrid,
646 start, end, count, flags);
647 }
648 else {
649 myrid = 0x14 + 8 * unit;
650 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
651 SYS_RES_IOPORT, &myrid,
652 start, end, count, flags);
653 if (res) {
654 start = rman_get_start(res) + 2;
655 end = start + ATA_ALTIOSIZE - 1;
656 count = ATA_ALTIOSIZE;
657 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
658 SYS_RES_IOPORT, myrid, res);
659 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
660 SYS_RES_IOPORT, &myrid,
661 start, end, count, flags);
662 }
663 }
664 break;
665
666 case ATA_BMADDR_RID:
667 if (controller->bmaddr) {
668 myrid = 0x20;
669 start = (unit == 0 ?
670 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
671 end = start + ATA_BMIOSIZE - 1;
672 count = ATA_BMIOSIZE;
673 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
674 SYS_RES_IOPORT, &myrid,
675 start, end, count, flags);
676 }
677 }
678 return res;
679 }
680
681 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
682 if (ATA_MASTERDEV(dev)) {
683#ifdef __alpha__
684 return alpha_platform_alloc_ide_intr(unit);
685#else
686 int irq = (unit == 0 ? 14 : 15);
687
688 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
689 SYS_RES_IRQ, rid, irq, irq, 1, flags);
690#endif
691 }
692 else {
693 /* primary and secondary channels share interrupt, keep track */
694 if (!controller->irq)
695 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
696 dev, SYS_RES_IRQ,
697 rid, 0, ~0, 1, flags);
698 controller->irqcnt++;
699 return controller->irq;
700 }
701 }
702 return 0;
703}
704
705static int
706ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
707 struct resource *r)
708{
709 struct ata_pci_controller *controller = device_get_softc(dev);
710 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
711
712 if (type == SYS_RES_IOPORT) {
713 switch (rid) {
714 case ATA_IOADDR_RID:
715 if (ATA_MASTERDEV(dev))
716 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
717 SYS_RES_IOPORT, 0x0, r);
718 else
719 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
720 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
721 break;
722
723 case ATA_ALTADDR_RID:
724 if (ATA_MASTERDEV(dev))
725 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
726 SYS_RES_IOPORT, 0x0, r);
727 else
728 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
729 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
730 break;
731
732 case ATA_BMADDR_RID:
733 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
734 SYS_RES_IOPORT, 0x20, r);
735 default:
736 return ENOENT;
737 }
738 }
739 if (type == SYS_RES_IRQ) {
740 if (rid != ATA_IRQ_RID)
741 return ENOENT;
742
743 if (ATA_MASTERDEV(dev)) {
744#ifdef __alpha__
745 return alpha_platform_release_ide_intr(unit, r);
746#else
747 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
748 SYS_RES_IRQ, rid, r);
749#endif
750 }
751 else {
752 /* primary and secondary channels share interrupt, keep track */
753 if (--controller->irqcnt)
754 return 0;
755 controller->irq = NULL;
756 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
757 SYS_RES_IRQ, rid, r);
758 }
759 }
760 return EINVAL;
761}
762
763static int
764ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
765 int flags, driver_intr_t *intr, void *arg,
766 void **cookiep)
767{
768 if (ATA_MASTERDEV(dev)) {
769#ifdef __alpha__
770 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
771#else
772 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
773 flags, intr, arg, cookiep);
774#endif
775 }
776 else
777 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
778 flags, intr, arg, cookiep);
779}
780
781static int
782ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
783 void *cookie)
784{
785 if (ATA_MASTERDEV(dev)) {
786#ifdef __alpha__
787 return alpha_platform_teardown_ide_intr(child, irq, cookie);
788#else
789 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
790#endif
791 }
792 else
793 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
794}
795
796static device_method_t ata_pci_methods[] = {
797 /* device interface */
798 DEVMETHOD(device_probe, ata_pci_probe),
799 DEVMETHOD(device_attach, ata_pci_attach),
800 DEVMETHOD(device_shutdown, bus_generic_shutdown),
801 DEVMETHOD(device_suspend, bus_generic_suspend),
802 DEVMETHOD(device_resume, bus_generic_resume),
803
804 /* bus methods */
805 DEVMETHOD(bus_print_child, ata_pci_print_child),
806 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
807 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
808 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
809 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
810 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
811 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
812 { 0, 0 }
813};
814
815static driver_t ata_pci_driver = {
816 "atapci",
817 ata_pci_methods,
818 sizeof(struct ata_pci_controller),
819};
820
821static devclass_t ata_pci_devclass;
822
823DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
824
825static int
826ata_pcisub_probe(device_t dev)
827{
828 struct ata_channel *ch = device_get_softc(dev);
829 device_t *children;
830 int count, i;
831
832 /* find channel number on this controller */
833 device_get_children(device_get_parent(dev), &children, &count);
834 for (i = 0; i < count; i++) {
835 if (children[i] == dev)
836 ch->unit = i;
837 }
838 free(children, M_TEMP);
839 ch->chiptype = pci_get_devid(device_get_parent(dev));
840 ch->intr_func = ata_pci_intr;
841 return ata_probe(dev);
842}
843
844static device_method_t ata_pcisub_methods[] = {
845 /* device interface */
846 DEVMETHOD(device_probe, ata_pcisub_probe),
847 DEVMETHOD(device_attach, ata_attach),
848 DEVMETHOD(device_detach, ata_detach),
849 DEVMETHOD(device_resume, ata_resume),
850 { 0, 0 }
851};
852
853static driver_t ata_pcisub_driver = {
854 "ata",
855 ata_pcisub_methods,
856 sizeof(struct ata_channel),
857};
858
859DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
| 472 /* set prefetch, postwrite */
473 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
474
475 /* set fifo configuration half'n'half */
476 pci_write_config(dev, 0x43,
477 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
478
479 /* set status register read retry */
480 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
481
482 /* set DMA read & end-of-sector fifo flush */
483 pci_write_config(dev, 0x46,
484 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
485
486 /* set sector size */
487 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
488 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
489 break;
490
491 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
492 pci_write_config(dev, 0x64,
493 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
494 0x00004000, 4);
495 break;
496
497 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
498 pci_write_config(dev, 0x5a,
499 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
500 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
501 break;
502
503 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
504 pci_write_config(dev, 0x71, 0x01, 1);
505 break;
506
507 case 0x10001042: /* RZ 100? known bad, no DMA */
508 case 0x10011042:
509 case 0x06401095: /* CMD 640 known bad, no DMA */
510 controller->bmio = NULL;
511 device_printf(dev, "Busmastering DMA disabled\n");
512 }
513
514 if (controller->bmio) {
515 controller->bmaddr = rman_get_start(controller->bmio);
516 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
517 SYS_RES_IOPORT, rid, controller->bmio);
518 controller->bmio = NULL;
519 }
520
521 /*
522 * the Cypress chip is a mess, it contains two ATA functions, but
523 * both channels are visible on the first one.
524 * simply ignore the second function for now, as the right
525 * solution (ignoring the second channel on the first function)
526 * doesn't work with the crappy ATA interrupt setup on the alpha.
527 */
528 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
529 return 0;
530
531 ata_pci_add_child(dev, 0);
532
533 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
534 ata_pci_add_child(dev, 1);
535
536 return bus_generic_attach(dev);
537}
538
539static int
540ata_pci_intr(struct ata_channel *ch)
541{
542 u_int8_t dmastat;
543
544 /*
545 * since we might share the IRQ with another device, and in some
546 * cases with our twin channel, we only want to process interrupts
547 * that we know this channel generated.
548 */
549 switch (ch->chiptype) {
550 case 0x00041103: /* HighPoint HPT366/368/370/372 */
551 case 0x00051103: /* HighPoint HPT372 */
552 case 0x00081103: /* HighPoint HPT374 */
553 if (((dmastat = ata_dmastatus(ch)) &
554 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
555 return 1;
556 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
557 DELAY(1);
558 return 0;
559
560 case 0x06481095: /* CMD 648 */
561 case 0x06491095: /* CMD 649 */
562 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
563 (ch->unit ? 0x08 : 0x04)))
564 return 1;
565 break;
566
567 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
568 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
569 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
570 case 0x0d30105a: /* Promise OEM ATA100 */
571 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
572 (ch->unit ? 0x00004000 : 0x00000400)))
573 return 1;
574 break;
575
576 case 0x4d68105a: /* Promise TX2 ATA100 */
577 case 0x6268105a: /* Promise TX2 ATA100 */
578 case 0x4d69105a: /* Promise TX2 ATA133 */
579 case 0x5275105a: /* Promise TX2 ATA133 */
580 case 0x6269105a: /* Promise TX2 ATA133 */
581 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
582 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
583 return 1;
584 break;
585 }
586
587 if (ch->flags & ATA_DMA_ACTIVE) {
588 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
589 return 1;
590 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
591 DELAY(1);
592 }
593 return 0;
594}
595
596static int
597ata_pci_print_child(device_t dev, device_t child)
598{
599 struct ata_channel *ch = device_get_softc(child);
600 int retval = 0;
601
602 retval += bus_print_child_header(dev, child);
603 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
604
605 if (ATA_MASTERDEV(dev))
606 retval += printf(" irq %d", 14 + ch->unit);
607
608 retval += bus_print_child_footer(dev, child);
609
610 return retval;
611}
612
613static struct resource *
614ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
615 u_long start, u_long end, u_long count, u_int flags)
616{
617 struct ata_pci_controller *controller = device_get_softc(dev);
618 struct resource *res = NULL;
619 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
620 int myrid;
621
622 if (type == SYS_RES_IOPORT) {
623 switch (*rid) {
624 case ATA_IOADDR_RID:
625 if (ATA_MASTERDEV(dev)) {
626 myrid = 0;
627 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
628 end = start + ATA_IOSIZE - 1;
629 count = ATA_IOSIZE;
630 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
631 SYS_RES_IOPORT, &myrid,
632 start, end, count, flags);
633 }
634 else {
635 myrid = 0x10 + 8 * unit;
636 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
637 SYS_RES_IOPORT, &myrid,
638 start, end, count, flags);
639 }
640 break;
641
642 case ATA_ALTADDR_RID:
643 if (ATA_MASTERDEV(dev)) {
644 myrid = 0;
645 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
646 end = start + ATA_ALTIOSIZE - 1;
647 count = ATA_ALTIOSIZE;
648 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
649 SYS_RES_IOPORT, &myrid,
650 start, end, count, flags);
651 }
652 else {
653 myrid = 0x14 + 8 * unit;
654 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
655 SYS_RES_IOPORT, &myrid,
656 start, end, count, flags);
657 if (res) {
658 start = rman_get_start(res) + 2;
659 end = start + ATA_ALTIOSIZE - 1;
660 count = ATA_ALTIOSIZE;
661 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
662 SYS_RES_IOPORT, myrid, res);
663 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
664 SYS_RES_IOPORT, &myrid,
665 start, end, count, flags);
666 }
667 }
668 break;
669
670 case ATA_BMADDR_RID:
671 if (controller->bmaddr) {
672 myrid = 0x20;
673 start = (unit == 0 ?
674 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
675 end = start + ATA_BMIOSIZE - 1;
676 count = ATA_BMIOSIZE;
677 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
678 SYS_RES_IOPORT, &myrid,
679 start, end, count, flags);
680 }
681 }
682 return res;
683 }
684
685 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
686 if (ATA_MASTERDEV(dev)) {
687#ifdef __alpha__
688 return alpha_platform_alloc_ide_intr(unit);
689#else
690 int irq = (unit == 0 ? 14 : 15);
691
692 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
693 SYS_RES_IRQ, rid, irq, irq, 1, flags);
694#endif
695 }
696 else {
697 /* primary and secondary channels share interrupt, keep track */
698 if (!controller->irq)
699 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
700 dev, SYS_RES_IRQ,
701 rid, 0, ~0, 1, flags);
702 controller->irqcnt++;
703 return controller->irq;
704 }
705 }
706 return 0;
707}
708
709static int
710ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
711 struct resource *r)
712{
713 struct ata_pci_controller *controller = device_get_softc(dev);
714 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
715
716 if (type == SYS_RES_IOPORT) {
717 switch (rid) {
718 case ATA_IOADDR_RID:
719 if (ATA_MASTERDEV(dev))
720 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
721 SYS_RES_IOPORT, 0x0, r);
722 else
723 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
724 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
725 break;
726
727 case ATA_ALTADDR_RID:
728 if (ATA_MASTERDEV(dev))
729 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
730 SYS_RES_IOPORT, 0x0, r);
731 else
732 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
733 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
734 break;
735
736 case ATA_BMADDR_RID:
737 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
738 SYS_RES_IOPORT, 0x20, r);
739 default:
740 return ENOENT;
741 }
742 }
743 if (type == SYS_RES_IRQ) {
744 if (rid != ATA_IRQ_RID)
745 return ENOENT;
746
747 if (ATA_MASTERDEV(dev)) {
748#ifdef __alpha__
749 return alpha_platform_release_ide_intr(unit, r);
750#else
751 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
752 SYS_RES_IRQ, rid, r);
753#endif
754 }
755 else {
756 /* primary and secondary channels share interrupt, keep track */
757 if (--controller->irqcnt)
758 return 0;
759 controller->irq = NULL;
760 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
761 SYS_RES_IRQ, rid, r);
762 }
763 }
764 return EINVAL;
765}
766
767static int
768ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
769 int flags, driver_intr_t *intr, void *arg,
770 void **cookiep)
771{
772 if (ATA_MASTERDEV(dev)) {
773#ifdef __alpha__
774 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
775#else
776 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
777 flags, intr, arg, cookiep);
778#endif
779 }
780 else
781 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
782 flags, intr, arg, cookiep);
783}
784
785static int
786ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
787 void *cookie)
788{
789 if (ATA_MASTERDEV(dev)) {
790#ifdef __alpha__
791 return alpha_platform_teardown_ide_intr(child, irq, cookie);
792#else
793 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
794#endif
795 }
796 else
797 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
798}
799
800static device_method_t ata_pci_methods[] = {
801 /* device interface */
802 DEVMETHOD(device_probe, ata_pci_probe),
803 DEVMETHOD(device_attach, ata_pci_attach),
804 DEVMETHOD(device_shutdown, bus_generic_shutdown),
805 DEVMETHOD(device_suspend, bus_generic_suspend),
806 DEVMETHOD(device_resume, bus_generic_resume),
807
808 /* bus methods */
809 DEVMETHOD(bus_print_child, ata_pci_print_child),
810 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
811 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
812 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
813 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
814 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
815 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
816 { 0, 0 }
817};
818
819static driver_t ata_pci_driver = {
820 "atapci",
821 ata_pci_methods,
822 sizeof(struct ata_pci_controller),
823};
824
825static devclass_t ata_pci_devclass;
826
827DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
828
829static int
830ata_pcisub_probe(device_t dev)
831{
832 struct ata_channel *ch = device_get_softc(dev);
833 device_t *children;
834 int count, i;
835
836 /* find channel number on this controller */
837 device_get_children(device_get_parent(dev), &children, &count);
838 for (i = 0; i < count; i++) {
839 if (children[i] == dev)
840 ch->unit = i;
841 }
842 free(children, M_TEMP);
843 ch->chiptype = pci_get_devid(device_get_parent(dev));
844 ch->intr_func = ata_pci_intr;
845 return ata_probe(dev);
846}
847
848static device_method_t ata_pcisub_methods[] = {
849 /* device interface */
850 DEVMETHOD(device_probe, ata_pcisub_probe),
851 DEVMETHOD(device_attach, ata_attach),
852 DEVMETHOD(device_detach, ata_detach),
853 DEVMETHOD(device_resume, ata_resume),
854 { 0, 0 }
855};
856
857static driver_t ata_pcisub_driver = {
858 "ata",
859 ata_pcisub_methods,
860 sizeof(struct ata_channel),
861};
862
863DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
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