1/*-
2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-pci.c 100380 2002-07-19 22:14:54Z jhb $
| 28 * $FreeBSD: head/sys/dev/ata/ata-pci.c 103255 2002-09-12 15:25:59Z sos $
|
29 */
30
31#include "opt_ata.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/disk.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/bio.h>
39#include <sys/malloc.h>
40#include <sys/devicestat.h>
41#include <sys/sysctl.h>
42#include <machine/stdarg.h>
43#include <machine/resource.h>
44#include <machine/bus.h>
45#ifdef __alpha__
46#include <machine/md_var.h>
47#endif
48#include <sys/rman.h>
49#include <pci/pcivar.h>
50#include <pci/pcireg.h>
51#include <dev/ata/ata-all.h>
52
53/* device structures */
54struct ata_pci_controller {
55 struct resource *bmio;
56 int bmaddr;
57 struct resource *irq;
58 int irqcnt;
59};
60
61/* misc defines */
62#define IOMASK 0xfffffffc
63#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
64#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
65 (pci_get_progif(dev) & 0x05) != 0x05)
66
67int
68ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
69{
70 device_t *children;
71 int nchildren, i;
72
73 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 return 0;
75
76 for (i = 0; i < nchildren; i++) {
77 if (pci_get_devid(children[i]) == devid &&
78 pci_get_revid(children[i]) >= revid) {
79 free(children, M_TEMP);
80 return 1;
81 }
82 }
83 free(children, M_TEMP);
84 return 0;
85}
86
87static void
88ata_via_southbridge_fixup(device_t dev)
89{
90 device_t *children;
91 int nchildren, i;
92
93 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 return;
95
96 for (i = 0; i < nchildren; i++) {
97 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
98 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
99 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
100 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
101 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
102
103 if ((reg76 & 0xf0) != 0xd0) {
104 device_printf(dev,
105 "Correcting VIA config for southbridge data corruption bug\n");
106 pci_write_config(children[i], 0x75, 0x80, 1);
107 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
108 }
109 break;
110 }
111 }
112 free(children, M_TEMP);
113}
114
115static const char *
116ata_pci_match(device_t dev)
117{
118 if (pci_get_class(dev) != PCIC_STORAGE)
119 return NULL;
120
121 switch (pci_get_devid(dev)) {
122 /* supported chipsets */
123 case 0x12308086:
124 return "Intel PIIX ATA controller";
125
126 case 0x70108086:
127 return "Intel PIIX3 ATA controller";
128
129 case 0x71118086:
130 case 0x71998086:
131 case 0x84ca8086:
132 return "Intel PIIX4 ATA33 controller";
133
134 case 0x24218086:
135 return "Intel ICH0 ATA33 controller";
136
137 case 0x24118086:
138 case 0x76018086:
139 return "Intel ICH ATA66 controller";
140
141 case 0x244a8086:
142 case 0x244b8086:
143 return "Intel ICH2 ATA100 controller";
144
145 case 0x248a8086:
146 case 0x248b8086:
147 return "Intel ICH3 ATA100 controller";
148
149 case 0x24cb8086:
150 return "Intel ICH4 ATA100 controller";
151
152 case 0x522910b9:
153 if (pci_get_revid(dev) >= 0xc4)
154 return "AcerLabs Aladdin ATA100 controller";
155 else if (pci_get_revid(dev) >= 0xc2)
156 return "AcerLabs Aladdin ATA66 controller";
157 else if (pci_get_revid(dev) >= 0x20)
158 return "AcerLabs Aladdin ATA33 controller";
159 else
160 return "AcerLabs Aladdin ATA controller";
161
162 case 0x05711106:
163 if (ata_find_dev(dev, 0x05861106, 0x02))
164 return "VIA 82C586 ATA33 controller";
165 if (ata_find_dev(dev, 0x05861106, 0))
166 return "VIA 82C586 ATA controller";
167 if (ata_find_dev(dev, 0x05961106, 0x12))
168 return "VIA 82C596 ATA66 controller";
169 if (ata_find_dev(dev, 0x05961106, 0))
170 return "VIA 82C596 ATA33 controller";
171 if (ata_find_dev(dev, 0x06861106, 0x40))
172 return "VIA 82C686 ATA100 controller";
173 if (ata_find_dev(dev, 0x06861106, 0x10))
174 return "VIA 82C686 ATA66 controller";
175 if (ata_find_dev(dev, 0x06861106, 0))
176 return "VIA 82C686 ATA33 controller";
177 if (ata_find_dev(dev, 0x82311106, 0))
178 return "VIA 8231 ATA100 controller";
179 if (ata_find_dev(dev, 0x30741106, 0) ||
180 ata_find_dev(dev, 0x31091106, 0))
181 return "VIA 8233 ATA100 controller";
182 if (ata_find_dev(dev, 0x31471106, 0))
183 return "VIA 8233 ATA133 controller";
184 return "VIA Apollo ATA controller";
185
186 case 0x55131039:
187 if (ata_find_dev(dev, 0x06301039, 0x30) ||
188 ata_find_dev(dev, 0x06331039, 0) ||
189 ata_find_dev(dev, 0x06351039, 0) ||
190 ata_find_dev(dev, 0x06401039, 0) ||
191 ata_find_dev(dev, 0x06451039, 0) ||
192 ata_find_dev(dev, 0x06501039, 0) ||
193 ata_find_dev(dev, 0x07301039, 0) ||
194 ata_find_dev(dev, 0x07331039, 0) ||
195 ata_find_dev(dev, 0x07351039, 0) ||
196 ata_find_dev(dev, 0x07401039, 0) ||
197 ata_find_dev(dev, 0x07451039, 0) ||
198 ata_find_dev(dev, 0x07501039, 0))
199 return "SiS 5591 ATA100 controller";
200 else if (ata_find_dev(dev, 0x05301039, 0) ||
201 ata_find_dev(dev, 0x05401039, 0) ||
202 ata_find_dev(dev, 0x06201039, 0) ||
203 ata_find_dev(dev, 0x06301039, 0))
204 return "SiS 5591 ATA66 controller";
205 else
206 return "SiS 5591 ATA33 controller";
207
| 29 */
30
31#include "opt_ata.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/disk.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/bio.h>
39#include <sys/malloc.h>
40#include <sys/devicestat.h>
41#include <sys/sysctl.h>
42#include <machine/stdarg.h>
43#include <machine/resource.h>
44#include <machine/bus.h>
45#ifdef __alpha__
46#include <machine/md_var.h>
47#endif
48#include <sys/rman.h>
49#include <pci/pcivar.h>
50#include <pci/pcireg.h>
51#include <dev/ata/ata-all.h>
52
53/* device structures */
54struct ata_pci_controller {
55 struct resource *bmio;
56 int bmaddr;
57 struct resource *irq;
58 int irqcnt;
59};
60
61/* misc defines */
62#define IOMASK 0xfffffffc
63#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
64#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
65 (pci_get_progif(dev) & 0x05) != 0x05)
66
67int
68ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
69{
70 device_t *children;
71 int nchildren, i;
72
73 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 return 0;
75
76 for (i = 0; i < nchildren; i++) {
77 if (pci_get_devid(children[i]) == devid &&
78 pci_get_revid(children[i]) >= revid) {
79 free(children, M_TEMP);
80 return 1;
81 }
82 }
83 free(children, M_TEMP);
84 return 0;
85}
86
87static void
88ata_via_southbridge_fixup(device_t dev)
89{
90 device_t *children;
91 int nchildren, i;
92
93 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 return;
95
96 for (i = 0; i < nchildren; i++) {
97 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
98 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
99 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
100 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
101 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
102
103 if ((reg76 & 0xf0) != 0xd0) {
104 device_printf(dev,
105 "Correcting VIA config for southbridge data corruption bug\n");
106 pci_write_config(children[i], 0x75, 0x80, 1);
107 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
108 }
109 break;
110 }
111 }
112 free(children, M_TEMP);
113}
114
115static const char *
116ata_pci_match(device_t dev)
117{
118 if (pci_get_class(dev) != PCIC_STORAGE)
119 return NULL;
120
121 switch (pci_get_devid(dev)) {
122 /* supported chipsets */
123 case 0x12308086:
124 return "Intel PIIX ATA controller";
125
126 case 0x70108086:
127 return "Intel PIIX3 ATA controller";
128
129 case 0x71118086:
130 case 0x71998086:
131 case 0x84ca8086:
132 return "Intel PIIX4 ATA33 controller";
133
134 case 0x24218086:
135 return "Intel ICH0 ATA33 controller";
136
137 case 0x24118086:
138 case 0x76018086:
139 return "Intel ICH ATA66 controller";
140
141 case 0x244a8086:
142 case 0x244b8086:
143 return "Intel ICH2 ATA100 controller";
144
145 case 0x248a8086:
146 case 0x248b8086:
147 return "Intel ICH3 ATA100 controller";
148
149 case 0x24cb8086:
150 return "Intel ICH4 ATA100 controller";
151
152 case 0x522910b9:
153 if (pci_get_revid(dev) >= 0xc4)
154 return "AcerLabs Aladdin ATA100 controller";
155 else if (pci_get_revid(dev) >= 0xc2)
156 return "AcerLabs Aladdin ATA66 controller";
157 else if (pci_get_revid(dev) >= 0x20)
158 return "AcerLabs Aladdin ATA33 controller";
159 else
160 return "AcerLabs Aladdin ATA controller";
161
162 case 0x05711106:
163 if (ata_find_dev(dev, 0x05861106, 0x02))
164 return "VIA 82C586 ATA33 controller";
165 if (ata_find_dev(dev, 0x05861106, 0))
166 return "VIA 82C586 ATA controller";
167 if (ata_find_dev(dev, 0x05961106, 0x12))
168 return "VIA 82C596 ATA66 controller";
169 if (ata_find_dev(dev, 0x05961106, 0))
170 return "VIA 82C596 ATA33 controller";
171 if (ata_find_dev(dev, 0x06861106, 0x40))
172 return "VIA 82C686 ATA100 controller";
173 if (ata_find_dev(dev, 0x06861106, 0x10))
174 return "VIA 82C686 ATA66 controller";
175 if (ata_find_dev(dev, 0x06861106, 0))
176 return "VIA 82C686 ATA33 controller";
177 if (ata_find_dev(dev, 0x82311106, 0))
178 return "VIA 8231 ATA100 controller";
179 if (ata_find_dev(dev, 0x30741106, 0) ||
180 ata_find_dev(dev, 0x31091106, 0))
181 return "VIA 8233 ATA100 controller";
182 if (ata_find_dev(dev, 0x31471106, 0))
183 return "VIA 8233 ATA133 controller";
184 return "VIA Apollo ATA controller";
185
186 case 0x55131039:
187 if (ata_find_dev(dev, 0x06301039, 0x30) ||
188 ata_find_dev(dev, 0x06331039, 0) ||
189 ata_find_dev(dev, 0x06351039, 0) ||
190 ata_find_dev(dev, 0x06401039, 0) ||
191 ata_find_dev(dev, 0x06451039, 0) ||
192 ata_find_dev(dev, 0x06501039, 0) ||
193 ata_find_dev(dev, 0x07301039, 0) ||
194 ata_find_dev(dev, 0x07331039, 0) ||
195 ata_find_dev(dev, 0x07351039, 0) ||
196 ata_find_dev(dev, 0x07401039, 0) ||
197 ata_find_dev(dev, 0x07451039, 0) ||
198 ata_find_dev(dev, 0x07501039, 0))
199 return "SiS 5591 ATA100 controller";
200 else if (ata_find_dev(dev, 0x05301039, 0) ||
201 ata_find_dev(dev, 0x05401039, 0) ||
202 ata_find_dev(dev, 0x06201039, 0) ||
203 ata_find_dev(dev, 0x06301039, 0))
204 return "SiS 5591 ATA66 controller";
205 else
206 return "SiS 5591 ATA33 controller";
207
|
| 208 case 0x06801095:
209 return "Sil 0680 ATA133 controller";
210
|
208 case 0x06491095:
209 return "CMD 649 ATA100 controller";
210
211 case 0x06481095:
212 return "CMD 648 ATA66 controller";
213
214 case 0x06461095:
215 return "CMD 646 ATA controller";
216
217 case 0xc6931080:
218 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
219 return "Cypress 82C693 ATA controller";
220 return NULL;
221
222 case 0x01021078:
223 return "Cyrix 5530 ATA33 controller";
224
225 case 0x74091022:
226 return "AMD 756 ATA66 controller";
227
228 case 0x74111022:
229 return "AMD 766 ATA100 controller";
230
231 case 0x74411022:
232 return "AMD 768 ATA100 controller";
233
234 case 0x01bc10de:
235 return "nVIDIA nForce ATA100 controller";
236
237 case 0x02111166:
238 return "ServerWorks ROSB4 ATA33 controller";
239
240 case 0x02121166:
241 if (pci_get_revid(dev) >= 0x92)
242 return "ServerWorks CSB5 ATA100 controller";
243 else
244 return "ServerWorks CSB5 ATA66 controller";
245
246 case 0x4d33105a:
247 return "Promise ATA33 controller";
248
249 case 0x0d38105a:
250 case 0x4d38105a:
251 return "Promise ATA66 controller";
252
253 case 0x0d30105a:
254 case 0x4d30105a:
255 return "Promise ATA100 controller";
256
257 case 0x4d68105a:
258 case 0x6268105a:
259 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
260 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
261 static long start = 0, end = 0;
262
263 /* we belive we are on a TX4, now do our (simple) magic */
264 if (pci_get_slot(dev) == 1) {
265 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
266 return "Promise TX4 ATA100 controller (channel 0+1)";
267 }
268 else if (pci_get_slot(dev) == 2 && start && end) {
269 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
270 start = end = 0;
271 return "Promise TX4 ATA100 controller (channel 2+3)";
272 }
273 else
274 start = end = 0;
275 }
276 return "Promise TX2 ATA100 controller";
277
278 case 0x4d69105a:
279 case 0x5275105a:
280 case 0x6269105a:
281 return "Promise TX2 ATA133 controller";
282
283 case 0x00041103:
284 switch (pci_get_revid(dev)) {
285 case 0x00:
286 case 0x01:
287 return "HighPoint HPT366 ATA66 controller";
288 case 0x02:
289 return "HighPoint HPT368 ATA66 controller";
290 case 0x03:
291 case 0x04:
292 return "HighPoint HPT370 ATA100 controller";
293 case 0x05:
294 return "HighPoint HPT372 ATA133 controller";
295 }
296 return NULL;
297
298 case 0x00051103:
299 switch (pci_get_revid(dev)) {
300 case 0x01:
301 return "HighPoint HPT372 ATA133 controller";
302 }
303 return NULL;
304
305 case 0x00081103:
306 switch (pci_get_revid(dev)) {
307 case 0x07:
308 return "HighPoint HPT374 ATA133 controller";
309 }
310 return NULL;
311
312 case 0x000116ca:
313 return "Cenatek Rocket Drive controller";
314
315 /* unsupported but known chipsets, generic DMA only */
316 case 0x10001042:
317 case 0x10011042:
318 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
319
320 case 0x06401095:
321 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
322
323 /* unknown chipsets, try generic DMA if it seems possible */
324 default:
325 if (pci_get_class(dev) == PCIC_STORAGE &&
326 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
327 return "Generic PCI ATA controller";
328 }
329 return NULL;
330}
331
332static int
333ata_pci_probe(device_t dev)
334{
335 const char *desc = ata_pci_match(dev);
336
337 if (desc) {
338 device_set_desc(dev, desc);
339 return 0;
340 }
341 else
342 return ENXIO;
343}
344
345static int
346ata_pci_add_child(device_t dev, int unit)
347{
348 device_t child;
349
350 /* check if this is located at one of the std addresses */
351 if (ATA_MASTERDEV(dev)) {
352 if (!(child = device_add_child(dev, "ata", unit)))
353 return ENOMEM;
354 }
355 else {
356 if (!(child =
357 device_add_child(dev, "ata",
358 devclass_find_free_unit(ata_devclass, 2))))
359 return ENOMEM;
360 }
361 return 0;
362}
363
364static int
365ata_pci_attach(device_t dev)
366{
367 struct ata_pci_controller *controller = device_get_softc(dev);
368 u_int8_t class, subclass;
369 u_int32_t type, cmd;
370 int rid;
371
372 /* set up vendor-specific stuff */
373 type = pci_get_devid(dev);
374 class = pci_get_class(dev);
375 subclass = pci_get_subclass(dev);
376 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
377
378 if (!(cmd & PCIM_CMD_PORTEN)) {
379 device_printf(dev, "ATA channel disabled by BIOS\n");
380 return 0;
381 }
382
383#ifdef __sparc64__
384 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
385 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
386 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
387 }
388#endif
389 /* is busmastering supported ? */
390 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
391 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
392
393 /* is there a valid port range to connect to ? */
394 rid = 0x20;
395 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
396 0, ~0, 1, RF_ACTIVE);
397 if (!controller->bmio)
398 device_printf(dev, "Busmastering DMA not configured\n");
399 }
400 else
401 device_printf(dev, "Busmastering DMA not supported\n");
402
403 /* do extra chipset specific setups */
404 switch (type) {
405
406 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */
407 pci_write_config(dev, 0x53,
408 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
409 break;
410
411 case 0x0d30105a: /* Promise 66 & 100 (before TX2) need the clock changed */
412 case 0x4d30105a:
413 case 0x0d38105a:
414 case 0x4d38105a:
415 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
416 /* FALLTHROUGH */
417
418 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
419 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
420 break;
421
422 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */
423 if (pci_get_revid(dev) < 2) { /* HPT366 */
424 /* turn off interrupt prediction */
425 pci_write_config(dev, 0x51,
426 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
427 break;
428 }
429 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
430 /* turn off interrupt prediction */
431 pci_write_config(dev, 0x51,
432 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
433 pci_write_config(dev, 0x55,
434 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
435
436 /* turn on interrupts */
437 pci_write_config(dev, 0x5a,
438 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
439
440 /* set clocks etc */
441 pci_write_config(dev, 0x5b, 0x22, 1);
442 break;
443 }
444 /* FALLTHROUGH */
445
446 case 0x00051103: /* HighPoint HPT372 default setup */
447 case 0x00081103: /* HighPoint HPT374 default setup */
448 /* turn off interrupt prediction */
449 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
450 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
451
452 /* turn on interrupts */
453 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
454
455 /* set clocks etc */
456 pci_write_config(dev, 0x5b,
457 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
458 break;
459
460 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
461 /* prepare for ATA-66 on the 82C686a and 82C596b */
462 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
463 !ata_find_dev(dev, 0x06861106, 0x40)) ||
464 ata_find_dev(dev, 0x05961106, 0x12))
465 pci_write_config(dev, 0x50, 0x030b030b, 4);
466
467 /* the southbridge might need the data corruption fix */
468 if (ata_find_dev(dev, 0x06861106, 0x40) ||
469 ata_find_dev(dev, 0x82311106, 0x10))
470 ata_via_southbridge_fixup(dev);
471 /* FALLTHROUGH */
472
473 case 0x74091022: /* AMD 756 default setup */
474 case 0x74111022: /* AMD 766 default setup */
475 case 0x74411022: /* AMD 768 default setup */
476 case 0x01bc10de: /* nVIDIA nForce default setup */
477 /* set prefetch, postwrite */
478 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
479
480 /* set fifo configuration half'n'half */
481 pci_write_config(dev, 0x43,
482 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
483
484 /* set status register read retry */
485 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
486
487 /* set DMA read & end-of-sector fifo flush */
488 pci_write_config(dev, 0x46,
489 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
490
491 /* set sector size */
492 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
493 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
494 break;
495
496 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
497 pci_write_config(dev, 0x64,
498 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
499 0x00004000, 4);
500 break;
501
502 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
503 pci_write_config(dev, 0x5a,
504 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
505 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
506 break;
507
| 211 case 0x06491095:
212 return "CMD 649 ATA100 controller";
213
214 case 0x06481095:
215 return "CMD 648 ATA66 controller";
216
217 case 0x06461095:
218 return "CMD 646 ATA controller";
219
220 case 0xc6931080:
221 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
222 return "Cypress 82C693 ATA controller";
223 return NULL;
224
225 case 0x01021078:
226 return "Cyrix 5530 ATA33 controller";
227
228 case 0x74091022:
229 return "AMD 756 ATA66 controller";
230
231 case 0x74111022:
232 return "AMD 766 ATA100 controller";
233
234 case 0x74411022:
235 return "AMD 768 ATA100 controller";
236
237 case 0x01bc10de:
238 return "nVIDIA nForce ATA100 controller";
239
240 case 0x02111166:
241 return "ServerWorks ROSB4 ATA33 controller";
242
243 case 0x02121166:
244 if (pci_get_revid(dev) >= 0x92)
245 return "ServerWorks CSB5 ATA100 controller";
246 else
247 return "ServerWorks CSB5 ATA66 controller";
248
249 case 0x4d33105a:
250 return "Promise ATA33 controller";
251
252 case 0x0d38105a:
253 case 0x4d38105a:
254 return "Promise ATA66 controller";
255
256 case 0x0d30105a:
257 case 0x4d30105a:
258 return "Promise ATA100 controller";
259
260 case 0x4d68105a:
261 case 0x6268105a:
262 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
263 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
264 static long start = 0, end = 0;
265
266 /* we belive we are on a TX4, now do our (simple) magic */
267 if (pci_get_slot(dev) == 1) {
268 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
269 return "Promise TX4 ATA100 controller (channel 0+1)";
270 }
271 else if (pci_get_slot(dev) == 2 && start && end) {
272 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
273 start = end = 0;
274 return "Promise TX4 ATA100 controller (channel 2+3)";
275 }
276 else
277 start = end = 0;
278 }
279 return "Promise TX2 ATA100 controller";
280
281 case 0x4d69105a:
282 case 0x5275105a:
283 case 0x6269105a:
284 return "Promise TX2 ATA133 controller";
285
286 case 0x00041103:
287 switch (pci_get_revid(dev)) {
288 case 0x00:
289 case 0x01:
290 return "HighPoint HPT366 ATA66 controller";
291 case 0x02:
292 return "HighPoint HPT368 ATA66 controller";
293 case 0x03:
294 case 0x04:
295 return "HighPoint HPT370 ATA100 controller";
296 case 0x05:
297 return "HighPoint HPT372 ATA133 controller";
298 }
299 return NULL;
300
301 case 0x00051103:
302 switch (pci_get_revid(dev)) {
303 case 0x01:
304 return "HighPoint HPT372 ATA133 controller";
305 }
306 return NULL;
307
308 case 0x00081103:
309 switch (pci_get_revid(dev)) {
310 case 0x07:
311 return "HighPoint HPT374 ATA133 controller";
312 }
313 return NULL;
314
315 case 0x000116ca:
316 return "Cenatek Rocket Drive controller";
317
318 /* unsupported but known chipsets, generic DMA only */
319 case 0x10001042:
320 case 0x10011042:
321 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
322
323 case 0x06401095:
324 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
325
326 /* unknown chipsets, try generic DMA if it seems possible */
327 default:
328 if (pci_get_class(dev) == PCIC_STORAGE &&
329 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
330 return "Generic PCI ATA controller";
331 }
332 return NULL;
333}
334
335static int
336ata_pci_probe(device_t dev)
337{
338 const char *desc = ata_pci_match(dev);
339
340 if (desc) {
341 device_set_desc(dev, desc);
342 return 0;
343 }
344 else
345 return ENXIO;
346}
347
348static int
349ata_pci_add_child(device_t dev, int unit)
350{
351 device_t child;
352
353 /* check if this is located at one of the std addresses */
354 if (ATA_MASTERDEV(dev)) {
355 if (!(child = device_add_child(dev, "ata", unit)))
356 return ENOMEM;
357 }
358 else {
359 if (!(child =
360 device_add_child(dev, "ata",
361 devclass_find_free_unit(ata_devclass, 2))))
362 return ENOMEM;
363 }
364 return 0;
365}
366
367static int
368ata_pci_attach(device_t dev)
369{
370 struct ata_pci_controller *controller = device_get_softc(dev);
371 u_int8_t class, subclass;
372 u_int32_t type, cmd;
373 int rid;
374
375 /* set up vendor-specific stuff */
376 type = pci_get_devid(dev);
377 class = pci_get_class(dev);
378 subclass = pci_get_subclass(dev);
379 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
380
381 if (!(cmd & PCIM_CMD_PORTEN)) {
382 device_printf(dev, "ATA channel disabled by BIOS\n");
383 return 0;
384 }
385
386#ifdef __sparc64__
387 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
388 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
389 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
390 }
391#endif
392 /* is busmastering supported ? */
393 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
394 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
395
396 /* is there a valid port range to connect to ? */
397 rid = 0x20;
398 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
399 0, ~0, 1, RF_ACTIVE);
400 if (!controller->bmio)
401 device_printf(dev, "Busmastering DMA not configured\n");
402 }
403 else
404 device_printf(dev, "Busmastering DMA not supported\n");
405
406 /* do extra chipset specific setups */
407 switch (type) {
408
409 case 0x522910b9: /* AcerLabs Aladdin need to activate the ATAPI FIFO */
410 pci_write_config(dev, 0x53,
411 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
412 break;
413
414 case 0x0d30105a: /* Promise 66 & 100 (before TX2) need the clock changed */
415 case 0x4d30105a:
416 case 0x0d38105a:
417 case 0x4d38105a:
418 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
419 /* FALLTHROUGH */
420
421 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
422 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
423 break;
424
425 case 0x00041103: /* HighPoint HPT366/368/370/372 default setup */
426 if (pci_get_revid(dev) < 2) { /* HPT366 */
427 /* turn off interrupt prediction */
428 pci_write_config(dev, 0x51,
429 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
430 break;
431 }
432 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
433 /* turn off interrupt prediction */
434 pci_write_config(dev, 0x51,
435 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
436 pci_write_config(dev, 0x55,
437 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
438
439 /* turn on interrupts */
440 pci_write_config(dev, 0x5a,
441 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
442
443 /* set clocks etc */
444 pci_write_config(dev, 0x5b, 0x22, 1);
445 break;
446 }
447 /* FALLTHROUGH */
448
449 case 0x00051103: /* HighPoint HPT372 default setup */
450 case 0x00081103: /* HighPoint HPT374 default setup */
451 /* turn off interrupt prediction */
452 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
453 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
454
455 /* turn on interrupts */
456 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
457
458 /* set clocks etc */
459 pci_write_config(dev, 0x5b,
460 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
461 break;
462
463 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
464 /* prepare for ATA-66 on the 82C686a and 82C596b */
465 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
466 !ata_find_dev(dev, 0x06861106, 0x40)) ||
467 ata_find_dev(dev, 0x05961106, 0x12))
468 pci_write_config(dev, 0x50, 0x030b030b, 4);
469
470 /* the southbridge might need the data corruption fix */
471 if (ata_find_dev(dev, 0x06861106, 0x40) ||
472 ata_find_dev(dev, 0x82311106, 0x10))
473 ata_via_southbridge_fixup(dev);
474 /* FALLTHROUGH */
475
476 case 0x74091022: /* AMD 756 default setup */
477 case 0x74111022: /* AMD 766 default setup */
478 case 0x74411022: /* AMD 768 default setup */
479 case 0x01bc10de: /* nVIDIA nForce default setup */
480 /* set prefetch, postwrite */
481 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
482
483 /* set fifo configuration half'n'half */
484 pci_write_config(dev, 0x43,
485 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
486
487 /* set status register read retry */
488 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
489
490 /* set DMA read & end-of-sector fifo flush */
491 pci_write_config(dev, 0x46,
492 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
493
494 /* set sector size */
495 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
496 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
497 break;
498
499 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
500 pci_write_config(dev, 0x64,
501 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
502 0x00004000, 4);
503 break;
504
505 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
506 pci_write_config(dev, 0x5a,
507 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
508 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
509 break;
510
|
| 511 case 0x06801095: /* Sil 0680 set ATA reference clock speed */
512 if (pci_read_config(dev, 0x8a, 1) != 0x10)
513 pci_write_config(dev, 0x8a,
514 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
515 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
516 device_printf(dev, "Sil 0680 could not set clock\n");
517 break;
518
|
508 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
509 pci_write_config(dev, 0x71, 0x01, 1);
510 break;
511
512 case 0x10001042: /* RZ 100? known bad, no DMA */
513 case 0x10011042:
514 case 0x06401095: /* CMD 640 known bad, no DMA */
515 controller->bmio = NULL;
516 device_printf(dev, "Busmastering DMA disabled\n");
517 }
518
519 if (controller->bmio) {
520 controller->bmaddr = rman_get_start(controller->bmio);
521 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
522 SYS_RES_IOPORT, rid, controller->bmio);
523 controller->bmio = NULL;
524 }
525
526 /*
527 * the Cypress chip is a mess, it contains two ATA functions, but
528 * both channels are visible on the first one.
529 * simply ignore the second function for now, as the right
530 * solution (ignoring the second channel on the first function)
531 * doesn't work with the crappy ATA interrupt setup on the alpha.
532 */
533 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
534 return 0;
535
536 ata_pci_add_child(dev, 0);
537
538 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
539 ata_pci_add_child(dev, 1);
540
541 return bus_generic_attach(dev);
542}
543
544static int
545ata_pci_intr(struct ata_channel *ch)
546{
547 u_int8_t dmastat;
548
549 /*
550 * since we might share the IRQ with another device, and in some
551 * cases with our twin channel, we only want to process interrupts
552 * that we know this channel generated.
553 */
554 switch (ch->chiptype) {
555 case 0x00041103: /* HighPoint HPT366/368/370/372 */
556 case 0x00051103: /* HighPoint HPT372 */
557 case 0x00081103: /* HighPoint HPT374 */
558 if (((dmastat = ata_dmastatus(ch)) &
559 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
560 return 1;
561 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
562 DELAY(1);
563 return 0;
564
565 case 0x06481095: /* CMD 648 */
566 case 0x06491095: /* CMD 649 */
567 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
568 (ch->unit ? 0x08 : 0x04)))
569 return 1;
570 break;
571
572 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
573 case 0x0d38105a: /* Promise Fasttrak 66 */
574 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
575 case 0x0d30105a: /* Promise OEM ATA100 */
576 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
577 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
578 (ch->unit ? 0x00004000 : 0x00000400)))
579 return 1;
580 break;
581
582 case 0x4d68105a: /* Promise TX2 ATA100 */
583 case 0x6268105a: /* Promise TX2 ATA100 */
584 case 0x4d69105a: /* Promise TX2 ATA133 */
585 case 0x5275105a: /* Promise TX2 ATA133 */
586 case 0x6269105a: /* Promise TX2 ATA133 */
587 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
588 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
589 return 1;
590 break;
591 }
592
593 if (ch->flags & ATA_DMA_ACTIVE) {
594 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
595 return 1;
596 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
597 DELAY(1);
598 }
599 return 0;
600}
601
602static int
603ata_pci_print_child(device_t dev, device_t child)
604{
605 struct ata_channel *ch = device_get_softc(child);
606 int retval = 0;
607
608 retval += bus_print_child_header(dev, child);
609 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
610
611 if (ATA_MASTERDEV(dev))
612 retval += printf(" irq %d", 14 + ch->unit);
613
614 retval += bus_print_child_footer(dev, child);
615
616 return retval;
617}
618
619static struct resource *
620ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
621 u_long start, u_long end, u_long count, u_int flags)
622{
623 struct ata_pci_controller *controller = device_get_softc(dev);
624 struct resource *res = NULL;
625 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
626 int myrid;
627
628 if (type == SYS_RES_IOPORT) {
629 switch (*rid) {
630 case ATA_IOADDR_RID:
631 if (ATA_MASTERDEV(dev)) {
632 myrid = 0;
633 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
634 end = start + ATA_IOSIZE - 1;
635 count = ATA_IOSIZE;
636 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
637 SYS_RES_IOPORT, &myrid,
638 start, end, count, flags);
639 }
640 else {
641 myrid = 0x10 + 8 * unit;
642 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
643 SYS_RES_IOPORT, &myrid,
644 start, end, count, flags);
645 }
646 break;
647
648 case ATA_ALTADDR_RID:
649 if (ATA_MASTERDEV(dev)) {
650 myrid = 0;
651 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
652 end = start + ATA_ALTIOSIZE - 1;
653 count = ATA_ALTIOSIZE;
654 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
655 SYS_RES_IOPORT, &myrid,
656 start, end, count, flags);
657 }
658 else {
659 myrid = 0x14 + 8 * unit;
660 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
661 SYS_RES_IOPORT, &myrid,
662 start, end, count, flags);
663 if (res) {
664 start = rman_get_start(res) + 2;
665 end = start + ATA_ALTIOSIZE - 1;
666 count = ATA_ALTIOSIZE;
667 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
668 SYS_RES_IOPORT, myrid, res);
669 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
670 SYS_RES_IOPORT, &myrid,
671 start, end, count, flags);
672 }
673 }
674 break;
675
676 case ATA_BMADDR_RID:
677 if (controller->bmaddr) {
678 myrid = 0x20;
679 start = (unit == 0 ?
680 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
681 end = start + ATA_BMIOSIZE - 1;
682 count = ATA_BMIOSIZE;
683 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
684 SYS_RES_IOPORT, &myrid,
685 start, end, count, flags);
686 }
687 }
688 return res;
689 }
690
691 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
692 if (ATA_MASTERDEV(dev)) {
693#ifdef __alpha__
694 return alpha_platform_alloc_ide_intr(unit);
695#else
696 int irq = (unit == 0 ? 14 : 15);
697
698 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
699 SYS_RES_IRQ, rid, irq, irq, 1, flags);
700#endif
701 }
702 else {
703 /* primary and secondary channels share interrupt, keep track */
704 if (!controller->irq)
705 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
706 dev, SYS_RES_IRQ,
707 rid, 0, ~0, 1, flags);
708 controller->irqcnt++;
709 return controller->irq;
710 }
711 }
712 return 0;
713}
714
715static int
716ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
717 struct resource *r)
718{
719 struct ata_pci_controller *controller = device_get_softc(dev);
720 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
721
722 if (type == SYS_RES_IOPORT) {
723 switch (rid) {
724 case ATA_IOADDR_RID:
725 if (ATA_MASTERDEV(dev))
726 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
727 SYS_RES_IOPORT, 0x0, r);
728 else
729 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
730 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
731 break;
732
733 case ATA_ALTADDR_RID:
734 if (ATA_MASTERDEV(dev))
735 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
736 SYS_RES_IOPORT, 0x0, r);
737 else
738 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
739 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
740 break;
741
742 case ATA_BMADDR_RID:
743 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
744 SYS_RES_IOPORT, 0x20, r);
745 default:
746 return ENOENT;
747 }
748 }
749 if (type == SYS_RES_IRQ) {
750 if (rid != ATA_IRQ_RID)
751 return ENOENT;
752
753 if (ATA_MASTERDEV(dev)) {
754#ifdef __alpha__
755 return alpha_platform_release_ide_intr(unit, r);
756#else
757 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
758 SYS_RES_IRQ, rid, r);
759#endif
760 }
761 else {
762 /* primary and secondary channels share interrupt, keep track */
763 if (--controller->irqcnt)
764 return 0;
765 controller->irq = NULL;
766 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
767 SYS_RES_IRQ, rid, r);
768 }
769 }
770 return EINVAL;
771}
772
773static int
774ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
775 int flags, driver_intr_t *intr, void *arg,
776 void **cookiep)
777{
778 if (ATA_MASTERDEV(dev)) {
779#ifdef __alpha__
780 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
781#else
782 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
783 flags, intr, arg, cookiep);
784#endif
785 }
786 else
787 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
788 flags, intr, arg, cookiep);
789}
790
791static int
792ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
793 void *cookie)
794{
795 if (ATA_MASTERDEV(dev)) {
796#ifdef __alpha__
797 return alpha_platform_teardown_ide_intr(child, irq, cookie);
798#else
799 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
800#endif
801 }
802 else
803 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
804}
805
806static device_method_t ata_pci_methods[] = {
807 /* device interface */
808 DEVMETHOD(device_probe, ata_pci_probe),
809 DEVMETHOD(device_attach, ata_pci_attach),
810 DEVMETHOD(device_shutdown, bus_generic_shutdown),
811 DEVMETHOD(device_suspend, bus_generic_suspend),
812 DEVMETHOD(device_resume, bus_generic_resume),
813
814 /* bus methods */
815 DEVMETHOD(bus_print_child, ata_pci_print_child),
816 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
817 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
818 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
819 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
820 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
821 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
822 { 0, 0 }
823};
824
825static driver_t ata_pci_driver = {
826 "atapci",
827 ata_pci_methods,
828 sizeof(struct ata_pci_controller),
829};
830
831static devclass_t ata_pci_devclass;
832
833DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
834
835static int
836ata_pcisub_probe(device_t dev)
837{
838 struct ata_channel *ch = device_get_softc(dev);
839 device_t *children;
840 int count, i;
841
842 /* find channel number on this controller */
843 device_get_children(device_get_parent(dev), &children, &count);
844 for (i = 0; i < count; i++) {
845 if (children[i] == dev)
846 ch->unit = i;
847 }
848 free(children, M_TEMP);
849 ch->chiptype = pci_get_devid(device_get_parent(dev));
850 ch->intr_func = ata_pci_intr;
851 return ata_probe(dev);
852}
853
854static device_method_t ata_pcisub_methods[] = {
855 /* device interface */
856 DEVMETHOD(device_probe, ata_pcisub_probe),
857 DEVMETHOD(device_attach, ata_attach),
858 DEVMETHOD(device_detach, ata_detach),
859 DEVMETHOD(device_resume, ata_resume),
860 { 0, 0 }
861};
862
863static driver_t ata_pcisub_driver = {
864 "ata",
865 ata_pcisub_methods,
866 sizeof(struct ata_channel),
867};
868
869DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
| 519 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
520 pci_write_config(dev, 0x71, 0x01, 1);
521 break;
522
523 case 0x10001042: /* RZ 100? known bad, no DMA */
524 case 0x10011042:
525 case 0x06401095: /* CMD 640 known bad, no DMA */
526 controller->bmio = NULL;
527 device_printf(dev, "Busmastering DMA disabled\n");
528 }
529
530 if (controller->bmio) {
531 controller->bmaddr = rman_get_start(controller->bmio);
532 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
533 SYS_RES_IOPORT, rid, controller->bmio);
534 controller->bmio = NULL;
535 }
536
537 /*
538 * the Cypress chip is a mess, it contains two ATA functions, but
539 * both channels are visible on the first one.
540 * simply ignore the second function for now, as the right
541 * solution (ignoring the second channel on the first function)
542 * doesn't work with the crappy ATA interrupt setup on the alpha.
543 */
544 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
545 return 0;
546
547 ata_pci_add_child(dev, 0);
548
549 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
550 ata_pci_add_child(dev, 1);
551
552 return bus_generic_attach(dev);
553}
554
555static int
556ata_pci_intr(struct ata_channel *ch)
557{
558 u_int8_t dmastat;
559
560 /*
561 * since we might share the IRQ with another device, and in some
562 * cases with our twin channel, we only want to process interrupts
563 * that we know this channel generated.
564 */
565 switch (ch->chiptype) {
566 case 0x00041103: /* HighPoint HPT366/368/370/372 */
567 case 0x00051103: /* HighPoint HPT372 */
568 case 0x00081103: /* HighPoint HPT374 */
569 if (((dmastat = ata_dmastatus(ch)) &
570 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
571 return 1;
572 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
573 DELAY(1);
574 return 0;
575
576 case 0x06481095: /* CMD 648 */
577 case 0x06491095: /* CMD 649 */
578 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
579 (ch->unit ? 0x08 : 0x04)))
580 return 1;
581 break;
582
583 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
584 case 0x0d38105a: /* Promise Fasttrak 66 */
585 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
586 case 0x0d30105a: /* Promise OEM ATA100 */
587 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
588 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
589 (ch->unit ? 0x00004000 : 0x00000400)))
590 return 1;
591 break;
592
593 case 0x4d68105a: /* Promise TX2 ATA100 */
594 case 0x6268105a: /* Promise TX2 ATA100 */
595 case 0x4d69105a: /* Promise TX2 ATA133 */
596 case 0x5275105a: /* Promise TX2 ATA133 */
597 case 0x6269105a: /* Promise TX2 ATA133 */
598 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
599 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
600 return 1;
601 break;
602 }
603
604 if (ch->flags & ATA_DMA_ACTIVE) {
605 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
606 return 1;
607 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
608 DELAY(1);
609 }
610 return 0;
611}
612
613static int
614ata_pci_print_child(device_t dev, device_t child)
615{
616 struct ata_channel *ch = device_get_softc(child);
617 int retval = 0;
618
619 retval += bus_print_child_header(dev, child);
620 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
621
622 if (ATA_MASTERDEV(dev))
623 retval += printf(" irq %d", 14 + ch->unit);
624
625 retval += bus_print_child_footer(dev, child);
626
627 return retval;
628}
629
630static struct resource *
631ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
632 u_long start, u_long end, u_long count, u_int flags)
633{
634 struct ata_pci_controller *controller = device_get_softc(dev);
635 struct resource *res = NULL;
636 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
637 int myrid;
638
639 if (type == SYS_RES_IOPORT) {
640 switch (*rid) {
641 case ATA_IOADDR_RID:
642 if (ATA_MASTERDEV(dev)) {
643 myrid = 0;
644 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
645 end = start + ATA_IOSIZE - 1;
646 count = ATA_IOSIZE;
647 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
648 SYS_RES_IOPORT, &myrid,
649 start, end, count, flags);
650 }
651 else {
652 myrid = 0x10 + 8 * unit;
653 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
654 SYS_RES_IOPORT, &myrid,
655 start, end, count, flags);
656 }
657 break;
658
659 case ATA_ALTADDR_RID:
660 if (ATA_MASTERDEV(dev)) {
661 myrid = 0;
662 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
663 end = start + ATA_ALTIOSIZE - 1;
664 count = ATA_ALTIOSIZE;
665 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
666 SYS_RES_IOPORT, &myrid,
667 start, end, count, flags);
668 }
669 else {
670 myrid = 0x14 + 8 * unit;
671 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
672 SYS_RES_IOPORT, &myrid,
673 start, end, count, flags);
674 if (res) {
675 start = rman_get_start(res) + 2;
676 end = start + ATA_ALTIOSIZE - 1;
677 count = ATA_ALTIOSIZE;
678 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
679 SYS_RES_IOPORT, myrid, res);
680 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
681 SYS_RES_IOPORT, &myrid,
682 start, end, count, flags);
683 }
684 }
685 break;
686
687 case ATA_BMADDR_RID:
688 if (controller->bmaddr) {
689 myrid = 0x20;
690 start = (unit == 0 ?
691 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
692 end = start + ATA_BMIOSIZE - 1;
693 count = ATA_BMIOSIZE;
694 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
695 SYS_RES_IOPORT, &myrid,
696 start, end, count, flags);
697 }
698 }
699 return res;
700 }
701
702 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
703 if (ATA_MASTERDEV(dev)) {
704#ifdef __alpha__
705 return alpha_platform_alloc_ide_intr(unit);
706#else
707 int irq = (unit == 0 ? 14 : 15);
708
709 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
710 SYS_RES_IRQ, rid, irq, irq, 1, flags);
711#endif
712 }
713 else {
714 /* primary and secondary channels share interrupt, keep track */
715 if (!controller->irq)
716 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
717 dev, SYS_RES_IRQ,
718 rid, 0, ~0, 1, flags);
719 controller->irqcnt++;
720 return controller->irq;
721 }
722 }
723 return 0;
724}
725
726static int
727ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
728 struct resource *r)
729{
730 struct ata_pci_controller *controller = device_get_softc(dev);
731 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
732
733 if (type == SYS_RES_IOPORT) {
734 switch (rid) {
735 case ATA_IOADDR_RID:
736 if (ATA_MASTERDEV(dev))
737 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
738 SYS_RES_IOPORT, 0x0, r);
739 else
740 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
741 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
742 break;
743
744 case ATA_ALTADDR_RID:
745 if (ATA_MASTERDEV(dev))
746 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
747 SYS_RES_IOPORT, 0x0, r);
748 else
749 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
750 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
751 break;
752
753 case ATA_BMADDR_RID:
754 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
755 SYS_RES_IOPORT, 0x20, r);
756 default:
757 return ENOENT;
758 }
759 }
760 if (type == SYS_RES_IRQ) {
761 if (rid != ATA_IRQ_RID)
762 return ENOENT;
763
764 if (ATA_MASTERDEV(dev)) {
765#ifdef __alpha__
766 return alpha_platform_release_ide_intr(unit, r);
767#else
768 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
769 SYS_RES_IRQ, rid, r);
770#endif
771 }
772 else {
773 /* primary and secondary channels share interrupt, keep track */
774 if (--controller->irqcnt)
775 return 0;
776 controller->irq = NULL;
777 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
778 SYS_RES_IRQ, rid, r);
779 }
780 }
781 return EINVAL;
782}
783
784static int
785ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
786 int flags, driver_intr_t *intr, void *arg,
787 void **cookiep)
788{
789 if (ATA_MASTERDEV(dev)) {
790#ifdef __alpha__
791 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
792#else
793 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
794 flags, intr, arg, cookiep);
795#endif
796 }
797 else
798 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
799 flags, intr, arg, cookiep);
800}
801
802static int
803ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
804 void *cookie)
805{
806 if (ATA_MASTERDEV(dev)) {
807#ifdef __alpha__
808 return alpha_platform_teardown_ide_intr(child, irq, cookie);
809#else
810 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
811#endif
812 }
813 else
814 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
815}
816
817static device_method_t ata_pci_methods[] = {
818 /* device interface */
819 DEVMETHOD(device_probe, ata_pci_probe),
820 DEVMETHOD(device_attach, ata_pci_attach),
821 DEVMETHOD(device_shutdown, bus_generic_shutdown),
822 DEVMETHOD(device_suspend, bus_generic_suspend),
823 DEVMETHOD(device_resume, bus_generic_resume),
824
825 /* bus methods */
826 DEVMETHOD(bus_print_child, ata_pci_print_child),
827 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
828 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
829 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
830 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
831 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
832 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
833 { 0, 0 }
834};
835
836static driver_t ata_pci_driver = {
837 "atapci",
838 ata_pci_methods,
839 sizeof(struct ata_pci_controller),
840};
841
842static devclass_t ata_pci_devclass;
843
844DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
845
846static int
847ata_pcisub_probe(device_t dev)
848{
849 struct ata_channel *ch = device_get_softc(dev);
850 device_t *children;
851 int count, i;
852
853 /* find channel number on this controller */
854 device_get_children(device_get_parent(dev), &children, &count);
855 for (i = 0; i < count; i++) {
856 if (children[i] == dev)
857 ch->unit = i;
858 }
859 free(children, M_TEMP);
860 ch->chiptype = pci_get_devid(device_get_parent(dev));
861 ch->intr_func = ata_pci_intr;
862 return ata_probe(dev);
863}
864
865static device_method_t ata_pcisub_methods[] = {
866 /* device interface */
867 DEVMETHOD(device_probe, ata_pcisub_probe),
868 DEVMETHOD(device_attach, ata_attach),
869 DEVMETHOD(device_detach, ata_detach),
870 DEVMETHOD(device_resume, ata_resume),
871 { 0, 0 }
872};
873
874static driver_t ata_pcisub_driver = {
875 "ata",
876 ata_pcisub_methods,
877 sizeof(struct ata_channel),
878};
879
880DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
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