1/*-
|
2 * Copyright (c) 1998 - 2003 S�ren Schmidt <sos@FreeBSD.org>
|
| 2 * Copyright (c) 1998 - 2004 S�ren Schmidt <sos@FreeBSD.org> |
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
|
30__FBSDID("$FreeBSD: head/sys/dev/ata/ata-lowlevel.c 123421 2003-12-10 23:06:24Z sos $");
|
| 30__FBSDID("$FreeBSD: head/sys/dev/ata/ata-lowlevel.c 124403 2004-01-11 22:08:34Z sos $"); |
31
32#include "opt_ata.h"
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/ata.h>
36#include <sys/kernel.h>
37#include <sys/conf.h>
38#include <sys/bus.h>
|
39#include <sys/mutex.h>
|
| 39#include <sys/sema.h> |
40#include <sys/taskqueue.h>
41#include <machine/bus.h>
42#include <sys/rman.h>
43#include <dev/ata/ata-all.h>
44
45/* prototypes */
46static int ata_transaction(struct ata_request *);
47static void ata_interrupt(void *);
48static void ata_reset(struct ata_channel *);
49static int ata_wait(struct ata_device *, u_int8_t);
50static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);
51static void ata_pio_read(struct ata_request *, int);
52static void ata_pio_write(struct ata_request *, int);
53
54/* local vars */
55static int atadebug = 0;
56
57/*
58 * low level ATA functions
59 */
60void
61ata_generic_hw(struct ata_channel *ch)
62{
63 ch->hw.reset = ata_reset;
64 ch->hw.transaction = ata_transaction;
65 ch->hw.interrupt = ata_interrupt;
66}
67
68/* must be called with ATA channel locked */
69static int
70ata_transaction(struct ata_request *request)
71{
|
72 /* safety check, device might have been detached FIXME SOS */
73 if (!request->device->param) {
74 request->result = ENXIO;
75 return ATA_OP_FINISHED;
76 }
77 |
78 /* record the request as running */
79 request->device->channel->running = request;
80
|
81 ATA_DEBUG_RQ(request, "transaction");
82 |
83 /* disable ATAPI DMA writes if HW doesn't support it */
84 if ((request->device->channel->flags & ATA_ATAPI_DMA_RO) &&
85 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
86 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
87 request->flags &= ~ATA_R_DMA;
88
89 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
90
91 /* ATA PIO data transfer and control commands */
92 default:
93 {
|
86 /* record command direction here as our request might be done later */
|
| 94 /* record command direction here as our request might be gone later */ |
95 int write = (request->flags & ATA_R_WRITE);
96
97 /* issue command */
98 if (ata_command(request->device, request->u.ata.command,
99 request->u.ata.lba, request->u.ata.count,
100 request->u.ata.feature)) {
101 ata_prtdev(request->device, "error issueing PIO command\n");
102 request->result = EIO;
103 break;
104 }
105
106 /* if write command output the data */
107 if (write) {
108 if (ata_wait(request->device,
109 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
110 ata_prtdev(request->device,"timeout waiting for write DRQ");
111 request->result = EIO;
112 break;
113 }
114 ata_pio_write(request, request->transfersize);
115 }
116 }
|
| 117 |
118 /* return and wait for interrupt */
119 return ATA_OP_CONTINUES;
120
121 /* ATA DMA data transfer commands */
122 case ATA_R_DMA:
123 /* check sanity, setup SG list and DMA engine */
124 if (request->device->channel->dma->load(request->device,
125 request->data,
126 request->bytecount,
127 request->flags & ATA_R_READ)) {
128 ata_prtdev(request->device, "setting up DMA failed\n");
129 request->result = EIO;
130 break;
131 }
132
133 /* issue command */
134 if (ata_command(request->device, request->u.ata.command,
135 request->u.ata.lba, request->u.ata.count,
136 request->u.ata.feature)) {
137 ata_prtdev(request->device, "error issuing DMA command\n");
138 request->result = EIO;
139 break;
140 }
141
142 /* start DMA engine */
143 if (request->device->channel->dma->start(request->device->channel)) {
144 ata_prtdev(request->device, "error starting DMA\n");
145 request->result = EIO;
146 break;
147 }
|
| 148 |
149 /* return and wait for interrupt */
150 return ATA_OP_CONTINUES;
151
152 /* ATAPI PIO commands */
153 case ATA_R_ATAPI:
154 /* is this just a POLL DSC command ? */
155 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
156 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
157 ATA_D_IBM | request->device->unit);
158 DELAY(10);
159 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
160 request->result = EBUSY;
161 break;
162 }
163
164 /* start ATAPI operation */
165 if (ata_command(request->device, ATA_PACKET_CMD,
166 request->transfersize << 8, 0, 0)) {
167 ata_prtdev(request->device, "error issuing ATA PACKET command\n");
168 request->result = EIO;
169 break;
170 }
171
172 /* command interrupt device ? just return and wait for interrupt */
173 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
174 return ATA_OP_CONTINUES;
175
176 /* wait for ready to write ATAPI command block */
177 {
178 int timeout = 5000; /* might be less for fast devices */
179 while (timeout--) {
180 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
181 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
182
183 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
184 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
185 break;
186 DELAY(20);
187 }
188 if (timeout <= 0) {
189 ata_prtdev(request->device,
190 "timeout waiting for ATAPI ready\n");
191 request->result = EIO;
192 break;
193 }
194 }
195
196 /* this seems to be needed for some (slow) devices */
197 DELAY(10);
198
199 /* output actual command block */
200 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
201 (int16_t *)request->u.atapi.ccb,
202 (request->device->param->config & ATA_PROTO_MASK) ==
203 ATA_PROTO_ATAPI_12 ? 6 : 8);
204
205 /* return and wait for interrupt */
206 return ATA_OP_CONTINUES;
207
208 case ATA_R_ATAPI|ATA_R_DMA:
209 /* is this just a POLL DSC command ? */
210 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
211 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
212 ATA_D_IBM | request->device->unit);
213 DELAY(10);
214 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
215 request->result = EBUSY;
216 break;
217 }
218
219 /* check sanity, setup SG list and DMA engine */
220 if (request->device->channel->dma->load(request->device,
221 request->data,
222 request->bytecount,
223 request->flags & ATA_R_READ)) {
224 ata_prtdev(request->device, "setting up DMA failed\n");
225 request->result = EIO;
226 break;
227 }
228
229 /* start ATAPI operation */
230 if (ata_command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) {
231 ata_prtdev(request->device, "error issuing ATAPI packet command\n");
232 request->result = EIO;
233 break;
234 }
235
236 /* wait for ready to write ATAPI command block */
237 {
238 int timeout = 5000; /* might be less for fast devices */
239 while (timeout--) {
240 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
241 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
242
243 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
244 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
245 break;
246 DELAY(20);
247 }
248 if (timeout <= 0) {
249 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n");
250 request->result = EIO;
251 break;
252 }
253 }
254
255 /* this seems to be needed for some (slow) devices */
256 DELAY(10);
257
258 /* output actual command block */
259 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
260 (int16_t *)request->u.atapi.ccb,
261 (request->device->param->config & ATA_PROTO_MASK) ==
262 ATA_PROTO_ATAPI_12 ? 6 : 8);
263
264 /* start DMA engine */
265 if (request->device->channel->dma->start(request->device->channel)) {
266 request->result = EIO;
267 break;
268 }
269
270 /* return and wait for interrupt */
271 return ATA_OP_CONTINUES;
272 }
273
274 /* request finish here */
275 if (request->device->channel->dma->flags & ATA_DMA_ACTIVE)
276 request->device->channel->dma->unload(request->device->channel);
277 request->device->channel->running = NULL;
278 return ATA_OP_FINISHED;
279}
280
281static void
282ata_interrupt(void *data)
283{
284 struct ata_channel *ch = (struct ata_channel *)data;
285 struct ata_request *request = ch->running;
286 int length;
287
288 /* ignore this interrupt if there is no running request */
289 if (!request) {
290 if (ATA_LOCK_CH(ch, ATA_CONTROL)) {
291 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
292 u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR);
293
294 if (bootverbose)
295 ata_printf(ch, -1,
296 "spurious interrupt - status=0x%02x error=0x%02x\n",
297 status, error);
298 ATA_UNLOCK_CH(ch);
299 }
300 else {
301 if (bootverbose)
302 ata_printf(ch, -1, "spurious interrupt - channel busy\n");
303 }
304 return;
305 }
306
|
307 ATA_DEBUG_RQ(request, "interrupt");
308 |
309 /* ignore interrupt if device is busy */
|
298 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
|
310 if (!(request->flags & ATA_R_TIMEOUT) &&
311 ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { |
312 DELAY(100);
313 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ))
314 return;
315 }
316
|
317 ATA_DEBUG_RQ(request, "interrupt accepted");
318 |
319 /* clear interrupt and get status */
320 request->status = ATA_IDX_INB(ch, ATA_STATUS);
321
|
322 request->flags |= ATA_R_INTR_SEEN;
323 |
324 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
325
326 /* ATA PIO data transfer and control commands */
327 default:
328
329 /* on control commands read back registers to the request struct */
330 if (request->flags & ATA_R_CONTROL) {
331 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
332 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
333 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
334 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16);
335 }
336
337 /* if we got an error we are done with the HW */
338 if (request->status & ATA_S_ERROR) {
339 request->error = ATA_IDX_INB(ch, ATA_ERROR);
340 break;
341 }
342
343 /* are we moving data ? */
344 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
345
346 /* if read data get it */
347 if (request->flags & ATA_R_READ)
348 ata_pio_read(request, request->transfersize);
349
350 /* update how far we've gotten */
351 request->donecount += request->transfersize;
352
353 /* do we need a scoop more ? */
354 if (request->bytecount > request->donecount) {
355
356 /* set this transfer size according to HW capabilities */
357 request->transfersize =
358 min((request->bytecount - request->donecount),
359 request->transfersize);
360
361 /* if data write command, output the data */
362 if (request->flags & ATA_R_WRITE) {
363
364 /* if we get an error here we are done with the HW */
365 if (ata_wait(request->device,
366 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
367 ata_prtdev(request->device,
368 "timeout waiting for write DRQ");
369 request->status = ATA_IDX_INB(ch, ATA_STATUS);
370 break;
371 }
372
373 /* output data and return waiting for new interrupt */
374 ata_pio_write(request, request->transfersize);
375 return;
376 }
377
378 /* if data read command, return & wait for interrupt */
379 if (request->flags & ATA_R_READ)
380 return;
381 }
382 }
383 /* done with HW */
384 break;
385
386 /* ATA DMA data transfer commands */
387 case ATA_R_DMA:
388 /* stop DMA engine and get status */
389 request->dmastat = ch->dma->stop(ch);
390
391 /* did we get error or data */
392 if (request->status & ATA_S_ERROR)
393 request->error = ATA_IDX_INB(ch, ATA_ERROR);
394 else if (request->dmastat & ATA_BMSTAT_ERROR)
395 request->status |= ATA_S_ERROR;
396 else
397 request->donecount = request->bytecount;
398
399 /* release SG list etc */
400 ch->dma->unload(ch);
401
402 /* done with HW */
403 break;
404
405 /* ATAPI PIO commands */
406 case ATA_R_ATAPI:
407 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
408
409 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
410 (request->status & ATA_S_DRQ)) {
411
412 case ATAPI_P_CMDOUT:
413 /* this seems to be needed for some (slow) devices */
414 DELAY(10);
415
416 if (!(request->status & ATA_S_DRQ)) {
417 ata_prtdev(request->device, "command interrupt without DRQ\n");
418 request->status = ATA_S_ERROR;
419 break;
420 }
421 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
422 (request->device->param->config &
423 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
424 /* return wait for interrupt */
425 return;
426
427 case ATAPI_P_WRITE:
428 if (request->flags & ATA_R_READ) {
429 request->status = ATA_S_ERROR;
430 ata_prtdev(request->device,
431 "%s trying to write on read buffer\n",
432 ata_cmd2str(request));
433 break;
434 }
435 ata_pio_write(request, length);
436 request->donecount += length;
437
438 /* set next transfer size according to HW capabilities */
439 request->transfersize = min((request->bytecount-request->donecount),
440 request->transfersize);
441 /* return wait for interrupt */
442 return;
443
444 case ATAPI_P_READ:
445 if (request->flags & ATA_R_WRITE) {
446 request->status = ATA_S_ERROR;
447 ata_prtdev(request->device,
448 "%s trying to read on write buffer\n",
449 ata_cmd2str(request));
450 break;
451 }
452 ata_pio_read(request, length);
453 request->donecount += length;
454
455 /* set next transfer size according to HW capabilities */
456 request->transfersize = min((request->bytecount-request->donecount),
457 request->transfersize);
458 /* return wait for interrupt */
459 return;
460
461 case ATAPI_P_DONEDRQ:
462 ata_prtdev(request->device,
463 "WARNING - %s DONEDRQ non conformant device\n",
464 ata_cmd2str(request));
465 if (request->flags & ATA_R_READ) {
466 ata_pio_read(request, length);
467 request->donecount += length;
468 }
469 else if (request->flags & ATA_R_WRITE) {
470 ata_pio_write(request, length);
471 request->donecount += length;
472 }
473 else
474 request->status = ATA_S_ERROR;
475 /* FALLTHROUGH */
476
477 case ATAPI_P_ABORT:
478 case ATAPI_P_DONE:
479 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
480 request->error = ATA_IDX_INB(ch, ATA_ERROR);
481 break;
482
483 default:
484 ata_prtdev(request->device, "unknown transfer phase\n");
485 request->status = ATA_S_ERROR;
486 }
487
488 /* done with HW */
489 break;
490
491 /* ATAPI DMA commands */
492 case ATA_R_ATAPI|ATA_R_DMA:
493
494 /* stop the engine and get engine status */
495 request->dmastat = ch->dma->stop(ch);
496
497 /* did we get error or data */
498 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
499 request->error = ATA_IDX_INB(ch, ATA_ERROR);
500 else if (request->dmastat & ATA_BMSTAT_ERROR)
501 request->status |= ATA_S_ERROR;
502 else
503 request->donecount = request->bytecount;
504
505 /* release SG list etc */
506 ch->dma->unload(ch);
507
508 /* done with HW */
509 break;
510 }
511
|
512 /* if we timed out, we hold on to the channel, ata_reinit() will unlock */
513 if (request->flags & ATA_R_TIMEOUT) {
514 ata_finish(request);
515 return;
516 }
517
518 /* schedule completition for this request */ |
519 ata_finish(request);
520
521 /* unlock the ATA channel for new work */
522 ch->running = NULL;
523 ATA_UNLOCK_CH(ch);
524 ch->locking(ch, ATA_LF_UNLOCK);
525}
526
527/* must be called with ATA channel locked */
528static void
529ata_reset(struct ata_channel *ch)
530{
531 u_int8_t err, lsb, msb, ostat0, ostat1;
532 u_int8_t stat0 = 0, stat1 = 0;
533 int mask = 0, timeout;
534
535 /* do we have any signs of ATA/ATAPI HW being present ? */
536 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
537 DELAY(10);
538 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
539 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
540 stat0 = ATA_S_BUSY;
541 mask |= 0x01;
542 }
543
544 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
545 DELAY(10);
546 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
547
548 /* in some setups we dont want to test for a slave */
549 if (!(ch->flags & ATA_NO_SLAVE)) {
550 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
551 stat1 = ATA_S_BUSY;
552 mask |= 0x02;
553 }
554 }
555
|
532 /* if nothing showed up no need to get any further */
|
| 556 /* if nothing showed up there is no need to get any further */ |
557 /* SOS is that too strong?, we just might loose devices here XXX */
558 ch->devices = 0;
559 if (!mask)
560 return;
561
562 if (bootverbose)
563 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
564 mask, ostat0, ostat1);
565
|
542 /* reset channel */
|
566 /* reset host end of channel (if supported) */
567 if (ch->reset)
568 ch->reset(ch);
569
570 /* reset (both) devices on this channel */ |
571 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
572 DELAY(10);
573 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET);
574 DELAY(10000);
575 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS);
576 DELAY(100000);
577 ATA_IDX_INB(ch, ATA_ERROR);
578
579 /* wait for BUSY to go inactive */
580 for (timeout = 0; timeout < 310; timeout++) {
581 if (stat0 & ATA_S_BUSY) {
582 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
583 DELAY(10);
584 err = ATA_IDX_INB(ch, ATA_ERROR);
585 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
586 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
587 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
588 if (bootverbose)
589 ata_printf(ch, ATA_MASTER,
590 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
591 stat0, err, lsb, msb);
592 if (!(stat0 & ATA_S_BUSY)) {
593 if ((err & 0x7f) == ATA_E_ILI) {
594 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
595 ch->devices |= ATA_ATAPI_MASTER;
596 }
597 else if (stat0 & ATA_S_READY) {
598 ch->devices |= ATA_ATA_MASTER;
599 }
600 }
601 else if ((stat0 & 0x4f) && err == lsb && err == msb) {
602 stat0 |= ATA_S_BUSY;
603 }
604 }
605 }
606 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) {
607 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
608 DELAY(10);
609 err = ATA_IDX_INB(ch, ATA_ERROR);
610 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
611 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
612 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
613 if (bootverbose)
614 ata_printf(ch, ATA_SLAVE,
615 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
616 stat1, err, lsb, msb);
617 if (!(stat1 & ATA_S_BUSY)) {
618 if ((err & 0x7f) == ATA_E_ILI) {
619 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
620 ch->devices |= ATA_ATAPI_SLAVE;
621 }
622 else if (stat1 & ATA_S_READY) {
623 ch->devices |= ATA_ATA_SLAVE;
624 }
625 }
626 else if ((stat1 & 0x4f) && err == lsb && err == msb) {
627 stat1 |= ATA_S_BUSY;
628 }
629 }
630 }
631 if (mask == 0x01) /* wait for master only */
632 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20))
633 break;
634 if (mask == 0x02) /* wait for slave only */
635 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20))
636 break;
637 if (mask == 0x03) { /* wait for both master & slave */
638 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
639 break;
640 if (stat0 == 0xff && timeout > 20)
641 mask &= ~0x01;
642 if (stat1 == 0xff && timeout > 20)
643 mask &= ~0x02;
644 }
645 DELAY(100000);
646 }
647
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648 /* enable interrupt */
649 DELAY(10);
650 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_4BIT);
651 |
652 if (stat0 & ATA_S_BUSY)
653 mask &= ~0x01;
654 if (stat1 & ATA_S_BUSY)
655 mask &= ~0x02;
656
657 if (bootverbose)
658 ata_printf(ch, -1,
659 "reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n",
660 mask, stat0, stat1, ch->devices,
661 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
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630#if 0
631 if (!mask)
632 return;
633
634 if (mask & 0x01 && ostat0 != 0x00 &&
635 !(ch->devices & (ATA_ATA_MASTER | ATA_ATAPI_MASTER))) {
636 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
637 DELAY(10);
638 ATA_IDX_OUTB(ch, ATA_ERROR, 0x58);
639 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5);
640 err = ATA_IDX_INB(ch, ATA_ERROR);
641 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
642 if (bootverbose)
643 ata_printf(ch, ATA_MASTER, "ATA err=0x%02x lsb=0x%02x\n", err, lsb);
644 if (err != 0x58 && lsb == 0xa5)
645 ch->devices |= ATA_ATA_MASTER;
646 }
647 if (mask & 0x02 && ostat1 != 0x00 &&
648 !(ch->devices & (ATA_ATA_SLAVE | ATA_ATAPI_SLAVE))) {
649 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
650 DELAY(10);
651 ATA_IDX_OUTB(ch, ATA_ERROR, 0x58);
652 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5);
653 err = ATA_IDX_INB(ch, ATA_ERROR);
654 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
655 if (bootverbose)
656 ata_printf(ch, ATA_SLAVE, "ATA err=0x%02x lsb=0x%02x\n", err, lsb);
657 if (err != 0x58 && lsb == 0xa5)
658 ch->devices |= ATA_ATA_SLAVE;
659 }
660
661 if (bootverbose)
662 ata_printf(ch, -1, "reset tp3 devices=0x%b\n", ch->devices,
663 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
664#endif
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662}
663
664static int
665ata_wait(struct ata_device *atadev, u_int8_t mask)
666{
667 u_int8_t status;
668 int timeout = 0;
669
670 DELAY(1);
671
672 /* wait 5 seconds for device to get !BUSY */
673 while (timeout < 5000000) {
674 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
675
676 /* if drive fails status, reselect the drive just to be sure */
677 if (status == 0xff) {
678 ata_prtdev(atadev, "WARNING no status, reselecting device\n");
679 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
680 DELAY(10);
681 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
682 if (status == 0xff)
683 return -1;
684 }
685
686 /* are we done ? */
687 if (!(status & ATA_S_BUSY))
688 break;
689
690 if (timeout > 1000) {
691 timeout += 1000;
692 DELAY(1000);
693 }
694 else {
695 timeout += 10;
696 DELAY(10);
697 }
698 }
699 if (timeout >= 5000000)
700 return -1;
701 if (!mask)
702 return (status & ATA_S_ERROR);
703
704 DELAY(1);
705
706 /* wait 50 msec for bits wanted */
707 timeout = 5000;
708 while (timeout--) {
709 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
710 if ((status & mask) == mask)
711 return (status & ATA_S_ERROR);
712 DELAY (10);
713 }
714 return -1;
715}
716
717static int
718ata_command(struct ata_device *atadev, u_int8_t command,
719 u_int64_t lba, u_int16_t count, u_int16_t feature)
720{
721 if (atadebug)
722 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, "
723 "lba=%jd, count=%d, feature=%d\n",
724 rman_get_start(atadev->channel->r_io[ATA_DATA].res),
725 command, (intmax_t)lba, count, feature);
726
727 /* select device */
728 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
729
730 /* ready to issue command ? */
731 if (ata_wait(atadev, 0) < 0) {
732 ata_prtdev(atadev, "timeout sending command=%02x\n", command);
733 return -1;
734 }
735
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739 /* enable interrupt */
740 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT);
741
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736 /* only use 48bit addressing if needed (avoid bugs and overhead) */
737 if ((lba > 268435455 || count > 256) && atadev->param &&
738 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) {
739
740 /* translate command into 48bit version */
741 switch (command) {
742 case ATA_READ:
743 command = ATA_READ48; break;
744 case ATA_READ_MUL:
745 command = ATA_READ_MUL48; break;
746 case ATA_READ_DMA:
747 command = ATA_READ_DMA48; break;
748 case ATA_READ_DMA_QUEUED:
749 command = ATA_READ_DMA_QUEUED48; break;
750 case ATA_WRITE:
751 command = ATA_WRITE48; break;
752 case ATA_WRITE_MUL:
753 command = ATA_WRITE_MUL48; break;
754 case ATA_WRITE_DMA:
755 command = ATA_WRITE_DMA48; break;
756 case ATA_WRITE_DMA_QUEUED:
757 command = ATA_WRITE_DMA_QUEUED48; break;
758 case ATA_FLUSHCACHE:
759 command = ATA_FLUSHCACHE48; break;
760 default:
761 ata_prtdev(atadev, "can't translate cmd to 48bit version\n");
762 return -1;
763 }
764 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff);
765 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff);
766 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff);
767 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff);
768 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff);
769 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
770 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff);
771 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
772 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff);
773 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
774 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit);
775 atadev->channel->flags |= ATA_48BIT_ACTIVE;
776 }
777 else {
778 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature);
779 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count);
780 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
781 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
782 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
783 if (atadev->flags & ATA_D_USE_CHS)
784 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
785 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf));
786 else
787 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
788 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf));
789 atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
790 }
791
792 /* issue command to controller */
793 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command);
794
795 return 0;
796}
797
798static void
799ata_pio_read(struct ata_request *request, int length)
800{
801 int size = min(request->transfersize, length);
802 struct ata_channel *ch = request->device->channel;
803 int resid;
804
805 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
806 ATA_IDX_INSW_STRM(ch, ATA_DATA,
807 (void*)((uintptr_t)request->data+request->donecount),
808 size / sizeof(int16_t));
809 else
810 ATA_IDX_INSL_STRM(ch, ATA_DATA,
811 (void*)((uintptr_t)request->data+request->donecount),
812 size / sizeof(int32_t));
813
814 if (request->transfersize < length) {
815 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n",
816 ata_cmd2str(request), length, request->transfersize);
817 for (resid = request->transfersize; resid < length;
818 resid += sizeof(int16_t))
819 ATA_IDX_INW(ch, ATA_DATA);
820 }
821}
822
823static void
824ata_pio_write(struct ata_request *request, int length)
825{
826 int size = min(request->transfersize, length);
827 struct ata_channel *ch = request->device->channel;
828 int resid;
829
830 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
831 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
832 (void*)((uintptr_t)request->data+request->donecount),
833 size / sizeof(int16_t));
834 else
835 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
836 (void*)((uintptr_t)request->data+request->donecount),
837 size / sizeof(int32_t));
838
839 if (request->transfersize < length) {
840 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n",
841 ata_cmd2str(request), length, request->transfersize);
842 for (resid = request->transfersize; resid < length;
843 resid += sizeof(int16_t))
844 ATA_IDX_OUTW(ch, ATA_DATA, 0);
845 }
846}
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