1/*-
2 * Copyright (c) 1998 - 2003 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: head/sys/dev/ata/ata-lowlevel.c 123421 2003-12-10 23:06:24Z sos $");
31
32#include "opt_ata.h"
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/ata.h>
36#include <sys/kernel.h>
37#include <sys/conf.h>
38#include <sys/bus.h>
39#include <sys/mutex.h>
40#include <sys/taskqueue.h>
41#include <machine/bus.h>
42#include <sys/rman.h>
43#include <dev/ata/ata-all.h>
44
45/* prototypes */
46static int ata_transaction(struct ata_request *);
47static void ata_interrupt(void *);
48static void ata_reset(struct ata_channel *);
49static int ata_wait(struct ata_device *, u_int8_t);
50static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);
51static void ata_pio_read(struct ata_request *, int);
52static void ata_pio_write(struct ata_request *, int);
53
54/* local vars */
55static int atadebug = 0;
56
57/*
58 * low level ATA functions
59 */
60void
61ata_generic_hw(struct ata_channel *ch)
62{
63 ch->hw.reset = ata_reset;
64 ch->hw.transaction = ata_transaction;
65 ch->hw.interrupt = ata_interrupt;
66}
67
68/* must be called with ATA channel locked */
69static int
70ata_transaction(struct ata_request *request)
71{
72 /* record the request as running */
73 request->device->channel->running = request;
74
75 /* disable ATAPI DMA writes if HW doesn't support it */
76 if ((request->device->channel->flags & ATA_ATAPI_DMA_RO) &&
77 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
78 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
79 request->flags &= ~ATA_R_DMA;
80
81 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
82
83 /* ATA PIO data transfer and control commands */
84 default:
85 {
86 /* record command direction here as our request might be done later */
87 int write = (request->flags & ATA_R_WRITE);
88
89 /* issue command */
90 if (ata_command(request->device, request->u.ata.command,
91 request->u.ata.lba, request->u.ata.count,
92 request->u.ata.feature)) {
93 ata_prtdev(request->device, "error issueing PIO command\n");
94 request->result = EIO;
95 break;
96 }
97
98 /* if write command output the data */
99 if (write) {
100 if (ata_wait(request->device,
101 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
102 ata_prtdev(request->device,"timeout waiting for write DRQ");
103 request->result = EIO;
104 break;
105 }
106 ata_pio_write(request, request->transfersize);
107 }
108 }
109 /* return and wait for interrupt */
110 return ATA_OP_CONTINUES;
111
112 /* ATA DMA data transfer commands */
113 case ATA_R_DMA:
114 /* check sanity, setup SG list and DMA engine */
115 if (request->device->channel->dma->load(request->device,
116 request->data,
117 request->bytecount,
118 request->flags & ATA_R_READ)) {
119 ata_prtdev(request->device, "setting up DMA failed\n");
120 request->result = EIO;
121 break;
122 }
123
124 /* issue command */
125 if (ata_command(request->device, request->u.ata.command,
126 request->u.ata.lba, request->u.ata.count,
127 request->u.ata.feature)) {
128 ata_prtdev(request->device, "error issuing DMA command\n");
129 request->result = EIO;
130 break;
131 }
132
133 /* start DMA engine */
134 if (request->device->channel->dma->start(request->device->channel)) {
135 ata_prtdev(request->device, "error starting DMA\n");
136 request->result = EIO;
137 break;
138 }
139 /* return and wait for interrupt */
140 return ATA_OP_CONTINUES;
141
142 /* ATAPI PIO commands */
143 case ATA_R_ATAPI:
144 /* is this just a POLL DSC command ? */
145 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
146 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
147 ATA_D_IBM | request->device->unit);
148 DELAY(10);
149 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
150 request->result = EBUSY;
151 break;
152 }
153
154 /* start ATAPI operation */
155 if (ata_command(request->device, ATA_PACKET_CMD,
156 request->transfersize << 8, 0, 0)) {
157 ata_prtdev(request->device, "error issuing ATA PACKET command\n");
158 request->result = EIO;
159 break;
160 }
161
162 /* command interrupt device ? just return and wait for interrupt */
163 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
164 return ATA_OP_CONTINUES;
165
166 /* wait for ready to write ATAPI command block */
167 {
168 int timeout = 5000; /* might be less for fast devices */
169 while (timeout--) {
170 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
171 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
172
173 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
174 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
175 break;
176 DELAY(20);
177 }
178 if (timeout <= 0) {
179 ata_prtdev(request->device,
180 "timeout waiting for ATAPI ready\n");
181 request->result = EIO;
182 break;
183 }
184 }
185
186 /* this seems to be needed for some (slow) devices */
187 DELAY(10);
188
189 /* output actual command block */
190 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
191 (int16_t *)request->u.atapi.ccb,
192 (request->device->param->config & ATA_PROTO_MASK) ==
193 ATA_PROTO_ATAPI_12 ? 6 : 8);
194
195 /* return and wait for interrupt */
196 return ATA_OP_CONTINUES;
197
198 case ATA_R_ATAPI|ATA_R_DMA:
199 /* is this just a POLL DSC command ? */
200 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
201 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
202 ATA_D_IBM | request->device->unit);
203 DELAY(10);
204 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
205 request->result = EBUSY;
206 break;
207 }
208
209 /* check sanity, setup SG list and DMA engine */
210 if (request->device->channel->dma->load(request->device,
211 request->data,
212 request->bytecount,
213 request->flags & ATA_R_READ)) {
214 ata_prtdev(request->device, "setting up DMA failed\n");
215 request->result = EIO;
216 break;
217 }
218
219 /* start ATAPI operation */
220 if (ata_command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) {
221 ata_prtdev(request->device, "error issuing ATAPI packet command\n");
222 request->result = EIO;
223 break;
224 }
225
226 /* wait for ready to write ATAPI command block */
227 {
228 int timeout = 5000; /* might be less for fast devices */
229 while (timeout--) {
230 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
231 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
232
233 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
234 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
235 break;
236 DELAY(20);
237 }
238 if (timeout <= 0) {
239 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n");
240 request->result = EIO;
241 break;
242 }
243 }
244
245 /* this seems to be needed for some (slow) devices */
246 DELAY(10);
247
248 /* output actual command block */
249 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
250 (int16_t *)request->u.atapi.ccb,
251 (request->device->param->config & ATA_PROTO_MASK) ==
252 ATA_PROTO_ATAPI_12 ? 6 : 8);
253
254 /* start DMA engine */
255 if (request->device->channel->dma->start(request->device->channel)) {
256 request->result = EIO;
257 break;
258 }
259
260 /* return and wait for interrupt */
261 return ATA_OP_CONTINUES;
262 }
263
264 /* request finish here */
265 if (request->device->channel->dma->flags & ATA_DMA_ACTIVE)
266 request->device->channel->dma->unload(request->device->channel);
267 request->device->channel->running = NULL;
268 return ATA_OP_FINISHED;
269}
270
271static void
272ata_interrupt(void *data)
273{
274 struct ata_channel *ch = (struct ata_channel *)data;
275 struct ata_request *request = ch->running;
276 int length;
277
278 /* ignore this interrupt if there is no running request */
279 if (!request) {
280 if (ATA_LOCK_CH(ch, ATA_CONTROL)) {
281 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
282 u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR);
283
284 if (bootverbose)
285 ata_printf(ch, -1,
286 "spurious interrupt - status=0x%02x error=0x%02x\n",
287 status, error);
288 ATA_UNLOCK_CH(ch);
289 }
290 else {
291 if (bootverbose)
292 ata_printf(ch, -1, "spurious interrupt - channel busy\n");
293 }
294 return;
295 }
296
297 /* ignore interrupt if device is busy */
298 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
299 DELAY(100);
300 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ))
301 return;
302 }
303
304 /* clear interrupt and get status */
305 request->status = ATA_IDX_INB(ch, ATA_STATUS);
306
307 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
308
309 /* ATA PIO data transfer and control commands */
310 default:
311
312 /* on control commands read back registers to the request struct */
313 if (request->flags & ATA_R_CONTROL) {
314 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
315 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
316 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
317 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16);
318 }
319
320 /* if we got an error we are done with the HW */
321 if (request->status & ATA_S_ERROR) {
322 request->error = ATA_IDX_INB(ch, ATA_ERROR);
323 break;
324 }
325
326 /* are we moving data ? */
327 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
328
329 /* if read data get it */
330 if (request->flags & ATA_R_READ)
331 ata_pio_read(request, request->transfersize);
332
333 /* update how far we've gotten */
334 request->donecount += request->transfersize;
335
336 /* do we need a scoop more ? */
337 if (request->bytecount > request->donecount) {
338
339 /* set this transfer size according to HW capabilities */
340 request->transfersize =
341 min((request->bytecount - request->donecount),
342 request->transfersize);
343
344 /* if data write command, output the data */
345 if (request->flags & ATA_R_WRITE) {
346
347 /* if we get an error here we are done with the HW */
348 if (ata_wait(request->device,
349 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
350 ata_prtdev(request->device,
351 "timeout waiting for write DRQ");
352 request->status = ATA_IDX_INB(ch, ATA_STATUS);
353 break;
354 }
355
356 /* output data and return waiting for new interrupt */
357 ata_pio_write(request, request->transfersize);
358 return;
359 }
360
361 /* if data read command, return & wait for interrupt */
362 if (request->flags & ATA_R_READ)
363 return;
364 }
365 }
366 /* done with HW */
367 break;
368
369 /* ATA DMA data transfer commands */
370 case ATA_R_DMA:
371 /* stop DMA engine and get status */
372 request->dmastat = ch->dma->stop(ch);
373
374 /* did we get error or data */
375 if (request->status & ATA_S_ERROR)
376 request->error = ATA_IDX_INB(ch, ATA_ERROR);
377 else if (request->dmastat & ATA_BMSTAT_ERROR)
378 request->status |= ATA_S_ERROR;
379 else
380 request->donecount = request->bytecount;
381
382 /* release SG list etc */
383 ch->dma->unload(ch);
384
385 /* done with HW */
386 break;
387
388 /* ATAPI PIO commands */
389 case ATA_R_ATAPI:
390 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
391
392 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
393 (request->status & ATA_S_DRQ)) {
394
395 case ATAPI_P_CMDOUT:
396 /* this seems to be needed for some (slow) devices */
397 DELAY(10);
398
399 if (!(request->status & ATA_S_DRQ)) {
400 ata_prtdev(request->device, "command interrupt without DRQ\n");
401 request->status = ATA_S_ERROR;
402 break;
403 }
404 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
405 (request->device->param->config &
406 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
407 /* return wait for interrupt */
408 return;
409
410 case ATAPI_P_WRITE:
411 if (request->flags & ATA_R_READ) {
412 request->status = ATA_S_ERROR;
413 ata_prtdev(request->device,
414 "%s trying to write on read buffer\n",
415 ata_cmd2str(request));
416 break;
417 }
418 ata_pio_write(request, length);
419 request->donecount += length;
420
421 /* set next transfer size according to HW capabilities */
422 request->transfersize = min((request->bytecount-request->donecount),
423 request->transfersize);
424 /* return wait for interrupt */
425 return;
426
427 case ATAPI_P_READ:
428 if (request->flags & ATA_R_WRITE) {
429 request->status = ATA_S_ERROR;
430 ata_prtdev(request->device,
431 "%s trying to read on write buffer\n",
432 ata_cmd2str(request));
433 break;
434 }
435 ata_pio_read(request, length);
436 request->donecount += length;
437
438 /* set next transfer size according to HW capabilities */
439 request->transfersize = min((request->bytecount-request->donecount),
440 request->transfersize);
441 /* return wait for interrupt */
442 return;
443
444 case ATAPI_P_DONEDRQ:
445 ata_prtdev(request->device,
446 "WARNING - %s DONEDRQ non conformant device\n",
447 ata_cmd2str(request));
448 if (request->flags & ATA_R_READ) {
449 ata_pio_read(request, length);
450 request->donecount += length;
451 }
452 else if (request->flags & ATA_R_WRITE) {
453 ata_pio_write(request, length);
454 request->donecount += length;
455 }
456 else
457 request->status = ATA_S_ERROR;
458 /* FALLTHROUGH */
459
460 case ATAPI_P_ABORT:
461 case ATAPI_P_DONE:
462 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
463 request->error = ATA_IDX_INB(ch, ATA_ERROR);
464 break;
465
466 default:
467 ata_prtdev(request->device, "unknown transfer phase\n");
468 request->status = ATA_S_ERROR;
469 }
470
471 /* done with HW */
472 break;
473
474 /* ATAPI DMA commands */
475 case ATA_R_ATAPI|ATA_R_DMA:
476
477 /* stop the engine and get engine status */
478 request->dmastat = ch->dma->stop(ch);
479
480 /* did we get error or data */
481 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
482 request->error = ATA_IDX_INB(ch, ATA_ERROR);
483 else if (request->dmastat & ATA_BMSTAT_ERROR)
484 request->status |= ATA_S_ERROR;
485 else
486 request->donecount = request->bytecount;
487
488 /* release SG list etc */
489 ch->dma->unload(ch);
490
491 /* done with HW */
492 break;
493 }
494
495 ata_finish(request);
496
497 /* unlock the ATA channel for new work */
498 ch->running = NULL;
499 ATA_UNLOCK_CH(ch);
500 ch->locking(ch, ATA_LF_UNLOCK);
501}
502
503/* must be called with ATA channel locked */
504static void
505ata_reset(struct ata_channel *ch)
506{
507 u_int8_t err, lsb, msb, ostat0, ostat1;
508 u_int8_t stat0 = 0, stat1 = 0;
509 int mask = 0, timeout;
510
511 /* do we have any signs of ATA/ATAPI HW being present ? */
512 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
513 DELAY(10);
514 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
515 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
516 stat0 = ATA_S_BUSY;
517 mask |= 0x01;
518 }
519
520 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
521 DELAY(10);
522 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
523
524 /* in some setups we dont want to test for a slave */
525 if (!(ch->flags & ATA_NO_SLAVE)) {
526 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
527 stat1 = ATA_S_BUSY;
528 mask |= 0x02;
529 }
530 }
531
532 /* if nothing showed up no need to get any further */
533 /* SOS is that too strong?, we just might loose devices here XXX */
534 ch->devices = 0;
535 if (!mask)
536 return;
537
538 if (bootverbose)
539 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
540 mask, ostat0, ostat1);
541
542 /* reset channel */
543 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
544 DELAY(10);
545 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET);
546 DELAY(10000);
547 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS);
548 DELAY(100000);
549 ATA_IDX_INB(ch, ATA_ERROR);
550
551 /* wait for BUSY to go inactive */
552 for (timeout = 0; timeout < 310; timeout++) {
553 if (stat0 & ATA_S_BUSY) {
554 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
555 DELAY(10);
556 err = ATA_IDX_INB(ch, ATA_ERROR);
557 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
558 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
559 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
560 if (bootverbose)
561 ata_printf(ch, ATA_MASTER,
562 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
563 stat0, err, lsb, msb);
564 if (!(stat0 & ATA_S_BUSY)) {
565 if ((err & 0x7f) == ATA_E_ILI) {
566 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
567 ch->devices |= ATA_ATAPI_MASTER;
568 }
569 else if (stat0 & ATA_S_READY) {
570 ch->devices |= ATA_ATA_MASTER;
571 }
572 }
573 else if ((stat0 & 0x4f) && err == lsb && err == msb) {
574 stat0 |= ATA_S_BUSY;
575 }
576 }
577 }
578 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) {
579 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
580 DELAY(10);
581 err = ATA_IDX_INB(ch, ATA_ERROR);
582 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
583 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
584 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
585 if (bootverbose)
586 ata_printf(ch, ATA_SLAVE,
587 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
588 stat1, err, lsb, msb);
589 if (!(stat1 & ATA_S_BUSY)) {
590 if ((err & 0x7f) == ATA_E_ILI) {
591 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
592 ch->devices |= ATA_ATAPI_SLAVE;
593 }
594 else if (stat1 & ATA_S_READY) {
595 ch->devices |= ATA_ATA_SLAVE;
596 }
597 }
598 else if ((stat1 & 0x4f) && err == lsb && err == msb) {
599 stat1 |= ATA_S_BUSY;
600 }
601 }
602 }
603 if (mask == 0x01) /* wait for master only */
604 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20))
605 break;
606 if (mask == 0x02) /* wait for slave only */
607 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20))
608 break;
609 if (mask == 0x03) { /* wait for both master & slave */
610 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
611 break;
612 if (stat0 == 0xff && timeout > 20)
613 mask &= ~0x01;
614 if (stat1 == 0xff && timeout > 20)
615 mask &= ~0x02;
616 }
617 DELAY(100000);
618 }
619
620 if (stat0 & ATA_S_BUSY)
621 mask &= ~0x01;
622 if (stat1 & ATA_S_BUSY)
623 mask &= ~0x02;
624
625 if (bootverbose)
626 ata_printf(ch, -1,
627 "reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n",
628 mask, stat0, stat1, ch->devices,
629 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
630#if 0
631 if (!mask)
632 return;
633
634 if (mask & 0x01 && ostat0 != 0x00 &&
635 !(ch->devices & (ATA_ATA_MASTER | ATA_ATAPI_MASTER))) {
636 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
637 DELAY(10);
638 ATA_IDX_OUTB(ch, ATA_ERROR, 0x58);
639 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5);
640 err = ATA_IDX_INB(ch, ATA_ERROR);
641 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
642 if (bootverbose)
643 ata_printf(ch, ATA_MASTER, "ATA err=0x%02x lsb=0x%02x\n", err, lsb);
644 if (err != 0x58 && lsb == 0xa5)
645 ch->devices |= ATA_ATA_MASTER;
646 }
647 if (mask & 0x02 && ostat1 != 0x00 &&
648 !(ch->devices & (ATA_ATA_SLAVE | ATA_ATAPI_SLAVE))) {
649 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
650 DELAY(10);
651 ATA_IDX_OUTB(ch, ATA_ERROR, 0x58);
652 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5);
653 err = ATA_IDX_INB(ch, ATA_ERROR);
654 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
655 if (bootverbose)
656 ata_printf(ch, ATA_SLAVE, "ATA err=0x%02x lsb=0x%02x\n", err, lsb);
657 if (err != 0x58 && lsb == 0xa5)
658 ch->devices |= ATA_ATA_SLAVE;
659 }
660
661 if (bootverbose)
662 ata_printf(ch, -1, "reset tp3 devices=0x%b\n", ch->devices,
663 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
664#endif
665}
666
667static int
668ata_wait(struct ata_device *atadev, u_int8_t mask)
669{
670 u_int8_t status;
671 int timeout = 0;
672
673 DELAY(1);
674
675 /* wait 5 seconds for device to get !BUSY */
676 while (timeout < 5000000) {
677 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
678
679 /* if drive fails status, reselect the drive just to be sure */
680 if (status == 0xff) {
681 ata_prtdev(atadev, "WARNING no status, reselecting device\n");
682 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
683 DELAY(10);
684 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
685 if (status == 0xff)
686 return -1;
687 }
688
689 /* are we done ? */
690 if (!(status & ATA_S_BUSY))
691 break;
692
693 if (timeout > 1000) {
694 timeout += 1000;
695 DELAY(1000);
696 }
697 else {
698 timeout += 10;
699 DELAY(10);
700 }
701 }
702 if (timeout >= 5000000)
703 return -1;
704 if (!mask)
705 return (status & ATA_S_ERROR);
706
707 DELAY(1);
708
709 /* wait 50 msec for bits wanted */
710 timeout = 5000;
711 while (timeout--) {
712 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
713 if ((status & mask) == mask)
714 return (status & ATA_S_ERROR);
715 DELAY (10);
716 }
717 return -1;
718}
719
720static int
721ata_command(struct ata_device *atadev, u_int8_t command,
722 u_int64_t lba, u_int16_t count, u_int16_t feature)
723{
724 if (atadebug)
725 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, "
726 "lba=%jd, count=%d, feature=%d\n",
727 rman_get_start(atadev->channel->r_io[ATA_DATA].res),
728 command, (intmax_t)lba, count, feature);
729
730 /* select device */
731 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
732
733 /* ready to issue command ? */
734 if (ata_wait(atadev, 0) < 0) {
735 ata_prtdev(atadev, "timeout sending command=%02x\n", command);
736 return -1;
737 }
738
739 /* enable interrupt */
740 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT);
741
742 /* only use 48bit addressing if needed (avoid bugs and overhead) */
743 if ((lba > 268435455 || count > 256) && atadev->param &&
744 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) {
745
746 /* translate command into 48bit version */
747 switch (command) {
748 case ATA_READ:
749 command = ATA_READ48; break;
750 case ATA_READ_MUL:
751 command = ATA_READ_MUL48; break;
752 case ATA_READ_DMA:
753 command = ATA_READ_DMA48; break;
754 case ATA_READ_DMA_QUEUED:
755 command = ATA_READ_DMA_QUEUED48; break;
756 case ATA_WRITE:
757 command = ATA_WRITE48; break;
758 case ATA_WRITE_MUL:
759 command = ATA_WRITE_MUL48; break;
760 case ATA_WRITE_DMA:
761 command = ATA_WRITE_DMA48; break;
762 case ATA_WRITE_DMA_QUEUED:
763 command = ATA_WRITE_DMA_QUEUED48; break;
764 case ATA_FLUSHCACHE:
765 command = ATA_FLUSHCACHE48; break;
766 default:
767 ata_prtdev(atadev, "can't translate cmd to 48bit version\n");
768 return -1;
769 }
770 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff);
771 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff);
772 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff);
773 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff);
774 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff);
775 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
776 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff);
777 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
778 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff);
779 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
780 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit);
781 atadev->channel->flags |= ATA_48BIT_ACTIVE;
782 }
783 else {
784 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature);
785 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count);
786 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
787 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
788 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
789 if (atadev->flags & ATA_D_USE_CHS)
790 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
791 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf));
792 else
793 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
794 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf));
795 atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
796 }
797
798 /* issue command to controller */
799 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command);
800
801 return 0;
802}
803
804static void
805ata_pio_read(struct ata_request *request, int length)
806{
807 int size = min(request->transfersize, length);
808 struct ata_channel *ch = request->device->channel;
809 int resid;
810
811 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
812 ATA_IDX_INSW_STRM(ch, ATA_DATA,
813 (void*)((uintptr_t)request->data+request->donecount),
814 size / sizeof(int16_t));
815 else
816 ATA_IDX_INSL_STRM(ch, ATA_DATA,
817 (void*)((uintptr_t)request->data+request->donecount),
818 size / sizeof(int32_t));
819
820 if (request->transfersize < length) {
821 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n",
822 ata_cmd2str(request), length, request->transfersize);
823 for (resid = request->transfersize; resid < length;
824 resid += sizeof(int16_t))
825 ATA_IDX_INW(ch, ATA_DATA);
826 }
827}
828
829static void
830ata_pio_write(struct ata_request *request, int length)
831{
832 int size = min(request->transfersize, length);
833 struct ata_channel *ch = request->device->channel;
834 int resid;
835
836 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
837 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
838 (void*)((uintptr_t)request->data+request->donecount),
839 size / sizeof(int16_t));
840 else
841 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
842 (void*)((uintptr_t)request->data+request->donecount),
843 size / sizeof(int32_t));
844
845 if (request->transfersize < length) {
846 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n",
847 ata_cmd2str(request), length, request->transfersize);
848 for (resid = request->transfersize; resid < length;
849 resid += sizeof(int16_t))
850 ATA_IDX_OUTW(ch, ATA_DATA, 0);
851 }
852}
2 * Copyright (c) 1998 - 2003 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: head/sys/dev/ata/ata-lowlevel.c 123421 2003-12-10 23:06:24Z sos $");
31
32#include "opt_ata.h"
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/ata.h>
36#include <sys/kernel.h>
37#include <sys/conf.h>
38#include <sys/bus.h>
39#include <sys/mutex.h>
40#include <sys/taskqueue.h>
41#include <machine/bus.h>
42#include <sys/rman.h>
43#include <dev/ata/ata-all.h>
44
45/* prototypes */
46static int ata_transaction(struct ata_request *);
47static void ata_interrupt(void *);
48static void ata_reset(struct ata_channel *);
49static int ata_wait(struct ata_device *, u_int8_t);
50static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t);
51static void ata_pio_read(struct ata_request *, int);
52static void ata_pio_write(struct ata_request *, int);
53
54/* local vars */
55static int atadebug = 0;
56
57/*
58 * low level ATA functions
59 */
60void
61ata_generic_hw(struct ata_channel *ch)
62{
63 ch->hw.reset = ata_reset;
64 ch->hw.transaction = ata_transaction;
65 ch->hw.interrupt = ata_interrupt;
66}
67
68/* must be called with ATA channel locked */
69static int
70ata_transaction(struct ata_request *request)
71{
72 /* record the request as running */
73 request->device->channel->running = request;
74
75 /* disable ATAPI DMA writes if HW doesn't support it */
76 if ((request->device->channel->flags & ATA_ATAPI_DMA_RO) &&
77 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
78 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
79 request->flags &= ~ATA_R_DMA;
80
81 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
82
83 /* ATA PIO data transfer and control commands */
84 default:
85 {
86 /* record command direction here as our request might be done later */
87 int write = (request->flags & ATA_R_WRITE);
88
89 /* issue command */
90 if (ata_command(request->device, request->u.ata.command,
91 request->u.ata.lba, request->u.ata.count,
92 request->u.ata.feature)) {
93 ata_prtdev(request->device, "error issueing PIO command\n");
94 request->result = EIO;
95 break;
96 }
97
98 /* if write command output the data */
99 if (write) {
100 if (ata_wait(request->device,
101 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
102 ata_prtdev(request->device,"timeout waiting for write DRQ");
103 request->result = EIO;
104 break;
105 }
106 ata_pio_write(request, request->transfersize);
107 }
108 }
109 /* return and wait for interrupt */
110 return ATA_OP_CONTINUES;
111
112 /* ATA DMA data transfer commands */
113 case ATA_R_DMA:
114 /* check sanity, setup SG list and DMA engine */
115 if (request->device->channel->dma->load(request->device,
116 request->data,
117 request->bytecount,
118 request->flags & ATA_R_READ)) {
119 ata_prtdev(request->device, "setting up DMA failed\n");
120 request->result = EIO;
121 break;
122 }
123
124 /* issue command */
125 if (ata_command(request->device, request->u.ata.command,
126 request->u.ata.lba, request->u.ata.count,
127 request->u.ata.feature)) {
128 ata_prtdev(request->device, "error issuing DMA command\n");
129 request->result = EIO;
130 break;
131 }
132
133 /* start DMA engine */
134 if (request->device->channel->dma->start(request->device->channel)) {
135 ata_prtdev(request->device, "error starting DMA\n");
136 request->result = EIO;
137 break;
138 }
139 /* return and wait for interrupt */
140 return ATA_OP_CONTINUES;
141
142 /* ATAPI PIO commands */
143 case ATA_R_ATAPI:
144 /* is this just a POLL DSC command ? */
145 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
146 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
147 ATA_D_IBM | request->device->unit);
148 DELAY(10);
149 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
150 request->result = EBUSY;
151 break;
152 }
153
154 /* start ATAPI operation */
155 if (ata_command(request->device, ATA_PACKET_CMD,
156 request->transfersize << 8, 0, 0)) {
157 ata_prtdev(request->device, "error issuing ATA PACKET command\n");
158 request->result = EIO;
159 break;
160 }
161
162 /* command interrupt device ? just return and wait for interrupt */
163 if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
164 return ATA_OP_CONTINUES;
165
166 /* wait for ready to write ATAPI command block */
167 {
168 int timeout = 5000; /* might be less for fast devices */
169 while (timeout--) {
170 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
171 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
172
173 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
174 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
175 break;
176 DELAY(20);
177 }
178 if (timeout <= 0) {
179 ata_prtdev(request->device,
180 "timeout waiting for ATAPI ready\n");
181 request->result = EIO;
182 break;
183 }
184 }
185
186 /* this seems to be needed for some (slow) devices */
187 DELAY(10);
188
189 /* output actual command block */
190 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
191 (int16_t *)request->u.atapi.ccb,
192 (request->device->param->config & ATA_PROTO_MASK) ==
193 ATA_PROTO_ATAPI_12 ? 6 : 8);
194
195 /* return and wait for interrupt */
196 return ATA_OP_CONTINUES;
197
198 case ATA_R_ATAPI|ATA_R_DMA:
199 /* is this just a POLL DSC command ? */
200 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
201 ATA_IDX_OUTB(request->device->channel, ATA_DRIVE,
202 ATA_D_IBM | request->device->unit);
203 DELAY(10);
204 if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC))
205 request->result = EBUSY;
206 break;
207 }
208
209 /* check sanity, setup SG list and DMA engine */
210 if (request->device->channel->dma->load(request->device,
211 request->data,
212 request->bytecount,
213 request->flags & ATA_R_READ)) {
214 ata_prtdev(request->device, "setting up DMA failed\n");
215 request->result = EIO;
216 break;
217 }
218
219 /* start ATAPI operation */
220 if (ata_command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) {
221 ata_prtdev(request->device, "error issuing ATAPI packet command\n");
222 request->result = EIO;
223 break;
224 }
225
226 /* wait for ready to write ATAPI command block */
227 {
228 int timeout = 5000; /* might be less for fast devices */
229 while (timeout--) {
230 int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON);
231 int status = ATA_IDX_INB(request->device->channel, ATA_STATUS);
232
233 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
234 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
235 break;
236 DELAY(20);
237 }
238 if (timeout <= 0) {
239 ata_prtdev(request->device,"timeout waiting for ATAPI ready\n");
240 request->result = EIO;
241 break;
242 }
243 }
244
245 /* this seems to be needed for some (slow) devices */
246 DELAY(10);
247
248 /* output actual command block */
249 ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA,
250 (int16_t *)request->u.atapi.ccb,
251 (request->device->param->config & ATA_PROTO_MASK) ==
252 ATA_PROTO_ATAPI_12 ? 6 : 8);
253
254 /* start DMA engine */
255 if (request->device->channel->dma->start(request->device->channel)) {
256 request->result = EIO;
257 break;
258 }
259
260 /* return and wait for interrupt */
261 return ATA_OP_CONTINUES;
262 }
263
264 /* request finish here */
265 if (request->device->channel->dma->flags & ATA_DMA_ACTIVE)
266 request->device->channel->dma->unload(request->device->channel);
267 request->device->channel->running = NULL;
268 return ATA_OP_FINISHED;
269}
270
271static void
272ata_interrupt(void *data)
273{
274 struct ata_channel *ch = (struct ata_channel *)data;
275 struct ata_request *request = ch->running;
276 int length;
277
278 /* ignore this interrupt if there is no running request */
279 if (!request) {
280 if (ATA_LOCK_CH(ch, ATA_CONTROL)) {
281 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
282 u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR);
283
284 if (bootverbose)
285 ata_printf(ch, -1,
286 "spurious interrupt - status=0x%02x error=0x%02x\n",
287 status, error);
288 ATA_UNLOCK_CH(ch);
289 }
290 else {
291 if (bootverbose)
292 ata_printf(ch, -1, "spurious interrupt - channel busy\n");
293 }
294 return;
295 }
296
297 /* ignore interrupt if device is busy */
298 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
299 DELAY(100);
300 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ))
301 return;
302 }
303
304 /* clear interrupt and get status */
305 request->status = ATA_IDX_INB(ch, ATA_STATUS);
306
307 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
308
309 /* ATA PIO data transfer and control commands */
310 default:
311
312 /* on control commands read back registers to the request struct */
313 if (request->flags & ATA_R_CONTROL) {
314 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
315 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
316 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
317 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16);
318 }
319
320 /* if we got an error we are done with the HW */
321 if (request->status & ATA_S_ERROR) {
322 request->error = ATA_IDX_INB(ch, ATA_ERROR);
323 break;
324 }
325
326 /* are we moving data ? */
327 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
328
329 /* if read data get it */
330 if (request->flags & ATA_R_READ)
331 ata_pio_read(request, request->transfersize);
332
333 /* update how far we've gotten */
334 request->donecount += request->transfersize;
335
336 /* do we need a scoop more ? */
337 if (request->bytecount > request->donecount) {
338
339 /* set this transfer size according to HW capabilities */
340 request->transfersize =
341 min((request->bytecount - request->donecount),
342 request->transfersize);
343
344 /* if data write command, output the data */
345 if (request->flags & ATA_R_WRITE) {
346
347 /* if we get an error here we are done with the HW */
348 if (ata_wait(request->device,
349 (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) {
350 ata_prtdev(request->device,
351 "timeout waiting for write DRQ");
352 request->status = ATA_IDX_INB(ch, ATA_STATUS);
353 break;
354 }
355
356 /* output data and return waiting for new interrupt */
357 ata_pio_write(request, request->transfersize);
358 return;
359 }
360
361 /* if data read command, return & wait for interrupt */
362 if (request->flags & ATA_R_READ)
363 return;
364 }
365 }
366 /* done with HW */
367 break;
368
369 /* ATA DMA data transfer commands */
370 case ATA_R_DMA:
371 /* stop DMA engine and get status */
372 request->dmastat = ch->dma->stop(ch);
373
374 /* did we get error or data */
375 if (request->status & ATA_S_ERROR)
376 request->error = ATA_IDX_INB(ch, ATA_ERROR);
377 else if (request->dmastat & ATA_BMSTAT_ERROR)
378 request->status |= ATA_S_ERROR;
379 else
380 request->donecount = request->bytecount;
381
382 /* release SG list etc */
383 ch->dma->unload(ch);
384
385 /* done with HW */
386 break;
387
388 /* ATAPI PIO commands */
389 case ATA_R_ATAPI:
390 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
391
392 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
393 (request->status & ATA_S_DRQ)) {
394
395 case ATAPI_P_CMDOUT:
396 /* this seems to be needed for some (slow) devices */
397 DELAY(10);
398
399 if (!(request->status & ATA_S_DRQ)) {
400 ata_prtdev(request->device, "command interrupt without DRQ\n");
401 request->status = ATA_S_ERROR;
402 break;
403 }
404 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
405 (request->device->param->config &
406 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
407 /* return wait for interrupt */
408 return;
409
410 case ATAPI_P_WRITE:
411 if (request->flags & ATA_R_READ) {
412 request->status = ATA_S_ERROR;
413 ata_prtdev(request->device,
414 "%s trying to write on read buffer\n",
415 ata_cmd2str(request));
416 break;
417 }
418 ata_pio_write(request, length);
419 request->donecount += length;
420
421 /* set next transfer size according to HW capabilities */
422 request->transfersize = min((request->bytecount-request->donecount),
423 request->transfersize);
424 /* return wait for interrupt */
425 return;
426
427 case ATAPI_P_READ:
428 if (request->flags & ATA_R_WRITE) {
429 request->status = ATA_S_ERROR;
430 ata_prtdev(request->device,
431 "%s trying to read on write buffer\n",
432 ata_cmd2str(request));
433 break;
434 }
435 ata_pio_read(request, length);
436 request->donecount += length;
437
438 /* set next transfer size according to HW capabilities */
439 request->transfersize = min((request->bytecount-request->donecount),
440 request->transfersize);
441 /* return wait for interrupt */
442 return;
443
444 case ATAPI_P_DONEDRQ:
445 ata_prtdev(request->device,
446 "WARNING - %s DONEDRQ non conformant device\n",
447 ata_cmd2str(request));
448 if (request->flags & ATA_R_READ) {
449 ata_pio_read(request, length);
450 request->donecount += length;
451 }
452 else if (request->flags & ATA_R_WRITE) {
453 ata_pio_write(request, length);
454 request->donecount += length;
455 }
456 else
457 request->status = ATA_S_ERROR;
458 /* FALLTHROUGH */
459
460 case ATAPI_P_ABORT:
461 case ATAPI_P_DONE:
462 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
463 request->error = ATA_IDX_INB(ch, ATA_ERROR);
464 break;
465
466 default:
467 ata_prtdev(request->device, "unknown transfer phase\n");
468 request->status = ATA_S_ERROR;
469 }
470
471 /* done with HW */
472 break;
473
474 /* ATAPI DMA commands */
475 case ATA_R_ATAPI|ATA_R_DMA:
476
477 /* stop the engine and get engine status */
478 request->dmastat = ch->dma->stop(ch);
479
480 /* did we get error or data */
481 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
482 request->error = ATA_IDX_INB(ch, ATA_ERROR);
483 else if (request->dmastat & ATA_BMSTAT_ERROR)
484 request->status |= ATA_S_ERROR;
485 else
486 request->donecount = request->bytecount;
487
488 /* release SG list etc */
489 ch->dma->unload(ch);
490
491 /* done with HW */
492 break;
493 }
494
495 ata_finish(request);
496
497 /* unlock the ATA channel for new work */
498 ch->running = NULL;
499 ATA_UNLOCK_CH(ch);
500 ch->locking(ch, ATA_LF_UNLOCK);
501}
502
503/* must be called with ATA channel locked */
504static void
505ata_reset(struct ata_channel *ch)
506{
507 u_int8_t err, lsb, msb, ostat0, ostat1;
508 u_int8_t stat0 = 0, stat1 = 0;
509 int mask = 0, timeout;
510
511 /* do we have any signs of ATA/ATAPI HW being present ? */
512 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
513 DELAY(10);
514 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
515 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
516 stat0 = ATA_S_BUSY;
517 mask |= 0x01;
518 }
519
520 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
521 DELAY(10);
522 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
523
524 /* in some setups we dont want to test for a slave */
525 if (!(ch->flags & ATA_NO_SLAVE)) {
526 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
527 stat1 = ATA_S_BUSY;
528 mask |= 0x02;
529 }
530 }
531
532 /* if nothing showed up no need to get any further */
533 /* SOS is that too strong?, we just might loose devices here XXX */
534 ch->devices = 0;
535 if (!mask)
536 return;
537
538 if (bootverbose)
539 ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
540 mask, ostat0, ostat1);
541
542 /* reset channel */
543 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
544 DELAY(10);
545 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET);
546 DELAY(10000);
547 ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS);
548 DELAY(100000);
549 ATA_IDX_INB(ch, ATA_ERROR);
550
551 /* wait for BUSY to go inactive */
552 for (timeout = 0; timeout < 310; timeout++) {
553 if (stat0 & ATA_S_BUSY) {
554 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
555 DELAY(10);
556 err = ATA_IDX_INB(ch, ATA_ERROR);
557 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
558 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
559 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
560 if (bootverbose)
561 ata_printf(ch, ATA_MASTER,
562 "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
563 stat0, err, lsb, msb);
564 if (!(stat0 & ATA_S_BUSY)) {
565 if ((err & 0x7f) == ATA_E_ILI) {
566 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
567 ch->devices |= ATA_ATAPI_MASTER;
568 }
569 else if (stat0 & ATA_S_READY) {
570 ch->devices |= ATA_ATA_MASTER;
571 }
572 }
573 else if ((stat0 & 0x4f) && err == lsb && err == msb) {
574 stat0 |= ATA_S_BUSY;
575 }
576 }
577 }
578 if (!((mask == 0x03) && (stat0 & ATA_S_BUSY)) && (stat1 & ATA_S_BUSY)) {
579 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
580 DELAY(10);
581 err = ATA_IDX_INB(ch, ATA_ERROR);
582 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
583 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
584 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
585 if (bootverbose)
586 ata_printf(ch, ATA_SLAVE,
587 " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
588 stat1, err, lsb, msb);
589 if (!(stat1 & ATA_S_BUSY)) {
590 if ((err & 0x7f) == ATA_E_ILI) {
591 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
592 ch->devices |= ATA_ATAPI_SLAVE;
593 }
594 else if (stat1 & ATA_S_READY) {
595 ch->devices |= ATA_ATA_SLAVE;
596 }
597 }
598 else if ((stat1 & 0x4f) && err == lsb && err == msb) {
599 stat1 |= ATA_S_BUSY;
600 }
601 }
602 }
603 if (mask == 0x01) /* wait for master only */
604 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20))
605 break;
606 if (mask == 0x02) /* wait for slave only */
607 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20))
608 break;
609 if (mask == 0x03) { /* wait for both master & slave */
610 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
611 break;
612 if (stat0 == 0xff && timeout > 20)
613 mask &= ~0x01;
614 if (stat1 == 0xff && timeout > 20)
615 mask &= ~0x02;
616 }
617 DELAY(100000);
618 }
619
620 if (stat0 & ATA_S_BUSY)
621 mask &= ~0x01;
622 if (stat1 & ATA_S_BUSY)
623 mask &= ~0x02;
624
625 if (bootverbose)
626 ata_printf(ch, -1,
627 "reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n",
628 mask, stat0, stat1, ch->devices,
629 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
630#if 0
631 if (!mask)
632 return;
633
634 if (mask & 0x01 && ostat0 != 0x00 &&
635 !(ch->devices & (ATA_ATA_MASTER | ATA_ATAPI_MASTER))) {
636 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
637 DELAY(10);
638 ATA_IDX_OUTB(ch, ATA_ERROR, 0x58);
639 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5);
640 err = ATA_IDX_INB(ch, ATA_ERROR);
641 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
642 if (bootverbose)
643 ata_printf(ch, ATA_MASTER, "ATA err=0x%02x lsb=0x%02x\n", err, lsb);
644 if (err != 0x58 && lsb == 0xa5)
645 ch->devices |= ATA_ATA_MASTER;
646 }
647 if (mask & 0x02 && ostat1 != 0x00 &&
648 !(ch->devices & (ATA_ATA_SLAVE | ATA_ATAPI_SLAVE))) {
649 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
650 DELAY(10);
651 ATA_IDX_OUTB(ch, ATA_ERROR, 0x58);
652 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5);
653 err = ATA_IDX_INB(ch, ATA_ERROR);
654 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
655 if (bootverbose)
656 ata_printf(ch, ATA_SLAVE, "ATA err=0x%02x lsb=0x%02x\n", err, lsb);
657 if (err != 0x58 && lsb == 0xa5)
658 ch->devices |= ATA_ATA_SLAVE;
659 }
660
661 if (bootverbose)
662 ata_printf(ch, -1, "reset tp3 devices=0x%b\n", ch->devices,
663 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
664#endif
665}
666
667static int
668ata_wait(struct ata_device *atadev, u_int8_t mask)
669{
670 u_int8_t status;
671 int timeout = 0;
672
673 DELAY(1);
674
675 /* wait 5 seconds for device to get !BUSY */
676 while (timeout < 5000000) {
677 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
678
679 /* if drive fails status, reselect the drive just to be sure */
680 if (status == 0xff) {
681 ata_prtdev(atadev, "WARNING no status, reselecting device\n");
682 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
683 DELAY(10);
684 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
685 if (status == 0xff)
686 return -1;
687 }
688
689 /* are we done ? */
690 if (!(status & ATA_S_BUSY))
691 break;
692
693 if (timeout > 1000) {
694 timeout += 1000;
695 DELAY(1000);
696 }
697 else {
698 timeout += 10;
699 DELAY(10);
700 }
701 }
702 if (timeout >= 5000000)
703 return -1;
704 if (!mask)
705 return (status & ATA_S_ERROR);
706
707 DELAY(1);
708
709 /* wait 50 msec for bits wanted */
710 timeout = 5000;
711 while (timeout--) {
712 status = ATA_IDX_INB(atadev->channel, ATA_STATUS);
713 if ((status & mask) == mask)
714 return (status & ATA_S_ERROR);
715 DELAY (10);
716 }
717 return -1;
718}
719
720static int
721ata_command(struct ata_device *atadev, u_int8_t command,
722 u_int64_t lba, u_int16_t count, u_int16_t feature)
723{
724 if (atadebug)
725 ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, "
726 "lba=%jd, count=%d, feature=%d\n",
727 rman_get_start(atadev->channel->r_io[ATA_DATA].res),
728 command, (intmax_t)lba, count, feature);
729
730 /* select device */
731 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit);
732
733 /* ready to issue command ? */
734 if (ata_wait(atadev, 0) < 0) {
735 ata_prtdev(atadev, "timeout sending command=%02x\n", command);
736 return -1;
737 }
738
739 /* enable interrupt */
740 ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT);
741
742 /* only use 48bit addressing if needed (avoid bugs and overhead) */
743 if ((lba > 268435455 || count > 256) && atadev->param &&
744 atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) {
745
746 /* translate command into 48bit version */
747 switch (command) {
748 case ATA_READ:
749 command = ATA_READ48; break;
750 case ATA_READ_MUL:
751 command = ATA_READ_MUL48; break;
752 case ATA_READ_DMA:
753 command = ATA_READ_DMA48; break;
754 case ATA_READ_DMA_QUEUED:
755 command = ATA_READ_DMA_QUEUED48; break;
756 case ATA_WRITE:
757 command = ATA_WRITE48; break;
758 case ATA_WRITE_MUL:
759 command = ATA_WRITE_MUL48; break;
760 case ATA_WRITE_DMA:
761 command = ATA_WRITE_DMA48; break;
762 case ATA_WRITE_DMA_QUEUED:
763 command = ATA_WRITE_DMA_QUEUED48; break;
764 case ATA_FLUSHCACHE:
765 command = ATA_FLUSHCACHE48; break;
766 default:
767 ata_prtdev(atadev, "can't translate cmd to 48bit version\n");
768 return -1;
769 }
770 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff);
771 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff);
772 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff);
773 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff);
774 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff);
775 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
776 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff);
777 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
778 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff);
779 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
780 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit);
781 atadev->channel->flags |= ATA_48BIT_ACTIVE;
782 }
783 else {
784 ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature);
785 ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count);
786 ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff);
787 ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff);
788 ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff);
789 if (atadev->flags & ATA_D_USE_CHS)
790 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
791 ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf));
792 else
793 ATA_IDX_OUTB(atadev->channel, ATA_DRIVE,
794 ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf));
795 atadev->channel->flags &= ~ATA_48BIT_ACTIVE;
796 }
797
798 /* issue command to controller */
799 ATA_IDX_OUTB(atadev->channel, ATA_CMD, command);
800
801 return 0;
802}
803
804static void
805ata_pio_read(struct ata_request *request, int length)
806{
807 int size = min(request->transfersize, length);
808 struct ata_channel *ch = request->device->channel;
809 int resid;
810
811 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
812 ATA_IDX_INSW_STRM(ch, ATA_DATA,
813 (void*)((uintptr_t)request->data+request->donecount),
814 size / sizeof(int16_t));
815 else
816 ATA_IDX_INSL_STRM(ch, ATA_DATA,
817 (void*)((uintptr_t)request->data+request->donecount),
818 size / sizeof(int32_t));
819
820 if (request->transfersize < length) {
821 ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n",
822 ata_cmd2str(request), length, request->transfersize);
823 for (resid = request->transfersize; resid < length;
824 resid += sizeof(int16_t))
825 ATA_IDX_INW(ch, ATA_DATA);
826 }
827}
828
829static void
830ata_pio_write(struct ata_request *request, int length)
831{
832 int size = min(request->transfersize, length);
833 struct ata_channel *ch = request->device->channel;
834 int resid;
835
836 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
837 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
838 (void*)((uintptr_t)request->data+request->donecount),
839 size / sizeof(int16_t));
840 else
841 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
842 (void*)((uintptr_t)request->data+request->donecount),
843 size / sizeof(int32_t));
844
845 if (request->transfersize < length) {
846 ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n",
847 ata_cmd2str(request), length, request->transfersize);
848 for (resid = request->transfersize; resid < length;
849 resid += sizeof(int16_t))
850 ATA_IDX_OUTW(ch, ATA_DATA, 0);
851 }
852}