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ata-dma.c (107562) ata-dma.c (108931)
1/*-
2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
1/*-
2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 107562 2002-12-03 20:20:44Z sos $
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 108931 2003-01-08 10:03:31Z sos $
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/ata.h>
34#include <sys/endian.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>

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1505{
1506 struct ata_channel *ch = atadev->channel;
1507 struct ata_dmastate *ds = &atadev->dmastate;
1508 struct ata_dmasetup_data_cb_args cba;
1509
1510 if (ds->flags & ATA_DS_ACTIVE)
1511 panic("ata_dmasetup: transfer active on this device!");
1512
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/ata.h>
34#include <sys/endian.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>

--- 1468 unchanged lines hidden (view full) ---

1505{
1506 struct ata_channel *ch = atadev->channel;
1507 struct ata_dmastate *ds = &atadev->dmastate;
1508 struct ata_dmasetup_data_cb_args cba;
1509
1510 if (ds->flags & ATA_DS_ACTIVE)
1511 panic("ata_dmasetup: transfer active on this device!");
1512
1513 switch(ch->chiptype) {
1514 case 0x0d38105a: /* Promise Fasttrak 66 */
1515 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1516 case 0x0d30105a: /* Promise OEM ATA 100 */
1517 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1518 ATA_OUTB(ch->r_bmio, 0x11,
1519 ATA_INB(ch->r_bmio, 0x11) | (atadev->unit ? 0x08 : 0x02));
1520
1521 ATA_OUTL(ch->r_bmio, (atadev->unit ? 0x24 : 0x20),
1522 (dir ? 0x05000000 : 0x06000000) | (count >> 1));
1523 break;
1524 }
1525
1513 cba.dmatab = ds->dmatab;
1514 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE);
1515 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count,
1516 ata_dmasetupd_cb, &cba, 0) || cba.error)
1517 return -1;
1518
1519 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE);
1520 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD :
1521 BUS_DMASYNC_PREWRITE);
1522
1523 ch->flags |= ATA_DMA_ACTIVE;
1526 cba.dmatab = ds->dmatab;
1527 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE);
1528 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count,
1529 ata_dmasetupd_cb, &cba, 0) || cba.error)
1530 return -1;
1531
1532 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE);
1533 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD :
1534 BUS_DMASYNC_PREWRITE);
1535
1536 ch->flags |= ATA_DMA_ACTIVE;
1524 ds->flags = ATA_DS_ACTIVE;
1525 if (dir)
1526 ds->flags |= ATA_DS_READ;
1537 ds->flags = dir ? (ATA_DS_ACTIVE | ATA_DS_READ) : ATA_DS_ACTIVE;
1527
1528 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab);
1529 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1530 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1538
1539 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab);
1540 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1541 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1531 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1532 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1542 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1543 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1533 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1544 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1534 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1545 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1535 return 0;
1536}
1537
1538int
1539ata_dmadone(struct ata_device *atadev)
1540{
1546 return 0;
1547}
1548
1549int
1550ata_dmadone(struct ata_device *atadev)
1551{
1541 struct ata_channel *ch;
1542 struct ata_dmastate *ds;
1552 struct ata_channel *ch = atadev->channel;
1553 struct ata_dmastate *ds = &atadev->dmastate;
1543 int error;
1544
1554 int error;
1555
1545 ch = atadev->channel;
1546 ds = &atadev->dmastate;
1556 switch(ch->chiptype) {
1557 case 0x0d38105a: /* Promise Fasttrak 66 */
1558 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1559 case 0x0d30105a: /* Promise OEM ATA 100 */
1560 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1561 ATA_OUTL(ch->r_bmio, (atadev->unit ? 0x24 : 0x20), 0);
1562 ATA_OUTB(ch->r_bmio, 0x11,
1563 ATA_INB(ch->r_bmio, 0x11) & ~(atadev->unit ? 0x08 : 0x02));
1564 break;
1565 }
1566
1547 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ?
1548 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1549 bus_dmamap_unload(ds->ddmatag, ds->ddmamap);
1567 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ?
1568 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1569 bus_dmamap_unload(ds->ddmatag, ds->ddmamap);
1550
1570
1551 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1552 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1553 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1554 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1555 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1556 ch->flags &= ~ATA_DMA_ACTIVE;
1557 ds->flags = 0;
1558 return (error & ATA_BMSTAT_MASK);

--- 209 unchanged lines hidden --- 		1571 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1572 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1573 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1574 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1575 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1576 ch->flags &= ~ATA_DMA_ACTIVE;
1577 ds->flags = 0;
1578 return (error & ATA_BMSTAT_MASK);

--- 209 unchanged lines hidden ---