29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <sys/disk.h> 38#include <sys/devicestat.h> 39#include <pci/pcivar.h> 40#include <machine/bus.h> 41#include <sys/rman.h> 42#include <dev/ata/ata-all.h> 43 44/* prototypes */ 45static void ata_dmacreate(struct ata_device *, int, int); 46static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int); 47static void ata_dmasetupc_cb(void *, bus_dma_segment_t *, int, int); 48static void cyrix_timing(struct ata_device *, int, int); 49static void promise_timing(struct ata_device *, int, int); 50static void hpt_timing(struct ata_device *, int, int); 51static int hpt_cable80(struct ata_device *); 52 53/* misc defines */ 54#define ATAPI_DEVICE(atadev) \ 55 ((atadev->unit == ATA_MASTER && \ 56 atadev->channel->devices & ATA_ATAPI_MASTER) || \ 57 (atadev->unit == ATA_SLAVE && \ 58 atadev->channel->devices & ATA_ATAPI_SLAVE)) 59 60#define MAXSEGSZ PAGE_SIZE 61#define MAXTABSZ PAGE_SIZE 62#define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS)) 63 64struct ata_dc_cb_args { 65 bus_addr_t maddr; 66 int error; 67}; 68 69static void 70ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 71{ 72 struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc; 73 74 if (!(cba->error = error)) 75 cba->maddr = segs[0].ds_addr; 76} 77 78int 79ata_dmaalloc(struct ata_device *atadev) 80{ 81 struct ata_channel *ch; 82 struct ata_dc_cb_args ccba; 83 struct ata_dmastate *ds; 84 int error; 85 86 ch = atadev->channel; 87 ds = &atadev->dmastate; 88 if (!ds->cdmatag) { 89 if ((error = bus_dma_tag_create(ch->dmatag, 1, PAGE_SIZE, 90 BUS_SPACE_MAXADDR_32BIT, 91 BUS_SPACE_MAXADDR, NULL, NULL, 92 MAXTABSZ, 1, MAXTABSZ, 93 BUS_DMA_ALLOCNOW, &ds->cdmatag))) 94 return error; 95 } 96 if (!ds->ddmatag) { 97 if ((error = bus_dma_tag_create(ch->dmatag, ch->alignment + 1, 0, 98 BUS_SPACE_MAXADDR_32BIT, 99 BUS_SPACE_MAXADDR, NULL, NULL, 100 MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ, 101 BUS_DMA_ALLOCNOW, &ds->ddmatag))) 102 return error; 103 } 104 if (!ds->mdmatab) { 105 if ((error = bus_dmamem_alloc(ds->cdmatag, (void **)&ds->dmatab, 0, 106 &ds->cdmamap))) 107 return error; 108 109 if ((error = bus_dmamap_load(ds->cdmatag, ds->cdmamap, ds->dmatab, 110 MAXTABSZ, ata_dmasetupc_cb, &ccba, 111 0)) != 0 || ccba.error != 0) { 112 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 113 return error; 114 } 115 ds->mdmatab = ccba.maddr; 116 } 117 if (!ds->ddmamap) { 118 if ((error = bus_dmamap_create(ds->ddmatag, 0, &ds->ddmamap)) != 0) 119 return error; 120 } 121 return 0; 122} 123 124void 125ata_dmafree(struct ata_device *atadev) 126{ 127 struct ata_dmastate *ds; 128 129 ds = &atadev->dmastate; 130 if (ds->mdmatab) { 131 bus_dmamap_unload(ds->cdmatag, ds->cdmamap); 132 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 133 ds->mdmatab = 0; 134 ds->cdmamap = NULL; 135 ds->dmatab = NULL; 136 } 137 if (ds->ddmamap) { 138 bus_dmamap_destroy(ds->ddmatag, ds->ddmamap); 139 ds->ddmamap = NULL; 140 } 141 if (ds->cdmatag) { 142 bus_dma_tag_destroy(ds->cdmatag); 143 ds->cdmatag = NULL; 144 } 145 if (ds->ddmatag) { 146 bus_dma_tag_destroy(ds->ddmatag); 147 ds->ddmatag = NULL; 148 } 149} 150 151void 152ata_dmafreetags(struct ata_channel *ch) 153{ 154 155 if (ch->dmatag) { 156 bus_dma_tag_destroy(ch->dmatag); 157 ch->dmatag = NULL; 158 } 159} 160 161static void 162ata_dmacreate(struct ata_device *atadev, int apiomode, int mode) 163{ 164 165 atadev->mode = mode; 166 if (!atadev->channel->dmatag) { 167 if (bus_dma_tag_create(NULL, 1, 0, 168 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 169 NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES, 170 BUS_SPACE_MAXSIZE_32BIT, 0, 171 &atadev->channel->dmatag)) { 172 ata_prtdev(atadev, "DMA tag allocation failed, disabling DMA\n"); 173 ata_dmainit(atadev, apiomode, -1, -1); 174 } 175 } 176} 177 178void 179ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode) 180{ 181 device_t parent = device_get_parent(atadev->channel->dev); 182 int chiptype = atadev->channel->chiptype; 183 int chiprev = pci_get_revid(parent); 184 int channel = atadev->channel->unit; 185 int device = ATA_DEV(atadev->unit); 186 int devno = (channel << 1) + device; 187 int error; 188 189 /* set our most pessimistic default mode */ 190 atadev->mode = ATA_PIO; 191 192 if (!atadev->channel->r_bmio) 193 return; 194 195 /* if simplex controller, only allow DMA on primary channel */ 196 if (channel == 1) { 197 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT, 198 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 199 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 200 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 201 ATA_BMSTAT_DMA_SIMPLEX) { 202 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 203 return; 204 } 205 } 206 207 /* DMA engine address alignment is usually 1 word (2 bytes) */ 208 atadev->channel->alignment = 0x1; 209 210#if 1 211 if (udmamode > 2 && !atadev->param->hwres_cblid) { 212 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 213 udmamode = 2; 214 } 215#endif 216 switch (chiptype) { 217 218 case 0x248a8086: /* Intel ICH3 mobile */ 219 case 0x248b8086: /* Intel ICH3 */ 220 case 0x244a8086: /* Intel ICH2 mobile */ 221 case 0x244b8086: /* Intel ICH2 */ 222 if (udmamode >= 5) { 223 int32_t mask48, new48; 224 int16_t word54; 225 226 word54 = pci_read_config(parent, 0x54, 2); 227 if (word54 & (0x10 << devno)) { 228 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 229 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 230 if (bootverbose) 231 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 232 (error) ? "failed" : "success"); 233 if (!error) { 234 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 235 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 236 pci_write_config(parent, 0x48, 237 (pci_read_config(parent, 0x48, 4) & 238 ~mask48) | new48, 4); 239 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 240 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 241 return; 242 } 243 } 244 } 245 /* make sure eventual ATA100 mode from the BIOS is disabled */ 246 pci_write_config(parent, 0x54, 247 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 248 /* FALLTHROUGH */ 249 250 case 0x24118086: /* Intel ICH */ 251 case 0x76018086: /* Intel ICH */ 252 if (udmamode >= 4) { 253 int32_t mask48, new48; 254 int16_t word54; 255 256 word54 = pci_read_config(parent, 0x54, 2); 257 if (word54 & (0x10 << devno)) { 258 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 259 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 260 if (bootverbose) 261 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 262 (error) ? "failed" : "success"); 263 if (!error) { 264 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 265 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 266 pci_write_config(parent, 0x48, 267 (pci_read_config(parent, 0x48, 4) & 268 ~mask48) | new48, 4); 269 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 270 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 271 return; 272 } 273 } 274 } 275 /* make sure eventual ATA66 mode from the BIOS is disabled */ 276 pci_write_config(parent, 0x54, 277 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 278 /* FALLTHROUGH */ 279 280 case 0x71118086: /* Intel PIIX4 */ 281 case 0x84CA8086: /* Intel PIIX4 */ 282 case 0x71998086: /* Intel PIIX4e */ 283 case 0x24218086: /* Intel ICH0 */ 284 if (udmamode >= 2) { 285 int32_t mask48, new48; 286 287 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 288 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 289 if (bootverbose) 290 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 291 (error) ? "failed" : "success"); 292 if (!error) { 293 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 294 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 295 pci_write_config(parent, 0x48, 296 (pci_read_config(parent, 0x48, 4) & 297 ~mask48) | new48, 4); 298 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 299 return; 300 } 301 } 302 /* make sure eventual ATA33 mode from the BIOS is disabled */ 303 pci_write_config(parent, 0x48, 304 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 305 /* FALLTHROUGH */ 306 307 case 0x70108086: /* Intel PIIX3 */ 308 if (wdmamode >= 2 && apiomode >= 4) { 309 int32_t mask40, new40, mask44, new44; 310 311 /* if SITRE not set doit for both channels */ 312 if (!((pci_read_config(parent, 0x40, 4) >> (channel<<8)) & 0x4000)){ 313 new40 = pci_read_config(parent, 0x40, 4); 314 new44 = pci_read_config(parent, 0x44, 4); 315 if (!(new40 & 0x00004000)) { 316 new44 &= ~0x0000000f; 317 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 318 } 319 if (!(new40 & 0x40000000)) { 320 new44 &= ~0x000000f0; 321 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 322 } 323 new40 |= 0x40004000; 324 pci_write_config(parent, 0x40, new40, 4); 325 pci_write_config(parent, 0x44, new44, 4); 326 } 327 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 328 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 329 if (bootverbose) 330 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 331 (error) ? "failed" : "success"); 332 if (!error) { 333 if (device == ATA_MASTER) { 334 mask40 = 0x0000330f; 335 new40 = 0x00002307; 336 mask44 = 0; 337 new44 = 0; 338 } 339 else { 340 mask40 = 0x000000f0; 341 new40 = 0x00000070; 342 mask44 = 0x0000000f; 343 new44 = 0x0000000b; 344 } 345 if (channel) { 346 mask40 <<= 16; 347 new40 <<= 16; 348 mask44 <<= 4; 349 new44 <<= 4; 350 } 351 pci_write_config(parent, 0x40, 352 (pci_read_config(parent, 0x40, 4) & ~mask40)| 353 new40, 4); 354 pci_write_config(parent, 0x44, 355 (pci_read_config(parent, 0x44, 4) & ~mask44)| 356 new44, 4); 357 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 358 return; 359 } 360 } 361 /* we could set PIO mode timings, but we assume the BIOS did that */ 362 break; 363 364 case 0x12308086: /* Intel PIIX */ 365 if (wdmamode >= 2 && apiomode >= 4) { 366 int32_t word40; 367 368 word40 = pci_read_config(parent, 0x40, 4); 369 word40 >>= channel * 16; 370 371 /* Check for timing config usable for DMA on controller */ 372 if (!((word40 & 0x3300) == 0x2300 && 373 ((word40 >> (device ? 4 : 0)) & 1) == 1)) 374 break; 375 376 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 377 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 378 if (bootverbose) 379 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 380 (error) ? "failed" : "success"); 381 if (!error) { 382 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 383 return; 384 } 385 } 386 break; 387 388 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 389 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 390 if (chiprev < 0xc2 && 391 atadev->channel->devices & ATA_ATAPI_MASTER && 392 atadev->channel->devices & ATA_ATAPI_SLAVE) { 393 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 394 break; 395 } 396 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4); 397 if (udmamode >= 5 && chiprev >= 0xc4) { 398 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 399 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 400 if (bootverbose) 401 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 402 (error) ? "failed" : "success"); 403 if (!error) { 404 int32_t word54 = pci_read_config(parent, 0x54, 4); 405 406 pci_write_config(parent, 0x4b, 407 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 408 word54 &= ~(0x000f000f << (devno << 2)); 409 word54 |= (0x000f0005 << (devno << 2)); 410 pci_write_config(parent, 0x54, word54, 4); 411 pci_write_config(parent, 0x53, 412 pci_read_config(parent, 0x53, 1) | 0x03, 1); 413 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 414 return; 415 } 416 } 417 if (udmamode >= 4 && chiprev >= 0xc2) { 418 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 419 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 420 if (bootverbose) 421 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 422 (error) ? "failed" : "success"); 423 if (!error) { 424 int32_t word54 = pci_read_config(parent, 0x54, 4); 425 426 pci_write_config(parent, 0x4b, 427 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 428 word54 &= ~(0x000f000f << (devno << 2)); 429 word54 |= (0x00080005 << (devno << 2)); 430 pci_write_config(parent, 0x54, word54, 4); 431 pci_write_config(parent, 0x53, 432 pci_read_config(parent, 0x53, 1) | 0x03, 1); 433 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 434 return; 435 } 436 } 437 if (udmamode >= 2 && chiprev >= 0x20) { 438 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 439 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 440 if (bootverbose) 441 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 442 (error) ? "failed" : "success"); 443 if (!error) { 444 int32_t word54 = pci_read_config(parent, 0x54, 4); 445 446 word54 &= ~(0x000f000f << (devno << 2)); 447 word54 |= (0x000a0005 << (devno << 2)); 448 pci_write_config(parent, 0x54, word54, 4); 449 pci_write_config(parent, 0x53, 450 pci_read_config(parent, 0x53, 1) | 0x03, 1); 451 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 452 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 453 return; 454 } 455 } 456 457 /* make sure eventual UDMA mode from the BIOS is disabled */ 458 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 459 ~(0x0008 << (devno << 2)), 2); 460 461 if (wdmamode >= 2 && apiomode >= 4) { 462 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 463 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 464 if (bootverbose) 465 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 466 (error) ? "failed" : "success"); 467 if (!error) { 468 pci_write_config(parent, 0x53, 469 pci_read_config(parent, 0x53, 1) | 0x03, 1); 470 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 471 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 472 return; 473 } 474 } 475 pci_write_config(parent, 0x53, 476 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 477 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 478 ATA_PIO0 + apiomode, 479 ATA_C_F_SETXFER, ATA_WAIT_READY); 480 if (bootverbose) 481 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n", 482 (error) ? "failed" : "success", 483 (apiomode >= 0) ? apiomode : 0); 484 if (!error) { 485 int32_t word54 = pci_read_config(parent, 0x54, 4); 486 int32_t timing; 487 488 switch(ATA_PIO0 + apiomode) { 489 case ATA_PIO0: timing = 0x006d0003; 490 case ATA_PIO1: timing = 0x00580002; 491 case ATA_PIO2: timing = 0x00440001; 492 case ATA_PIO3: timing = 0x00330001; 493 case ATA_PIO4: timing = 0x00310001; 494 default: timing = 0x006d0003; 495 } 496 pci_write_config(parent, 0x58 + (channel << 2), timing, 4); 497 word54 &= ~(0x000f000f << (devno << 2)); 498 word54 |= (0x00000004 << (devno << 2)); 499 pci_write_config(parent, 0x54, word54, 4); 500 atadev->mode = ATA_PIO0 + apiomode; 501 return; 502 } 503 break; 504 505 case 0x74411022: /* AMD 768 */ 506 case 0x74111022: /* AMD 766 */ 507 if (udmamode >= 5) { 508 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 509 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 510 if (bootverbose) 511 ata_prtdev(atadev, "%s setting UDMA5 on AMD chip\n", 512 (error) ? "failed" : "success"); 513 if (!error) { 514 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 515 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 516 return; 517 } 518 } 519 /* FALLTHROUGH */ 520 521 case 0x74091022: /* AMD 756 */ 522 if (udmamode >= 4) { 523 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 524 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 525 if (bootverbose) 526 ata_prtdev(atadev, "%s setting UDMA4 on AMD chip\n", 527 (error) ? "failed" : "success"); 528 if (!error) { 529 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 530 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 531 return; 532 } 533 } 534 goto via_82c586; 535 536 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 537 { 538 int via_modes[4][7] = { 539 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */ 540 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */ 541 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */ 542 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }}; /* ATA133 */ 543 int *reg_val = NULL; 544 545 if (ata_find_dev(parent, 0x31471106, 0)) { /* 8233a */ 546 udmamode = imin(udmamode, 6); 547 reg_val = via_modes[3]; 548 } 549 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 550 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 551 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 552 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 553 udmamode = imin(udmamode, 5); 554 reg_val = via_modes[2]; 555 } 556 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 557 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 558 udmamode = imin(udmamode, 4); 559 reg_val = via_modes[1]; 560 } 561 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */ 562 udmamode = imin(udmamode, 2); 563 reg_val = via_modes[1]; 564 } 565 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 566 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 567via_82c586: 568 udmamode = imin(udmamode, 2); 569 reg_val = via_modes[0]; 570 } 571 else 572 udmamode = 0; 573 574 if (udmamode >= 6) { 575 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 576 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 577 if (bootverbose) 578 ata_prtdev(atadev, "%s setting UDMA6 on VIA chip\n", 579 (error) ? "failed" : "success"); 580 if (!error) { 581 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 582 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 583 return; 584 } 585 } 586 if (udmamode >= 5) { 587 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 588 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 589 if (bootverbose) 590 ata_prtdev(atadev, "%s setting UDMA5 on VIA chip\n", 591 (error) ? "failed" : "success"); 592 if (!error) { 593 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 594 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 595 return; 596 } 597 } 598 if (udmamode >= 4) { 599 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 600 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 601 if (bootverbose) 602 ata_prtdev(atadev, "%s setting UDMA4 on VIA chip\n", 603 (error) ? "failed" : "success"); 604 if (!error) { 605 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 606 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 607 return; 608 } 609 } 610 if (udmamode >= 2) { 611 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 612 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 613 if (bootverbose) 614 ata_prtdev(atadev, "%s setting UDMA2 on VIA chip\n", 615 (error) ? "failed" : "success"); 616 if (!error) { 617 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 618 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 619 return; 620 } 621 } 622 623 } 624 if (wdmamode >= 2 && apiomode >= 4) { 625 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 626 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 627 if (bootverbose) 628 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 629 (error) ? "failed" : "success", 630 (chiptype == 0x74091022) ? "AMD" : "VIA"); 631 if (!error) { 632 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 633 pci_write_config(parent, 0x4b - devno, 0x31, 1); 634 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 635 return; 636 } 637 } 638 /* we could set PIO mode timings, but we assume the BIOS did that */ 639 break; 640 641 case 0x55131039: /* SiS 5591 */ 642 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 643 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */ 644 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */ 645 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */ 646 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */ 647 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */ 648 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */ 649 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */ 650 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */ 651 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */ 652 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */ 653 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */ 654 int8_t reg = 0x40 + (devno << 1); 655 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 656 657 if (udmamode >= 5) { 658 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 659 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 660 if (bootverbose) 661 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 662 (error) ? "failed" : "success"); 663 if (!error) { 664 pci_write_config(parent, reg, val | 0x8000, 2); 665 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 666 return; 667 } 668 } 669 if (udmamode >= 4) { 670 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 671 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 672 if (bootverbose) 673 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 674 (error) ? "failed" : "success"); 675 if (!error) { 676 pci_write_config(parent, reg, val | 0x9000, 2); 677 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 678 return; 679 } 680 } 681 if (udmamode >= 2) { 682 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 683 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 684 if (bootverbose) 685 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 686 (error) ? "failed" : "success"); 687 if (!error) { 688 pci_write_config(parent, reg, val | 0xb000, 2); 689 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 690 return; 691 } 692 } 693 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 694 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 695 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 696 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 697 int8_t reg = 0x40 + (devno << 1); 698 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 699 700 if (udmamode >= 4) { 701 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 702 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 703 if (bootverbose) 704 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 705 (error) ? "failed" : "success"); 706 if (!error) { 707 pci_write_config(parent, reg, val | 0x9000, 2); 708 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 709 return; 710 } 711 } 712 if (udmamode >= 2) { 713 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 714 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 715 if (bootverbose) 716 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 717 (error) ? "failed" : "success"); 718 if (!error) { 719 pci_write_config(parent, reg, val | 0xa000, 2); 720 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 721 return; 722 } 723 } 724 } else if (udmamode >= 2 && chiprev > 0xc1) { 725 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 726 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 727 if (bootverbose) 728 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 729 (error) ? "failed" : "success"); 730 if (!error) { 731 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 732 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 733 return; 734 } 735 } 736 if (wdmamode >=2 && apiomode >= 4) { 737 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 738 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 739 if (bootverbose) 740 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 741 (error) ? "failed" : "success"); 742 if (!error) { 743 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 744 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 745 return; 746 } 747 } 748 /* we could set PIO mode timings, but we assume the BIOS did that */ 749 break; 750 751 case 0x06491095: /* CMD 649 ATA100 controller */ 752 if (udmamode >= 5) { 753 u_int8_t umode; 754 755 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 756 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 757 if (bootverbose) 758 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 759 (error) ? "failed" : "success"); 760 if (!error) { 761 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 762 umode &= ~(device ? 0xca : 0x35); 763 umode |= (device ? 0x0a : 0x05); 764 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 765 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 766 return; 767 } 768 } 769 /* FALLTHROUGH */ 770 771 case 0x06481095: /* CMD 648 ATA66 controller */ 772 if (udmamode >= 4) { 773 u_int8_t umode; 774 775 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 776 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 777 if (bootverbose) 778 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 779 (error) ? "failed" : "success"); 780 if (!error) { 781 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 782 umode &= ~(device ? 0xca : 0x35); 783 umode |= (device ? 0x4a : 0x15); 784 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 785 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 786 return; 787 } 788 } 789 if (udmamode >= 2) { 790 u_int8_t umode; 791 792 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 793 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 794 if (bootverbose) 795 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 796 (error) ? "failed" : "success"); 797 if (!error) { 798 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 799 umode &= ~(device ? 0xca : 0x35); 800 umode |= (device ? 0x42 : 0x11); 801 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 802 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 803 return; 804 } 805 } 806 /* make sure eventual UDMA mode from the BIOS is disabled */ 807 pci_write_config(parent, channel ? 0x7b : 0x73, 808 pci_read_config(parent, channel ? 0x7b : 0x73, 1) & 809 ~(device ? 0xca : 0x53), 1); 810 /* FALLTHROUGH */ 811 812 case 0x06461095: /* CMD 646 ATA controller */ 813 if (wdmamode >= 2 && apiomode >= 4) { 814 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 815 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 816 if (bootverbose) 817 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 818 error ? "failed" : "success"); 819 if (!error) { 820 int32_t offset = (devno < 3) ? (devno << 1) : 7; 821 822 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 823 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 824 return; 825 } 826 } 827 /* we could set PIO mode timings, but we assume the BIOS did that */ 828 break; 829 830 case 0xc6931080: /* Cypress 82c693 ATA controller */ 831 if (wdmamode >= 2 && apiomode >= 4) { 832 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 833 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 834 if (bootverbose) 835 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 836 error ? "failed" : "success"); 837 if (!error) { 838 pci_write_config(atadev->channel->dev, 839 channel ? 0x4e:0x4c, 0x2020, 2); 840 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 841 return; 842 } 843 } 844 /* we could set PIO mode timings, but we assume the BIOS did that */ 845 break; 846 847 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 848 atadev->channel->alignment = 0xf; 849 if (udmamode >= 2) { 850 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 851 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 852 if (bootverbose) 853 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 854 (error) ? "failed" : "success"); 855 if (!error) { 856 cyrix_timing(atadev, devno, ATA_UDMA2); 857 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 858 return; 859 } 860 } 861 if (wdmamode >= 2 && apiomode >= 4) { 862 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 863 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 864 if (bootverbose) 865 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 866 (error) ? "failed" : "success"); 867 if (!error) { 868 cyrix_timing(atadev, devno, ATA_WDMA2); 869 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 870 return; 871 } 872 } 873 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 874 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 875 ATA_WAIT_READY); 876 if (bootverbose) 877 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 878 (error) ? "failed" : "success", 879 ata_mode2str(ATA_PIO0 + apiomode)); 880 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode); 881 atadev->mode = ATA_PIO0 + apiomode; 882 return; 883 884 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 885 if (udmamode >= 5 && chiprev >= 0x92) { 886 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 887 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 888 if (bootverbose) 889 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 890 (error) ? "failed" : "success"); 891 if (!error) { 892 u_int16_t reg56; 893 894 pci_write_config(parent, 0x54, 895 pci_read_config(parent, 0x54, 1) | 896 (0x01 << devno), 1); 897 reg56 = pci_read_config(parent, 0x56, 2); 898 reg56 &= ~(0xf << (devno * 4)); 899 reg56 |= (0x5 << (devno * 4)); 900 pci_write_config(parent, 0x56, reg56, 2); 901 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 902 return; 903 } 904 } 905 if (udmamode >= 4) { 906 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 907 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 908 if (bootverbose) 909 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 910 (error) ? "failed" : "success"); 911 if (!error) { 912 u_int16_t reg56; 913 914 pci_write_config(parent, 0x54, 915 pci_read_config(parent, 0x54, 1) | 916 (0x01 << devno), 1); 917 reg56 = pci_read_config(parent, 0x56, 2); 918 reg56 &= ~(0xf << (devno * 4)); 919 reg56 |= (0x4 << (devno * 4)); 920 pci_write_config(parent, 0x56, reg56, 2); 921 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 922 return; 923 } 924 } 925 /* FALLTHROUGH */ 926 927 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 928 if (udmamode >= 2) { 929 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 930 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 931 if (bootverbose) 932 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 933 (error) ? "failed" : "success"); 934 if (!error) { 935 u_int16_t reg56; 936 937 pci_write_config(parent, 0x54, 938 pci_read_config(parent, 0x54, 1) | 939 (0x01 << devno), 1); 940 reg56 = pci_read_config(parent, 0x56, 2); 941 reg56 &= ~(0xf << (devno * 4)); 942 reg56 |= (0x2 << (devno * 4)); 943 pci_write_config(parent, 0x56, reg56, 2); 944 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 945 return; 946 } 947 } 948 if (wdmamode >= 2 && apiomode >= 4) { 949 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 950 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 951 if (bootverbose) 952 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 953 (error) ? "failed" : "success"); 954 if (!error) { 955 int offset = devno ^ 0x01; 956 int word44 = pci_read_config(parent, 0x44, 4); 957 958 pci_write_config(parent, 0x54, 959 pci_read_config(parent, 0x54, 1) & 960 ~(0x01 << devno), 1); 961 word44 &= ~(0xff << (offset << 8)); 962 word44 |= (0x20 << (offset << 8)); 963 pci_write_config(parent, 0x44, 0x20, 4); 964 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 965 return; 966 } 967 } 968 /* we could set PIO mode timings, but we assume the BIOS did that */ 969 break; 970 971 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 972 case 0x5275105a: /* Promise TX2 ATA133 controllers */
|
974 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 975 if (udmamode >= 6 && 976 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 977 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 978 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 979 if (bootverbose) 980 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 981 (error) ? "failed" : "success"); 982 if (!error) { 983 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 984 return; 985 } 986 } 987 /* FALLTHROUGH */ 988 989 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 990 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 991 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 992 if (udmamode >= 5 && 993 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 994 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 995 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 996 if (bootverbose) 997 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 998 (error) ? "failed" : "success"); 999 if (!error) { 1000 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1001 return; 1002 } 1003 } 1004 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1005 if (udmamode >= 4 && 1006 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1007 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1008 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1009 if (bootverbose) 1010 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1011 (error) ? "failed" : "success"); 1012 if (!error) { 1013 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1014 return; 1015 } 1016 } 1017 if (udmamode >= 2) { 1018 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1019 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1020 if (bootverbose) 1021 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 1022 (error) ? "failed" : "success"); 1023 if (!error) { 1024 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1025 return; 1026 } 1027 } 1028 if (wdmamode >= 2 && apiomode >= 4) { 1029 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1030 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1031 if (bootverbose) 1032 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1033 (error) ? "failed" : "success"); 1034 if (!error) { 1035 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1036 return; 1037 } 1038 } 1039 break; 1040 1041 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 1042 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 1043 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && 1044 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1045 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1046 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1047 if (bootverbose) 1048 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1049 (error) ? "failed" : "success"); 1050 if (!error) { 1051 promise_timing(atadev, devno, ATA_UDMA5); 1052 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1053 return; 1054 } 1055 } 1056 /* FALLTHROUGH */ 1057 1058 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 1059 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && 1060 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1061 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1062 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1063 if (bootverbose) 1064 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1065 (error) ? "failed" : "success"); 1066 if (!error) { 1067 promise_timing(atadev, devno, ATA_UDMA4); 1068 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1069 return; 1070 } 1071 } 1072 /* FALLTHROUGH */ 1073 1074 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 1075 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1076 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1077 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1078 if (bootverbose) 1079 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 1080 (error) ? "failed" : "success"); 1081 if (!error) { 1082 promise_timing(atadev, devno, ATA_UDMA2); 1083 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1084 return; 1085 } 1086 } 1087 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1088 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1089 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1090 if (bootverbose) 1091 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1092 (error) ? "failed" : "success"); 1093 if (!error) { 1094 promise_timing(atadev, devno, ATA_WDMA2); 1095 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1096 return; 1097 } 1098 } 1099 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1100 ATA_PIO0 + apiomode, 1101 ATA_C_F_SETXFER, ATA_WAIT_READY); 1102 if (bootverbose) 1103 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 1104 (error) ? "failed" : "success", 1105 (apiomode >= 0) ? apiomode : 0); 1106 promise_timing(atadev, devno, ATA_PIO0 + apiomode); 1107 atadev->mode = ATA_PIO0 + apiomode; 1108 return; 1109 1110 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 1111 case 0x00051103: /* HighPoint HPT372 controllers */ 1112 case 0x00081103: /* HighPoint HPT374 controllers */ 1113 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) && 1114 ((chiptype == 0x00041103 && chiprev >= 0x05) || 1115 (chiptype == 0x00051103 && chiprev >= 0x01) || 1116 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1117 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1118 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1119 if (bootverbose) 1120 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 1121 (error) ? "failed" : "success"); 1122 if (!error) { 1123 hpt_timing(atadev, devno, ATA_UDMA6); 1124 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1125 return; 1126 } 1127 } 1128 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) && 1129 ((chiptype == 0x00041103 && chiprev >= 0x03) || 1130 (chiptype == 0x00051103 && chiprev >= 0x01) || 1131 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1132 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1133 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1134 if (bootverbose) 1135 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 1136 (error) ? "failed" : "success"); 1137 if (!error) { 1138 hpt_timing(atadev, devno, ATA_UDMA5); 1139 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1140 return; 1141 } 1142 } 1143 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) { 1144 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1145 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1146 if (bootverbose) 1147 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1148 (error) ? "failed" : "success"); 1149 if (!error) { 1150 hpt_timing(atadev, devno, ATA_UDMA4); 1151 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1152 return; 1153 } 1154 } 1155 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1156 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1157 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1158 if (bootverbose) 1159 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1160 (error) ? "failed" : "success"); 1161 if (!error) { 1162 hpt_timing(atadev, devno, ATA_UDMA2); 1163 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1164 return; 1165 } 1166 } 1167 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1168 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1169 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1170 if (bootverbose) 1171 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1172 (error) ? "failed" : "success"); 1173 if (!error) { 1174 hpt_timing(atadev, devno, ATA_WDMA2); 1175 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1176 return; 1177 } 1178 } 1179 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1180 ATA_PIO0 + apiomode, 1181 ATA_C_F_SETXFER, ATA_WAIT_READY); 1182 if (bootverbose) 1183 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1184 (error) ? "failed" : "success", 1185 (apiomode >= 0) ? apiomode : 0); 1186 hpt_timing(atadev, devno, ATA_PIO0 + apiomode); 1187 atadev->mode = ATA_PIO0 + apiomode; 1188 return; 1189 1190 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1191 if (wdmamode >= 0 && 1192 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1193 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) 1194 ata_dmacreate(atadev, apiomode, ATA_DMA); 1195 else 1196 atadev->mode = ATA_PIO; 1197 return; 1198 1199 default: /* unknown controller chip */ 1200 /* better not try generic DMA on ATAPI devices it almost never works */ 1201 if (ATAPI_DEVICE(atadev)) 1202 break; 1203 1204 /* if controller says its setup for DMA take the easy way out */ 1205 /* the downside is we dont know what DMA mode we are in */ 1206 if ((udmamode >= 0 || wdmamode >= 2) && 1207 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1208 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 1209 ata_dmacreate(atadev, apiomode, ATA_DMA); 1210 return; 1211 } 1212 1213 /* well, we have no support for this, but try anyways */ 1214 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) { 1215 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1216 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1217 if (bootverbose) 1218 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1219 (error) ? "failed" : "success"); 1220 if (!error) { 1221 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1222 return; 1223 } 1224 } 1225 } 1226 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1227 ATA_C_F_SETXFER, ATA_WAIT_READY); 1228 if (bootverbose) 1229 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1230 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1231 if (!error) 1232 atadev->mode = ATA_PIO0 + apiomode; 1233 else { 1234 if (bootverbose) 1235 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1236 atadev->mode = ATA_PIO; 1237 } 1238} 1239 1240struct ata_dmasetup_data_cb_args { 1241 struct ata_dmaentry *dmatab; 1242 int error; 1243}; 1244 1245static void 1246ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1247{ 1248 struct ata_dmasetup_data_cb_args *cba = 1249 (struct ata_dmasetup_data_cb_args *)xsc; 1250 bus_size_t cnt; 1251 u_int32_t lastcount; 1252 int i, j; 1253 1254 cba->error = error; 1255 if (error != 0) 1256 return; 1257 lastcount = j = 0; 1258 for (i = 0; i < nsegs; i++) { 1259 /* 1260 * A maximum segment size was specified for bus_dma_tag_create, but 1261 * some busdma code does not seem to honor this, so fix up if needed. 1262 */ 1263 for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) { 1264 cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt); 1265 lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff; 1266 cba->dmatab[j].count = htole32(lastcount); 1267 } 1268 } 1269 cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT); 1270} 1271 1272int 1273ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count) 1274{ 1275 struct ata_channel *ch = atadev->channel; 1276 struct ata_dmastate *ds = &atadev->dmastate; 1277 struct ata_dmasetup_data_cb_args cba; 1278 1279 if (ds->flags & ATA_DS_ACTIVE) 1280 panic("ata_dmasetup: transfer active on this device!"); 1281 1282 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1283 ata_prtdev(atadev, "non aligned DMA transfer attempted\n"); 1284 return -1; 1285 } 1286 1287 if (!count) { 1288 ata_prtdev(atadev, "zero length DMA transfer attempted\n"); 1289 return -1; 1290 } 1291 1292 cba.dmatab = ds->dmatab; 1293 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count, 1294 ata_dmasetupd_cb, &cba, 0) || cba.error) 1295 ds->flags = ATA_DS_ACTIVE; 1296 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE); 1297 1298 return 0; 1299} 1300 1301void 1302ata_dmastart(struct ata_device *atadev, int dir) 1303{ 1304 struct ata_channel *ch; 1305 struct ata_dmastate *ds; 1306 1307 ch = atadev->channel; 1308 ds = &atadev->dmastate; 1309 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD : 1310 BUS_DMASYNC_PREWRITE); 1311 if (dir) 1312 ds->flags |= ATA_DS_READ; 1313 ch->flags |= ATA_DMA_ACTIVE; 1314 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab); 1315 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1316 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1317 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1318 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1319 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1320 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1321} 1322 1323int 1324ata_dmadone(struct ata_device *atadev) 1325{ 1326 struct ata_channel *ch; 1327 struct ata_dmastate *ds; 1328 int error; 1329 1330 ch = atadev->channel; 1331 ds = &atadev->dmastate; 1332 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ? 1333 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1334 bus_dmamap_unload(ds->ddmatag, ds->ddmamap); 1335 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1336 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1337 ch->flags &= ~ATA_DMA_ACTIVE; 1338 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1339 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1340 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1341 ds->flags = 0; 1342 return error & ATA_BMSTAT_MASK; 1343} 1344 1345int 1346ata_dmastatus(struct ata_channel *ch) 1347{ 1348 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1349} 1350 1351static void 1352cyrix_timing(struct ata_device *atadev, int devno, int mode) 1353{ 1354 u_int32_t reg20 = 0x0000e132; 1355 u_int32_t reg24 = 0x00017771; 1356 1357 switch (mode) { 1358 case ATA_PIO0: reg20 = 0x0000e132; break; 1359 case ATA_PIO1: reg20 = 0x00018121; break; 1360 case ATA_PIO2: reg20 = 0x00024020; break; 1361 case ATA_PIO3: reg20 = 0x00032010; break; 1362 case ATA_PIO4: reg20 = 0x00040010; break; 1363 case ATA_WDMA2: reg24 = 0x00002020; break; 1364 case ATA_UDMA2: reg24 = 0x00911030; break; 1365 } 1366 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20); 1367 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24); 1368} 1369 1370static void 1371promise_timing(struct ata_device *atadev, int devno, int mode) 1372{ 1373 u_int32_t timing = 0; 1374 /* XXX: Endianess */ 1375 struct promise_timing { 1376 u_int8_t pa:4; 1377 u_int8_t prefetch:1; 1378 u_int8_t iordy:1; 1379 u_int8_t errdy:1; 1380 u_int8_t syncin:1; 1381 u_int8_t pb:5; 1382 u_int8_t mb:3; 1383 u_int8_t mc:4; 1384 u_int8_t dmaw:1; 1385 u_int8_t dmar:1; 1386 u_int8_t iordyp:1; 1387 u_int8_t dmarqp:1; 1388 u_int8_t reserved:8; 1389 } *t = (struct promise_timing*)&timing; 1390 1391 t->iordy = 1; t->iordyp = 1; 1392 if (mode >= ATA_DMA) { 1393 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1394 } 1395 1396 switch (atadev->channel->chiptype) { 1397 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1398 switch (mode) { 1399 default: 1400 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1401 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1402 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1403 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1404 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1405 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1406 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1407 } 1408 break; 1409 1410 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1411 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1412 case 0x0d30105a: /* Promise OEM ATA 100 */ 1413 switch (mode) { 1414 default: 1415 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1416 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1417 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1418 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1419 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1420 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1421 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1422 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1423 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1424 } 1425 break; 1426 } 1427 pci_write_config(device_get_parent(atadev->channel->dev), 1428 0x60 + (devno << 2), timing, 4); 1429} 1430 1431static void 1432hpt_timing(struct ata_device *atadev, int devno, int mode) 1433{ 1434 device_t parent = device_get_parent(atadev->channel->dev); 1435 u_int32_t chiptype = atadev->channel->chiptype; 1436 int chiprev = pci_get_revid(parent); 1437 u_int32_t timing; 1438 1439 if (chiptype == 0x00081103 && chiprev >= 0x07) { 1440 switch (mode) { /* HPT374 */ 1441 case ATA_PIO0: timing = 0x0ac1f48a; break; 1442 case ATA_PIO1: timing = 0x0ac1f465; break; 1443 case ATA_PIO2: timing = 0x0a81f454; break; 1444 case ATA_PIO3: timing = 0x0a81f443; break; 1445 case ATA_PIO4: timing = 0x0a81f442; break; 1446 case ATA_WDMA2: timing = 0x22808242; break; 1447 case ATA_UDMA2: timing = 0x120c8242; break; 1448 case ATA_UDMA4: timing = 0x12ac8242; break; 1449 case ATA_UDMA5: timing = 0x12848242; break; 1450 case ATA_UDMA6: timing = 0x12808242; break; 1451 default: timing = 0x0d029d5e; 1452 } 1453 } 1454 else if ((chiptype == 0x00041103 && chiprev >= 0x05) || 1455 (chiptype == 0x00051103 && chiprev >= 0x01)) { 1456 switch (mode) { /* HPT372 */ 1457 case ATA_PIO0: timing = 0x0d029d5e; break; 1458 case ATA_PIO1: timing = 0x0d029d26; break; 1459 case ATA_PIO2: timing = 0x0c829ca6; break; 1460 case ATA_PIO3: timing = 0x0c829c84; break; 1461 case ATA_PIO4: timing = 0x0c829c62; break; 1462 case ATA_WDMA2: timing = 0x2c829262; break; 1463 case ATA_UDMA2: timing = 0x1c91dc62; break; 1464 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1465 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1466 case ATA_UDMA6: timing = 0x1c81dc62; break; 1467 default: timing = 0x0d029d5e; 1468 } 1469 } 1470 else if (chiptype == 0x00041103 && chiprev >= 0x03) { 1471 switch (mode) { /* HPT370 */ 1472 case ATA_PIO0: timing = 0x06914e57; break; 1473 case ATA_PIO1: timing = 0x06914e43; break; 1474 case ATA_PIO2: timing = 0x06514e33; break; 1475 case ATA_PIO3: timing = 0x06514e22; break; 1476 case ATA_PIO4: timing = 0x06514e21; break; 1477 case ATA_WDMA2: timing = 0x26514e21; break; 1478 case ATA_UDMA2: timing = 0x16494e31; break; 1479 case ATA_UDMA4: timing = 0x16454e31; break; 1480 case ATA_UDMA5: timing = 0x16454e31; break; 1481 default: timing = 0x06514e57; 1482 } 1483 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1484 } 1485 else { /* HPT36[68] */ 1486 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1487 case 0x85: /* 25Mhz */ 1488 switch (mode) { 1489 case ATA_PIO0: timing = 0x40d08585; break; 1490 case ATA_PIO1: timing = 0x40d08572; break; 1491 case ATA_PIO2: timing = 0x40ca8542; break; 1492 case ATA_PIO3: timing = 0x40ca8532; break; 1493 case ATA_PIO4: timing = 0x40ca8521; break; 1494 case ATA_WDMA2: timing = 0x20ca8521; break; 1495 case ATA_UDMA2: timing = 0x10cf8521; break; 1496 case ATA_UDMA4: timing = 0x10c98521; break; 1497 default: timing = 0x01208585; 1498 } 1499 break; 1500 default: 1501 case 0xa7: /* 33MHz */ 1502 switch (mode) { 1503 case ATA_PIO0: timing = 0x40d0a7aa; break; 1504 case ATA_PIO1: timing = 0x40d0a7a3; break; 1505 case ATA_PIO2: timing = 0x40d0a753; break; 1506 case ATA_PIO3: timing = 0x40c8a742; break; 1507 case ATA_PIO4: timing = 0x40c8a731; break; 1508 case ATA_WDMA2: timing = 0x20c8a731; break; 1509 case ATA_UDMA2: timing = 0x10caa731; break; 1510 case ATA_UDMA4: timing = 0x10c9a731; break; 1511 default: timing = 0x0120a7a7; 1512 } 1513 break; 1514 case 0xd9: /* 40Mhz */ 1515 switch (mode) { 1516 case ATA_PIO0: timing = 0x4018d9d9; break; 1517 case ATA_PIO1: timing = 0x4010d9c7; break; 1518 case ATA_PIO2: timing = 0x4010d997; break; 1519 case ATA_PIO3: timing = 0x4010d974; break; 1520 case ATA_PIO4: timing = 0x4008d963; break; 1521 case ATA_WDMA2: timing = 0x2008d943; break; 1522 case ATA_UDMA2: timing = 0x100bd943; break; 1523 case ATA_UDMA4: timing = 0x100fd943; break; 1524 default: timing = 0x0120d9d9; 1525 } 1526 } 1527 } 1528 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1529} 1530 1531static int 1532hpt_cable80(struct ata_device *atadev) 1533{ 1534 device_t parent = device_get_parent(atadev->channel->dev); 1535 u_int8_t reg, val, res; 1536 1537 if (atadev->channel->chiptype==0x00081103 && pci_get_function(parent)==1) { 1538 reg = atadev->channel->unit ? 0x57 : 0x53; 1539 val = pci_read_config(parent, reg, 1); 1540 pci_write_config(parent, reg, val | 0x80, 1); 1541 } 1542 else { 1543 reg = 0x5b; 1544 val = pci_read_config(parent, reg, 1); 1545 pci_write_config(parent, reg, val & 0xfe, 1); 1546 } 1547 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); 1548 pci_write_config(parent, reg, val, 1); 1549 return !res; 1550}
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