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1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 56988 2000-02-04 10:20:22Z sos $
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 57325 2000-02-18 20:57:33Z sos $
29 */
30
31#include "pci.h"
32#include "apm.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/buf.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>
37#include <sys/disk.h>
38#include <sys/devicestat.h>
39#include <vm/vm.h>
40#include <vm/pmap.h>
41#if NPCI > 0
42#include <pci/pcivar.h>
43#endif
45#if NAPM > 0
46#include <machine/apm_bios.h>
47#endif
44#include <dev/ata/ata-all.h>
45#include <dev/ata/ata-disk.h>
46
47#if NPCI > 0
48
49/* prototypes */
50static void promise_timing(struct ata_softc *, int32_t, int32_t);
51static void hpt366_timing(struct ata_softc *, int32_t, int32_t);
52
53/* misc defines */
54#ifdef __alpha__
55#undef vtophys
56#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
57#endif
58
59void
60ata_dmainit(struct ata_softc *scp, int32_t device,
61 int32_t apiomode, int32_t wdmamode, int32_t udmamode)
62{
63 device_t parent = device_get_parent(scp->dev);
64 int32_t devno = (scp->unit << 1) + ATA_DEV(device);
65 int32_t error;
66
67 /* set our most pessimistic default mode */
68 scp->mode[ATA_DEV(device)] = ATA_PIO;
69
70 if (!scp->bmaddr)
71 return;

--- 36 unchanged lines hidden (view full) ---

108 if (bootverbose)
109 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
110 (error) ? "failed" : "success",
111 (scp->chiptype == 0x24118086) ? "ICH" :
112 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
113 if (!error) {
114 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
115 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
119 pci_write_config(scp->dev, 0x48,
120 (pci_read_config(scp->dev, 0x48, 4) &
116 pci_write_config(parent, 0x48,
117 (pci_read_config(parent, 0x48, 4) &
118 ~mask48) | new48, 4);
119 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
120 return;
121 }
122 }
123 /* FALLTHROUGH */
124
125 case 0x70108086: /* Intel PIIX3 */
126 if (wdmamode >= 2 && apiomode >= 4) {
127 int32_t mask40, new40, mask44, new44;
128
129 /* if SITRE not set doit for both channels */
133 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){
134 new40 = pci_read_config(scp->dev, 0x40, 4);
135 new44 = pci_read_config(scp->dev, 0x44, 4);
130 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
131 new40 = pci_read_config(parent, 0x40, 4);
132 new44 = pci_read_config(parent, 0x44, 4);
133 if (!(new40 & 0x00004000)) {
134 new44 &= ~0x0000000f;
135 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
136 }
137 if (!(new40 & 0x40000000)) {
138 new44 &= ~0x000000f0;
139 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
140 }
141 new40 |= 0x40004000;
145 pci_write_config(scp->dev, 0x40, new40, 4);
146 pci_write_config(scp->dev, 0x44, new44, 4);
142 pci_write_config(parent, 0x40, new40, 4);
143 pci_write_config(parent, 0x44, new44, 4);
144 }
145 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
146 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
147 if (bootverbose)
148 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
149 (error) ? "failed" : "success",
150 (scp->chiptype == 0x70108086) ? "PIIX3" :
151 (scp->chiptype == 0x24118086) ? "ICH" :

--- 12 unchanged lines hidden (view full) ---

164 new44 = 0x0000000b;
165 }
166 if (scp->unit) {
167 mask40 <<= 16;
168 new40 <<= 16;
169 mask44 <<= 4;
170 new44 <<= 4;
171 }
175 pci_write_config(scp->dev, 0x40,
176 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)|
172 pci_write_config(parent, 0x40,
173 (pci_read_config(parent, 0x40, 4) & ~mask40)|
174 new40, 4);
178 pci_write_config(scp->dev, 0x44,
179 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)|
175 pci_write_config(parent, 0x44,
176 (pci_read_config(parent, 0x44, 4) & ~mask44)|
177 new44, 4);
178 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
179 return;
180 }
181 }
182 /* we could set PIO mode timings, but we assume the BIOS did that */
183 break;
184
185 case 0x12308086: /* Intel PIIX */
186 if (wdmamode >= 2 && apiomode >= 4) {
187 int32_t word40;
188
192 word40 = pci_read_config(scp->dev, 0x40, 4);
189 word40 = pci_read_config(parent, 0x40, 4);
190 word40 >>= scp->unit * 16;
191
192 /* Check for timing config usable for DMA on controller */
193 if (!((word40 & 0x3300) == 0x2300 &&
194 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
195 break;
196
197 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,

--- 12 unchanged lines hidden (view full) ---

210 case 0x522910b9: /* AcerLabs Aladdin IV/V */
211 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
212 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
213 ata_printf(scp, device,
214 "Aladdin: two atapi devices on this channel, no DMA\n");
215 break;
216 }
217 if (udmamode >= 2) {
221 int32_t word54 = pci_read_config(scp->dev, 0x54, 4);
218 int32_t word54 = pci_read_config(parent, 0x54, 4);
219
220 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
221 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
222 if (bootverbose)
223 ata_printf(scp, device,
224 "%s setting up UDMA2 mode on Aladdin chip\n",
225 (error) ? "failed" : "success");
226 if (!error) {
227 word54 |= 0x5555;
228 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2)));
232 pci_write_config(scp->dev, 0x54, word54, 4);
233 pci_write_config(scp->dev, 0x53,
234 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1);
229 pci_write_config(parent, 0x54, word54, 4);
230 pci_write_config(parent, 0x53,
231 pci_read_config(parent, 0x53, 1) | 0x03, 1);
232 scp->flags |= ATA_ATAPI_DMA_RO;
233 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
234 return;
235 }
236 }
237 if (wdmamode >= 2 && apiomode >= 4) {
238 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
239 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
240 if (bootverbose)
241 ata_printf(scp, device,
242 "%s setting up WDMA2 mode on Aladdin chip\n",
243 (error) ? "failed" : "success");
244 if (!error) {
248 pci_write_config(scp->dev, 0x53,
249 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1);
245 pci_write_config(parent, 0x53,
246 pci_read_config(parent, 0x53, 1) | 0x03, 1);
247 scp->flags |= ATA_ATAPI_DMA_RO;
248 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
249 return;
250 }
251 }
252 /* we could set PIO mode timings, but we assume the BIOS did that */
253 break;
254
255 case 0x06861106: /* VIA 82C686 */
256 if (udmamode >= 4) {
257 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
258 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
259 if (bootverbose)
260 ata_printf(scp, device,
261 "%s setting up UDMA4 mode on VIA chip\n",
262 (error) ? "failed" : "success");
263 if (!error) {
267 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1);
264 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
265 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
266 return;
267 }
268 }
269 if (udmamode >= 2) {
270 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
271 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
272 if (bootverbose)
273 ata_printf(scp, device,
274 "%s setting up UDMA2 mode on VIA chip\n",
275 (error) ? "failed" : "success");
276 if (!error) {
280 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1);
277 pci_write_config(parent, 0x53 - devno, 0xea, 1);
278 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
279 return;
280 }
281 }
282 goto via_generic;
283
284 case 0x74091022: /* AMD 756 */
285 if (udmamode >= 4) {
286 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
287 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
288 if (bootverbose)
289 ata_printf(scp, device,
290 "%s setting up UDMA4 mode on AMD chip\n",
291 (error) ? "failed" : "success");
292 if (!error) {
296 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1);
293 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
294 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
295 return;
296 }
297 }
298 /* FALLTHROUGH */
299
300 case 0x05961106: /* VIA 82C596 */
301 case 0x05861106: /* VIA 82C586 */

--- 5 unchanged lines hidden (view full) ---

307 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
308 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
309 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
310 if (bootverbose)
311 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
312 (error) ? "failed" : "success",
313 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
314 if (!error) {
318 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1);
315 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
316 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
317 return;
318 }
319 }
320 /* FALLTHROUGH */
321
322 case 0x05711106: /* VIA 82C571 */
323via_generic:
324 if (wdmamode >= 2 && apiomode >= 4) {
325 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
326 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
327 if (bootverbose)
328 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
329 (error) ? "failed" : "success",
330 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
331 if (!error) {
335 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1);
336 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1);
332 pci_write_config(parent, 0x53 - devno, 0x82, 1);
333 pci_write_config(parent, 0x4b - devno, 0x31, 1);
334 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
335 return;
336 }
337 }
338 /* we could set PIO mode timings, but we assume the BIOS did that */
339 break;
340
341 case 0x55131039: /* SiS 5591 */
342 if (udmamode >= 2) {
343 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
344 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
345 if (bootverbose)
346 ata_printf(scp, device,
347 "%s setting up UDMA2 mode on SiS chip\n",
348 (error) ? "failed" : "success");
349 if (!error) {
353 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2);
350 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
351 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
352 return;
353 }
354 }
355 if (wdmamode >=2 && apiomode >= 4) {
356 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
357 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
358 if (bootverbose)
359 ata_printf(scp, device,
360 "%s setting up WDMA2 mode on SiS chip\n",
361 (error) ? "failed" : "success");
362 if (!error) {
366 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2);
363 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
364 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
365 return;
366 }
367 }
368 /* we could set PIO mode timings, but we assume the BIOS did that */
369 break;
370
371 case 0x06461095: /* CMD 646 ATA controller */
372 if (wdmamode >= 2 && apiomode >= 4) {
373 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
374 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
375 if (bootverbose)
376 ata_printf(scp, device,
377 "%s setting up WDMA2 mode on CMD646 chip\n",
378 error ? "failed" : "success");
379 if (!error) {
380 int32_t offset = (devno < 3) ? (devno << 1) : 7;
381
382 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
383 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
384 return;
385 }
386 }
387 /* we could set PIO mode timings, but we assume the BIOS did that */
388 break;
389
390 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
391 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
392 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
393 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
394 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
395 break;
396
397 if (udmamode >=4 && scp->chiptype == 0x4d38105a &&
382 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
398 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
400 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
401 if (bootverbose)
402 ata_printf(scp, device,
403 "%s setting up UDMA4 mode on Promise chip\n",
404 (error) ? "failed" : "success");
405 if (!error) {
406 promise_timing(scp, devno, ATA_UDMA4);

--- 40 unchanged lines hidden (view full) ---

447 return;
448
449 case 0x00041103: /* HighPoint HPT366 controller */
450 /* no ATAPI devices for now */
451 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
452 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
453 break;
454
439 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) {
455 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) {
456 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
457 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
458 if (bootverbose)
459 ata_printf(scp, device,
460 "%s setting up UDMA4 mode on HPT366 chip\n",
461 (error) ? "failed" : "success");
462 if (!error) {
463 hpt366_timing(scp, devno, ATA_UDMA4);

--- 195 unchanged lines hidden (view full) ---

659 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
660 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
661 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
662 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
663 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
664 }
665 break;
666 }
651 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4);
667 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
668}
669
670static void
671hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
672{
673 device_t parent = device_get_parent(scp->dev);
674 u_int32_t timing;
675
659 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) {
676 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
677 case 0x85: /* 25Mhz */
678 switch (mode) {
679 case ATA_PIO0: timing = 0xc0d08585; break;
680 case ATA_PIO1: timing = 0xc0d08572; break;
681 case ATA_PIO2: timing = 0xc0ca8542; break;
682 case ATA_PIO3: timing = 0xc0ca8532; break;
683 case ATA_PIO4: timing = 0xc0ca8521; break;
684 case ATA_WDMA2: timing = 0xa0ca8521; break;

--- 24 unchanged lines hidden (view full) ---

709 case ATA_PIO3: timing = 0xc010d974; break;
710 case ATA_PIO4: timing = 0xc008d963; break;
711 case ATA_WDMA2: timing = 0xa008d943; break;
712 case ATA_UDMA2: timing = 0x900bd943; break;
713 case ATA_UDMA4: timing = 0x900fd943; break;
714 default: timing = 0x0120d9d9;
715 }
716 }
700 pci_write_config(scp->dev, 0x40 + (devno << 2) , (timing & ~0x80000000), 4);
717 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4);
718}
719
720#else /* NPCI > 0 */
721
722void
723ata_dmainit(struct ata_softc *scp, int32_t device,
724 int32_t piomode, int32_t wdmamode, int32_t udmamode)
725{

--- 27 unchanged lines hidden ---