1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 86322 2001-11-13 11:37:23Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 87198 2001-12-02 10:48:52Z sos $
|
29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/ata.h>
35#include <sys/bio.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <pci/pcivar.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46
47/* prototypes */
48static void cyrix_timing(struct ata_softc *, int, int);
49static void promise_timing(struct ata_softc *, int, int);
50static void hpt_timing(struct ata_softc *, int, int);
51
52/* misc defines */
53#ifdef __alpha__
54#undef vtophys
55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
56#endif
57#define ATAPI_DEVICE(scp, device) \
58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \
59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
60
61
62void *
63ata_dmaalloc(struct ata_softc *scp, int device)
64{
65 void *dmatab;
66
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
72 dmatab = NULL;
73 }
74 }
75 return dmatab;
76}
77
78void
79ata_dmainit(struct ata_softc *scp, int device,
80 int apiomode, int wdmamode, int udmamode)
81{
82 device_t parent = device_get_parent(scp->dev);
83 int devno = (scp->channel << 1) + ATA_DEV(device);
84 int error;
85
86 /* set our most pessimistic default mode */
87 scp->mode[ATA_DEV(device)] = ATA_PIO;
88
89 if (!scp->r_bmio)
90 return;
91
92 /* if simplex controller, only allow DMA on primary channel */
93 if (scp->channel == 1) {
94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 ata_printf(scp, device, "simplex device, DMA on primary only\n");
99 return;
100 }
101 }
102
103 /* DMA engine address alignment is usually 1 word (2 bytes) */
104 scp->alignment = 0x1;
105
106#if 1
107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) {
108 ata_printf(scp, device,
109 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
110 udmamode = 2;
111 }
112#endif
113 switch (scp->chiptype) {
114
115 case 0x248a8086: /* Intel ICH3 mobile */
116 case 0x248b8086: /* Intel ICH3 */
117 case 0x244a8086: /* Intel ICH2 mobile */
118 case 0x244b8086: /* Intel ICH2 */
119 if (udmamode >= 5) {
120 int32_t mask48, new48;
121 int16_t word54;
122
123 word54 = pci_read_config(parent, 0x54, 2);
124 if (word54 & (0x10 << devno)) {
125 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
126 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
127 if (bootverbose)
128 ata_printf(scp, device,
129 "%s setting UDMA5 on Intel chip\n",
130 (error) ? "failed" : "success");
131 if (!error) {
132 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
133 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
134 pci_write_config(parent, 0x48,
135 (pci_read_config(parent, 0x48, 4) &
136 ~mask48) | new48, 4);
137 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
138 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
139 return;
140 }
141 }
142 }
143 /* make sure eventual ATA100 mode from the BIOS is disabled */
144 pci_write_config(parent, 0x54,
145 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
146 /* FALLTHROUGH */
147
148 case 0x24118086: /* Intel ICH */
149 case 0x76018086: /* Intel ICH */
150 if (udmamode >= 4) {
151 int32_t mask48, new48;
152 int16_t word54;
153
154 word54 = pci_read_config(parent, 0x54, 2);
155 if (word54 & (0x10 << devno)) {
156 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
157 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
158 if (bootverbose)
159 ata_printf(scp, device,
160 "%s setting UDMA4 on Intel chip\n",
161 (error) ? "failed" : "success");
162 if (!error) {
163 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
164 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
165 pci_write_config(parent, 0x48,
166 (pci_read_config(parent, 0x48, 4) &
167 ~mask48) | new48, 4);
168 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
169 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
170 return;
171 }
172 }
173 }
174 /* make sure eventual ATA66 mode from the BIOS is disabled */
175 pci_write_config(parent, 0x54,
176 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
177 /* FALLTHROUGH */
178
179 case 0x71118086: /* Intel PIIX4 */
180 case 0x84CA8086: /* Intel PIIX4 */
181 case 0x71998086: /* Intel PIIX4e */
182 case 0x24218086: /* Intel ICH0 */
183 if (udmamode >= 2) {
184 int32_t mask48, new48;
185
186 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
187 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
188 if (bootverbose)
189 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n",
190 (error) ? "failed" : "success");
191 if (!error) {
192 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
193 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
194 pci_write_config(parent, 0x48,
195 (pci_read_config(parent, 0x48, 4) &
196 ~mask48) | new48, 4);
197 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
198 return;
199 }
200 }
201 /* make sure eventual ATA33 mode from the BIOS is disabled */
202 pci_write_config(parent, 0x48,
203 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
204 /* FALLTHROUGH */
205
206 case 0x70108086: /* Intel PIIX3 */
207 if (wdmamode >= 2 && apiomode >= 4) {
208 int32_t mask40, new40, mask44, new44;
209
210 /* if SITRE not set doit for both channels */
211 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) {
212 new40 = pci_read_config(parent, 0x40, 4);
213 new44 = pci_read_config(parent, 0x44, 4);
214 if (!(new40 & 0x00004000)) {
215 new44 &= ~0x0000000f;
216 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
217 }
218 if (!(new40 & 0x40000000)) {
219 new44 &= ~0x000000f0;
220 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
221 }
222 new40 |= 0x40004000;
223 pci_write_config(parent, 0x40, new40, 4);
224 pci_write_config(parent, 0x44, new44, 4);
225 }
226 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
227 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
228 if (bootverbose)
229 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n",
230 (error) ? "failed" : "success");
231 if (!error) {
232 if (device == ATA_MASTER) {
233 mask40 = 0x0000330f;
234 new40 = 0x00002307;
235 mask44 = 0;
236 new44 = 0;
237 }
238 else {
239 mask40 = 0x000000f0;
240 new40 = 0x00000070;
241 mask44 = 0x0000000f;
242 new44 = 0x0000000b;
243 }
244 if (scp->channel) {
245 mask40 <<= 16;
246 new40 <<= 16;
247 mask44 <<= 4;
248 new44 <<= 4;
249 }
250 pci_write_config(parent, 0x40,
251 (pci_read_config(parent, 0x40, 4) & ~mask40)|
252 new40, 4);
253 pci_write_config(parent, 0x44,
254 (pci_read_config(parent, 0x44, 4) & ~mask44)|
255 new44, 4);
256 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
257 return;
258 }
259 }
260 /* we could set PIO mode timings, but we assume the BIOS did that */
261 break;
262
263 case 0x12308086: /* Intel PIIX */
264 if (wdmamode >= 2 && apiomode >= 4) {
265 int32_t word40;
266
267 word40 = pci_read_config(parent, 0x40, 4);
268 word40 >>= scp->channel * 16;
269
270 /* Check for timing config usable for DMA on controller */
271 if (!((word40 & 0x3300) == 0x2300 &&
272 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
273 break;
274
275 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
276 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
277 if (bootverbose)
278 ata_printf(scp, device,
279 "%s setting WDMA2 on Intel chip\n",
280 (error) ? "failed" : "success");
281 if (!error) {
282 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
283 return;
284 }
285 }
286 break;
287
288 case 0x522910b9: /* AcerLabs Aladdin IV/V */
289 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
290 if (pci_get_revid(parent) < 0xC2 &&
291 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
292 ata_printf(scp, device,
293 "Aladdin: two atapi devices on this channel, no DMA\n");
294 break;
295 }
296 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) {
297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
298 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
299 if (bootverbose)
300 ata_printf(scp, device,
301 "%s setting UDMA5 on Acer chip\n",
302 (error) ? "failed" : "success");
303 if (!error) {
304 int32_t word54 = pci_read_config(parent, 0x54, 4);
305
306 pci_write_config(parent, 0x4b,
307 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
308 word54 &= ~(0x000f000f << (devno << 2));
309 word54 |= (0x000f0005 << (devno << 2));
310 pci_write_config(parent, 0x54, word54, 4);
311 pci_write_config(parent, 0x53,
312 pci_read_config(parent, 0x53, 1) | 0x03, 1);
313 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
314 return;
315 }
316 }
317 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) {
318 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
319 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
320 if (bootverbose)
321 ata_printf(scp, device,
322 "%s setting UDMA4 on Acer chip\n",
323 (error) ? "failed" : "success");
324 if (!error) {
325 int32_t word54 = pci_read_config(parent, 0x54, 4);
326
327 pci_write_config(parent, 0x4b,
328 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
329 word54 &= ~(0x000f000f << (devno << 2));
330 word54 |= (0x00080005 << (devno << 2));
331 pci_write_config(parent, 0x54, word54, 4);
332 pci_write_config(parent, 0x53,
333 pci_read_config(parent, 0x53, 1) | 0x03, 1);
334 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
335 return;
336 }
337 }
338 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
339 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
340 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
341 if (bootverbose)
342 ata_printf(scp, device,
343 "%s setting UDMA2 on Acer chip\n",
344 (error) ? "failed" : "success");
345 if (!error) {
346 int32_t word54 = pci_read_config(parent, 0x54, 4);
347
348 word54 &= ~(0x000f000f << (devno << 2));
349 word54 |= (0x000a0005 << (devno << 2));
350 pci_write_config(parent, 0x54, word54, 4);
351 pci_write_config(parent, 0x53,
352 pci_read_config(parent, 0x53, 1) | 0x03, 1);
353 scp->flags |= ATA_ATAPI_DMA_RO;
354 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
355 return;
356 }
357 }
358
359 /* make sure eventual UDMA mode from the BIOS is disabled */
360 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
361 ~(0x0008 << (devno << 2)), 2);
362
363 if (wdmamode >= 2 && apiomode >= 4) {
364 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
365 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
366 if (bootverbose)
367 ata_printf(scp, device,
368 "%s setting WDMA2 on Acer chip\n",
369 (error) ? "failed" : "success");
370 if (!error) {
371 pci_write_config(parent, 0x53,
372 pci_read_config(parent, 0x53, 1) | 0x03, 1);
373 scp->flags |= ATA_ATAPI_DMA_RO;
374 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
375 return;
376 }
377 }
378 pci_write_config(parent, 0x53,
379 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
380 /* we could set PIO mode timings, but we assume the BIOS did that */
381 break;
382
383 case 0x74111022: /* AMD 766 */
384 if (udmamode >= 5) {
385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
386 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
387 if (bootverbose)
388 ata_printf(scp, device,
389 "%s setting UDMA5 on AMD chip\n",
390 (error) ? "failed" : "success");
391 if (!error) {
392 pci_write_config(parent, 0x53 - devno, 0xc6, 1);
393 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
394 return;
395 }
396 }
397 /* FALLTHROUGH */
398
399 case 0x74091022: /* AMD 756 */
400 if (udmamode >= 4) {
401 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
402 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
403 if (bootverbose)
404 ata_printf(scp, device,
405 "%s setting UDMA4 on AMD chip\n",
406 (error) ? "failed" : "success");
407 if (!error) {
408 pci_write_config(parent, 0x53 - devno, 0xc5, 1);
409 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
410 return;
411 }
412 }
413 goto via_82c586;
414
415 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */
416 if (ata_find_dev(parent, 0x06861106, 0x40) ||
417 ata_find_dev(parent, 0x82311106, 0) ||
418 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */
419 if (udmamode >= 5) {
420 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
421 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
422 if (bootverbose)
423 ata_printf(scp, device,
424 "%s setting UDMA5 on VIA chip\n",
425 (error) ? "failed" : "success");
426 if (!error) {
427 pci_write_config(parent, 0x53 - devno, 0xf0, 1);
428 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
429 return;
430 }
431 }
432 if (udmamode >= 4) {
433 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
434 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
435 if (bootverbose)
436 ata_printf(scp, device,
437 "%s setting UDMA4 on VIA chip\n",
438 (error) ? "failed" : "success");
439 if (!error) {
440 pci_write_config(parent, 0x53 - devno, 0xf1, 1);
441 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
442 return;
443 }
444 }
445 if (udmamode >= 2) {
446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
447 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
448 if (bootverbose)
449 ata_printf(scp, device,
450 "%s setting UDMA2 on VIA chip\n",
451 (error) ? "failed" : "success");
452 if (!error) {
453 pci_write_config(parent, 0x53 - devno, 0xf4, 1);
454 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
455 return;
456 }
457 }
458 }
459 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */
460 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
461 if (udmamode >= 4) {
462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
463 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
464 if (bootverbose)
465 ata_printf(scp, device,
466 "%s setting UDMA4 on VIA chip\n",
467 (error) ? "failed" : "success");
468 if (!error) {
469 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
470 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
471 return;
472 }
473 }
474 if (udmamode >= 2) {
475 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
476 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
477 if (bootverbose)
478 ata_printf(scp, device,
479 "%s setting UDMA2 on VIA chip\n",
480 (error) ? "failed" : "success");
481 if (!error) {
482 pci_write_config(parent, 0x53 - devno, 0xea, 1);
483 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
484 return;
485 }
486 }
487 }
488 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
489 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
490via_82c586:
491 if (udmamode >= 2) {
492 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
493 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
494 if (bootverbose)
495 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
496 (error) ? "failed" : "success",
497 ((scp->chiptype == 0x74091022) ||
498 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA");
499 if (!error) {
500 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
501 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
502 return;
503 }
504 }
505 }
506 if (wdmamode >= 2 && apiomode >= 4) {
507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
508 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
509 if (bootverbose)
510 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
511 (error) ? "failed" : "success",
512 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
513 if (!error) {
514 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
515 pci_write_config(parent, 0x4b - devno, 0x31, 1);
516 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
517 return;
518 }
519 }
520 /* we could set PIO mode timings, but we assume the BIOS did that */
521 break;
522
523 case 0x55131039: /* SiS 5591 */
| 29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/ata.h>
35#include <sys/bio.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <pci/pcivar.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46
47/* prototypes */
48static void cyrix_timing(struct ata_softc *, int, int);
49static void promise_timing(struct ata_softc *, int, int);
50static void hpt_timing(struct ata_softc *, int, int);
51
52/* misc defines */
53#ifdef __alpha__
54#undef vtophys
55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
56#endif
57#define ATAPI_DEVICE(scp, device) \
58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \
59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
60
61
62void *
63ata_dmaalloc(struct ata_softc *scp, int device)
64{
65 void *dmatab;
66
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
72 dmatab = NULL;
73 }
74 }
75 return dmatab;
76}
77
78void
79ata_dmainit(struct ata_softc *scp, int device,
80 int apiomode, int wdmamode, int udmamode)
81{
82 device_t parent = device_get_parent(scp->dev);
83 int devno = (scp->channel << 1) + ATA_DEV(device);
84 int error;
85
86 /* set our most pessimistic default mode */
87 scp->mode[ATA_DEV(device)] = ATA_PIO;
88
89 if (!scp->r_bmio)
90 return;
91
92 /* if simplex controller, only allow DMA on primary channel */
93 if (scp->channel == 1) {
94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 ata_printf(scp, device, "simplex device, DMA on primary only\n");
99 return;
100 }
101 }
102
103 /* DMA engine address alignment is usually 1 word (2 bytes) */
104 scp->alignment = 0x1;
105
106#if 1
107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) {
108 ata_printf(scp, device,
109 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
110 udmamode = 2;
111 }
112#endif
113 switch (scp->chiptype) {
114
115 case 0x248a8086: /* Intel ICH3 mobile */
116 case 0x248b8086: /* Intel ICH3 */
117 case 0x244a8086: /* Intel ICH2 mobile */
118 case 0x244b8086: /* Intel ICH2 */
119 if (udmamode >= 5) {
120 int32_t mask48, new48;
121 int16_t word54;
122
123 word54 = pci_read_config(parent, 0x54, 2);
124 if (word54 & (0x10 << devno)) {
125 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
126 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
127 if (bootverbose)
128 ata_printf(scp, device,
129 "%s setting UDMA5 on Intel chip\n",
130 (error) ? "failed" : "success");
131 if (!error) {
132 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
133 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
134 pci_write_config(parent, 0x48,
135 (pci_read_config(parent, 0x48, 4) &
136 ~mask48) | new48, 4);
137 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
138 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
139 return;
140 }
141 }
142 }
143 /* make sure eventual ATA100 mode from the BIOS is disabled */
144 pci_write_config(parent, 0x54,
145 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
146 /* FALLTHROUGH */
147
148 case 0x24118086: /* Intel ICH */
149 case 0x76018086: /* Intel ICH */
150 if (udmamode >= 4) {
151 int32_t mask48, new48;
152 int16_t word54;
153
154 word54 = pci_read_config(parent, 0x54, 2);
155 if (word54 & (0x10 << devno)) {
156 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
157 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
158 if (bootverbose)
159 ata_printf(scp, device,
160 "%s setting UDMA4 on Intel chip\n",
161 (error) ? "failed" : "success");
162 if (!error) {
163 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
164 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
165 pci_write_config(parent, 0x48,
166 (pci_read_config(parent, 0x48, 4) &
167 ~mask48) | new48, 4);
168 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
169 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
170 return;
171 }
172 }
173 }
174 /* make sure eventual ATA66 mode from the BIOS is disabled */
175 pci_write_config(parent, 0x54,
176 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
177 /* FALLTHROUGH */
178
179 case 0x71118086: /* Intel PIIX4 */
180 case 0x84CA8086: /* Intel PIIX4 */
181 case 0x71998086: /* Intel PIIX4e */
182 case 0x24218086: /* Intel ICH0 */
183 if (udmamode >= 2) {
184 int32_t mask48, new48;
185
186 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
187 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
188 if (bootverbose)
189 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n",
190 (error) ? "failed" : "success");
191 if (!error) {
192 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
193 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
194 pci_write_config(parent, 0x48,
195 (pci_read_config(parent, 0x48, 4) &
196 ~mask48) | new48, 4);
197 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
198 return;
199 }
200 }
201 /* make sure eventual ATA33 mode from the BIOS is disabled */
202 pci_write_config(parent, 0x48,
203 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
204 /* FALLTHROUGH */
205
206 case 0x70108086: /* Intel PIIX3 */
207 if (wdmamode >= 2 && apiomode >= 4) {
208 int32_t mask40, new40, mask44, new44;
209
210 /* if SITRE not set doit for both channels */
211 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) {
212 new40 = pci_read_config(parent, 0x40, 4);
213 new44 = pci_read_config(parent, 0x44, 4);
214 if (!(new40 & 0x00004000)) {
215 new44 &= ~0x0000000f;
216 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
217 }
218 if (!(new40 & 0x40000000)) {
219 new44 &= ~0x000000f0;
220 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
221 }
222 new40 |= 0x40004000;
223 pci_write_config(parent, 0x40, new40, 4);
224 pci_write_config(parent, 0x44, new44, 4);
225 }
226 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
227 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
228 if (bootverbose)
229 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n",
230 (error) ? "failed" : "success");
231 if (!error) {
232 if (device == ATA_MASTER) {
233 mask40 = 0x0000330f;
234 new40 = 0x00002307;
235 mask44 = 0;
236 new44 = 0;
237 }
238 else {
239 mask40 = 0x000000f0;
240 new40 = 0x00000070;
241 mask44 = 0x0000000f;
242 new44 = 0x0000000b;
243 }
244 if (scp->channel) {
245 mask40 <<= 16;
246 new40 <<= 16;
247 mask44 <<= 4;
248 new44 <<= 4;
249 }
250 pci_write_config(parent, 0x40,
251 (pci_read_config(parent, 0x40, 4) & ~mask40)|
252 new40, 4);
253 pci_write_config(parent, 0x44,
254 (pci_read_config(parent, 0x44, 4) & ~mask44)|
255 new44, 4);
256 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
257 return;
258 }
259 }
260 /* we could set PIO mode timings, but we assume the BIOS did that */
261 break;
262
263 case 0x12308086: /* Intel PIIX */
264 if (wdmamode >= 2 && apiomode >= 4) {
265 int32_t word40;
266
267 word40 = pci_read_config(parent, 0x40, 4);
268 word40 >>= scp->channel * 16;
269
270 /* Check for timing config usable for DMA on controller */
271 if (!((word40 & 0x3300) == 0x2300 &&
272 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
273 break;
274
275 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
276 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
277 if (bootverbose)
278 ata_printf(scp, device,
279 "%s setting WDMA2 on Intel chip\n",
280 (error) ? "failed" : "success");
281 if (!error) {
282 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
283 return;
284 }
285 }
286 break;
287
288 case 0x522910b9: /* AcerLabs Aladdin IV/V */
289 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
290 if (pci_get_revid(parent) < 0xC2 &&
291 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
292 ata_printf(scp, device,
293 "Aladdin: two atapi devices on this channel, no DMA\n");
294 break;
295 }
296 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) {
297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
298 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
299 if (bootverbose)
300 ata_printf(scp, device,
301 "%s setting UDMA5 on Acer chip\n",
302 (error) ? "failed" : "success");
303 if (!error) {
304 int32_t word54 = pci_read_config(parent, 0x54, 4);
305
306 pci_write_config(parent, 0x4b,
307 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
308 word54 &= ~(0x000f000f << (devno << 2));
309 word54 |= (0x000f0005 << (devno << 2));
310 pci_write_config(parent, 0x54, word54, 4);
311 pci_write_config(parent, 0x53,
312 pci_read_config(parent, 0x53, 1) | 0x03, 1);
313 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
314 return;
315 }
316 }
317 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) {
318 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
319 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
320 if (bootverbose)
321 ata_printf(scp, device,
322 "%s setting UDMA4 on Acer chip\n",
323 (error) ? "failed" : "success");
324 if (!error) {
325 int32_t word54 = pci_read_config(parent, 0x54, 4);
326
327 pci_write_config(parent, 0x4b,
328 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
329 word54 &= ~(0x000f000f << (devno << 2));
330 word54 |= (0x00080005 << (devno << 2));
331 pci_write_config(parent, 0x54, word54, 4);
332 pci_write_config(parent, 0x53,
333 pci_read_config(parent, 0x53, 1) | 0x03, 1);
334 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
335 return;
336 }
337 }
338 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
339 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
340 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
341 if (bootverbose)
342 ata_printf(scp, device,
343 "%s setting UDMA2 on Acer chip\n",
344 (error) ? "failed" : "success");
345 if (!error) {
346 int32_t word54 = pci_read_config(parent, 0x54, 4);
347
348 word54 &= ~(0x000f000f << (devno << 2));
349 word54 |= (0x000a0005 << (devno << 2));
350 pci_write_config(parent, 0x54, word54, 4);
351 pci_write_config(parent, 0x53,
352 pci_read_config(parent, 0x53, 1) | 0x03, 1);
353 scp->flags |= ATA_ATAPI_DMA_RO;
354 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
355 return;
356 }
357 }
358
359 /* make sure eventual UDMA mode from the BIOS is disabled */
360 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
361 ~(0x0008 << (devno << 2)), 2);
362
363 if (wdmamode >= 2 && apiomode >= 4) {
364 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
365 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
366 if (bootverbose)
367 ata_printf(scp, device,
368 "%s setting WDMA2 on Acer chip\n",
369 (error) ? "failed" : "success");
370 if (!error) {
371 pci_write_config(parent, 0x53,
372 pci_read_config(parent, 0x53, 1) | 0x03, 1);
373 scp->flags |= ATA_ATAPI_DMA_RO;
374 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
375 return;
376 }
377 }
378 pci_write_config(parent, 0x53,
379 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
380 /* we could set PIO mode timings, but we assume the BIOS did that */
381 break;
382
383 case 0x74111022: /* AMD 766 */
384 if (udmamode >= 5) {
385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
386 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
387 if (bootverbose)
388 ata_printf(scp, device,
389 "%s setting UDMA5 on AMD chip\n",
390 (error) ? "failed" : "success");
391 if (!error) {
392 pci_write_config(parent, 0x53 - devno, 0xc6, 1);
393 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
394 return;
395 }
396 }
397 /* FALLTHROUGH */
398
399 case 0x74091022: /* AMD 756 */
400 if (udmamode >= 4) {
401 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
402 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
403 if (bootverbose)
404 ata_printf(scp, device,
405 "%s setting UDMA4 on AMD chip\n",
406 (error) ? "failed" : "success");
407 if (!error) {
408 pci_write_config(parent, 0x53 - devno, 0xc5, 1);
409 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
410 return;
411 }
412 }
413 goto via_82c586;
414
415 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */
416 if (ata_find_dev(parent, 0x06861106, 0x40) ||
417 ata_find_dev(parent, 0x82311106, 0) ||
418 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */
419 if (udmamode >= 5) {
420 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
421 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
422 if (bootverbose)
423 ata_printf(scp, device,
424 "%s setting UDMA5 on VIA chip\n",
425 (error) ? "failed" : "success");
426 if (!error) {
427 pci_write_config(parent, 0x53 - devno, 0xf0, 1);
428 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
429 return;
430 }
431 }
432 if (udmamode >= 4) {
433 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
434 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
435 if (bootverbose)
436 ata_printf(scp, device,
437 "%s setting UDMA4 on VIA chip\n",
438 (error) ? "failed" : "success");
439 if (!error) {
440 pci_write_config(parent, 0x53 - devno, 0xf1, 1);
441 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
442 return;
443 }
444 }
445 if (udmamode >= 2) {
446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
447 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
448 if (bootverbose)
449 ata_printf(scp, device,
450 "%s setting UDMA2 on VIA chip\n",
451 (error) ? "failed" : "success");
452 if (!error) {
453 pci_write_config(parent, 0x53 - devno, 0xf4, 1);
454 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
455 return;
456 }
457 }
458 }
459 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */
460 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
461 if (udmamode >= 4) {
462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
463 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
464 if (bootverbose)
465 ata_printf(scp, device,
466 "%s setting UDMA4 on VIA chip\n",
467 (error) ? "failed" : "success");
468 if (!error) {
469 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
470 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
471 return;
472 }
473 }
474 if (udmamode >= 2) {
475 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
476 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
477 if (bootverbose)
478 ata_printf(scp, device,
479 "%s setting UDMA2 on VIA chip\n",
480 (error) ? "failed" : "success");
481 if (!error) {
482 pci_write_config(parent, 0x53 - devno, 0xea, 1);
483 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
484 return;
485 }
486 }
487 }
488 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
489 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
490via_82c586:
491 if (udmamode >= 2) {
492 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
493 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
494 if (bootverbose)
495 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
496 (error) ? "failed" : "success",
497 ((scp->chiptype == 0x74091022) ||
498 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA");
499 if (!error) {
500 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
501 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
502 return;
503 }
504 }
505 }
506 if (wdmamode >= 2 && apiomode >= 4) {
507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
508 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
509 if (bootverbose)
510 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
511 (error) ? "failed" : "success",
512 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
513 if (!error) {
514 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
515 pci_write_config(parent, 0x4b - devno, 0x31, 1);
516 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
517 return;
518 }
519 }
520 /* we could set PIO mode timings, but we assume the BIOS did that */
521 break;
522
523 case 0x55131039: /* SiS 5591 */
|
524 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
525 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
526 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
527 if (bootverbose)
528 ata_printf(scp, device,
529 "%s setting UDMA2 on SiS chip\n",
530 (error) ? "failed" : "success");
531 if (!error) {
532 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
533 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
534 return;
| 524 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
525 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */
526 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */
527 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */
528 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */
529 ata_find_dev(parent, 0x07351039, 0x00)) { /* SiS 735 */
530 int8_t reg = 0x40 + (devno << 1);
531 int16_t val = pci_read_config(parent, reg, 2) & 0x00ff;
532
533 if (udmamode >= 5) {
534 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
535 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
536 if (bootverbose)
537 ata_printf(scp, device,
538 "%s setting UDMA5 on SiS chip\n",
539 (error) ? "failed" : "success");
540 if (!error) {
541 pci_write_config(parent, reg, val | 0x8100, 2);
542 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
543 return;
544 }
|
535 }
| 545 }
|
| 546 if (udmamode >= 4) {
547 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
548 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
549 if (bootverbose)
550 ata_printf(scp, device,
551 "%s setting UDMA4 on SiS chip\n",
552 (error) ? "failed" : "success");
553 if (!error) {
554 pci_write_config(parent, reg, val | 0x8200, 2);
555 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
556 return;
557 }
558 }
559 if (udmamode >= 2) {
560 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
561 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
562 if (bootverbose)
563 ata_printf(scp, device,
564 "%s setting UDMA2 on SiS chip\n",
565 (error) ? "failed" : "success");
566 if (!error) {
567 pci_write_config(parent, reg, val | 0x8500, 2);
568 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
569 return;
570 }
571 }
572 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
573 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
574 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
575 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
576 int8_t reg = 0x40 + (devno << 1);
577 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
578
579 if (udmamode >= 4) {
580 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
581 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
582 if (bootverbose)
583 ata_printf(scp, device,
584 "%s setting UDMA4 on SiS chip\n",
585 (error) ? "failed" : "success");
586 if (!error) {
587 pci_write_config(parent, reg, val | 0x9000, 2);
588 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
589 return;
590 }
591 }
592 if (udmamode >= 2) {
593 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
594 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
595 if (bootverbose)
596 ata_printf(scp, device,
597 "%s setting UDMA2 on SiS chip\n",
598 (error) ? "failed" : "success");
599 if (!error) {
600 pci_write_config(parent, reg, val | 0xb000, 2);
601 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
602 return;
603 }
604 }
605 } else { /* SiS 5591 */
606 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
607 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
608 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
609 if (bootverbose)
610 ata_printf(scp, device,
611 "%s setting UDMA2 on SiS chip\n",
612 (error) ? "failed" : "success");
613 if (!error) {
614 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
615 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
616 return;
617 }
618 }
|
536 }
537 if (wdmamode >=2 && apiomode >= 4) {
538 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
539 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
540 if (bootverbose)
541 ata_printf(scp, device,
542 "%s setting WDMA2 on SiS chip\n",
543 (error) ? "failed" : "success");
544 if (!error) {
545 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
546 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
547 return;
548 }
549 }
550 /* we could set PIO mode timings, but we assume the BIOS did that */
551 break;
552
553 case 0x06491095: /* CMD 649 ATA100 controller */
554 if (udmamode >= 5) {
555 u_int8_t umode;
556
557 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
558 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
559 if (bootverbose)
560 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n",
561 (error) ? "failed" : "success");
562 if (!error) {
563 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
564 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
565 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
566 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
567 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
568 return;
569 }
570 }
571 /* FALLTHROUGH */
572
573 case 0x06481095: /* CMD 648 ATA66 controller */
574 if (udmamode >= 4) {
575 u_int8_t umode;
576
577 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
578 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
579 if (bootverbose)
580 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n",
581 (error) ? "failed" : "success");
582 if (!error) {
583 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
584 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
585 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
586 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
587 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
588 return;
589 }
590 }
591 if (udmamode >= 2) {
592 u_int8_t umode;
593
594 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
595 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
596 if (bootverbose)
597 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n",
598 (error) ? "failed" : "success");
599 if (!error) {
600 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
601 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
602 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
603 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
604 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
605 return;
606 }
607 }
608 /* make sure eventual UDMA mode from the BIOS is disabled */
609 pci_write_config(parent, scp->channel ? 0x7b : 0x73,
610 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)&
611 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
612 /* FALLTHROUGH */
613
614 case 0x06461095: /* CMD 646 ATA controller */
615 if (wdmamode >= 2 && apiomode >= 4) {
616 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
617 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
618 if (bootverbose)
619 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n",
620 error ? "failed" : "success");
621 if (!error) {
622 int32_t offset = (devno < 3) ? (devno << 1) : 7;
623
624 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
625 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
626 return;
627 }
628 }
629 /* we could set PIO mode timings, but we assume the BIOS did that */
630 break;
631
632 case 0xc6931080: /* Cypress 82c693 ATA controller */
633 if (wdmamode >= 2 && apiomode >= 4) {
634 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
635 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
636 if (bootverbose)
637 ata_printf(scp, device,
638 "%s setting WDMA2 on Cypress chip\n",
639 error ? "failed" : "success");
640 if (!error) {
641 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2);
642 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
643 return;
644 }
645 }
646 /* we could set PIO mode timings, but we assume the BIOS did that */
647 break;
648
649 case 0x01021078: /* Cyrix 5530 ATA33 controller */
650 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
651 if (udmamode >= 2) {
652 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
653 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
654 if (bootverbose)
655 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
656 (error) ? "failed" : "success");
657 if (!error) {
658 cyrix_timing(scp, devno, ATA_UDMA2);
659 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
660 return;
661 }
662 }
663 if (wdmamode >= 2 && apiomode >= 4) {
664 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
665 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
666 if (bootverbose)
667 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
668 (error) ? "failed" : "success");
669 if (!error) {
670 cyrix_timing(scp, devno, ATA_WDMA2);
671 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
672 return;
673 }
674 }
675 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
676 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
677 ATA_WAIT_READY);
678 if (bootverbose)
679 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
680 (error) ? "failed" : "success",
681 ata_mode2str(ATA_PIO0 + apiomode));
682 cyrix_timing(scp, devno, ATA_PIO0 + apiomode);
683 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
684 return;
685
686 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
687 if (udmamode >= 2) {
688 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
689 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
690 if (bootverbose)
691 ata_printf(scp, device,
692 "%s setting UDMA2 on ServerWorks chip\n",
693 (error) ? "failed" : "success");
694 if (!error) {
695 u_int16_t reg56;
696
697 pci_write_config(parent, 0x54,
698 pci_read_config(parent, 0x54, 1) |
699 (0x01 << devno), 1);
700 reg56 = pci_read_config(parent, 0x56, 2);
701 reg56 &= ~(0xf << (devno * 4));
702 reg56 |= (0x2 << (devno * 4));
703 pci_write_config(parent, 0x56, reg56, 2);
704 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
705 return;
706 }
707 }
708 if (wdmamode >= 2 && apiomode >= 4) {
709 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
710 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
711 if (bootverbose)
712 ata_printf(scp, device,
713 "%s setting WDMA2 on ServerWorks chip\n",
714 (error) ? "failed" : "success");
715 if (!error) {
716 int offset = (scp->channel * 2) + (device == ATA_MASTER);
717 int word44 = pci_read_config(parent, 0x44, 4);
718
719 pci_write_config(parent, 0x54,
720 pci_read_config(parent, 0x54, 1) &
721 ~(0x01 << devno), 1);
722 word44 &= ~(0xff << (offset << 8));
723 word44 |= (0x20 << (offset << 8));
724 pci_write_config(parent, 0x44, 0x20, 4);
725 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
726 return;
727 }
728 }
729 /* we could set PIO mode timings, but we assume the BIOS did that */
730 break;
731
732 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
733 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */
734 case 0x4d69105a: /* Promise ATA133 controllers */
735 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
736 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
737 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
738 ATA_UDMA + udmamode, ATA_C_F_SETXFER,
739 ATA_WAIT_READY);
740 if (bootverbose)
741 ata_printf(scp, device, "%s setting %s on Promise chip\n",
742 (error) ? "failed" : "success",
743 ata_mode2str(ATA_UDMA + udmamode));
744 if (!error) {
745 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode;
746 return;
747 }
748 }
749 if (udmamode >= 2) {
750 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
751 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
752 if (bootverbose)
753 ata_printf(scp, device, "%s setting %s on Promise chip\n",
754 (error) ? "failed" : "success", "UDMA2");
755 if (!error) {
756 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
757 return;
758 }
759 }
760 if (wdmamode >= 2 && apiomode >= 4) {
761 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
762 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
763 if (bootverbose)
764 ata_printf(scp, device, "%s setting %s on Promise chip\n",
765 (error) ? "failed" : "success", "WDMA2");
766 if (!error) {
767 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
768 return;
769 }
770 }
771 break;
772
773 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
774 case 0x0d30105a: /* Promise OEM ATA100 controllers */
775 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 &&
776 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
777 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
778 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
779 if (bootverbose)
780 ata_printf(scp, device,
781 "%s setting UDMA5 on Promise chip\n",
782 (error) ? "failed" : "success");
783 if (!error) {
784 promise_timing(scp, devno, ATA_UDMA5);
785 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
786 return;
787 }
788 }
789 /* FALLTHROUGH */
790
791 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
792 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 &&
793 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
794 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
795 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
796 if (bootverbose)
797 ata_printf(scp, device,
798 "%s setting UDMA4 on Promise chip\n",
799 (error) ? "failed" : "success");
800 if (!error) {
801 promise_timing(scp, devno, ATA_UDMA4);
802 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
803 return;
804 }
805 }
806 /* FALLTHROUGH */
807
808 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
809 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
810 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
811 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
812 if (bootverbose)
813 ata_printf(scp, device,
814 "%s setting UDMA2 on Promise chip\n",
815 (error) ? "failed" : "success");
816 if (!error) {
817 promise_timing(scp, devno, ATA_UDMA2);
818 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
819 return;
820 }
821 }
822 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
823 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
824 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
825 if (bootverbose)
826 ata_printf(scp, device,
827 "%s setting WDMA2 on Promise chip\n",
828 (error) ? "failed" : "success");
829 if (!error) {
830 promise_timing(scp, devno, ATA_WDMA2);
831 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
832 return;
833 }
834 }
835 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
836 ATA_PIO0 + apiomode,
837 ATA_C_F_SETXFER, ATA_WAIT_READY);
838 if (bootverbose)
839 ata_printf(scp, device,
840 "%s setting PIO%d on Promise chip\n",
841 (error) ? "failed" : "success",
842 (apiomode >= 0) ? apiomode : 0);
843 promise_timing(scp, devno, ATA_PIO0 + apiomode);
844 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
845 return;
846
847 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
848 if (!ATAPI_DEVICE(scp, device) &&
849 udmamode >= 6 && pci_get_revid(parent) >= 0x05 &&
850 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
851 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
852 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
853 if (bootverbose)
854 ata_printf(scp, device,
855 "%s setting UDMA6 on HighPoint chip\n",
856 (error) ? "failed" : "success");
857 if (!error) {
858 hpt_timing(scp, devno, ATA_UDMA6);
859 scp->mode[ATA_DEV(device)] = ATA_UDMA6;
860 return;
861 }
862 }
863 if (!ATAPI_DEVICE(scp, device) &&
864 udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
865 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
866 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
867 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
868 if (bootverbose)
869 ata_printf(scp, device,
870 "%s setting UDMA5 on HighPoint chip\n",
871 (error) ? "failed" : "success");
872 if (!error) {
873 hpt_timing(scp, devno, ATA_UDMA5);
874 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
875 return;
876 }
877 }
878 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 &&
879 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
880 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
881 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
882 if (bootverbose)
883 ata_printf(scp, device,
884 "%s setting UDMA4 on HighPoint chip\n",
885 (error) ? "failed" : "success");
886 if (!error) {
887 hpt_timing(scp, devno, ATA_UDMA4);
888 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
889 return;
890 }
891 }
892 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
893 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
894 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
895 if (bootverbose)
896 ata_printf(scp, device,
897 "%s setting UDMA2 on HighPoint chip\n",
898 (error) ? "failed" : "success");
899 if (!error) {
900 hpt_timing(scp, devno, ATA_UDMA2);
901 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
902 return;
903 }
904 }
905 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
906 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
907 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
908 if (bootverbose)
909 ata_printf(scp, device,
910 "%s setting WDMA2 on HighPoint chip\n",
911 (error) ? "failed" : "success");
912 if (!error) {
913 hpt_timing(scp, devno, ATA_WDMA2);
914 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
915 return;
916 }
917 }
918 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
919 ATA_PIO0 + apiomode,
920 ATA_C_F_SETXFER, ATA_WAIT_READY);
921 if (bootverbose)
922 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n",
923 (error) ? "failed" : "success",
924 (apiomode >= 0) ? apiomode : 0);
925 hpt_timing(scp, devno, ATA_PIO0 + apiomode);
926 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
927 return;
928
929 default: /* unknown controller chip */
930 /* better not try generic DMA on ATAPI devices it almost never works */
931 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
932 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
933 break;
934
935 /* if controller says its setup for DMA take the easy way out */
936 /* the downside is we dont know what DMA mode we are in */
937 if ((udmamode >= 0 || wdmamode > 1) &&
938 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
939 ((device==ATA_MASTER) ?
940 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
941 scp->mode[ATA_DEV(device)] = ATA_DMA;
942 return;
943 }
944
945 /* well, we have no support for this, but try anyways */
946 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) {
947 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
948 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
949 if (bootverbose)
950 ata_printf(scp, device,
951 "%s setting WDMA2 on generic chip\n",
952 (error) ? "failed" : "success");
953 if (!error) {
954 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
955 return;
956 }
957 }
958 }
959 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
960 ATA_C_F_SETXFER,ATA_WAIT_READY);
961 if (bootverbose)
962 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
963 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
964 if (!error)
965 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
966 else {
967 if (bootverbose)
968 ata_printf(scp, device, "using PIO mode set by BIOS\n");
969 scp->mode[ATA_DEV(device)] = ATA_PIO;
970 }
971}
972
973int
974ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
975 caddr_t data, int32_t count)
976{
977 u_int32_t dma_count, dma_base;
978 int i = 0;
979
980 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
981 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
982 return -1;
983 }
984
985 if (!count) {
986 ata_printf(scp, device, "zero length DMA transfer attempted\n");
987 return -1;
988 }
989
990 dma_base = vtophys(data);
991 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
992 data += dma_count;
993 count -= dma_count;
994
995 while (count) {
996 dmatab[i].base = dma_base;
997 dmatab[i].count = (dma_count & 0xffff);
998 i++;
999 if (i >= ATA_DMA_ENTRIES) {
1000 ata_printf(scp, device, "too many segments in DMA table\n");
1001 return -1;
1002 }
1003 dma_base = vtophys(data);
1004 dma_count = min(count, PAGE_SIZE);
1005 data += min(count, PAGE_SIZE);
1006 count -= min(count, PAGE_SIZE);
1007 }
1008 dmatab[i].base = dma_base;
1009 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1010 return 0;
1011}
1012
1013void
1014ata_dmastart(struct ata_softc *scp, int device,
1015 struct ata_dmaentry *dmatab, int dir)
1016{
1017 scp->flags |= ATA_DMA_ACTIVE;
1018 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1019 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1020 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
1021 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) |
1022 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1023 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
1024 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1025}
1026
1027int
1028ata_dmadone(struct ata_softc *scp)
1029{
1030 int error;
1031
1032 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
1033 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1034 scp->flags &= ~ATA_DMA_ACTIVE;
1035 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT);
1036 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
1037 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1038 return error & ATA_BMSTAT_MASK;
1039}
1040
1041int
1042ata_dmastatus(struct ata_softc *scp)
1043{
1044 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1045}
1046
1047static void
1048cyrix_timing(struct ata_softc *scp, int devno, int mode)
1049{
1050 u_int32_t reg20 = 0x0000e132;
1051 u_int32_t reg24 = 0x00017771;
1052
1053 switch (mode) {
1054 case ATA_PIO0: reg20 = 0x0000e132; break;
1055 case ATA_PIO1: reg20 = 0x00018121; break;
1056 case ATA_PIO2: reg20 = 0x00024020; break;
1057 case ATA_PIO3: reg20 = 0x00032010; break;
1058 case ATA_PIO4: reg20 = 0x00040010; break;
1059 case ATA_WDMA2: reg24 = 0x00002020; break;
1060 case ATA_UDMA2: reg24 = 0x00911030; break;
1061 }
1062 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20);
1063 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24);
1064}
1065
1066static void
1067promise_timing(struct ata_softc *scp, int devno, int mode)
1068{
1069 u_int32_t timing = 0;
1070 struct promise_timing {
1071 u_int8_t pa:4;
1072 u_int8_t prefetch:1;
1073 u_int8_t iordy:1;
1074 u_int8_t errdy:1;
1075 u_int8_t syncin:1;
1076 u_int8_t pb:5;
1077 u_int8_t mb:3;
1078 u_int8_t mc:4;
1079 u_int8_t dmaw:1;
1080 u_int8_t dmar:1;
1081 u_int8_t iordyp:1;
1082 u_int8_t dmarqp:1;
1083 u_int8_t reserved:8;
1084 } *t = (struct promise_timing*)&timing;
1085
1086 t->iordy = 1; t->iordyp = 1;
1087 if (mode >= ATA_DMA) {
1088 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1089 }
1090
1091 switch (scp->chiptype) {
1092 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1093 switch (mode) {
1094 default:
1095 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1096 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1097 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1098 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1099 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1100 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1101 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1102 }
1103 break;
1104
1105 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1106 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1107 case 0x0d30105a: /* Promise OEM ATA 100 */
1108 switch (mode) {
1109 default:
1110 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1111 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1112 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1113 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1114 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1115 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1116 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1117 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1118 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1119 }
1120 break;
1121 }
1122 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
1123}
1124
1125static void
1126hpt_timing(struct ata_softc *scp, int devno, int mode)
1127{
1128 device_t parent = device_get_parent(scp->dev);
1129 u_int32_t timing;
1130 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */
1131 switch (mode) {
1132 case ATA_PIO0: timing = 0x0d029d5e; break;
1133 case ATA_PIO1: timing = 0x0d029d26; break;
1134 case ATA_PIO2: timing = 0x0c829ca6; break;
1135 case ATA_PIO3: timing = 0x0c829c84; break;
1136 case ATA_PIO4: timing = 0x0c829c62; break;
1137 case ATA_WDMA2: timing = 0x2c829262; break;
1138 case ATA_UDMA2: timing = 0x1c91dc62; break;
1139 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1140 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1141 case ATA_UDMA6: timing = 0x1c81dc62; break;
1142 default: timing = 0x0d029d5e;
1143 }
1144 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1145 pci_write_config(parent, 0x5b, 0x20, 1);
1146 }
1147 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
1148 switch (mode) {
1149 case ATA_PIO0: timing = 0x06914e57; break;
1150 case ATA_PIO1: timing = 0x06914e43; break;
1151 case ATA_PIO2: timing = 0x06514e33; break;
1152 case ATA_PIO3: timing = 0x06514e22; break;
1153 case ATA_PIO4: timing = 0x06514e21; break;
1154 case ATA_WDMA2: timing = 0x26514e21; break;
1155 case ATA_UDMA2: timing = 0x16494e31; break;
1156 case ATA_UDMA4: timing = 0x16454e31; break;
1157 case ATA_UDMA5: timing = 0x16454e31; break;
1158 default: timing = 0x06514e57;
1159 }
1160 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1161 pci_write_config(parent, 0x5b, 0x22, 1);
1162 }
1163 else { /* HPT36[68] */
1164 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1165 case 0x85: /* 25Mhz */
1166 switch (mode) {
1167 case ATA_PIO0: timing = 0xc0d08585; break;
1168 case ATA_PIO1: timing = 0xc0d08572; break;
1169 case ATA_PIO2: timing = 0xc0ca8542; break;
1170 case ATA_PIO3: timing = 0xc0ca8532; break;
1171 case ATA_PIO4: timing = 0xc0ca8521; break;
1172 case ATA_WDMA2: timing = 0xa0ca8521; break;
1173 case ATA_UDMA2: timing = 0x90cf8521; break;
1174 case ATA_UDMA4: timing = 0x90c98521; break;
1175 default: timing = 0x01208585;
1176 }
1177 break;
1178 default:
1179 case 0xa7: /* 33MHz */
1180 switch (mode) {
1181 case ATA_PIO0: timing = 0xc0d0a7aa; break;
1182 case ATA_PIO1: timing = 0xc0d0a7a3; break;
1183 case ATA_PIO2: timing = 0xc0d0a753; break;
1184 case ATA_PIO3: timing = 0xc0c8a742; break;
1185 case ATA_PIO4: timing = 0xc0c8a731; break;
1186 case ATA_WDMA2: timing = 0xa0c8a731; break;
1187 case ATA_UDMA2: timing = 0x90caa731; break;
1188 case ATA_UDMA4: timing = 0x90c9a731; break;
1189 default: timing = 0x0120a7a7;
1190 }
1191 break;
1192 case 0xd9: /* 40Mhz */
1193 switch (mode) {
1194 case ATA_PIO0: timing = 0xc018d9d9; break;
1195 case ATA_PIO1: timing = 0xc010d9c7; break;
1196 case ATA_PIO2: timing = 0xc010d997; break;
1197 case ATA_PIO3: timing = 0xc010d974; break;
1198 case ATA_PIO4: timing = 0xc008d963; break;
1199 case ATA_WDMA2: timing = 0xa008d943; break;
1200 case ATA_UDMA2: timing = 0x900bd943; break;
1201 case ATA_UDMA4: timing = 0x900fd943; break;
1202 default: timing = 0x0120d9d9;
1203 }
1204 }
1205 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
1206 }
1207}
| 619 }
620 if (wdmamode >=2 && apiomode >= 4) {
621 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
622 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
623 if (bootverbose)
624 ata_printf(scp, device,
625 "%s setting WDMA2 on SiS chip\n",
626 (error) ? "failed" : "success");
627 if (!error) {
628 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
629 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
630 return;
631 }
632 }
633 /* we could set PIO mode timings, but we assume the BIOS did that */
634 break;
635
636 case 0x06491095: /* CMD 649 ATA100 controller */
637 if (udmamode >= 5) {
638 u_int8_t umode;
639
640 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
641 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
642 if (bootverbose)
643 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n",
644 (error) ? "failed" : "success");
645 if (!error) {
646 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
647 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
648 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
649 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
650 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
651 return;
652 }
653 }
654 /* FALLTHROUGH */
655
656 case 0x06481095: /* CMD 648 ATA66 controller */
657 if (udmamode >= 4) {
658 u_int8_t umode;
659
660 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
661 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
662 if (bootverbose)
663 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n",
664 (error) ? "failed" : "success");
665 if (!error) {
666 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
667 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
668 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
669 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
670 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
671 return;
672 }
673 }
674 if (udmamode >= 2) {
675 u_int8_t umode;
676
677 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
678 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
679 if (bootverbose)
680 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n",
681 (error) ? "failed" : "success");
682 if (!error) {
683 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
684 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
685 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
686 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
687 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
688 return;
689 }
690 }
691 /* make sure eventual UDMA mode from the BIOS is disabled */
692 pci_write_config(parent, scp->channel ? 0x7b : 0x73,
693 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)&
694 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
695 /* FALLTHROUGH */
696
697 case 0x06461095: /* CMD 646 ATA controller */
698 if (wdmamode >= 2 && apiomode >= 4) {
699 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
700 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
701 if (bootverbose)
702 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n",
703 error ? "failed" : "success");
704 if (!error) {
705 int32_t offset = (devno < 3) ? (devno << 1) : 7;
706
707 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
708 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
709 return;
710 }
711 }
712 /* we could set PIO mode timings, but we assume the BIOS did that */
713 break;
714
715 case 0xc6931080: /* Cypress 82c693 ATA controller */
716 if (wdmamode >= 2 && apiomode >= 4) {
717 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
718 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
719 if (bootverbose)
720 ata_printf(scp, device,
721 "%s setting WDMA2 on Cypress chip\n",
722 error ? "failed" : "success");
723 if (!error) {
724 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2);
725 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
726 return;
727 }
728 }
729 /* we could set PIO mode timings, but we assume the BIOS did that */
730 break;
731
732 case 0x01021078: /* Cyrix 5530 ATA33 controller */
733 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
734 if (udmamode >= 2) {
735 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
736 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
737 if (bootverbose)
738 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
739 (error) ? "failed" : "success");
740 if (!error) {
741 cyrix_timing(scp, devno, ATA_UDMA2);
742 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
743 return;
744 }
745 }
746 if (wdmamode >= 2 && apiomode >= 4) {
747 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
748 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
749 if (bootverbose)
750 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
751 (error) ? "failed" : "success");
752 if (!error) {
753 cyrix_timing(scp, devno, ATA_WDMA2);
754 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
755 return;
756 }
757 }
758 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
759 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
760 ATA_WAIT_READY);
761 if (bootverbose)
762 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
763 (error) ? "failed" : "success",
764 ata_mode2str(ATA_PIO0 + apiomode));
765 cyrix_timing(scp, devno, ATA_PIO0 + apiomode);
766 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
767 return;
768
769 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
770 if (udmamode >= 2) {
771 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
772 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
773 if (bootverbose)
774 ata_printf(scp, device,
775 "%s setting UDMA2 on ServerWorks chip\n",
776 (error) ? "failed" : "success");
777 if (!error) {
778 u_int16_t reg56;
779
780 pci_write_config(parent, 0x54,
781 pci_read_config(parent, 0x54, 1) |
782 (0x01 << devno), 1);
783 reg56 = pci_read_config(parent, 0x56, 2);
784 reg56 &= ~(0xf << (devno * 4));
785 reg56 |= (0x2 << (devno * 4));
786 pci_write_config(parent, 0x56, reg56, 2);
787 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
788 return;
789 }
790 }
791 if (wdmamode >= 2 && apiomode >= 4) {
792 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
793 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
794 if (bootverbose)
795 ata_printf(scp, device,
796 "%s setting WDMA2 on ServerWorks chip\n",
797 (error) ? "failed" : "success");
798 if (!error) {
799 int offset = (scp->channel * 2) + (device == ATA_MASTER);
800 int word44 = pci_read_config(parent, 0x44, 4);
801
802 pci_write_config(parent, 0x54,
803 pci_read_config(parent, 0x54, 1) &
804 ~(0x01 << devno), 1);
805 word44 &= ~(0xff << (offset << 8));
806 word44 |= (0x20 << (offset << 8));
807 pci_write_config(parent, 0x44, 0x20, 4);
808 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
809 return;
810 }
811 }
812 /* we could set PIO mode timings, but we assume the BIOS did that */
813 break;
814
815 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
816 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */
817 case 0x4d69105a: /* Promise ATA133 controllers */
818 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
819 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
820 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
821 ATA_UDMA + udmamode, ATA_C_F_SETXFER,
822 ATA_WAIT_READY);
823 if (bootverbose)
824 ata_printf(scp, device, "%s setting %s on Promise chip\n",
825 (error) ? "failed" : "success",
826 ata_mode2str(ATA_UDMA + udmamode));
827 if (!error) {
828 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode;
829 return;
830 }
831 }
832 if (udmamode >= 2) {
833 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
834 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
835 if (bootverbose)
836 ata_printf(scp, device, "%s setting %s on Promise chip\n",
837 (error) ? "failed" : "success", "UDMA2");
838 if (!error) {
839 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
840 return;
841 }
842 }
843 if (wdmamode >= 2 && apiomode >= 4) {
844 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
845 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
846 if (bootverbose)
847 ata_printf(scp, device, "%s setting %s on Promise chip\n",
848 (error) ? "failed" : "success", "WDMA2");
849 if (!error) {
850 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
851 return;
852 }
853 }
854 break;
855
856 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
857 case 0x0d30105a: /* Promise OEM ATA100 controllers */
858 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 &&
859 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
860 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
861 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
862 if (bootverbose)
863 ata_printf(scp, device,
864 "%s setting UDMA5 on Promise chip\n",
865 (error) ? "failed" : "success");
866 if (!error) {
867 promise_timing(scp, devno, ATA_UDMA5);
868 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
869 return;
870 }
871 }
872 /* FALLTHROUGH */
873
874 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
875 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 &&
876 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
877 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
878 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
879 if (bootverbose)
880 ata_printf(scp, device,
881 "%s setting UDMA4 on Promise chip\n",
882 (error) ? "failed" : "success");
883 if (!error) {
884 promise_timing(scp, devno, ATA_UDMA4);
885 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
886 return;
887 }
888 }
889 /* FALLTHROUGH */
890
891 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
892 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
893 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
894 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
895 if (bootverbose)
896 ata_printf(scp, device,
897 "%s setting UDMA2 on Promise chip\n",
898 (error) ? "failed" : "success");
899 if (!error) {
900 promise_timing(scp, devno, ATA_UDMA2);
901 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
902 return;
903 }
904 }
905 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
906 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
907 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
908 if (bootverbose)
909 ata_printf(scp, device,
910 "%s setting WDMA2 on Promise chip\n",
911 (error) ? "failed" : "success");
912 if (!error) {
913 promise_timing(scp, devno, ATA_WDMA2);
914 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
915 return;
916 }
917 }
918 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
919 ATA_PIO0 + apiomode,
920 ATA_C_F_SETXFER, ATA_WAIT_READY);
921 if (bootverbose)
922 ata_printf(scp, device,
923 "%s setting PIO%d on Promise chip\n",
924 (error) ? "failed" : "success",
925 (apiomode >= 0) ? apiomode : 0);
926 promise_timing(scp, devno, ATA_PIO0 + apiomode);
927 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
928 return;
929
930 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
931 if (!ATAPI_DEVICE(scp, device) &&
932 udmamode >= 6 && pci_get_revid(parent) >= 0x05 &&
933 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
934 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
935 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
936 if (bootverbose)
937 ata_printf(scp, device,
938 "%s setting UDMA6 on HighPoint chip\n",
939 (error) ? "failed" : "success");
940 if (!error) {
941 hpt_timing(scp, devno, ATA_UDMA6);
942 scp->mode[ATA_DEV(device)] = ATA_UDMA6;
943 return;
944 }
945 }
946 if (!ATAPI_DEVICE(scp, device) &&
947 udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
948 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
949 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
950 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
951 if (bootverbose)
952 ata_printf(scp, device,
953 "%s setting UDMA5 on HighPoint chip\n",
954 (error) ? "failed" : "success");
955 if (!error) {
956 hpt_timing(scp, devno, ATA_UDMA5);
957 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
958 return;
959 }
960 }
961 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 &&
962 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
963 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
964 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
965 if (bootverbose)
966 ata_printf(scp, device,
967 "%s setting UDMA4 on HighPoint chip\n",
968 (error) ? "failed" : "success");
969 if (!error) {
970 hpt_timing(scp, devno, ATA_UDMA4);
971 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
972 return;
973 }
974 }
975 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
976 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
977 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
978 if (bootverbose)
979 ata_printf(scp, device,
980 "%s setting UDMA2 on HighPoint chip\n",
981 (error) ? "failed" : "success");
982 if (!error) {
983 hpt_timing(scp, devno, ATA_UDMA2);
984 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
985 return;
986 }
987 }
988 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
989 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
990 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
991 if (bootverbose)
992 ata_printf(scp, device,
993 "%s setting WDMA2 on HighPoint chip\n",
994 (error) ? "failed" : "success");
995 if (!error) {
996 hpt_timing(scp, devno, ATA_WDMA2);
997 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
998 return;
999 }
1000 }
1001 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
1002 ATA_PIO0 + apiomode,
1003 ATA_C_F_SETXFER, ATA_WAIT_READY);
1004 if (bootverbose)
1005 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n",
1006 (error) ? "failed" : "success",
1007 (apiomode >= 0) ? apiomode : 0);
1008 hpt_timing(scp, devno, ATA_PIO0 + apiomode);
1009 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
1010 return;
1011
1012 default: /* unknown controller chip */
1013 /* better not try generic DMA on ATAPI devices it almost never works */
1014 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
1015 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
1016 break;
1017
1018 /* if controller says its setup for DMA take the easy way out */
1019 /* the downside is we dont know what DMA mode we are in */
1020 if ((udmamode >= 0 || wdmamode > 1) &&
1021 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
1022 ((device==ATA_MASTER) ?
1023 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1024 scp->mode[ATA_DEV(device)] = ATA_DMA;
1025 return;
1026 }
1027
1028 /* well, we have no support for this, but try anyways */
1029 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) {
1030 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
1031 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1032 if (bootverbose)
1033 ata_printf(scp, device,
1034 "%s setting WDMA2 on generic chip\n",
1035 (error) ? "failed" : "success");
1036 if (!error) {
1037 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
1038 return;
1039 }
1040 }
1041 }
1042 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1043 ATA_C_F_SETXFER,ATA_WAIT_READY);
1044 if (bootverbose)
1045 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
1046 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1047 if (!error)
1048 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
1049 else {
1050 if (bootverbose)
1051 ata_printf(scp, device, "using PIO mode set by BIOS\n");
1052 scp->mode[ATA_DEV(device)] = ATA_PIO;
1053 }
1054}
1055
1056int
1057ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
1058 caddr_t data, int32_t count)
1059{
1060 u_int32_t dma_count, dma_base;
1061 int i = 0;
1062
1063 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
1064 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
1065 return -1;
1066 }
1067
1068 if (!count) {
1069 ata_printf(scp, device, "zero length DMA transfer attempted\n");
1070 return -1;
1071 }
1072
1073 dma_base = vtophys(data);
1074 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1075 data += dma_count;
1076 count -= dma_count;
1077
1078 while (count) {
1079 dmatab[i].base = dma_base;
1080 dmatab[i].count = (dma_count & 0xffff);
1081 i++;
1082 if (i >= ATA_DMA_ENTRIES) {
1083 ata_printf(scp, device, "too many segments in DMA table\n");
1084 return -1;
1085 }
1086 dma_base = vtophys(data);
1087 dma_count = min(count, PAGE_SIZE);
1088 data += min(count, PAGE_SIZE);
1089 count -= min(count, PAGE_SIZE);
1090 }
1091 dmatab[i].base = dma_base;
1092 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1093 return 0;
1094}
1095
1096void
1097ata_dmastart(struct ata_softc *scp, int device,
1098 struct ata_dmaentry *dmatab, int dir)
1099{
1100 scp->flags |= ATA_DMA_ACTIVE;
1101 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1102 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1103 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
1104 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) |
1105 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1106 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
1107 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1108}
1109
1110int
1111ata_dmadone(struct ata_softc *scp)
1112{
1113 int error;
1114
1115 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
1116 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1117 scp->flags &= ~ATA_DMA_ACTIVE;
1118 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT);
1119 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
1120 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1121 return error & ATA_BMSTAT_MASK;
1122}
1123
1124int
1125ata_dmastatus(struct ata_softc *scp)
1126{
1127 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1128}
1129
1130static void
1131cyrix_timing(struct ata_softc *scp, int devno, int mode)
1132{
1133 u_int32_t reg20 = 0x0000e132;
1134 u_int32_t reg24 = 0x00017771;
1135
1136 switch (mode) {
1137 case ATA_PIO0: reg20 = 0x0000e132; break;
1138 case ATA_PIO1: reg20 = 0x00018121; break;
1139 case ATA_PIO2: reg20 = 0x00024020; break;
1140 case ATA_PIO3: reg20 = 0x00032010; break;
1141 case ATA_PIO4: reg20 = 0x00040010; break;
1142 case ATA_WDMA2: reg24 = 0x00002020; break;
1143 case ATA_UDMA2: reg24 = 0x00911030; break;
1144 }
1145 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20);
1146 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24);
1147}
1148
1149static void
1150promise_timing(struct ata_softc *scp, int devno, int mode)
1151{
1152 u_int32_t timing = 0;
1153 struct promise_timing {
1154 u_int8_t pa:4;
1155 u_int8_t prefetch:1;
1156 u_int8_t iordy:1;
1157 u_int8_t errdy:1;
1158 u_int8_t syncin:1;
1159 u_int8_t pb:5;
1160 u_int8_t mb:3;
1161 u_int8_t mc:4;
1162 u_int8_t dmaw:1;
1163 u_int8_t dmar:1;
1164 u_int8_t iordyp:1;
1165 u_int8_t dmarqp:1;
1166 u_int8_t reserved:8;
1167 } *t = (struct promise_timing*)&timing;
1168
1169 t->iordy = 1; t->iordyp = 1;
1170 if (mode >= ATA_DMA) {
1171 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1172 }
1173
1174 switch (scp->chiptype) {
1175 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1176 switch (mode) {
1177 default:
1178 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1179 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1180 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1181 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1182 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1183 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1184 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1185 }
1186 break;
1187
1188 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1189 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1190 case 0x0d30105a: /* Promise OEM ATA 100 */
1191 switch (mode) {
1192 default:
1193 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1194 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1195 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1196 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1197 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1198 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1199 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1200 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1201 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1202 }
1203 break;
1204 }
1205 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
1206}
1207
1208static void
1209hpt_timing(struct ata_softc *scp, int devno, int mode)
1210{
1211 device_t parent = device_get_parent(scp->dev);
1212 u_int32_t timing;
1213 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */
1214 switch (mode) {
1215 case ATA_PIO0: timing = 0x0d029d5e; break;
1216 case ATA_PIO1: timing = 0x0d029d26; break;
1217 case ATA_PIO2: timing = 0x0c829ca6; break;
1218 case ATA_PIO3: timing = 0x0c829c84; break;
1219 case ATA_PIO4: timing = 0x0c829c62; break;
1220 case ATA_WDMA2: timing = 0x2c829262; break;
1221 case ATA_UDMA2: timing = 0x1c91dc62; break;
1222 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1223 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1224 case ATA_UDMA6: timing = 0x1c81dc62; break;
1225 default: timing = 0x0d029d5e;
1226 }
1227 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1228 pci_write_config(parent, 0x5b, 0x20, 1);
1229 }
1230 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
1231 switch (mode) {
1232 case ATA_PIO0: timing = 0x06914e57; break;
1233 case ATA_PIO1: timing = 0x06914e43; break;
1234 case ATA_PIO2: timing = 0x06514e33; break;
1235 case ATA_PIO3: timing = 0x06514e22; break;
1236 case ATA_PIO4: timing = 0x06514e21; break;
1237 case ATA_WDMA2: timing = 0x26514e21; break;
1238 case ATA_UDMA2: timing = 0x16494e31; break;
1239 case ATA_UDMA4: timing = 0x16454e31; break;
1240 case ATA_UDMA5: timing = 0x16454e31; break;
1241 default: timing = 0x06514e57;
1242 }
1243 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1244 pci_write_config(parent, 0x5b, 0x22, 1);
1245 }
1246 else { /* HPT36[68] */
1247 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1248 case 0x85: /* 25Mhz */
1249 switch (mode) {
1250 case ATA_PIO0: timing = 0xc0d08585; break;
1251 case ATA_PIO1: timing = 0xc0d08572; break;
1252 case ATA_PIO2: timing = 0xc0ca8542; break;
1253 case ATA_PIO3: timing = 0xc0ca8532; break;
1254 case ATA_PIO4: timing = 0xc0ca8521; break;
1255 case ATA_WDMA2: timing = 0xa0ca8521; break;
1256 case ATA_UDMA2: timing = 0x90cf8521; break;
1257 case ATA_UDMA4: timing = 0x90c98521; break;
1258 default: timing = 0x01208585;
1259 }
1260 break;
1261 default:
1262 case 0xa7: /* 33MHz */
1263 switch (mode) {
1264 case ATA_PIO0: timing = 0xc0d0a7aa; break;
1265 case ATA_PIO1: timing = 0xc0d0a7a3; break;
1266 case ATA_PIO2: timing = 0xc0d0a753; break;
1267 case ATA_PIO3: timing = 0xc0c8a742; break;
1268 case ATA_PIO4: timing = 0xc0c8a731; break;
1269 case ATA_WDMA2: timing = 0xa0c8a731; break;
1270 case ATA_UDMA2: timing = 0x90caa731; break;
1271 case ATA_UDMA4: timing = 0x90c9a731; break;
1272 default: timing = 0x0120a7a7;
1273 }
1274 break;
1275 case 0xd9: /* 40Mhz */
1276 switch (mode) {
1277 case ATA_PIO0: timing = 0xc018d9d9; break;
1278 case ATA_PIO1: timing = 0xc010d9c7; break;
1279 case ATA_PIO2: timing = 0xc010d997; break;
1280 case ATA_PIO3: timing = 0xc010d974; break;
1281 case ATA_PIO4: timing = 0xc008d963; break;
1282 case ATA_WDMA2: timing = 0xa008d943; break;
1283 case ATA_UDMA2: timing = 0x900bd943; break;
1284 case ATA_UDMA4: timing = 0x900fd943; break;
1285 default: timing = 0x0120d9d9;
1286 }
1287 }
1288 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
1289 }
1290}
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