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ata-dma.c (64307) ata-dma.c (64479)
1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 64307 2000-08-06 19:51:58Z sos $
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 64479 2000-08-10 07:34:49Z sos $
29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bio.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>
37#include <sys/disk.h>
38#include <sys/devicestat.h>
39#include <vm/vm.h>
40#include <vm/pmap.h>
41#if NPCI > 0
42#include <pci/pcivar.h>
43#endif
44#include <dev/ata/ata-all.h>
45#include <dev/ata/ata-disk.h>
46
47#if NPCI > 0
48
49/* prototypes */
50static void promise_timing(struct ata_softc *, int32_t, int32_t);
51static void hpt_timing(struct ata_softc *, int32_t, int32_t);
52
53/* misc defines */
54#ifdef __alpha__
55#undef vtophys
56#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
57#endif
58
59void
60ata_dmainit(struct ata_softc *scp, int32_t device,
61 int32_t apiomode, int32_t wdmamode, int32_t udmamode)
62{
63 device_t parent = device_get_parent(scp->dev);
64 int devno = (scp->unit << 1) + ATA_DEV(device);
65 int error;
66
67 /* set our most pessimistic default mode */
68 scp->mode[ATA_DEV(device)] = ATA_PIO;
69
70 if (!scp->bmaddr)
71 return;
72
73 /* if simplex controller, only allow DMA on primary channel */
74 if (scp->unit == 1) {
75 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
76 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
77 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
78 ata_printf(scp, device, "simplex device, DMA on primary only\n");
79 return;
80 }
81 }
82
83 if (!scp->dmatab[ATA_DEV(device)]) {
84 void *dmatab;
85
86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT)))
87 return;
88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
90 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
91 free(dmatab, M_DEVBUF);
92 return;
93 }
94 scp->dmatab[ATA_DEV(device)] = dmatab;
95 }
96 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) {
97 ata_printf(scp, device,
98 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
99 udmamode = 2;
100 }
101
102 switch (scp->chiptype) {
103
104 case 0x244b8086: /* Intel ICH2 */
105 if (udmamode >= 5) {
106 int32_t mask48, new48;
107 int16_t word54;
108
109 word54 = pci_read_config(parent, 0x54, 2);
110 if (word54 & (0x10 << devno)) {
111 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
112 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
113 if (bootverbose)
114 ata_printf(scp, device,
115 "%s setting up UDMA5 mode on ICH2 chip\n",
116 (error) ? "failed" : "success");
117 if (!error) {
118 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
119 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
120 pci_write_config(parent, 0x48,
121 (pci_read_config(parent, 0x48, 4) &
122 ~mask48) | new48, 4);
29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bio.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>
37#include <sys/disk.h>
38#include <sys/devicestat.h>
39#include <vm/vm.h>
40#include <vm/pmap.h>
41#if NPCI > 0
42#include <pci/pcivar.h>
43#endif
44#include <dev/ata/ata-all.h>
45#include <dev/ata/ata-disk.h>
46
47#if NPCI > 0
48
49/* prototypes */
50static void promise_timing(struct ata_softc *, int32_t, int32_t);
51static void hpt_timing(struct ata_softc *, int32_t, int32_t);
52
53/* misc defines */
54#ifdef __alpha__
55#undef vtophys
56#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
57#endif
58
59void
60ata_dmainit(struct ata_softc *scp, int32_t device,
61 int32_t apiomode, int32_t wdmamode, int32_t udmamode)
62{
63 device_t parent = device_get_parent(scp->dev);
64 int devno = (scp->unit << 1) + ATA_DEV(device);
65 int error;
66
67 /* set our most pessimistic default mode */
68 scp->mode[ATA_DEV(device)] = ATA_PIO;
69
70 if (!scp->bmaddr)
71 return;
72
73 /* if simplex controller, only allow DMA on primary channel */
74 if (scp->unit == 1) {
75 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
76 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
77 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
78 ata_printf(scp, device, "simplex device, DMA on primary only\n");
79 return;
80 }
81 }
82
83 if (!scp->dmatab[ATA_DEV(device)]) {
84 void *dmatab;
85
86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT)))
87 return;
88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
90 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
91 free(dmatab, M_DEVBUF);
92 return;
93 }
94 scp->dmatab[ATA_DEV(device)] = dmatab;
95 }
96 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) {
97 ata_printf(scp, device,
98 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
99 udmamode = 2;
100 }
101
102 switch (scp->chiptype) {
103
104 case 0x244b8086: /* Intel ICH2 */
105 if (udmamode >= 5) {
106 int32_t mask48, new48;
107 int16_t word54;
108
109 word54 = pci_read_config(parent, 0x54, 2);
110 if (word54 & (0x10 << devno)) {
111 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
112 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
113 if (bootverbose)
114 ata_printf(scp, device,
115 "%s setting up UDMA5 mode on ICH2 chip\n",
116 (error) ? "failed" : "success");
117 if (!error) {
118 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
119 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
120 pci_write_config(parent, 0x48,
121 (pci_read_config(parent, 0x48, 4) &
122 ~mask48) | new48, 4);
123 pci_write_config(parent, 0x54, word54 & ~(0x1000<<devno),2);
123 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
124 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
125 return;
126 }
127 }
128 }
124 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
125 return;
126 }
127 }
128 }
129 if (udmamode >= 4) {
130 int16_t word54;
131
132 word54 = pci_read_config(parent, 0x54, 2);
133 pci_write_config(parent, 0x54, word54 & ~(0x1000 << devno), 2);
134 }
129 /* make sure eventual ATA100 mode from the BIOS is disabled */
130 pci_write_config(parent, 0x54,
131 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
135 /* FALLTHROUGH */
136
137 case 0x24118086: /* Intel ICH */
138 if (udmamode >= 4) {
139 int32_t mask48, new48;
140 int16_t word54;
141
142 word54 = pci_read_config(parent, 0x54, 2);
143 if (word54 & (0x10 << devno)) {
144 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
145 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
146 if (bootverbose)
147 ata_printf(scp, device,
148 "%s setting up UDMA4 mode on ICH%s chip\n",
149 (error) ? "failed" : "success",
150 (scp->chiptype == 0x244b8086) ? "2" : "");
151 if (!error) {
152 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
153 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
154 pci_write_config(parent, 0x48,
155 (pci_read_config(parent, 0x48, 4) &
156 ~mask48) | new48, 4);
157 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
158 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
159 return;
160 }
161 }
162 }
132 /* FALLTHROUGH */
133
134 case 0x24118086: /* Intel ICH */
135 if (udmamode >= 4) {
136 int32_t mask48, new48;
137 int16_t word54;
138
139 word54 = pci_read_config(parent, 0x54, 2);
140 if (word54 & (0x10 << devno)) {
141 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
142 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
143 if (bootverbose)
144 ata_printf(scp, device,
145 "%s setting up UDMA4 mode on ICH%s chip\n",
146 (error) ? "failed" : "success",
147 (scp->chiptype == 0x244b8086) ? "2" : "");
148 if (!error) {
149 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
150 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
151 pci_write_config(parent, 0x48,
152 (pci_read_config(parent, 0x48, 4) &
153 ~mask48) | new48, 4);
154 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
155 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
156 return;
157 }
158 }
159 }
163 if (udmamode >= 2) {
164 int16_t word54;
165
166 word54 = pci_read_config(parent, 0x54, 2);
167 pci_write_config(parent, 0x54, word54 & ~(1 << devno), 2);
168 }
160 /* make sure eventual ATA66 mode from the BIOS is disabled */
161 pci_write_config(parent, 0x54,
162 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
169 /* FALLTHROUGH */
170
171 case 0x71118086: /* Intel PIIX4 */
172 case 0x71998086: /* Intel PIIX4e */
173 case 0x24218086: /* Intel ICH0 */
174 if (udmamode >= 2) {
175 int32_t mask48, new48;
176
177 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
178 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
179 if (bootverbose)
180 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
181 (error) ? "failed" : "success",
182 (scp->chiptype == 0x244b8086) ? "ICH2" :
183 (scp->chiptype == 0x24118086) ? "ICH" :
184 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
185 if (!error) {
186 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
187 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
188 pci_write_config(parent, 0x48,
189 (pci_read_config(parent, 0x48, 4) &
190 ~mask48) | new48, 4);
191 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
192 return;
193 }
194 }
163 /* FALLTHROUGH */
164
165 case 0x71118086: /* Intel PIIX4 */
166 case 0x71998086: /* Intel PIIX4e */
167 case 0x24218086: /* Intel ICH0 */
168 if (udmamode >= 2) {
169 int32_t mask48, new48;
170
171 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
172 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
173 if (bootverbose)
174 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
175 (error) ? "failed" : "success",
176 (scp->chiptype == 0x244b8086) ? "ICH2" :
177 (scp->chiptype == 0x24118086) ? "ICH" :
178 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
179 if (!error) {
180 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
181 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
182 pci_write_config(parent, 0x48,
183 (pci_read_config(parent, 0x48, 4) &
184 ~mask48) | new48, 4);
185 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
186 return;
187 }
188 }
189 /* make sure eventual ATA33 mode from the BIOS is disabled */
190 pci_write_config(parent, 0x48,
191 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
195 /* FALLTHROUGH */
196
197 case 0x70108086: /* Intel PIIX3 */
198 if (wdmamode >= 2 && apiomode >= 4) {
199 int32_t mask40, new40, mask44, new44;
200
201 /* if SITRE not set doit for both channels */
202 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
203 new40 = pci_read_config(parent, 0x40, 4);
204 new44 = pci_read_config(parent, 0x44, 4);
205 if (!(new40 & 0x00004000)) {
206 new44 &= ~0x0000000f;
207 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
208 }
209 if (!(new40 & 0x40000000)) {
210 new44 &= ~0x000000f0;
211 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
212 }
213 new40 |= 0x40004000;
214 pci_write_config(parent, 0x40, new40, 4);
215 pci_write_config(parent, 0x44, new44, 4);
216 }
217 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
218 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
219 if (bootverbose)
220 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
221 (error) ? "failed" : "success",
222 (scp->chiptype == 0x244b8086) ? "ICH2" :
223 (scp->chiptype == 0x24118086) ? "ICH" :
224 (scp->chiptype == 0x24218086) ? "ICH0" :
225 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4");
226 if (!error) {
227 if (device == ATA_MASTER) {
228 mask40 = 0x0000330f;
229 new40 = 0x00002307;
230 mask44 = 0;
231 new44 = 0;
232 }
233 else {
234 mask40 = 0x000000f0;
235 new40 = 0x00000070;
236 mask44 = 0x0000000f;
237 new44 = 0x0000000b;
238 }
239 if (scp->unit) {
240 mask40 <<= 16;
241 new40 <<= 16;
242 mask44 <<= 4;
243 new44 <<= 4;
244 }
245 pci_write_config(parent, 0x40,
246 (pci_read_config(parent, 0x40, 4) & ~mask40)|
247 new40, 4);
248 pci_write_config(parent, 0x44,
249 (pci_read_config(parent, 0x44, 4) & ~mask44)|
250 new44, 4);
251 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
252 return;
253 }
254 }
255 /* we could set PIO mode timings, but we assume the BIOS did that */
256 break;
257
258 case 0x12308086: /* Intel PIIX */
259 if (wdmamode >= 2 && apiomode >= 4) {
260 int32_t word40;
261
262 word40 = pci_read_config(parent, 0x40, 4);
263 word40 >>= scp->unit * 16;
264
265 /* Check for timing config usable for DMA on controller */
266 if (!((word40 & 0x3300) == 0x2300 &&
267 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
268 break;
269
270 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
271 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
272 if (bootverbose)
273 ata_printf(scp, device,
274 "%s setting up WDMA2 mode on PIIX chip\n",
275 (error) ? "failed" : "success");
276 if (!error) {
277 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
278 return;
279 }
280 }
281 break;
282
283 case 0x522910b9: /* AcerLabs Aladdin IV/V */
284 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
285 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
286 ata_printf(scp, device,
287 "Aladdin: two atapi devices on this channel, no DMA\n");
288 break;
289 }
290 if (udmamode >= 2) {
291 int32_t word54 = pci_read_config(parent, 0x54, 4);
292
293 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
294 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
295 if (bootverbose)
296 ata_printf(scp, device,
297 "%s setting up UDMA2 mode on Aladdin chip\n",
298 (error) ? "failed" : "success");
299 if (!error) {
300 word54 &= ~(0x000f000f << (devno << 2));
301 word54 |= (0x000a0005 << (devno << 2));
302 pci_write_config(parent, 0x54, word54, 4);
303 pci_write_config(parent, 0x53,
304 pci_read_config(parent, 0x53, 1) | 0x03, 1);
305 scp->flags |= ATA_ATAPI_DMA_RO;
306 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
307 return;
308 }
309 }
310 if (wdmamode >= 2 && apiomode >= 4) {
311 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
312 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
313 if (bootverbose)
314 ata_printf(scp, device,
315 "%s setting up WDMA2 mode on Aladdin chip\n",
316 (error) ? "failed" : "success");
317 if (!error) {
318 pci_write_config(parent, 0x53,
319 pci_read_config(parent, 0x53, 1) | 0x03, 1);
320 scp->flags |= ATA_ATAPI_DMA_RO;
321 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
322 return;
323 }
324 }
325 pci_write_config(parent, 0x53,
326 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
327 /* we could set PIO mode timings, but we assume the BIOS did that */
328 break;
329
330 case 0x74091022: /* AMD 756 */
331 if (udmamode >= 4) {
332 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
333 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
334 if (bootverbose)
335 ata_printf(scp, device,
336 "%s setting up UDMA4 mode on AMD chip\n",
337 (error) ? "failed" : "success");
338 if (!error) {
339 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
340 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
341 return;
342 }
343 }
344 goto via_82c586;
345
346 case 0x06861106: /* VIA 82C686 */
347via_82c686:
348 if (udmamode >= 4) {
349 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
350 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
351 if (bootverbose)
352 ata_printf(scp, device,
353 "%s setting up UDMA4 mode on VIA chip\n",
354 (error) ? "failed" : "success");
355 if (!error) {
356 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
357 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
358 return;
359 }
360 }
361 if (udmamode >= 2) {
362 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
363 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
364 if (bootverbose)
365 ata_printf(scp, device,
366 "%s setting up UDMA2 mode on VIA chip\n",
367 (error) ? "failed" : "success");
368 if (!error) {
369 pci_write_config(parent, 0x53 - devno, 0xea, 1);
370 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
371 return;
372 }
373 }
374 goto via_generic;
375
376 case 0x05961106: /* VIA 82C596 */
377 /* 82c596 revision >= 0x12 is like the 82c686 */
378 if (ata_find_dev(parent, 0x05961106, 0x12))
379 goto via_82c686;
380 /* FALLTHROUGH */
381
382 case 0x05861106: /* VIA 82C586 */
383via_82c586:
384 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
385 if ((udmamode >= 2 && ata_find_dev(parent, 0x05861106, 0x02)) ||
386 (udmamode >= 2 && scp->chiptype == 0x05961106) ||
387 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
388 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
389 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
390 if (bootverbose)
391 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
392 (error) ? "failed" : "success",
393 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
394 if (!error) {
395 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
396 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
397 return;
398 }
399 }
400 /* FALLTHROUGH */
401
402 case 0x05711106: /* VIA 82C571 */
403via_generic:
404 if (wdmamode >= 2 && apiomode >= 4) {
405 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
406 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
407 if (bootverbose)
408 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
409 (error) ? "failed" : "success",
410 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
411 if (!error) {
412 pci_write_config(parent, 0x53 - devno, 0x82, 1);
413 pci_write_config(parent, 0x4b - devno, 0x31, 1);
414 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
415 return;
416 }
417 }
418 /* we could set PIO mode timings, but we assume the BIOS did that */
419 break;
420
421 case 0x55131039: /* SiS 5591 */
422 if (udmamode >= 2) {
423 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
424 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
425 if (bootverbose)
426 ata_printf(scp, device,
427 "%s setting up UDMA2 mode on SiS chip\n",
428 (error) ? "failed" : "success");
429 if (!error) {
430 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
431 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
432 return;
433 }
434 }
435 if (wdmamode >=2 && apiomode >= 4) {
436 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
437 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
438 if (bootverbose)
439 ata_printf(scp, device,
440 "%s setting up WDMA2 mode on SiS chip\n",
441 (error) ? "failed" : "success");
442 if (!error) {
443 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
444 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
445 return;
446 }
447 }
448 /* we could set PIO mode timings, but we assume the BIOS did that */
449 break;
450
451 case 0x06461095: /* CMD 646 ATA controller */
452 if (wdmamode >= 2 && apiomode >= 4) {
453 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
454 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
455 if (bootverbose)
456 ata_printf(scp, device,
457 "%s setting up WDMA2 mode on CMD646 chip\n",
458 error ? "failed" : "success");
459 if (!error) {
460 int32_t offset = (devno < 3) ? (devno << 1) : 7;
461
462 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
463 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
464 return;
465 }
466 }
467 /* we could set PIO mode timings, but we assume the BIOS did that */
468 break;
469
470 case 0xc6931080: /* Cypress 82c693 ATA controller */
471 if (wdmamode >= 2 && apiomode >= 4) {
472 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
473 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
474 if (bootverbose)
475 ata_printf(scp, device,
476 "%s setting up WDMA2 mode on Cypress chip\n",
477 error ? "failed" : "success");
478 if (!error) {
479 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2);
480 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
481 return;
482 }
483 }
484 /* we could set PIO mode timings, but we assume the BIOS did that */
485 break;
486
487 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
488 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
489 case 0x4d30105a: /* Promise Ultra100 / FastTrak100 controllers */
490 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
491 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
492 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
493 break;
494
495 if (udmamode >=5 && scp->chiptype == 0x4d30105a &&
496 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
497 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
498 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
499 if (bootverbose)
500 ata_printf(scp, device,
501 "%s setting up UDMA5 mode on Promise chip\n",
502 (error) ? "failed" : "success");
503 if (!error) {
504 promise_timing(scp, devno, ATA_UDMA5);
505 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
506 return;
507 }
508 }
509 if (udmamode >=4 &&
510 (scp->chiptype == 0x4d38105a || scp->chiptype == 0x4d30105a) &&
511 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
512 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
513 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
514 if (bootverbose)
515 ata_printf(scp, device,
516 "%s setting up UDMA4 mode on Promise chip\n",
517 (error) ? "failed" : "success");
518 if (!error) {
519 promise_timing(scp, devno, ATA_UDMA4);
520 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
521 return;
522 }
523 }
524 if (udmamode >= 2) {
525 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
526 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
527 if (bootverbose)
528 ata_printf(scp, device,
529 "%s setting up UDMA2 mode on Promise chip\n",
530 (error) ? "failed" : "success");
531 if (!error) {
532 promise_timing(scp, devno, ATA_UDMA2);
533 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
534 return;
535 }
536 }
537 if (wdmamode >= 2 && apiomode >= 4) {
538 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
539 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
540 if (bootverbose)
541 ata_printf(scp, device,
542 "%s setting up WDMA2 mode on Promise chip\n",
543 (error) ? "failed" : "success");
544 if (!error) {
545 promise_timing(scp, devno, ATA_WDMA2);
546 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
547 return;
548 }
549 }
550 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
551 ata_pio2mode(apiomode),
552 ATA_C_F_SETXFER, ATA_WAIT_READY);
553 if (bootverbose)
554 ata_printf(scp, device,
555 "%s setting up PIO%d mode on Promise chip\n",
556 (error) ? "failed" : "success",
557 (apiomode >= 0) ? apiomode : 0);
558 promise_timing(scp, devno, ata_pio2mode(apiomode));
559 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
560 return;
561
562 case 0x00041103: /* HighPoint HPT366/368/370 controllers */
563 /* no ATAPI devices for now */
564 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
565 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
566 break;
567
568 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
569 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
570 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
571 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
572 if (bootverbose)
573 ata_printf(scp, device,
574 "%s setting up UDMA5 mode on HPT370 chip\n",
575 (error) ? "failed" : "success");
576 if (!error) {
577 hpt_timing(scp, devno, ATA_UDMA5);
578 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
579 return;
580 }
581 }
582
583 if (udmamode >=4 &&
584 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
585 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
586 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
587 if (bootverbose)
588 ata_printf(scp, device,
589 "%s setting up UDMA4 mode on HPT366 chip\n",
590 (error) ? "failed" : "success");
591 if (!error) {
592 hpt_timing(scp, devno, ATA_UDMA4);
593 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
594 return;
595 }
596 }
597 if (udmamode >= 2) {
598 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
599 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
600 if (bootverbose)
601 ata_printf(scp, device,
602 "%s setting up UDMA2 mode on HPT366 chip\n",
603 (error) ? "failed" : "success");
604 if (!error) {
605 hpt_timing(scp, devno, ATA_UDMA2);
606 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
607 return;
608 }
609 }
610 if (wdmamode >= 2 && apiomode >= 4) {
611 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
612 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
613 if (bootverbose)
614 ata_printf(scp, device,
615 "%s setting up WDMA2 mode on HPT366 chip\n",
616 (error) ? "failed" : "success");
617 if (!error) {
618 hpt_timing(scp, devno, ATA_WDMA2);
619 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
620 return;
621 }
622 }
623 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
624 ata_pio2mode(apiomode),
625 ATA_C_F_SETXFER, ATA_WAIT_READY);
626 if (bootverbose)
627 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
628 (error) ? "failed" : "success",
629 (apiomode >= 0) ? apiomode : 0);
630 hpt_timing(scp, devno, ata_pio2mode(apiomode));
631 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
632 return;
633
634 default: /* unknown controller chip */
635 /* better not try generic DMA on ATAPI devices it almost never works */
636 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
637 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
638 break;
639
640 /* if controller says its setup for DMA take the easy way out */
641 /* the downside is we dont know what DMA mode we are in */
642 if ((udmamode >= 0 || wdmamode > 1) &&
643 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
644 ((device==ATA_MASTER) ?
645 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
646 scp->mode[ATA_DEV(device)] = ATA_DMA;
647 return;
648 }
649
650 /* well, we have no support for this, but try anyways */
651 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
652 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
653 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
654 if (bootverbose)
655 ata_printf(scp, device,
656 "%s setting up WDMA2 mode on generic chip\n",
657 (error) ? "failed" : "success");
658 if (!error) {
659 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
660 return;
661 }
662 }
663 }
664 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
665 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
666 if (bootverbose)
667 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n",
668 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
669 if (!error)
670 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
671 else {
672 if (bootverbose)
673 ata_printf(scp, device, "using PIO mode set by BIOS\n");
674 scp->mode[ATA_DEV(device)] = ATA_PIO;
675 }
676}
677
678int32_t
679ata_dmasetup(struct ata_softc *scp, int32_t device,
680 int8_t *data, int32_t count, int32_t flags)
681{
682 struct ata_dmaentry *dmatab;
683 u_int32_t dma_count, dma_base;
684 int i = 0;
685
686 if (((uintptr_t)data & 1) || (count & 1))
687 return -1;
688
689 if (!count) {
690 ata_printf(scp, device, "zero length DMA transfer attempted\n");
691 return -1;
692 }
693
694 dmatab = scp->dmatab[ATA_DEV(device)];
695 dma_base = vtophys(data);
696 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
697 data += dma_count;
698 count -= dma_count;
699
700 while (count) {
701 dmatab[i].base = dma_base;
702 dmatab[i].count = (dma_count & 0xffff);
703 i++;
704 if (i >= ATA_DMA_ENTRIES) {
705 ata_printf(scp, device, "too many segments in DMA table\n");
706 return -1;
707 }
708 dma_base = vtophys(data);
709 dma_count = min(count, PAGE_SIZE);
710 data += min(count, PAGE_SIZE);
711 count -= min(count, PAGE_SIZE);
712 }
713 dmatab[i].base = dma_base;
714 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
715 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
716 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
717 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
718 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
719 return 0;
720}
721
722void
723ata_dmastart(struct ata_softc *scp)
724{
725 scp->flags |= ATA_DMA_ACTIVE;
726 outb(scp->bmaddr + ATA_BMCMD_PORT,
727 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
728}
729
730int32_t
731ata_dmadone(struct ata_softc *scp)
732{
733 outb(scp->bmaddr + ATA_BMCMD_PORT,
734 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
735 scp->flags &= ~ATA_DMA_ACTIVE;
736 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
737}
738
739int32_t
740ata_dmastatus(struct ata_softc *scp)
741{
742 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
743}
744
745static void
746promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
747{
748 u_int32_t timing = 0;
749 struct promise_timing {
750 u_int8_t pa:4;
751 u_int8_t prefetch:1;
752 u_int8_t iordy:1;
753 u_int8_t errdy:1;
754 u_int8_t syncin:1;
755 u_int8_t pb:5;
756 u_int8_t mb:3;
757 u_int8_t mc:4;
758 u_int8_t dmaw:1;
759 u_int8_t dmar:1;
760 u_int8_t iordyp:1;
761 u_int8_t dmarqp:1;
762 u_int8_t reserved:8;
763 } *t = (struct promise_timing*)&timing;
764
765 t->iordy = 1; t->iordyp = 1;
766 if (mode >= ATA_DMA) {
767 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
768 }
769
770 switch (scp->chiptype) {
771 case 0x4d33105a: /* Promise 33's */
772 switch (mode) {
773 default:
774 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
775 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
776 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
777 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
778 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
779 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
780 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
781 }
782 break;
783
784 case 0x4d38105a: /* Promise 66's */
785 case 0x4d30105a: /* Promise 100's */
786 switch (mode) {
787 default:
788 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
789 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
790 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
791 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
792 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
793 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
794 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
795 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
796 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
797 }
798 break;
799 }
800 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
801}
802
803static void
804hpt_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
805{
806 device_t parent = device_get_parent(scp->dev);
807 u_int32_t timing;
808
809 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
810 switch (mode) {
811 case ATA_PIO0: timing = 0x06914e57; break;
812 case ATA_PIO1: timing = 0x06914e43; break;
813 case ATA_PIO2: timing = 0x06514e33; break;
814 case ATA_PIO3: timing = 0x06514e22; break;
815 case ATA_PIO4: timing = 0x06514e21; break;
816 case ATA_WDMA2: timing = 0x26514e21; break;
817 case ATA_UDMA2: timing = 0x16494e31; break;
818 case ATA_UDMA4: timing = 0x16454e31; break;
819 case ATA_UDMA5: timing = 0x16454e31; break;
820 default: timing = 0x06514e57;
821 }
822 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
823 pci_write_config(parent, 0x5b, 0x22, 1);
824 }
825 else { /* HPT36[68] */
826 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
827 case 0x85: /* 25Mhz */
828 switch (mode) {
829 case ATA_PIO0: timing = 0xc0d08585; break;
830 case ATA_PIO1: timing = 0xc0d08572; break;
831 case ATA_PIO2: timing = 0xc0ca8542; break;
832 case ATA_PIO3: timing = 0xc0ca8532; break;
833 case ATA_PIO4: timing = 0xc0ca8521; break;
834 case ATA_WDMA2: timing = 0xa0ca8521; break;
835 case ATA_UDMA2: timing = 0x90cf8521; break;
836 case ATA_UDMA4: timing = 0x90c98521; break;
837 default: timing = 0x01208585;
838 }
839 break;
840 default:
841 case 0xa7: /* 33MHz */
842 switch (mode) {
843 case ATA_PIO0: timing = 0xc0d0a7aa; break;
844 case ATA_PIO1: timing = 0xc0d0a7a3; break;
845 case ATA_PIO2: timing = 0xc0d0a753; break;
846 case ATA_PIO3: timing = 0xc0c8a742; break;
847 case ATA_PIO4: timing = 0xc0c8a731; break;
848 case ATA_WDMA2: timing = 0xa0c8a731; break;
849 case ATA_UDMA2: timing = 0x90caa731; break;
850 case ATA_UDMA4: timing = 0x90c9a731; break;
851 default: timing = 0x0120a7a7;
852 }
853 break;
854 case 0xd9: /* 40Mhz */
855 switch (mode) {
856 case ATA_PIO0: timing = 0xc018d9d9; break;
857 case ATA_PIO1: timing = 0xc010d9c7; break;
858 case ATA_PIO2: timing = 0xc010d997; break;
859 case ATA_PIO3: timing = 0xc010d974; break;
860 case ATA_PIO4: timing = 0xc008d963; break;
861 case ATA_WDMA2: timing = 0xa008d943; break;
862 case ATA_UDMA2: timing = 0x900bd943; break;
863 case ATA_UDMA4: timing = 0x900fd943; break;
864 default: timing = 0x0120d9d9;
865 }
866 }
867 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
868 }
869}
870
871#else /* NPCI > 0 */
872
873void
874ata_dmainit(struct ata_softc *scp, int32_t device,
875 int32_t piomode, int32_t wdmamode, int32_t udmamode)
876{
877}
878
879int32_t
880ata_dmasetup(struct ata_softc *scp, int32_t device,
881 int8_t *data, int32_t count, int32_t flags)
882{
883 return -1;
884}
885
886void
887ata_dmastart(struct ata_softc *scp)
888{
889}
890
891int32_t
892ata_dmadone(struct ata_softc *scp)
893{
894 return -1;
895}
896
897int32_t
898ata_dmastatus(struct ata_softc *scp)
899{
900 return -1;
901}
902
903#endif /* NPCI > 0 */
192 /* FALLTHROUGH */
193
194 case 0x70108086: /* Intel PIIX3 */
195 if (wdmamode >= 2 && apiomode >= 4) {
196 int32_t mask40, new40, mask44, new44;
197
198 /* if SITRE not set doit for both channels */
199 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
200 new40 = pci_read_config(parent, 0x40, 4);
201 new44 = pci_read_config(parent, 0x44, 4);
202 if (!(new40 & 0x00004000)) {
203 new44 &= ~0x0000000f;
204 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
205 }
206 if (!(new40 & 0x40000000)) {
207 new44 &= ~0x000000f0;
208 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
209 }
210 new40 |= 0x40004000;
211 pci_write_config(parent, 0x40, new40, 4);
212 pci_write_config(parent, 0x44, new44, 4);
213 }
214 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
215 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
216 if (bootverbose)
217 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
218 (error) ? "failed" : "success",
219 (scp->chiptype == 0x244b8086) ? "ICH2" :
220 (scp->chiptype == 0x24118086) ? "ICH" :
221 (scp->chiptype == 0x24218086) ? "ICH0" :
222 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4");
223 if (!error) {
224 if (device == ATA_MASTER) {
225 mask40 = 0x0000330f;
226 new40 = 0x00002307;
227 mask44 = 0;
228 new44 = 0;
229 }
230 else {
231 mask40 = 0x000000f0;
232 new40 = 0x00000070;
233 mask44 = 0x0000000f;
234 new44 = 0x0000000b;
235 }
236 if (scp->unit) {
237 mask40 <<= 16;
238 new40 <<= 16;
239 mask44 <<= 4;
240 new44 <<= 4;
241 }
242 pci_write_config(parent, 0x40,
243 (pci_read_config(parent, 0x40, 4) & ~mask40)|
244 new40, 4);
245 pci_write_config(parent, 0x44,
246 (pci_read_config(parent, 0x44, 4) & ~mask44)|
247 new44, 4);
248 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
249 return;
250 }
251 }
252 /* we could set PIO mode timings, but we assume the BIOS did that */
253 break;
254
255 case 0x12308086: /* Intel PIIX */
256 if (wdmamode >= 2 && apiomode >= 4) {
257 int32_t word40;
258
259 word40 = pci_read_config(parent, 0x40, 4);
260 word40 >>= scp->unit * 16;
261
262 /* Check for timing config usable for DMA on controller */
263 if (!((word40 & 0x3300) == 0x2300 &&
264 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
265 break;
266
267 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
268 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
269 if (bootverbose)
270 ata_printf(scp, device,
271 "%s setting up WDMA2 mode on PIIX chip\n",
272 (error) ? "failed" : "success");
273 if (!error) {
274 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
275 return;
276 }
277 }
278 break;
279
280 case 0x522910b9: /* AcerLabs Aladdin IV/V */
281 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
282 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
283 ata_printf(scp, device,
284 "Aladdin: two atapi devices on this channel, no DMA\n");
285 break;
286 }
287 if (udmamode >= 2) {
288 int32_t word54 = pci_read_config(parent, 0x54, 4);
289
290 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
291 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
292 if (bootverbose)
293 ata_printf(scp, device,
294 "%s setting up UDMA2 mode on Aladdin chip\n",
295 (error) ? "failed" : "success");
296 if (!error) {
297 word54 &= ~(0x000f000f << (devno << 2));
298 word54 |= (0x000a0005 << (devno << 2));
299 pci_write_config(parent, 0x54, word54, 4);
300 pci_write_config(parent, 0x53,
301 pci_read_config(parent, 0x53, 1) | 0x03, 1);
302 scp->flags |= ATA_ATAPI_DMA_RO;
303 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
304 return;
305 }
306 }
307 if (wdmamode >= 2 && apiomode >= 4) {
308 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
309 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
310 if (bootverbose)
311 ata_printf(scp, device,
312 "%s setting up WDMA2 mode on Aladdin chip\n",
313 (error) ? "failed" : "success");
314 if (!error) {
315 pci_write_config(parent, 0x53,
316 pci_read_config(parent, 0x53, 1) | 0x03, 1);
317 scp->flags |= ATA_ATAPI_DMA_RO;
318 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
319 return;
320 }
321 }
322 pci_write_config(parent, 0x53,
323 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
324 /* we could set PIO mode timings, but we assume the BIOS did that */
325 break;
326
327 case 0x74091022: /* AMD 756 */
328 if (udmamode >= 4) {
329 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
330 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
331 if (bootverbose)
332 ata_printf(scp, device,
333 "%s setting up UDMA4 mode on AMD chip\n",
334 (error) ? "failed" : "success");
335 if (!error) {
336 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
337 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
338 return;
339 }
340 }
341 goto via_82c586;
342
343 case 0x06861106: /* VIA 82C686 */
344via_82c686:
345 if (udmamode >= 4) {
346 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
347 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
348 if (bootverbose)
349 ata_printf(scp, device,
350 "%s setting up UDMA4 mode on VIA chip\n",
351 (error) ? "failed" : "success");
352 if (!error) {
353 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
354 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
355 return;
356 }
357 }
358 if (udmamode >= 2) {
359 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
360 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
361 if (bootverbose)
362 ata_printf(scp, device,
363 "%s setting up UDMA2 mode on VIA chip\n",
364 (error) ? "failed" : "success");
365 if (!error) {
366 pci_write_config(parent, 0x53 - devno, 0xea, 1);
367 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
368 return;
369 }
370 }
371 goto via_generic;
372
373 case 0x05961106: /* VIA 82C596 */
374 /* 82c596 revision >= 0x12 is like the 82c686 */
375 if (ata_find_dev(parent, 0x05961106, 0x12))
376 goto via_82c686;
377 /* FALLTHROUGH */
378
379 case 0x05861106: /* VIA 82C586 */
380via_82c586:
381 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
382 if ((udmamode >= 2 && ata_find_dev(parent, 0x05861106, 0x02)) ||
383 (udmamode >= 2 && scp->chiptype == 0x05961106) ||
384 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
386 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
387 if (bootverbose)
388 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
389 (error) ? "failed" : "success",
390 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
391 if (!error) {
392 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
393 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
394 return;
395 }
396 }
397 /* FALLTHROUGH */
398
399 case 0x05711106: /* VIA 82C571 */
400via_generic:
401 if (wdmamode >= 2 && apiomode >= 4) {
402 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
403 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
404 if (bootverbose)
405 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
406 (error) ? "failed" : "success",
407 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
408 if (!error) {
409 pci_write_config(parent, 0x53 - devno, 0x82, 1);
410 pci_write_config(parent, 0x4b - devno, 0x31, 1);
411 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
412 return;
413 }
414 }
415 /* we could set PIO mode timings, but we assume the BIOS did that */
416 break;
417
418 case 0x55131039: /* SiS 5591 */
419 if (udmamode >= 2) {
420 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
421 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
422 if (bootverbose)
423 ata_printf(scp, device,
424 "%s setting up UDMA2 mode on SiS chip\n",
425 (error) ? "failed" : "success");
426 if (!error) {
427 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
428 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
429 return;
430 }
431 }
432 if (wdmamode >=2 && apiomode >= 4) {
433 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
434 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
435 if (bootverbose)
436 ata_printf(scp, device,
437 "%s setting up WDMA2 mode on SiS chip\n",
438 (error) ? "failed" : "success");
439 if (!error) {
440 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
441 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
442 return;
443 }
444 }
445 /* we could set PIO mode timings, but we assume the BIOS did that */
446 break;
447
448 case 0x06461095: /* CMD 646 ATA controller */
449 if (wdmamode >= 2 && apiomode >= 4) {
450 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
451 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
452 if (bootverbose)
453 ata_printf(scp, device,
454 "%s setting up WDMA2 mode on CMD646 chip\n",
455 error ? "failed" : "success");
456 if (!error) {
457 int32_t offset = (devno < 3) ? (devno << 1) : 7;
458
459 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
460 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
461 return;
462 }
463 }
464 /* we could set PIO mode timings, but we assume the BIOS did that */
465 break;
466
467 case 0xc6931080: /* Cypress 82c693 ATA controller */
468 if (wdmamode >= 2 && apiomode >= 4) {
469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
470 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
471 if (bootverbose)
472 ata_printf(scp, device,
473 "%s setting up WDMA2 mode on Cypress chip\n",
474 error ? "failed" : "success");
475 if (!error) {
476 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2);
477 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
478 return;
479 }
480 }
481 /* we could set PIO mode timings, but we assume the BIOS did that */
482 break;
483
484 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
485 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
486 case 0x4d30105a: /* Promise Ultra100 / FastTrak100 controllers */
487 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
488 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
489 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
490 break;
491
492 if (udmamode >=5 && scp->chiptype == 0x4d30105a &&
493 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
494 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
495 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
496 if (bootverbose)
497 ata_printf(scp, device,
498 "%s setting up UDMA5 mode on Promise chip\n",
499 (error) ? "failed" : "success");
500 if (!error) {
501 promise_timing(scp, devno, ATA_UDMA5);
502 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
503 return;
504 }
505 }
506 if (udmamode >=4 &&
507 (scp->chiptype == 0x4d38105a || scp->chiptype == 0x4d30105a) &&
508 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
509 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
510 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
511 if (bootverbose)
512 ata_printf(scp, device,
513 "%s setting up UDMA4 mode on Promise chip\n",
514 (error) ? "failed" : "success");
515 if (!error) {
516 promise_timing(scp, devno, ATA_UDMA4);
517 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
518 return;
519 }
520 }
521 if (udmamode >= 2) {
522 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
523 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
524 if (bootverbose)
525 ata_printf(scp, device,
526 "%s setting up UDMA2 mode on Promise chip\n",
527 (error) ? "failed" : "success");
528 if (!error) {
529 promise_timing(scp, devno, ATA_UDMA2);
530 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
531 return;
532 }
533 }
534 if (wdmamode >= 2 && apiomode >= 4) {
535 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
536 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
537 if (bootverbose)
538 ata_printf(scp, device,
539 "%s setting up WDMA2 mode on Promise chip\n",
540 (error) ? "failed" : "success");
541 if (!error) {
542 promise_timing(scp, devno, ATA_WDMA2);
543 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
544 return;
545 }
546 }
547 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
548 ata_pio2mode(apiomode),
549 ATA_C_F_SETXFER, ATA_WAIT_READY);
550 if (bootverbose)
551 ata_printf(scp, device,
552 "%s setting up PIO%d mode on Promise chip\n",
553 (error) ? "failed" : "success",
554 (apiomode >= 0) ? apiomode : 0);
555 promise_timing(scp, devno, ata_pio2mode(apiomode));
556 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
557 return;
558
559 case 0x00041103: /* HighPoint HPT366/368/370 controllers */
560 /* no ATAPI devices for now */
561 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
562 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
563 break;
564
565 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
566 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
567 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
568 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
569 if (bootverbose)
570 ata_printf(scp, device,
571 "%s setting up UDMA5 mode on HPT370 chip\n",
572 (error) ? "failed" : "success");
573 if (!error) {
574 hpt_timing(scp, devno, ATA_UDMA5);
575 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
576 return;
577 }
578 }
579
580 if (udmamode >=4 &&
581 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
582 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
583 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
584 if (bootverbose)
585 ata_printf(scp, device,
586 "%s setting up UDMA4 mode on HPT366 chip\n",
587 (error) ? "failed" : "success");
588 if (!error) {
589 hpt_timing(scp, devno, ATA_UDMA4);
590 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
591 return;
592 }
593 }
594 if (udmamode >= 2) {
595 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
596 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
597 if (bootverbose)
598 ata_printf(scp, device,
599 "%s setting up UDMA2 mode on HPT366 chip\n",
600 (error) ? "failed" : "success");
601 if (!error) {
602 hpt_timing(scp, devno, ATA_UDMA2);
603 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
604 return;
605 }
606 }
607 if (wdmamode >= 2 && apiomode >= 4) {
608 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
609 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
610 if (bootverbose)
611 ata_printf(scp, device,
612 "%s setting up WDMA2 mode on HPT366 chip\n",
613 (error) ? "failed" : "success");
614 if (!error) {
615 hpt_timing(scp, devno, ATA_WDMA2);
616 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
617 return;
618 }
619 }
620 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
621 ata_pio2mode(apiomode),
622 ATA_C_F_SETXFER, ATA_WAIT_READY);
623 if (bootverbose)
624 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
625 (error) ? "failed" : "success",
626 (apiomode >= 0) ? apiomode : 0);
627 hpt_timing(scp, devno, ata_pio2mode(apiomode));
628 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
629 return;
630
631 default: /* unknown controller chip */
632 /* better not try generic DMA on ATAPI devices it almost never works */
633 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
634 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
635 break;
636
637 /* if controller says its setup for DMA take the easy way out */
638 /* the downside is we dont know what DMA mode we are in */
639 if ((udmamode >= 0 || wdmamode > 1) &&
640 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
641 ((device==ATA_MASTER) ?
642 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
643 scp->mode[ATA_DEV(device)] = ATA_DMA;
644 return;
645 }
646
647 /* well, we have no support for this, but try anyways */
648 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
649 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
650 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
651 if (bootverbose)
652 ata_printf(scp, device,
653 "%s setting up WDMA2 mode on generic chip\n",
654 (error) ? "failed" : "success");
655 if (!error) {
656 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
657 return;
658 }
659 }
660 }
661 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
662 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
663 if (bootverbose)
664 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n",
665 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
666 if (!error)
667 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
668 else {
669 if (bootverbose)
670 ata_printf(scp, device, "using PIO mode set by BIOS\n");
671 scp->mode[ATA_DEV(device)] = ATA_PIO;
672 }
673}
674
675int32_t
676ata_dmasetup(struct ata_softc *scp, int32_t device,
677 int8_t *data, int32_t count, int32_t flags)
678{
679 struct ata_dmaentry *dmatab;
680 u_int32_t dma_count, dma_base;
681 int i = 0;
682
683 if (((uintptr_t)data & 1) || (count & 1))
684 return -1;
685
686 if (!count) {
687 ata_printf(scp, device, "zero length DMA transfer attempted\n");
688 return -1;
689 }
690
691 dmatab = scp->dmatab[ATA_DEV(device)];
692 dma_base = vtophys(data);
693 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
694 data += dma_count;
695 count -= dma_count;
696
697 while (count) {
698 dmatab[i].base = dma_base;
699 dmatab[i].count = (dma_count & 0xffff);
700 i++;
701 if (i >= ATA_DMA_ENTRIES) {
702 ata_printf(scp, device, "too many segments in DMA table\n");
703 return -1;
704 }
705 dma_base = vtophys(data);
706 dma_count = min(count, PAGE_SIZE);
707 data += min(count, PAGE_SIZE);
708 count -= min(count, PAGE_SIZE);
709 }
710 dmatab[i].base = dma_base;
711 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
712 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
713 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
714 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
715 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
716 return 0;
717}
718
719void
720ata_dmastart(struct ata_softc *scp)
721{
722 scp->flags |= ATA_DMA_ACTIVE;
723 outb(scp->bmaddr + ATA_BMCMD_PORT,
724 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
725}
726
727int32_t
728ata_dmadone(struct ata_softc *scp)
729{
730 outb(scp->bmaddr + ATA_BMCMD_PORT,
731 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
732 scp->flags &= ~ATA_DMA_ACTIVE;
733 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
734}
735
736int32_t
737ata_dmastatus(struct ata_softc *scp)
738{
739 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
740}
741
742static void
743promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
744{
745 u_int32_t timing = 0;
746 struct promise_timing {
747 u_int8_t pa:4;
748 u_int8_t prefetch:1;
749 u_int8_t iordy:1;
750 u_int8_t errdy:1;
751 u_int8_t syncin:1;
752 u_int8_t pb:5;
753 u_int8_t mb:3;
754 u_int8_t mc:4;
755 u_int8_t dmaw:1;
756 u_int8_t dmar:1;
757 u_int8_t iordyp:1;
758 u_int8_t dmarqp:1;
759 u_int8_t reserved:8;
760 } *t = (struct promise_timing*)&timing;
761
762 t->iordy = 1; t->iordyp = 1;
763 if (mode >= ATA_DMA) {
764 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
765 }
766
767 switch (scp->chiptype) {
768 case 0x4d33105a: /* Promise 33's */
769 switch (mode) {
770 default:
771 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
772 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
773 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
774 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
775 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
776 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
777 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
778 }
779 break;
780
781 case 0x4d38105a: /* Promise 66's */
782 case 0x4d30105a: /* Promise 100's */
783 switch (mode) {
784 default:
785 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
786 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
787 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
788 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
789 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
790 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
791 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
792 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
793 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
794 }
795 break;
796 }
797 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
798}
799
800static void
801hpt_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
802{
803 device_t parent = device_get_parent(scp->dev);
804 u_int32_t timing;
805
806 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
807 switch (mode) {
808 case ATA_PIO0: timing = 0x06914e57; break;
809 case ATA_PIO1: timing = 0x06914e43; break;
810 case ATA_PIO2: timing = 0x06514e33; break;
811 case ATA_PIO3: timing = 0x06514e22; break;
812 case ATA_PIO4: timing = 0x06514e21; break;
813 case ATA_WDMA2: timing = 0x26514e21; break;
814 case ATA_UDMA2: timing = 0x16494e31; break;
815 case ATA_UDMA4: timing = 0x16454e31; break;
816 case ATA_UDMA5: timing = 0x16454e31; break;
817 default: timing = 0x06514e57;
818 }
819 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
820 pci_write_config(parent, 0x5b, 0x22, 1);
821 }
822 else { /* HPT36[68] */
823 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
824 case 0x85: /* 25Mhz */
825 switch (mode) {
826 case ATA_PIO0: timing = 0xc0d08585; break;
827 case ATA_PIO1: timing = 0xc0d08572; break;
828 case ATA_PIO2: timing = 0xc0ca8542; break;
829 case ATA_PIO3: timing = 0xc0ca8532; break;
830 case ATA_PIO4: timing = 0xc0ca8521; break;
831 case ATA_WDMA2: timing = 0xa0ca8521; break;
832 case ATA_UDMA2: timing = 0x90cf8521; break;
833 case ATA_UDMA4: timing = 0x90c98521; break;
834 default: timing = 0x01208585;
835 }
836 break;
837 default:
838 case 0xa7: /* 33MHz */
839 switch (mode) {
840 case ATA_PIO0: timing = 0xc0d0a7aa; break;
841 case ATA_PIO1: timing = 0xc0d0a7a3; break;
842 case ATA_PIO2: timing = 0xc0d0a753; break;
843 case ATA_PIO3: timing = 0xc0c8a742; break;
844 case ATA_PIO4: timing = 0xc0c8a731; break;
845 case ATA_WDMA2: timing = 0xa0c8a731; break;
846 case ATA_UDMA2: timing = 0x90caa731; break;
847 case ATA_UDMA4: timing = 0x90c9a731; break;
848 default: timing = 0x0120a7a7;
849 }
850 break;
851 case 0xd9: /* 40Mhz */
852 switch (mode) {
853 case ATA_PIO0: timing = 0xc018d9d9; break;
854 case ATA_PIO1: timing = 0xc010d9c7; break;
855 case ATA_PIO2: timing = 0xc010d997; break;
856 case ATA_PIO3: timing = 0xc010d974; break;
857 case ATA_PIO4: timing = 0xc008d963; break;
858 case ATA_WDMA2: timing = 0xa008d943; break;
859 case ATA_UDMA2: timing = 0x900bd943; break;
860 case ATA_UDMA4: timing = 0x900fd943; break;
861 default: timing = 0x0120d9d9;
862 }
863 }
864 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
865 }
866}
867
868#else /* NPCI > 0 */
869
870void
871ata_dmainit(struct ata_softc *scp, int32_t device,
872 int32_t piomode, int32_t wdmamode, int32_t udmamode)
873{
874}
875
876int32_t
877ata_dmasetup(struct ata_softc *scp, int32_t device,
878 int8_t *data, int32_t count, int32_t flags)
879{
880 return -1;
881}
882
883void
884ata_dmastart(struct ata_softc *scp)
885{
886}
887
888int32_t
889ata_dmadone(struct ata_softc *scp)
890{
891 return -1;
892}
893
894int32_t
895ata_dmastatus(struct ata_softc *scp)
896{
897 return -1;
898}
899
900#endif /* NPCI > 0 */