63void 64ata_dmainit(struct ata_softc *scp, int32_t device, 65 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 66{ 67 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 68 int32_t error; 69 70 /* set our most pessimistic default mode */ 71 scp->mode[ATA_DEV(device)] = ATA_PIO; 72 73 if (!scp->bmaddr) 74 return; 75 76 /* if simplex controller, only allow DMA on primary channel */ 77 if (scp->unit == 1) { 78 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 79 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 80 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 81 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 82 return; 83 } 84 } 85 86 if (!scp->dmatab[ATA_DEV(device)]) { 87 void *dmatab; 88 89 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 90 return; 91 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 92 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 93 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 94 free(dmatab, M_DEVBUF); 95 return; 96 } 97 scp->dmatab[ATA_DEV(device)] = dmatab; 98 } 99 100 switch (scp->chiptype) { 101 102 case 0x71118086: /* Intel PIIX4 */ 103 case 0x71998086: /* Intel PIIX4e */ 104 case 0x24118086: /* Intel ICH */ 105 case 0x24218086: /* Intel ICH0 */ 106 if (udmamode >= 2) { 107 int32_t mask48, new48; 108 109 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 110 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 111 if (bootverbose) 112 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 113 (error) ? "failed" : "success", 114 (scp->chiptype == 0x24118086) ? "ICH" : 115 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 116 if (!error) { 117 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 118 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 119 pci_write_config(scp->dev, 0x48, 120 (pci_read_config(scp->dev, 0x48, 4) & 121 ~mask48) | new48, 4); 122 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 123 return; 124 } 125 } 126 /* FALLTHROUGH */ 127 128 case 0x70108086: /* Intel PIIX3 */ 129 if (wdmamode >= 2 && apiomode >= 4) { 130 int32_t mask40, new40, mask44, new44; 131 132 /* if SITRE not set doit for both channels */ 133 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 134 new40 = pci_read_config(scp->dev, 0x40, 4); 135 new44 = pci_read_config(scp->dev, 0x44, 4); 136 if (!(new40 & 0x00004000)) { 137 new44 &= ~0x0000000f; 138 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 139 } 140 if (!(new40 & 0x40000000)) { 141 new44 &= ~0x000000f0; 142 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 143 } 144 new40 |= 0x40004000; 145 pci_write_config(scp->dev, 0x40, new40, 4); 146 pci_write_config(scp->dev, 0x44, new44, 4); 147 } 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 152 (error) ? "failed" : "success", 153 (scp->chiptype == 0x70108086) ? "PIIX3" : 154 (scp->chiptype == 0x24118086) ? "ICH" : 155 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 156 if (!error) { 157 if (device == ATA_MASTER) { 158 mask40 = 0x0000330f; 159 new40 = 0x00002307; 160 mask44 = 0; 161 new44 = 0; 162 } 163 else { 164 mask40 = 0x000000f0; 165 new40 = 0x00000070; 166 mask44 = 0x0000000f; 167 new44 = 0x0000000b; 168 } 169 if (scp->unit) { 170 mask40 <<= 16; 171 new40 <<= 16; 172 mask44 <<= 4; 173 new44 <<= 4; 174 } 175 pci_write_config(scp->dev, 0x40, 176 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)| 177 new40, 4); 178 pci_write_config(scp->dev, 0x44, 179 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)| 180 new44, 4); 181 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 182 return; 183 } 184 } 185 /* we could set PIO mode timings, but we assume the BIOS did that */ 186 break; 187 188 case 0x12308086: /* Intel PIIX */ 189 if (wdmamode >= 2 && apiomode >= 4) { 190 int32_t word40; 191 192 word40 = pci_read_config(scp->dev, 0x40, 4); 193 word40 >>= scp->unit * 16; 194 195 /* Check for timing config usable for DMA on controller */ 196 if (!((word40 & 0x3300) == 0x2300 && 197 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 198 break; 199 200 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 201 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 202 if (bootverbose) 203 ata_printf(scp, device, 204 "%s setting up WDMA2 mode on PIIX chip\n", 205 (error) ? "failed" : "success"); 206 if (!error) { 207 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 208 return; 209 } 210 } 211 break; 212 213 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 214 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 215 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 216 ata_printf(scp, device, 217 "Aladdin: two atapi devices on this channel, no DMA\n"); 218 break; 219 } 220 if (udmamode >= 2) { 221 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 222 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, 227 "%s setting up UDMA2 mode on Aladdin chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 word54 |= 0x5555; 231 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 232 pci_write_config(scp->dev, 0x54, word54, 4); 233 pci_write_config(scp->dev, 0x53, 234 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 235 scp->flags |= ATA_ATAPI_DMA_RO; 236 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 237 return; 238 } 239 } 240 if (wdmamode >= 2 && apiomode >= 4) { 241 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 242 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 243 if (bootverbose) 244 ata_printf(scp, device, 245 "%s setting up WDMA2 mode on Aladdin chip\n", 246 (error) ? "failed" : "success"); 247 if (!error) { 248 pci_write_config(scp->dev, 0x53, 249 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 250 scp->flags |= ATA_ATAPI_DMA_RO; 251 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 252 return; 253 } 254 } 255 /* we could set PIO mode timings, but we assume the BIOS did that */ 256 break; 257 258 case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */ 259 case 0x74091022: /* AMD 756 */ 260 /* UDMA modes on 82C686 */ 261 if (ata_find_dev(scp->dev, 0x06861106)) { 262 if (udmamode >= 4) { 263 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 264 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 265 if (bootverbose) 266 ata_printf(scp, device, 267 "%s setting up UDMA4 mode on VIA chip\n", 268 (error) ? "failed" : "success"); 269 if (!error) { 270 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1); 271 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 272 return; 273 } 274 } 275 if (udmamode >= 2) { 276 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 277 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 278 if (bootverbose) 279 ata_printf(scp, device, 280 "%s setting up UDMA2 mode on VIA chip\n", 281 (error) ? "failed" : "success"); 282 if (!error) { 283 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1); 284 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 285 return; 286 } 287 } 288 } 289 290 /* UDMA4 mode on AMD 756 */ 291 if (udmamode >= 4 && scp->chiptype == 0x74091022) { 292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 293 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 294 if (bootverbose) 295 ata_printf(scp, device, 296 "%s setting up UDMA4 mode on AMD chip\n", 297 (error) ? "failed" : "success"); 298 if (!error) { 299 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1); 300 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 301 return; 302 } 303 } 304 305 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 306 if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) && 307 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 308 (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) || 309 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 310 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 311 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 312 if (bootverbose) 313 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 314 (error) ? "failed" : "success", 315 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 316 if (!error) { 317 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1); 318 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 319 return; 320 } 321 } 322 if (wdmamode >= 2 && apiomode >= 4) { 323 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 324 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 325 if (bootverbose) 326 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 327 (error) ? "failed" : "success", 328 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 329 if (!error) { 330 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1); 331 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1); 332 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 333 return; 334 } 335 } 336 /* we could set PIO mode timings, but we assume the BIOS did that */ 337 break; 338 339 case 0x55131039: /* SiS 5591 */ 340 if (udmamode >= 2) { 341 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 342 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 343 if (bootverbose) 344 ata_printf(scp, device, 345 "%s setting up UDMA2 mode on SiS chip\n", 346 (error) ? "failed" : "success"); 347 if (!error) { 348 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2); 349 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 350 return; 351 } 352 } 353 if (wdmamode >=2 && apiomode >= 4) { 354 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 355 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 356 if (bootverbose) 357 ata_printf(scp, device, 358 "%s setting up WDMA2 mode on SiS chip\n", 359 (error) ? "failed" : "success"); 360 if (!error) { 361 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2); 362 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 363 return; 364 } 365 } 366 /* we could set PIO mode timings, but we assume the BIOS did that */ 367 break; 368 369 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 370 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 371 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 372 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 373 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 374 break; 375 376 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 377 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 379 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 380 if (bootverbose) 381 ata_printf(scp, device, 382 "%s setting up UDMA4 mode on Promise chip\n", 383 (error) ? "failed" : "success"); 384 if (!error) { 385 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2); 386 promise_timing(scp, devno, ATA_UDMA4); 387 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 388 return; 389 } 390 } 391 if (udmamode >= 2) { 392 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 393 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 394 if (bootverbose) 395 ata_printf(scp, device, 396 "%s setting up UDMA2 mode on Promise chip\n", 397 (error) ? "failed" : "success"); 398 if (!error) { 399 promise_timing(scp, devno, ATA_UDMA2); 400 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 401 return; 402 } 403 } 404 if (wdmamode >= 2 && apiomode >= 4) { 405 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 406 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 407 if (bootverbose) 408 ata_printf(scp, device, 409 "%s setting up WDMA2 mode on Promise chip\n", 410 (error) ? "failed" : "success"); 411 if (!error) { 412 promise_timing(scp, devno, ATA_WDMA2); 413 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 414 return; 415 } 416 } 417 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 418 ata_pio2mode(apiomode), 419 ATA_C_F_SETXFER, ATA_WAIT_READY); 420 if (bootverbose) 421 ata_printf(scp, device, 422 "%s setting up PIO%d mode on Promise chip\n", 423 (error) ? "failed" : "success", 424 (apiomode >= 0) ? apiomode : 0); 425 promise_timing(scp, devno, ata_pio2mode(apiomode)); 426 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 427 return; 428 429 case 0x00041103: /* HighPoint HPT366 controller */ 430 /* no ATAPI devices for now */ 431 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 432 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 433 break; 434 435 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 436 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 437 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 438 if (bootverbose) 439 ata_printf(scp, device, 440 "%s setting up UDMA4 mode on HPT366 chip\n", 441 (error) ? "failed" : "success"); 442 if (!error) { 443 hpt366_timing(scp, devno, ATA_UDMA4); 444 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 445 return; 446 } 447 } 448 if (udmamode >= 2) { 449 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 450 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 451 if (bootverbose) 452 ata_printf(scp, device, 453 "%s setting up UDMA2 mode on HPT366 chip\n", 454 (error) ? "failed" : "success"); 455 if (!error) { 456 hpt366_timing(scp, devno, ATA_UDMA2); 457 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 458 return; 459 } 460 } 461 if (wdmamode >= 2 && apiomode >= 4) { 462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 463 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 464 if (bootverbose) 465 ata_printf(scp, device, 466 "%s setting up WDMA2 mode on HPT366 chip\n", 467 (error) ? "failed" : "success"); 468 if (!error) { 469 hpt366_timing(scp, devno, ATA_WDMA2); 470 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 471 return; 472 } 473 } 474 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 475 ata_pio2mode(apiomode), 476 ATA_C_F_SETXFER, ATA_WAIT_READY); 477 if (bootverbose) 478 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 479 (error) ? "failed" : "success", 480 (apiomode >= 0) ? apiomode : 0); 481 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 482 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 483 return; 484 485 default: /* unknown controller chip */ 486 /* better not try generic DMA on ATAPI devices it almost never works */ 487 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 488 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 489 break; 490 491 /* if controller says its setup for DMA take the easy way out */ 492 /* the downside is we dont know what DMA mode we are in */ 493 if ((udmamode >= 0 || wdmamode > 1) && 494 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 495 ((device==ATA_MASTER) ? 496 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 497 scp->mode[ATA_DEV(device)] = ATA_DMA; 498 return; 499 } 500 501 /* well, we have no support for this, but try anyways */ 502 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 503 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 504 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 505 if (bootverbose) 506 ata_printf(scp, device, 507 "%s setting up WDMA2 mode on generic chip\n", 508 (error) ? "failed" : "success"); 509 if (!error) { 510 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 511 return; 512 } 513 } 514 } 515 if (bootverbose) 516 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 517} 518 519int32_t 520ata_dmasetup(struct ata_softc *scp, int32_t device, 521 int8_t *data, int32_t count, int32_t flags) 522{ 523 struct ata_dmaentry *dmatab; 524 u_int32_t dma_count, dma_base; 525 int32_t i = 0; 526 527 if (((uintptr_t)data & 1) || (count & 1)) 528 return -1; 529 530 if (!count) { 531 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 532 return -1; 533 } 534 535 dmatab = scp->dmatab[ATA_DEV(device)]; 536 dma_base = vtophys(data); 537 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 538 data += dma_count; 539 count -= dma_count; 540 541 while (count) { 542 dmatab[i].base = dma_base; 543 dmatab[i].count = (dma_count & 0xffff); 544 i++; 545 if (i >= ATA_DMA_ENTRIES) { 546 ata_printf(scp, device, "too many segments in DMA table\n"); 547 return -1; 548 } 549 dma_base = vtophys(data); 550 dma_count = min(count, PAGE_SIZE); 551 data += min(count, PAGE_SIZE); 552 count -= min(count, PAGE_SIZE); 553 } 554 dmatab[i].base = dma_base; 555 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 556 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 557 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 558 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 559 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 560 return 0; 561} 562 563void 564ata_dmastart(struct ata_softc *scp) 565{ 566 scp->flags |= ATA_DMA_ACTIVE; 567 outb(scp->bmaddr + ATA_BMCMD_PORT, 568 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 569} 570 571int32_t 572ata_dmadone(struct ata_softc *scp) 573{ 574 outb(scp->bmaddr + ATA_BMCMD_PORT, 575 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 576 scp->flags &= ~ATA_DMA_ACTIVE; 577 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 578} 579 580int32_t 581ata_dmastatus(struct ata_softc *scp) 582{ 583 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 584} 585 586static void 587promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 588{ 589 u_int32_t timing; 590 switch (mode) { 591 default: 592 case ATA_PIO0: timing = 0x004ff329; break; 593 case ATA_PIO1: timing = 0x004fec25; break; 594 case ATA_PIO2: timing = 0x004fe823; break; 595 case ATA_PIO3: timing = 0x004fe622; break; 596 case ATA_PIO4: timing = 0x004fe421; break; 597 case ATA_WDMA2: timing = 0x004367f3; break; 598 case ATA_UDMA2: timing = 0x004127f3; break; 599 case ATA_UDMA4: timing = 0x004127f3; break; 600 } 601 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4); 602} 603 604static void 605hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 606{ 607 u_int32_t timing; 608 609 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) { 610 case 0x85: /* 25Mhz */ 611 switch (mode) { 612 case ATA_PIO0: timing = 0xc0d08585; break; 613 case ATA_PIO1: timing = 0xc0d08572; break; 614 case ATA_PIO2: timing = 0xc0ca8542; break; 615 case ATA_PIO3: timing = 0xc0ca8532; break; 616 case ATA_PIO4: timing = 0xc0ca8521; break; 617 case ATA_WDMA2: timing = 0xa0ca8521; break; 618 case ATA_UDMA2: timing = 0x90cf8521; break; 619 case ATA_UDMA4: timing = 0x90c98521; break; 620 default: timing = 0x01208585; 621 } 622 break; 623 default: 624 case 0xa7: /* 33MHz */ 625 switch (mode) { 626 case ATA_PIO0: timing = 0xc0d0a7aa; break; 627 case ATA_PIO1: timing = 0xc0d0a7a3; break; 628 case ATA_PIO2: timing = 0xc0d0a753; break; 629 case ATA_PIO3: timing = 0xc0c8a742; break; 630 case ATA_PIO4: timing = 0xc0c8a731; break; 631 case ATA_WDMA2: timing = 0xa0c8a731; break; 632 case ATA_UDMA2: timing = 0x90caa731; break; 633 case ATA_UDMA4: timing = 0x90c9a731; break; 634 default: timing = 0x0120a7a7; 635 } 636 break; 637 case 0xd9: /* 40Mhz */ 638 switch (mode) { 639 case ATA_PIO0: timing = 0xc018d9d9; break; 640 case ATA_PIO1: timing = 0xc010d9c7; break; 641 case ATA_PIO2: timing = 0xc010d997; break; 642 case ATA_PIO3: timing = 0xc010d974; break; 643 case ATA_PIO4: timing = 0xc008d963; break; 644 case ATA_WDMA2: timing = 0xa008d943; break; 645 case ATA_UDMA2: timing = 0x900bd943; break; 646 case ATA_UDMA4: timing = 0x900fd943; break; 647 default: timing = 0x0120d9d9; 648 } 649 } 650 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4); 651} 652 653#else /* NPCI > 0 */ 654
| 63void 64ata_dmainit(struct ata_softc *scp, int32_t device, 65 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 66{ 67 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 68 int32_t error; 69 70 /* set our most pessimistic default mode */ 71 scp->mode[ATA_DEV(device)] = ATA_PIO; 72 73 if (!scp->bmaddr) 74 return; 75 76 /* if simplex controller, only allow DMA on primary channel */ 77 if (scp->unit == 1) { 78 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 79 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 80 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 81 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 82 return; 83 } 84 } 85 86 if (!scp->dmatab[ATA_DEV(device)]) { 87 void *dmatab; 88 89 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 90 return; 91 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 92 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 93 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 94 free(dmatab, M_DEVBUF); 95 return; 96 } 97 scp->dmatab[ATA_DEV(device)] = dmatab; 98 } 99 100 switch (scp->chiptype) { 101 102 case 0x71118086: /* Intel PIIX4 */ 103 case 0x71998086: /* Intel PIIX4e */ 104 case 0x24118086: /* Intel ICH */ 105 case 0x24218086: /* Intel ICH0 */ 106 if (udmamode >= 2) { 107 int32_t mask48, new48; 108 109 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 110 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 111 if (bootverbose) 112 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 113 (error) ? "failed" : "success", 114 (scp->chiptype == 0x24118086) ? "ICH" : 115 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 116 if (!error) { 117 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 118 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 119 pci_write_config(scp->dev, 0x48, 120 (pci_read_config(scp->dev, 0x48, 4) & 121 ~mask48) | new48, 4); 122 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 123 return; 124 } 125 } 126 /* FALLTHROUGH */ 127 128 case 0x70108086: /* Intel PIIX3 */ 129 if (wdmamode >= 2 && apiomode >= 4) { 130 int32_t mask40, new40, mask44, new44; 131 132 /* if SITRE not set doit for both channels */ 133 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 134 new40 = pci_read_config(scp->dev, 0x40, 4); 135 new44 = pci_read_config(scp->dev, 0x44, 4); 136 if (!(new40 & 0x00004000)) { 137 new44 &= ~0x0000000f; 138 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 139 } 140 if (!(new40 & 0x40000000)) { 141 new44 &= ~0x000000f0; 142 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 143 } 144 new40 |= 0x40004000; 145 pci_write_config(scp->dev, 0x40, new40, 4); 146 pci_write_config(scp->dev, 0x44, new44, 4); 147 } 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 152 (error) ? "failed" : "success", 153 (scp->chiptype == 0x70108086) ? "PIIX3" : 154 (scp->chiptype == 0x24118086) ? "ICH" : 155 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 156 if (!error) { 157 if (device == ATA_MASTER) { 158 mask40 = 0x0000330f; 159 new40 = 0x00002307; 160 mask44 = 0; 161 new44 = 0; 162 } 163 else { 164 mask40 = 0x000000f0; 165 new40 = 0x00000070; 166 mask44 = 0x0000000f; 167 new44 = 0x0000000b; 168 } 169 if (scp->unit) { 170 mask40 <<= 16; 171 new40 <<= 16; 172 mask44 <<= 4; 173 new44 <<= 4; 174 } 175 pci_write_config(scp->dev, 0x40, 176 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)| 177 new40, 4); 178 pci_write_config(scp->dev, 0x44, 179 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)| 180 new44, 4); 181 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 182 return; 183 } 184 } 185 /* we could set PIO mode timings, but we assume the BIOS did that */ 186 break; 187 188 case 0x12308086: /* Intel PIIX */ 189 if (wdmamode >= 2 && apiomode >= 4) { 190 int32_t word40; 191 192 word40 = pci_read_config(scp->dev, 0x40, 4); 193 word40 >>= scp->unit * 16; 194 195 /* Check for timing config usable for DMA on controller */ 196 if (!((word40 & 0x3300) == 0x2300 && 197 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 198 break; 199 200 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 201 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 202 if (bootverbose) 203 ata_printf(scp, device, 204 "%s setting up WDMA2 mode on PIIX chip\n", 205 (error) ? "failed" : "success"); 206 if (!error) { 207 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 208 return; 209 } 210 } 211 break; 212 213 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 214 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 215 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 216 ata_printf(scp, device, 217 "Aladdin: two atapi devices on this channel, no DMA\n"); 218 break; 219 } 220 if (udmamode >= 2) { 221 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 222 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, 227 "%s setting up UDMA2 mode on Aladdin chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 word54 |= 0x5555; 231 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 232 pci_write_config(scp->dev, 0x54, word54, 4); 233 pci_write_config(scp->dev, 0x53, 234 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 235 scp->flags |= ATA_ATAPI_DMA_RO; 236 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 237 return; 238 } 239 } 240 if (wdmamode >= 2 && apiomode >= 4) { 241 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 242 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 243 if (bootverbose) 244 ata_printf(scp, device, 245 "%s setting up WDMA2 mode on Aladdin chip\n", 246 (error) ? "failed" : "success"); 247 if (!error) { 248 pci_write_config(scp->dev, 0x53, 249 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 250 scp->flags |= ATA_ATAPI_DMA_RO; 251 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 252 return; 253 } 254 } 255 /* we could set PIO mode timings, but we assume the BIOS did that */ 256 break; 257 258 case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */ 259 case 0x74091022: /* AMD 756 */ 260 /* UDMA modes on 82C686 */ 261 if (ata_find_dev(scp->dev, 0x06861106)) { 262 if (udmamode >= 4) { 263 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 264 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 265 if (bootverbose) 266 ata_printf(scp, device, 267 "%s setting up UDMA4 mode on VIA chip\n", 268 (error) ? "failed" : "success"); 269 if (!error) { 270 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1); 271 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 272 return; 273 } 274 } 275 if (udmamode >= 2) { 276 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 277 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 278 if (bootverbose) 279 ata_printf(scp, device, 280 "%s setting up UDMA2 mode on VIA chip\n", 281 (error) ? "failed" : "success"); 282 if (!error) { 283 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1); 284 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 285 return; 286 } 287 } 288 } 289 290 /* UDMA4 mode on AMD 756 */ 291 if (udmamode >= 4 && scp->chiptype == 0x74091022) { 292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 293 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 294 if (bootverbose) 295 ata_printf(scp, device, 296 "%s setting up UDMA4 mode on AMD chip\n", 297 (error) ? "failed" : "success"); 298 if (!error) { 299 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1); 300 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 301 return; 302 } 303 } 304 305 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 306 if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) && 307 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 308 (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) || 309 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 310 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 311 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 312 if (bootverbose) 313 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 314 (error) ? "failed" : "success", 315 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 316 if (!error) { 317 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1); 318 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 319 return; 320 } 321 } 322 if (wdmamode >= 2 && apiomode >= 4) { 323 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 324 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 325 if (bootverbose) 326 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 327 (error) ? "failed" : "success", 328 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 329 if (!error) { 330 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1); 331 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1); 332 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 333 return; 334 } 335 } 336 /* we could set PIO mode timings, but we assume the BIOS did that */ 337 break; 338 339 case 0x55131039: /* SiS 5591 */ 340 if (udmamode >= 2) { 341 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 342 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 343 if (bootverbose) 344 ata_printf(scp, device, 345 "%s setting up UDMA2 mode on SiS chip\n", 346 (error) ? "failed" : "success"); 347 if (!error) { 348 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2); 349 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 350 return; 351 } 352 } 353 if (wdmamode >=2 && apiomode >= 4) { 354 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 355 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 356 if (bootverbose) 357 ata_printf(scp, device, 358 "%s setting up WDMA2 mode on SiS chip\n", 359 (error) ? "failed" : "success"); 360 if (!error) { 361 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2); 362 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 363 return; 364 } 365 } 366 /* we could set PIO mode timings, but we assume the BIOS did that */ 367 break; 368 369 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 370 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 371 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 372 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 373 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 374 break; 375 376 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 377 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 379 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 380 if (bootverbose) 381 ata_printf(scp, device, 382 "%s setting up UDMA4 mode on Promise chip\n", 383 (error) ? "failed" : "success"); 384 if (!error) { 385 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2); 386 promise_timing(scp, devno, ATA_UDMA4); 387 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 388 return; 389 } 390 } 391 if (udmamode >= 2) { 392 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 393 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 394 if (bootverbose) 395 ata_printf(scp, device, 396 "%s setting up UDMA2 mode on Promise chip\n", 397 (error) ? "failed" : "success"); 398 if (!error) { 399 promise_timing(scp, devno, ATA_UDMA2); 400 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 401 return; 402 } 403 } 404 if (wdmamode >= 2 && apiomode >= 4) { 405 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 406 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 407 if (bootverbose) 408 ata_printf(scp, device, 409 "%s setting up WDMA2 mode on Promise chip\n", 410 (error) ? "failed" : "success"); 411 if (!error) { 412 promise_timing(scp, devno, ATA_WDMA2); 413 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 414 return; 415 } 416 } 417 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 418 ata_pio2mode(apiomode), 419 ATA_C_F_SETXFER, ATA_WAIT_READY); 420 if (bootverbose) 421 ata_printf(scp, device, 422 "%s setting up PIO%d mode on Promise chip\n", 423 (error) ? "failed" : "success", 424 (apiomode >= 0) ? apiomode : 0); 425 promise_timing(scp, devno, ata_pio2mode(apiomode)); 426 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 427 return; 428 429 case 0x00041103: /* HighPoint HPT366 controller */ 430 /* no ATAPI devices for now */ 431 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 432 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 433 break; 434 435 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 436 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 437 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 438 if (bootverbose) 439 ata_printf(scp, device, 440 "%s setting up UDMA4 mode on HPT366 chip\n", 441 (error) ? "failed" : "success"); 442 if (!error) { 443 hpt366_timing(scp, devno, ATA_UDMA4); 444 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 445 return; 446 } 447 } 448 if (udmamode >= 2) { 449 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 450 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 451 if (bootverbose) 452 ata_printf(scp, device, 453 "%s setting up UDMA2 mode on HPT366 chip\n", 454 (error) ? "failed" : "success"); 455 if (!error) { 456 hpt366_timing(scp, devno, ATA_UDMA2); 457 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 458 return; 459 } 460 } 461 if (wdmamode >= 2 && apiomode >= 4) { 462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 463 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 464 if (bootverbose) 465 ata_printf(scp, device, 466 "%s setting up WDMA2 mode on HPT366 chip\n", 467 (error) ? "failed" : "success"); 468 if (!error) { 469 hpt366_timing(scp, devno, ATA_WDMA2); 470 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 471 return; 472 } 473 } 474 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 475 ata_pio2mode(apiomode), 476 ATA_C_F_SETXFER, ATA_WAIT_READY); 477 if (bootverbose) 478 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 479 (error) ? "failed" : "success", 480 (apiomode >= 0) ? apiomode : 0); 481 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 482 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 483 return; 484 485 default: /* unknown controller chip */ 486 /* better not try generic DMA on ATAPI devices it almost never works */ 487 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 488 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 489 break; 490 491 /* if controller says its setup for DMA take the easy way out */ 492 /* the downside is we dont know what DMA mode we are in */ 493 if ((udmamode >= 0 || wdmamode > 1) && 494 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 495 ((device==ATA_MASTER) ? 496 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 497 scp->mode[ATA_DEV(device)] = ATA_DMA; 498 return; 499 } 500 501 /* well, we have no support for this, but try anyways */ 502 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 503 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 504 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 505 if (bootverbose) 506 ata_printf(scp, device, 507 "%s setting up WDMA2 mode on generic chip\n", 508 (error) ? "failed" : "success"); 509 if (!error) { 510 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 511 return; 512 } 513 } 514 } 515 if (bootverbose) 516 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 517} 518 519int32_t 520ata_dmasetup(struct ata_softc *scp, int32_t device, 521 int8_t *data, int32_t count, int32_t flags) 522{ 523 struct ata_dmaentry *dmatab; 524 u_int32_t dma_count, dma_base; 525 int32_t i = 0; 526 527 if (((uintptr_t)data & 1) || (count & 1)) 528 return -1; 529 530 if (!count) { 531 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 532 return -1; 533 } 534 535 dmatab = scp->dmatab[ATA_DEV(device)]; 536 dma_base = vtophys(data); 537 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 538 data += dma_count; 539 count -= dma_count; 540 541 while (count) { 542 dmatab[i].base = dma_base; 543 dmatab[i].count = (dma_count & 0xffff); 544 i++; 545 if (i >= ATA_DMA_ENTRIES) { 546 ata_printf(scp, device, "too many segments in DMA table\n"); 547 return -1; 548 } 549 dma_base = vtophys(data); 550 dma_count = min(count, PAGE_SIZE); 551 data += min(count, PAGE_SIZE); 552 count -= min(count, PAGE_SIZE); 553 } 554 dmatab[i].base = dma_base; 555 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 556 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 557 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 558 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 559 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 560 return 0; 561} 562 563void 564ata_dmastart(struct ata_softc *scp) 565{ 566 scp->flags |= ATA_DMA_ACTIVE; 567 outb(scp->bmaddr + ATA_BMCMD_PORT, 568 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 569} 570 571int32_t 572ata_dmadone(struct ata_softc *scp) 573{ 574 outb(scp->bmaddr + ATA_BMCMD_PORT, 575 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 576 scp->flags &= ~ATA_DMA_ACTIVE; 577 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 578} 579 580int32_t 581ata_dmastatus(struct ata_softc *scp) 582{ 583 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 584} 585 586static void 587promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 588{ 589 u_int32_t timing; 590 switch (mode) { 591 default: 592 case ATA_PIO0: timing = 0x004ff329; break; 593 case ATA_PIO1: timing = 0x004fec25; break; 594 case ATA_PIO2: timing = 0x004fe823; break; 595 case ATA_PIO3: timing = 0x004fe622; break; 596 case ATA_PIO4: timing = 0x004fe421; break; 597 case ATA_WDMA2: timing = 0x004367f3; break; 598 case ATA_UDMA2: timing = 0x004127f3; break; 599 case ATA_UDMA4: timing = 0x004127f3; break; 600 } 601 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4); 602} 603 604static void 605hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 606{ 607 u_int32_t timing; 608 609 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) { 610 case 0x85: /* 25Mhz */ 611 switch (mode) { 612 case ATA_PIO0: timing = 0xc0d08585; break; 613 case ATA_PIO1: timing = 0xc0d08572; break; 614 case ATA_PIO2: timing = 0xc0ca8542; break; 615 case ATA_PIO3: timing = 0xc0ca8532; break; 616 case ATA_PIO4: timing = 0xc0ca8521; break; 617 case ATA_WDMA2: timing = 0xa0ca8521; break; 618 case ATA_UDMA2: timing = 0x90cf8521; break; 619 case ATA_UDMA4: timing = 0x90c98521; break; 620 default: timing = 0x01208585; 621 } 622 break; 623 default: 624 case 0xa7: /* 33MHz */ 625 switch (mode) { 626 case ATA_PIO0: timing = 0xc0d0a7aa; break; 627 case ATA_PIO1: timing = 0xc0d0a7a3; break; 628 case ATA_PIO2: timing = 0xc0d0a753; break; 629 case ATA_PIO3: timing = 0xc0c8a742; break; 630 case ATA_PIO4: timing = 0xc0c8a731; break; 631 case ATA_WDMA2: timing = 0xa0c8a731; break; 632 case ATA_UDMA2: timing = 0x90caa731; break; 633 case ATA_UDMA4: timing = 0x90c9a731; break; 634 default: timing = 0x0120a7a7; 635 } 636 break; 637 case 0xd9: /* 40Mhz */ 638 switch (mode) { 639 case ATA_PIO0: timing = 0xc018d9d9; break; 640 case ATA_PIO1: timing = 0xc010d9c7; break; 641 case ATA_PIO2: timing = 0xc010d997; break; 642 case ATA_PIO3: timing = 0xc010d974; break; 643 case ATA_PIO4: timing = 0xc008d963; break; 644 case ATA_WDMA2: timing = 0xa008d943; break; 645 case ATA_UDMA2: timing = 0x900bd943; break; 646 case ATA_UDMA4: timing = 0x900fd943; break; 647 default: timing = 0x0120d9d9; 648 } 649 } 650 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4); 651} 652 653#else /* NPCI > 0 */ 654
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