| ata-all.h (84419) | ata-all.h (84584) |
|---|---|
| 1/*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 84419 2001-10-03 11:36:25Z sos $ | 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 84584 2001-10-06 11:07:04Z sos $ |
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ --- 21 unchanged lines hidden (view full) --- 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */ 61#define ATA_C_NOP 0x00 /* NOP command */ 62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */ 63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */ 64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 65#define ATA_C_READ 0x20 /* read command */ | 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ --- 21 unchanged lines hidden (view full) --- 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */ 61#define ATA_C_NOP 0x00 /* NOP command */ 62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */ 63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */ 64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 65#define ATA_C_READ 0x20 /* read command */ |
| 66#define ATA_C_READ48 0x24 /* read command */ 67#define ATA_C_READ_DMA48 0x25 /* read w/DMA command */ 68#define ATA_C_READ_DMA_QUEUED48 0x26 /* read w/DMA QUEUED command */ 69#define ATA_C_READ_MUL48 0x29 /* read multi command */ |
|
| 66#define ATA_C_WRITE 0x30 /* write command */ | 70#define ATA_C_WRITE 0x30 /* write command */ |
| 71#define ATA_C_WRITE48 0x34 /* write command */ 72#define ATA_C_WRITE_DMA48 0x35 /* write w/DMA command */ 73#define ATA_C_WRITE_DMA_QUEUED48 0x36 /* write w/DMA QUEUED command */ 74#define ATA_C_WRITE_MUL48 0x39 /* write multi command */ |
|
| 67#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 68#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 69#define ATA_C_SERVICE 0xa2 /* service command */ 70#define ATA_C_READ_MUL 0xc4 /* read multi command */ 71#define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 72#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 73#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */ 74#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 75#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 76#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */ 77#define ATA_C_SLEEP 0xe6 /* sleep command */ 78#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */ | 75#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 76#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 77#define ATA_C_SERVICE 0xa2 /* service command */ 78#define ATA_C_READ_MUL 0xc4 /* read multi command */ 79#define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 80#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 81#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */ 82#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 83#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 84#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */ 85#define ATA_C_SLEEP 0xe6 /* sleep command */ 86#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */ |
| 87#define ATA_C_FLUSHCACHE48 0xea /* flush cache to disk */ |
|
| 79#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 80#define ATA_C_SETFEATURES 0xef /* features command */ 81#define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 82#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 83#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */ 84#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 85#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */ 86#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */ --- 38 unchanged lines hidden (view full) --- 125#define ATA_BMADDR_RID 2 126#define ATA_IRQ_RID 0 127 128/* busmaster DMA related defines */ 129#define ATA_DMA_ENTRIES 256 130#define ATA_DMA_EOT 0x80000000 131 132#define ATA_BMCMD_PORT 0x00 | 88#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 89#define ATA_C_SETFEATURES 0xef /* features command */ 90#define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 91#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 92#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */ 93#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 94#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */ 95#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */ --- 38 unchanged lines hidden (view full) --- 134#define ATA_BMADDR_RID 2 135#define ATA_IRQ_RID 0 136 137/* busmaster DMA related defines */ 138#define ATA_DMA_ENTRIES 256 139#define ATA_DMA_EOT 0x80000000 140 141#define ATA_BMCMD_PORT 0x00 |
| 133#define ATA_BMCMD_START_STOP 0x01 134#define ATA_BMCMD_WRITE_READ 0x08 | 142#define ATA_BMCMD_START_STOP 0x01 143#define ATA_BMCMD_WRITE_READ 0x08 |
| 135 136#define ATA_BMDEVSPEC_0 0x01 137 138#define ATA_BMSTAT_PORT 0x02 | 144 145#define ATA_BMDEVSPEC_0 0x01 146 147#define ATA_BMSTAT_PORT 0x02 |
| 139#define ATA_BMSTAT_ACTIVE 0x01 140#define ATA_BMSTAT_ERROR 0x02 141#define ATA_BMSTAT_INTERRUPT 0x04 142#define ATA_BMSTAT_MASK 0x07 143#define ATA_BMSTAT_DMA_MASTER 0x20 144#define ATA_BMSTAT_DMA_SLAVE 0x40 145#define ATA_BMSTAT_DMA_SIMPLEX 0x80 | 148#define ATA_BMSTAT_ACTIVE 0x01 149#define ATA_BMSTAT_ERROR 0x02 150#define ATA_BMSTAT_INTERRUPT 0x04 151#define ATA_BMSTAT_MASK 0x07 152#define ATA_BMSTAT_DMA_MASTER 0x20 153#define ATA_BMSTAT_DMA_SLAVE 0x40 154#define ATA_BMSTAT_DMA_SIMPLEX 0x80 |
| 146 147#define ATA_BMDEVSPEC_1 0x03 | 155 156#define ATA_BMDEVSPEC_1 0x03 |
| 148 | |
| 149#define ATA_BMDTP_PORT 0x04 150 151/* structure for holding DMA address data */ 152struct ata_dmaentry { | 157#define ATA_BMDTP_PORT 0x04 158 159/* structure for holding DMA address data */ 160struct ata_dmaentry { |
| 153 u_int32_t base; 154 u_int32_t count; | 161 u_int32_t base; 162 u_int32_t count; |
| 155}; 156 157/* structure describing an ATA device */ 158struct ata_softc { 159 struct device *dev; /* device handle */ 160 int channel; /* channel on this controller */ 161 struct resource *r_io; /* io addr resource handle */ 162 struct resource *r_altio; /* altio addr resource handle */ 163 struct resource *r_bmio; /* bmio addr resource handle */ 164 struct resource *r_irq; /* interrupt of this channel */ 165 void *ih; /* interrupt handle */ 166 int (*intr_func)(struct ata_softc *); /* interrupt function */ 167 u_int32_t chiptype; /* pciid of controller chip */ 168 u_int32_t alignment; /* dma engine min alignment */ 169 char *dev_name[2]; /* name of device */ 170 struct ata_params *dev_param[2]; /* ptr to devices params */ 171 void *dev_softc[2]; /* ptr to devices softc's */ 172 int mode[2]; /* transfer mode for devices */ 173 int flags; /* controller flags */ | 163}; 164 165/* structure describing an ATA device */ 166struct ata_softc { 167 struct device *dev; /* device handle */ 168 int channel; /* channel on this controller */ 169 struct resource *r_io; /* io addr resource handle */ 170 struct resource *r_altio; /* altio addr resource handle */ 171 struct resource *r_bmio; /* bmio addr resource handle */ 172 struct resource *r_irq; /* interrupt of this channel */ 173 void *ih; /* interrupt handle */ 174 int (*intr_func)(struct ata_softc *); /* interrupt function */ 175 u_int32_t chiptype; /* pciid of controller chip */ 176 u_int32_t alignment; /* dma engine min alignment */ 177 char *dev_name[2]; /* name of device */ 178 struct ata_params *dev_param[2]; /* ptr to devices params */ 179 void *dev_softc[2]; /* ptr to devices softc's */ 180 int mode[2]; /* transfer mode for devices */ 181 int flags; /* controller flags */ |
| 174#define ATA_DMA_ACTIVE 0x01 175#define ATA_ATAPI_DMA_RO 0x02 176#define ATA_USE_16BIT 0x04 177#define ATA_NO_SLAVE 0x08 178#define ATA_QUEUED 0x10 | 182#define ATA_NO_SLAVE 0x01 183#define ATA_USE_16BIT 0x02 184#define ATA_ATAPI_DMA_RO 0x04 185#define ATA_QUEUED 0x08 186#define ATA_DMA_ACTIVE 0x10 |
| 179 180 int devices; /* what is present */ 181#define ATA_ATA_MASTER 0x01 182#define ATA_ATA_SLAVE 0x02 183#define ATA_ATAPI_MASTER 0x04 184#define ATA_ATAPI_SLAVE 0x08 185 186 u_int8_t status; /* last controller status */ 187 u_int8_t error; /* last controller error */ 188 int active; /* active processing request */ 189#define ATA_IDLE 0x0000 190#define ATA_IMMEDIATE 0x0001 191#define ATA_WAIT_INTR 0x0002 192#define ATA_WAIT_READY 0x0004 | 187 188 int devices; /* what is present */ 189#define ATA_ATA_MASTER 0x01 190#define ATA_ATA_SLAVE 0x02 191#define ATA_ATAPI_MASTER 0x04 192#define ATA_ATAPI_SLAVE 0x08 193 194 u_int8_t status; /* last controller status */ 195 u_int8_t error; /* last controller error */ 196 int active; /* active processing request */ 197#define ATA_IDLE 0x0000 198#define ATA_IMMEDIATE 0x0001 199#define ATA_WAIT_INTR 0x0002 200#define ATA_WAIT_READY 0x0004 |
| 193#define ATA_ACTIVE 0x0008 194#define ATA_ACTIVE_ATA 0x0010 195#define ATA_ACTIVE_ATAPI 0x0020 196#define ATA_CONTROL 0x0040 | 201#define ATA_WAIT_MASK 0x0007 202#define ATA_USE_CHS 0x0008 203#define ATA_ACTIVE 0x0010 204#define ATA_ACTIVE_ATA 0x0020 205#define ATA_ACTIVE_ATAPI 0x0040 206#define ATA_CONTROL 0x0080 |
| 197 198 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 199 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 200 void *running; /* currently running request */ 201}; 202 203/* externs */ 204extern devclass_t ata_devclass; 205 206/* public prototypes */ 207int ata_probe(device_t); 208int ata_attach(device_t); 209int ata_detach(device_t); 210int ata_resume(device_t); 211 212void ata_start(struct ata_softc *); 213void ata_reset(struct ata_softc *); 214int ata_reinit(struct ata_softc *); 215int ata_wait(struct ata_softc *, int, u_int8_t); | 207 208 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 209 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 210 void *running; /* currently running request */ 211}; 212 213/* externs */ 214extern devclass_t ata_devclass; 215 216/* public prototypes */ 217int ata_probe(device_t); 218int ata_attach(device_t); 219int ata_detach(device_t); 220int ata_resume(device_t); 221 222void ata_start(struct ata_softc *); 223void ata_reset(struct ata_softc *); 224int ata_reinit(struct ata_softc *); 225int ata_wait(struct ata_softc *, int, u_int8_t); |
| 216int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int); | 226int ata_command(struct ata_softc *, int, u_int8_t, u_int64_t, u_int16_t, u_int8_t, int); |
| 217int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4); 218void ata_set_name(struct ata_softc *, int, char *, int); 219void ata_free_name(struct ata_softc *, int); 220int ata_get_lun(u_int32_t *); 221int ata_test_lun(u_int32_t *, int); 222void ata_free_lun(u_int32_t *, int); 223char *ata_mode2str(int); | 227int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4); 228void ata_set_name(struct ata_softc *, int, char *, int); 229void ata_free_name(struct ata_softc *, int); 230int ata_get_lun(u_int32_t *); 231int ata_test_lun(u_int32_t *, int); 232void ata_free_lun(u_int32_t *, int); 233char *ata_mode2str(int); |
| 224int ata_pio2mode(int); | |
| 225int ata_pmode(struct ata_params *); 226int ata_wmode(struct ata_params *); 227int ata_umode(struct ata_params *); 228int ata_find_dev(device_t, u_int32_t, u_int32_t); 229 230void *ata_dmaalloc(struct ata_softc *, int); 231void ata_dmainit(struct ata_softc *, int, int, int, int); 232int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int); --- 39 unchanged lines hidden --- | 234int ata_pmode(struct ata_params *); 235int ata_wmode(struct ata_params *); 236int ata_umode(struct ata_params *); 237int ata_find_dev(device_t, u_int32_t, u_int32_t); 238 239void *ata_dmaalloc(struct ata_softc *, int); 240void ata_dmainit(struct ata_softc *, int, int, int, int); 241int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int); --- 39 unchanged lines hidden --- |