Cross Reference: /freebsd-11.0-release/sys/dev/ata/ata-all.h

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ata-all.h (56744)	ata-all.h (57325)
1/- 2 Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *	1/- 2 Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 56744 2000-01-28 13:35:43Z sos $	28 * $FreeBSD: head/sys/dev/ata/ata-all.h 57325 2000-02-18 20:57:33Z sos $
29 / 30 31/ ATA register defines / 32#define ATA_DATA 0x00 / data register / 33#define ATA_ERROR 0x01 / (R) error register / 34#define ATA_E_NM 0x02 / no media / 35#define ATA_E_ABORT 0x04 / command aborted / 36#define ATA_E_MCR 0x08 / media change request / --- 44 unchanged lines hidden* (view full) --- 81#define ATA_S_DRQ 0x08 /* data request / 82#define ATA_S_DSC 0x10 / drive seek completed / 83#define ATA_S_SERVICE 0x10 / drive needs service / 84#define ATA_S_DWF 0x20 / drive write fault / 85#define ATA_S_DMA 0x20 / DMA ready / 86#define ATA_S_READY 0x40 / drive ready / 87#define ATA_S_BUSY 0x80 / busy */ 88	29 / 30 31/ ATA register defines / 32#define ATA_DATA 0x00 / data register / 33#define ATA_ERROR 0x01 / (R) error register / 34#define ATA_E_NM 0x02 / no media / 35#define ATA_E_ABORT 0x04 / command aborted / 36#define ATA_E_MCR 0x08 / media change request / --- 44 unchanged lines hidden* (view full) --- 81#define ATA_S_DRQ 0x08 /* data request / 82#define ATA_S_DSC 0x10 / drive seek completed / 83#define ATA_S_SERVICE 0x10 / drive needs service / 84#define ATA_S_DWF 0x20 / drive write fault / 85#define ATA_S_DMA 0x20 / DMA ready / 86#define ATA_S_READY 0x40 / drive ready / 87#define ATA_S_BUSY 0x80 / busy */ 88
89#define ATA_ALTPORT 0x206 /* alternate Status register */	89#define ATA_ALTPORT 0x206 /* alternate status register / 90#define ATA_ALTPORT_PCCARD 0x8 / ditto on PCCARD devices */
90#define ATA_A_IDS 0x02 /* disable interrupts / 91#define ATA_A_RESET 0x04 / RESET controller / 92#define ATA_A_4BIT 0x08 / 4 head bits */ 93	91#define ATA_A_IDS 0x02 /* disable interrupts / 92#define ATA_A_RESET 0x04 / RESET controller / 93#define ATA_A_4BIT 0x08 / 4 head bits */ 94
	95#define ATA_ALTIOSIZE 0x01 96
94/* misc defines / 95#define ATA_MASTER 0x00 96#define ATA_SLAVE 0x10 97#define ATA_IOSIZE 0x08 98#define ATA_OP_FINISHED 0x00 99#define ATA_OP_CONTINUES 0x01 100#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1) 101#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)] --- 14 unchanged lines hidden* (view full) --- 116#define ATA_BMSTAT_INTERRUPT 0x04 117#define ATA_BMSTAT_MASK 0x07 118#define ATA_BMSTAT_DMA_MASTER 0x20 119#define ATA_BMSTAT_DMA_SLAVE 0x40 120#define ATA_BMSTAT_DMA_SIMPLEX 0x80 121 122#define ATA_BMDTP_PORT 0x04 123	97/* misc defines / 98#define ATA_MASTER 0x00 99#define ATA_SLAVE 0x10 100#define ATA_IOSIZE 0x08 101#define ATA_OP_FINISHED 0x00 102#define ATA_OP_CONTINUES 0x01 103#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1) 104#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)] --- 14 unchanged lines hidden* (view full) --- 119#define ATA_BMSTAT_INTERRUPT 0x04 120#define ATA_BMSTAT_MASK 0x07 121#define ATA_BMSTAT_DMA_MASTER 0x20 122#define ATA_BMSTAT_DMA_SLAVE 0x40 123#define ATA_BMSTAT_DMA_SIMPLEX 0x80 124 125#define ATA_BMDTP_PORT 0x04 126
	127#define ATA_BMIOSIZE 0x20 128
124/* structure for holding DMA address data / 125struct ata_dmaentry { 126* u_int32_t base; 127 u_int32_t count; 128}; 129 130/* ATA/ATAPI device parameter information / 131struct ata_params { --- 112 unchanged lines hidden* (view full) --- 244 int16_t reserved129[30]; 245 int16_t cfapwrmode; 246 int16_t reserved161[84]; 247 int16_t integrity; 248}; 249 250/* structure describing an ATA device / 251*struct ata_softc {	129/* structure for holding DMA address data / 130struct ata_dmaentry { 131* u_int32_t base; 132 u_int32_t count; 133}; 134 135/* ATA/ATAPI device parameter information / 136struct ata_params { --- 112 unchanged lines hidden* (view full) --- 249 int16_t reserved129[30]; 250 int16_t cfapwrmode; 251 int16_t reserved161[84]; 252 int16_t integrity; 253}; 254 255/* structure describing an ATA device / 256*struct ata_softc {
252 int32_t unit; /* unit on this controller / 253* int32_t lun; /* logical unit # */
254 struct device dev; / device handle */	257 struct device dev; / device handle */
255 int32_t ioaddr; /* port addr / 256* int32_t altioaddr; /* alternate port addr / 257* int32_t bmaddr; /* bus master DMA port */	258 int32_t unit; /* unit on this controller / 259* struct resource r_io; / io addr resource handle / 260* struct resource r_altio; / altio addr resource handle / 261* struct resource r_bmio; / bmio addr resource handle / 262* struct resource r_irq; / interrupt of this channel / 263* int32_t ioaddr; /* physical port addr / 264* int32_t altioaddr; /* physical alt port addr / 265* int32_t bmaddr; /* physical bus master port */
258 int32_t chiptype; /* pciid of controller chip / 259* struct ata_params dev_param[2]; / ptr to devices params / 260* void dev_softc[2]; / ptr to devices softc's / 261* struct ata_dmaentry dmatab[2]; / DMA transfer tables / 262* int32_t mode[2]; /* transfer mode for devices / 263#define ATA_PIO 0x00 264#define ATA_PIO0 0x08 265#define ATA_PIO1 0x09 --- 4 unchanged lines hidden* (view full) --- 270#define ATA_WDMA2 0x22 271#define ATA_UDMA2 0x42 272#define ATA_UDMA4 0x44 273 274 int32_t flags; /* controller flags / 275#define ATA_DMA_ACTIVE 0x01 276#define ATA_ATAPI_DMA_RO 0x02 277*#define ATA_USE_16BIT 0x04	266 int32_t chiptype; /* pciid of controller chip / 267* struct ata_params dev_param[2]; / ptr to devices params / 268* void dev_softc[2]; / ptr to devices softc's / 269* struct ata_dmaentry dmatab[2]; / DMA transfer tables / 270* int32_t mode[2]; /* transfer mode for devices / 271#define ATA_PIO 0x00 272#define ATA_PIO0 0x08 273#define ATA_PIO1 0x09 --- 4 unchanged lines hidden* (view full) --- 278#define ATA_WDMA2 0x22 279#define ATA_UDMA2 0x42 280#define ATA_UDMA4 0x44 281 282 int32_t flags; /* controller flags / 283#define ATA_DMA_ACTIVE 0x01 284#define ATA_ATAPI_DMA_RO 0x02 285*#define ATA_USE_16BIT 0x04
	286#define ATA_ATTACHED 0x08
278 279 int32_t devices; /* what is present / 280#define ATA_ATA_MASTER 0x01 281#define ATA_ATA_SLAVE 0x02 282#define ATA_ATAPI_MASTER 0x04 283#define ATA_ATAPI_SLAVE 0x08 284* 285 u_int8_t status; /* last controller status / --- 6 unchanged lines hidden* (view full) --- 292#define ATA_ACTIVE 0x4 293#define ATA_ACTIVE_ATA 0x5 294#define ATA_ACTIVE_ATAPI 0x6 295#define ATA_REINITING 0x7 296 297 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue / 298* TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue / 299* void running; / currently running request */	287 288 int32_t devices; /* what is present / 289#define ATA_ATA_MASTER 0x01 290#define ATA_ATA_SLAVE 0x02 291#define ATA_ATAPI_MASTER 0x04 292#define ATA_ATAPI_SLAVE 0x08 293* 294 u_int8_t status; /* last controller status / --- 6 unchanged lines hidden* (view full) --- 301#define ATA_ACTIVE 0x4 302#define ATA_ACTIVE_ATA 0x5 303#define ATA_ACTIVE_ATAPI 0x6 304#define ATA_REINITING 0x7 305 306 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue / 307* TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue / 308* void running; / currently running request */
300#if NAPM > 0 301 struct apmhook resume_hook; /* hook for apm / 302#endif 303*
304}; 305	309}; 310
306/* array to hold all ata softc's / 307extern struct ata_softc atadevices[]; 308#define MAXATA 16	311/* To convert unit numbers to devices / 312*extern devclass_t ata_devclass;
309 310/* public prototypes / 311void ata_start(struct ata_softc ); 312void ata_reset(struct ata_softc , int32_t ); 313int32_t ata_reinit(struct ata_softc ); 314int32_t ata_wait(struct ata_softc , int32_t, u_int8_t); 315int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);	313 314/* public prototypes / 315void ata_start(struct ata_softc ); 316void ata_reset(struct ata_softc , int32_t ); 317int32_t ata_reinit(struct ata_softc ); 318int32_t ata_wait(struct ata_softc , int32_t, u_int8_t); 319int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
	320int ata_printf(struct ata_softc , int32_t, const char , ...) __printflike(3, 4); 321int ata_get_lun(u_int32_t ); 322void ata_free_lun(u_int32_t , int); 323int8_t ata_mode2str(int32_t); 324int8_t ata_pio2mode(int32_t); 325int ata_pmode(struct ata_params ); 326int ata_wmode(struct ata_params ); 327int ata_umode(struct ata_params ); 328
316void ata_dmainit(struct ata_softc , int32_t, int32_t, int32_t, int32_t); 317int32_t ata_dmasetup(struct ata_softc , int32_t, int8_t , int32_t, int32_t); 318void ata_dmastart(struct ata_softc ); 319int32_t ata_dmastatus(struct ata_softc ); 320int32_t ata_dmadone(struct ata_softc );	329void ata_dmainit(struct ata_softc , int32_t, int32_t, int32_t, int32_t); 330int32_t ata_dmasetup(struct ata_softc , int32_t, int8_t , int32_t, int32_t); 331void ata_dmastart(struct ata_softc ); 332int32_t ata_dmastatus(struct ata_softc ); 333int32_t ata_dmadone(struct ata_softc );
321int32_t ata_pmode(struct ata_params ); 322int32_t ata_wmode(struct ata_params ); 323int32_t ata_umode(struct ata_params ); 324int8_t ata_mode2str(int32_t); 325int8_t ata_pio2mode(int32_t); 326int32_t ata_find_dev(device_t, int32_t); 327int32_t ata_printf(struct ata_softc , int32_t, const char , ...) __printflike(3, 4);

ata-all.h (56744)	ata-all.h (57325)
1/- 2 Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *	1/- 2 Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 56744 2000-01-28 13:35:43Z sos $	28 * $FreeBSD: head/sys/dev/ata/ata-all.h 57325 2000-02-18 20:57:33Z sos $
29 / 30 31/ ATA register defines / 32#define ATA_DATA 0x00 / data register / 33#define ATA_ERROR 0x01 / (R) error register / 34#define ATA_E_NM 0x02 / no media / 35#define ATA_E_ABORT 0x04 / command aborted / 36#define ATA_E_MCR 0x08 / media change request / --- 44 unchanged lines hidden* (view full) --- 81#define ATA_S_DRQ 0x08 /* data request / 82#define ATA_S_DSC 0x10 / drive seek completed / 83#define ATA_S_SERVICE 0x10 / drive needs service / 84#define ATA_S_DWF 0x20 / drive write fault / 85#define ATA_S_DMA 0x20 / DMA ready / 86#define ATA_S_READY 0x40 / drive ready / 87#define ATA_S_BUSY 0x80 / busy */ 88	29 / 30 31/ ATA register defines / 32#define ATA_DATA 0x00 / data register / 33#define ATA_ERROR 0x01 / (R) error register / 34#define ATA_E_NM 0x02 / no media / 35#define ATA_E_ABORT 0x04 / command aborted / 36#define ATA_E_MCR 0x08 / media change request / --- 44 unchanged lines hidden* (view full) --- 81#define ATA_S_DRQ 0x08 /* data request / 82#define ATA_S_DSC 0x10 / drive seek completed / 83#define ATA_S_SERVICE 0x10 / drive needs service / 84#define ATA_S_DWF 0x20 / drive write fault / 85#define ATA_S_DMA 0x20 / DMA ready / 86#define ATA_S_READY 0x40 / drive ready / 87#define ATA_S_BUSY 0x80 / busy */ 88
89#define ATA_ALTPORT 0x206 /* alternate Status register */	89#define ATA_ALTPORT 0x206 /* alternate status register / 90#define ATA_ALTPORT_PCCARD 0x8 / ditto on PCCARD devices */
90#define ATA_A_IDS 0x02 /* disable interrupts / 91#define ATA_A_RESET 0x04 / RESET controller / 92#define ATA_A_4BIT 0x08 / 4 head bits */ 93	91#define ATA_A_IDS 0x02 /* disable interrupts / 92#define ATA_A_RESET 0x04 / RESET controller / 93#define ATA_A_4BIT 0x08 / 4 head bits */ 94
	95#define ATA_ALTIOSIZE 0x01 96
94/* misc defines / 95#define ATA_MASTER 0x00 96#define ATA_SLAVE 0x10 97#define ATA_IOSIZE 0x08 98#define ATA_OP_FINISHED 0x00 99#define ATA_OP_CONTINUES 0x01 100#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1) 101#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)] --- 14 unchanged lines hidden* (view full) --- 116#define ATA_BMSTAT_INTERRUPT 0x04 117#define ATA_BMSTAT_MASK 0x07 118#define ATA_BMSTAT_DMA_MASTER 0x20 119#define ATA_BMSTAT_DMA_SLAVE 0x40 120#define ATA_BMSTAT_DMA_SIMPLEX 0x80 121 122#define ATA_BMDTP_PORT 0x04 123	97/* misc defines / 98#define ATA_MASTER 0x00 99#define ATA_SLAVE 0x10 100#define ATA_IOSIZE 0x08 101#define ATA_OP_FINISHED 0x00 102#define ATA_OP_CONTINUES 0x01 103#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1) 104#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)] --- 14 unchanged lines hidden* (view full) --- 119#define ATA_BMSTAT_INTERRUPT 0x04 120#define ATA_BMSTAT_MASK 0x07 121#define ATA_BMSTAT_DMA_MASTER 0x20 122#define ATA_BMSTAT_DMA_SLAVE 0x40 123#define ATA_BMSTAT_DMA_SIMPLEX 0x80 124 125#define ATA_BMDTP_PORT 0x04 126
	127#define ATA_BMIOSIZE 0x20 128
124/* structure for holding DMA address data / 125struct ata_dmaentry { 126* u_int32_t base; 127 u_int32_t count; 128}; 129 130/* ATA/ATAPI device parameter information / 131struct ata_params { --- 112 unchanged lines hidden* (view full) --- 244 int16_t reserved129[30]; 245 int16_t cfapwrmode; 246 int16_t reserved161[84]; 247 int16_t integrity; 248}; 249 250/* structure describing an ATA device / 251*struct ata_softc {	129/* structure for holding DMA address data / 130struct ata_dmaentry { 131* u_int32_t base; 132 u_int32_t count; 133}; 134 135/* ATA/ATAPI device parameter information / 136struct ata_params { --- 112 unchanged lines hidden* (view full) --- 249 int16_t reserved129[30]; 250 int16_t cfapwrmode; 251 int16_t reserved161[84]; 252 int16_t integrity; 253}; 254 255/* structure describing an ATA device / 256*struct ata_softc {
252 int32_t unit; /* unit on this controller / 253* int32_t lun; /* logical unit # */
254 struct device dev; / device handle */	257 struct device dev; / device handle */
255 int32_t ioaddr; /* port addr / 256* int32_t altioaddr; /* alternate port addr / 257* int32_t bmaddr; /* bus master DMA port */	258 int32_t unit; /* unit on this controller / 259* struct resource r_io; / io addr resource handle / 260* struct resource r_altio; / altio addr resource handle / 261* struct resource r_bmio; / bmio addr resource handle / 262* struct resource r_irq; / interrupt of this channel / 263* int32_t ioaddr; /* physical port addr / 264* int32_t altioaddr; /* physical alt port addr / 265* int32_t bmaddr; /* physical bus master port */
258 int32_t chiptype; /* pciid of controller chip / 259* struct ata_params dev_param[2]; / ptr to devices params / 260* void dev_softc[2]; / ptr to devices softc's / 261* struct ata_dmaentry dmatab[2]; / DMA transfer tables / 262* int32_t mode[2]; /* transfer mode for devices / 263#define ATA_PIO 0x00 264#define ATA_PIO0 0x08 265#define ATA_PIO1 0x09 --- 4 unchanged lines hidden* (view full) --- 270#define ATA_WDMA2 0x22 271#define ATA_UDMA2 0x42 272#define ATA_UDMA4 0x44 273 274 int32_t flags; /* controller flags / 275#define ATA_DMA_ACTIVE 0x01 276#define ATA_ATAPI_DMA_RO 0x02 277*#define ATA_USE_16BIT 0x04	266 int32_t chiptype; /* pciid of controller chip / 267* struct ata_params dev_param[2]; / ptr to devices params / 268* void dev_softc[2]; / ptr to devices softc's / 269* struct ata_dmaentry dmatab[2]; / DMA transfer tables / 270* int32_t mode[2]; /* transfer mode for devices / 271#define ATA_PIO 0x00 272#define ATA_PIO0 0x08 273#define ATA_PIO1 0x09 --- 4 unchanged lines hidden* (view full) --- 278#define ATA_WDMA2 0x22 279#define ATA_UDMA2 0x42 280#define ATA_UDMA4 0x44 281 282 int32_t flags; /* controller flags / 283#define ATA_DMA_ACTIVE 0x01 284#define ATA_ATAPI_DMA_RO 0x02 285*#define ATA_USE_16BIT 0x04
	286#define ATA_ATTACHED 0x08
278 279 int32_t devices; /* what is present / 280#define ATA_ATA_MASTER 0x01 281#define ATA_ATA_SLAVE 0x02 282#define ATA_ATAPI_MASTER 0x04 283#define ATA_ATAPI_SLAVE 0x08 284* 285 u_int8_t status; /* last controller status / --- 6 unchanged lines hidden* (view full) --- 292#define ATA_ACTIVE 0x4 293#define ATA_ACTIVE_ATA 0x5 294#define ATA_ACTIVE_ATAPI 0x6 295#define ATA_REINITING 0x7 296 297 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue / 298* TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue / 299* void running; / currently running request */	287 288 int32_t devices; /* what is present / 289#define ATA_ATA_MASTER 0x01 290#define ATA_ATA_SLAVE 0x02 291#define ATA_ATAPI_MASTER 0x04 292#define ATA_ATAPI_SLAVE 0x08 293* 294 u_int8_t status; /* last controller status / --- 6 unchanged lines hidden* (view full) --- 301#define ATA_ACTIVE 0x4 302#define ATA_ACTIVE_ATA 0x5 303#define ATA_ACTIVE_ATAPI 0x6 304#define ATA_REINITING 0x7 305 306 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue / 307* TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue / 308* void running; / currently running request */
300#if NAPM > 0 301 struct apmhook resume_hook; /* hook for apm / 302#endif 303*
304}; 305	309}; 310
306/* array to hold all ata softc's / 307extern struct ata_softc atadevices[]; 308#define MAXATA 16	311/* To convert unit numbers to devices / 312*extern devclass_t ata_devclass;
309 310/* public prototypes / 311void ata_start(struct ata_softc ); 312void ata_reset(struct ata_softc , int32_t ); 313int32_t ata_reinit(struct ata_softc ); 314int32_t ata_wait(struct ata_softc , int32_t, u_int8_t); 315int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);	313 314/* public prototypes / 315void ata_start(struct ata_softc ); 316void ata_reset(struct ata_softc , int32_t ); 317int32_t ata_reinit(struct ata_softc ); 318int32_t ata_wait(struct ata_softc , int32_t, u_int8_t); 319int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
	320int ata_printf(struct ata_softc , int32_t, const char , ...) __printflike(3, 4); 321int ata_get_lun(u_int32_t ); 322void ata_free_lun(u_int32_t , int); 323int8_t ata_mode2str(int32_t); 324int8_t ata_pio2mode(int32_t); 325int ata_pmode(struct ata_params ); 326int ata_wmode(struct ata_params ); 327int ata_umode(struct ata_params ); 328
316void ata_dmainit(struct ata_softc , int32_t, int32_t, int32_t, int32_t); 317int32_t ata_dmasetup(struct ata_softc , int32_t, int8_t , int32_t, int32_t); 318void ata_dmastart(struct ata_softc ); 319int32_t ata_dmastatus(struct ata_softc ); 320int32_t ata_dmadone(struct ata_softc );	329void ata_dmainit(struct ata_softc , int32_t, int32_t, int32_t, int32_t); 330int32_t ata_dmasetup(struct ata_softc , int32_t, int8_t , int32_t, int32_t); 331void ata_dmastart(struct ata_softc ); 332int32_t ata_dmastatus(struct ata_softc ); 333int32_t ata_dmadone(struct ata_softc );
321int32_t ata_pmode(struct ata_params ); 322int32_t ata_wmode(struct ata_params ); 323int32_t ata_umode(struct ata_params ); 324int8_t ata_mode2str(int32_t); 325int8_t ata_pio2mode(int32_t); 326int32_t ata_find_dev(device_t, int32_t); 327int32_t ata_printf(struct ata_softc , int32_t, const char , ...) __printflike(3, 4);