| ata-all.h (56607) | ata-all.h (56686) |
|---|---|
| 1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 56607 2000-01-25 20:14:51Z sos $ | 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 56686 2000-01-27 19:00:51Z sos $ |
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ --- 218 unchanged lines hidden (view full) --- 255 int32_t ioaddr; /* port addr */ 256 int32_t altioaddr; /* alternate port addr */ 257 int32_t bmaddr; /* bus master DMA port */ 258 int32_t chiptype; /* pciid of controller chip */ 259 struct ata_params *dev_param[2]; /* ptr to devices params */ 260 void *dev_softc[2]; /* ptr to devices softc's */ 261 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 262 int32_t mode[2]; /* transfer mode for devices */ | 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ --- 218 unchanged lines hidden (view full) --- 255 int32_t ioaddr; /* port addr */ 256 int32_t altioaddr; /* alternate port addr */ 257 int32_t bmaddr; /* bus master DMA port */ 258 int32_t chiptype; /* pciid of controller chip */ 259 struct ata_params *dev_param[2]; /* ptr to devices params */ 260 void *dev_softc[2]; /* ptr to devices softc's */ 261 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 262 int32_t mode[2]; /* transfer mode for devices */ |
| 263#define ATA_PIO 0x00 |
|
| 263#define ATA_PIO0 0x08 264#define ATA_PIO1 0x09 265#define ATA_PIO2 0x0a 266#define ATA_PIO3 0x0b 267#define ATA_PIO4 0x0c | 264#define ATA_PIO0 0x08 265#define ATA_PIO1 0x09 266#define ATA_PIO2 0x0a 267#define ATA_PIO3 0x0b 268#define ATA_PIO4 0x0c |
| 269#define ATA_DMA 0x10 |
|
| 268#define ATA_WDMA2 0x22 269#define ATA_UDMA2 0x42 270#define ATA_UDMA4 0x44 | 270#define ATA_WDMA2 0x22 271#define ATA_UDMA2 0x42 272#define ATA_UDMA4 0x44 |
| 271#define ATA_DMA 0xff | |
| 272 273 int32_t flags; /* controller flags */ 274#define ATA_DMA_ACTIVE 0x01 275#define ATA_ATAPI_DMA_RO 0x02 276#define ATA_USE_16BIT 0x04 277 278 int32_t devices; /* what is present */ 279#define ATA_ATA_MASTER 0x01 280#define ATA_ATA_SLAVE 0x02 281#define ATA_ATAPI_MASTER 0x04 282#define ATA_ATAPI_SLAVE 0x08 283 284 u_int8_t status; /* last controller status */ 285 u_int8_t error; /* last controller error */ 286 int32_t active; /* active processing request */ 287#define ATA_IDLE 0x0 288#define ATA_IMMEDIATE 0x1 289#define ATA_WAIT_INTR 0x2 290#define ATA_WAIT_READY 0x3 | 273 274 int32_t flags; /* controller flags */ 275#define ATA_DMA_ACTIVE 0x01 276#define ATA_ATAPI_DMA_RO 0x02 277#define ATA_USE_16BIT 0x04 278 279 int32_t devices; /* what is present */ 280#define ATA_ATA_MASTER 0x01 281#define ATA_ATA_SLAVE 0x02 282#define ATA_ATAPI_MASTER 0x04 283#define ATA_ATAPI_SLAVE 0x08 284 285 u_int8_t status; /* last controller status */ 286 u_int8_t error; /* last controller error */ 287 int32_t active; /* active processing request */ 288#define ATA_IDLE 0x0 289#define ATA_IMMEDIATE 0x1 290#define ATA_WAIT_INTR 0x2 291#define ATA_WAIT_READY 0x3 |
| 291#define ATA_ACTIVE_ATA 0x4 292#define ATA_ACTIVE_ATAPI 0x5 293#define ATA_REINITING 0x6 | 292#define ATA_ACTIVE 0x4 293#define ATA_ACTIVE_ATA 0x5 294#define ATA_ACTIVE_ATAPI 0x6 295#define ATA_REINITING 0x7 |
| 294 295 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 296 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 297 void *running; /* currently running request */ 298#if NAPM > 0 299 struct apmhook resume_hook; /* hook for apm */ 300#endif 301 --- 24 unchanged lines hidden --- | 296 297 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 298 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 299 void *running; /* currently running request */ 300#if NAPM > 0 301 struct apmhook resume_hook; /* hook for apm */ 302#endif 303 --- 24 unchanged lines hidden --- |