| ata-all.h (48213) | ata-all.h (49614) |
|---|---|
| 1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
| 28 * $Id: ata-all.h,v 1.6 1999/04/18 20:48:15 sos Exp $ | 28 * $Id: ata-all.h,v 1.7 1999/06/25 09:02:57 sos Exp $ |
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_FEATURE 0x01 /* (W) feature register */ 35#define ATA_F_DMA 0x01 /* enable DMA */ 36#define ATA_F_OVL 0x02 /* enable overlap */ --- 45 unchanged lines hidden (view full) --- 82 83/* misc defines */ 84#define ATA_MASTER 0x00 85#define ATA_SLAVE 0x10 86#define ATA_IOSIZE 0x08 87#define ATA_OP_FINISHED 0x00 88#define ATA_OP_CONTINUES 0x01 89 | 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_FEATURE 0x01 /* (W) feature register */ 35#define ATA_F_DMA 0x01 /* enable DMA */ 36#define ATA_F_OVL 0x02 /* enable overlap */ --- 45 unchanged lines hidden (view full) --- 82 83/* misc defines */ 84#define ATA_MASTER 0x00 85#define ATA_SLAVE 0x10 86#define ATA_IOSIZE 0x08 87#define ATA_OP_FINISHED 0x00 88#define ATA_OP_CONTINUES 0x01 89 |
| 90/* devices types */ 91#define ATA_ATA_MASTER 0x01 92#define ATA_ATA_SLAVE 0x02 93#define ATA_ATAPI_MASTER 0x04 94#define ATA_ATAPI_SLAVE 0x08 95 | |
| 96/* busmaster DMA related defines */ 97#define ATA_BM_OFFSET1 0x08 98#define ATA_DMA_ENTRIES 256 99#define ATA_DMA_EOT 0x80000000 100 101#define ATA_BMCMD_PORT 0x00 102#define ATA_BMCMD_START_STOP 0x01 103#define ATA_BMCMD_WRITE_READ 0x08 --- 23 unchanged lines hidden (view full) --- 127 int32_t lun; /* logical unit # */ 128 struct device *dev; /* device handle */ 129 int32_t ioaddr; /* port addr */ 130 int32_t altioaddr; /* alternate port addr */ 131 int32_t bmaddr; /* bus master DMA port */ 132 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 133 int32_t flags; /* controller flags */ 134 int32_t devices; /* what is present */ | 90/* busmaster DMA related defines */ 91#define ATA_BM_OFFSET1 0x08 92#define ATA_DMA_ENTRIES 256 93#define ATA_DMA_EOT 0x80000000 94 95#define ATA_BMCMD_PORT 0x00 96#define ATA_BMCMD_START_STOP 0x01 97#define ATA_BMCMD_WRITE_READ 0x08 --- 23 unchanged lines hidden (view full) --- 121 int32_t lun; /* logical unit # */ 122 struct device *dev; /* device handle */ 123 int32_t ioaddr; /* port addr */ 124 int32_t altioaddr; /* alternate port addr */ 125 int32_t bmaddr; /* bus master DMA port */ 126 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 127 int32_t flags; /* controller flags */ 128 int32_t devices; /* what is present */ |
| 129#define ATA_ATA_MASTER 0x01 130#define ATA_ATA_SLAVE 0x02 131#define ATA_ATAPI_MASTER 0x04 132#define ATA_ATAPI_SLAVE 0x08 133 |
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| 135 u_int8_t status; /* last controller status */ 136 u_int8_t error; /* last controller error */ 137 int32_t active; /* active processing request */ 138#define ATA_IDLE 0x0 139#define ATA_IMMEDIATE 0x0 140#define ATA_WAIT_INTR 0x1 141#define ATA_IGNORE_INTR 0x2 142#define ATA_ACTIVE_ATA 0x3 --- 23 unchanged lines hidden --- | 134 u_int8_t status; /* last controller status */ 135 u_int8_t error; /* last controller error */ 136 int32_t active; /* active processing request */ 137#define ATA_IDLE 0x0 138#define ATA_IMMEDIATE 0x0 139#define ATA_WAIT_INTR 0x1 140#define ATA_IGNORE_INTR 0x2 141#define ATA_ACTIVE_ATA 0x3 --- 23 unchanged lines hidden --- |