1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 56744 2000-01-28 13:35:43Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 57325 2000-02-18 20:57:33Z sos $
|
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
62#define ATA_C_READ 0x20 /* read command */
63#define ATA_C_WRITE 0x30 /* write command */
64#define ATA_C_PACKET_CMD 0xa0 /* packet command */
65#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
66#define ATA_C_READ_MULTI 0xc4 /* read multi command */
67#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
68#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
69#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
70#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
71#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
72#define ATA_C_SETFEATURES 0xef /* features command */
73#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
74#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
75#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
76
77#define ATA_STATUS 0x07 /* status register */
78#define ATA_S_ERROR 0x01 /* error */
79#define ATA_S_INDEX 0x02 /* index */
80#define ATA_S_CORR 0x04 /* data corrected */
81#define ATA_S_DRQ 0x08 /* data request */
82#define ATA_S_DSC 0x10 /* drive seek completed */
83#define ATA_S_SERVICE 0x10 /* drive needs service */
84#define ATA_S_DWF 0x20 /* drive write fault */
85#define ATA_S_DMA 0x20 /* DMA ready */
86#define ATA_S_READY 0x40 /* drive ready */
87#define ATA_S_BUSY 0x80 /* busy */
88
| 29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
62#define ATA_C_READ 0x20 /* read command */
63#define ATA_C_WRITE 0x30 /* write command */
64#define ATA_C_PACKET_CMD 0xa0 /* packet command */
65#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
66#define ATA_C_READ_MULTI 0xc4 /* read multi command */
67#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
68#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
69#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
70#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
71#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
72#define ATA_C_SETFEATURES 0xef /* features command */
73#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
74#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
75#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
76
77#define ATA_STATUS 0x07 /* status register */
78#define ATA_S_ERROR 0x01 /* error */
79#define ATA_S_INDEX 0x02 /* index */
80#define ATA_S_CORR 0x04 /* data corrected */
81#define ATA_S_DRQ 0x08 /* data request */
82#define ATA_S_DSC 0x10 /* drive seek completed */
83#define ATA_S_SERVICE 0x10 /* drive needs service */
84#define ATA_S_DWF 0x20 /* drive write fault */
85#define ATA_S_DMA 0x20 /* DMA ready */
86#define ATA_S_READY 0x40 /* drive ready */
87#define ATA_S_BUSY 0x80 /* busy */
88
|
89#define ATA_ALTPORT 0x206 /* alternate Status register */
| 89#define ATA_ALTPORT 0x206 /* alternate status register */
90#define ATA_ALTPORT_PCCARD 0x8 /* ditto on PCCARD devices */
|
90#define ATA_A_IDS 0x02 /* disable interrupts */
91#define ATA_A_RESET 0x04 /* RESET controller */
92#define ATA_A_4BIT 0x08 /* 4 head bits */
93
| 91#define ATA_A_IDS 0x02 /* disable interrupts */
92#define ATA_A_RESET 0x04 /* RESET controller */
93#define ATA_A_4BIT 0x08 /* 4 head bits */
94
|
| 95#define ATA_ALTIOSIZE 0x01
96
|
94/* misc defines */
95#define ATA_MASTER 0x00
96#define ATA_SLAVE 0x10
97#define ATA_IOSIZE 0x08
98#define ATA_OP_FINISHED 0x00
99#define ATA_OP_CONTINUES 0x01
100#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1)
101#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)]
102
103
104/* busmaster DMA related defines */
105#define ATA_BM_OFFSET1 0x08
106#define ATA_DMA_ENTRIES 256
107#define ATA_DMA_EOT 0x80000000
108
109#define ATA_BMCMD_PORT 0x00
110#define ATA_BMCMD_START_STOP 0x01
111#define ATA_BMCMD_WRITE_READ 0x08
112
113#define ATA_BMSTAT_PORT 0x02
114#define ATA_BMSTAT_ACTIVE 0x01
115#define ATA_BMSTAT_ERROR 0x02
116#define ATA_BMSTAT_INTERRUPT 0x04
117#define ATA_BMSTAT_MASK 0x07
118#define ATA_BMSTAT_DMA_MASTER 0x20
119#define ATA_BMSTAT_DMA_SLAVE 0x40
120#define ATA_BMSTAT_DMA_SIMPLEX 0x80
121
122#define ATA_BMDTP_PORT 0x04
123
| 97/* misc defines */
98#define ATA_MASTER 0x00
99#define ATA_SLAVE 0x10
100#define ATA_IOSIZE 0x08
101#define ATA_OP_FINISHED 0x00
102#define ATA_OP_CONTINUES 0x01
103#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1)
104#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)]
105
106
107/* busmaster DMA related defines */
108#define ATA_BM_OFFSET1 0x08
109#define ATA_DMA_ENTRIES 256
110#define ATA_DMA_EOT 0x80000000
111
112#define ATA_BMCMD_PORT 0x00
113#define ATA_BMCMD_START_STOP 0x01
114#define ATA_BMCMD_WRITE_READ 0x08
115
116#define ATA_BMSTAT_PORT 0x02
117#define ATA_BMSTAT_ACTIVE 0x01
118#define ATA_BMSTAT_ERROR 0x02
119#define ATA_BMSTAT_INTERRUPT 0x04
120#define ATA_BMSTAT_MASK 0x07
121#define ATA_BMSTAT_DMA_MASTER 0x20
122#define ATA_BMSTAT_DMA_SLAVE 0x40
123#define ATA_BMSTAT_DMA_SIMPLEX 0x80
124
125#define ATA_BMDTP_PORT 0x04
126
|
| 127#define ATA_BMIOSIZE 0x20
128
|
124/* structure for holding DMA address data */
125struct ata_dmaentry {
126 u_int32_t base;
127 u_int32_t count;
128};
129
130/* ATA/ATAPI device parameter information */
131struct ata_params {
132 u_int8_t cmdsize :2; /* packet command size */
133#define ATAPI_PSIZE_12 0 /* 12 bytes */
134#define ATAPI_PSIZE_16 1 /* 16 bytes */
135
136 u_int8_t :3;
137 u_int8_t drqtype :2; /* DRQ type */
138#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
139#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
140#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
141
142 u_int8_t removable :1; /* device is removable */
143 u_int8_t device_type :5; /* device type */
144#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
145#define ATAPI_TYPE_TAPE 1 /* streaming tape */
146#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
147#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
148
149 u_int8_t :1;
150 u_int8_t proto :2; /* command protocol */
151#define ATAPI_PROTO_ATAPI 2
152
153 u_int16_t cylinders; /* number of cylinders */
154 int16_t reserved2;
155 u_int16_t heads; /* # heads */
156 int16_t unfbytespertrk; /* # unformatted bytes/track */
157 int16_t unfbytes; /* # unformatted bytes/sector */
158 u_int16_t sectors; /* # sectors/track */
159 int16_t vendorunique0[3];
160 int8_t serial[20]; /* serial number */
161 int16_t buffertype; /* buffer type */
162#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
163#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
164#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
165
166 int16_t buffersize; /* buf size, 512-byte units */
167 int16_t necc; /* ecc bytes appended */
168 int8_t revision[8]; /* firmware revision */
169 int8_t model[40]; /* model name */
170 int8_t nsecperint; /* sectors per interrupt */
171 int8_t vendorunique1;
172 int16_t usedmovsd; /* double word read/write? */
173
174 u_int8_t vendorcap; /* vendor capabilities */
175 u_int8_t dmaflag :1; /* DMA supported - always 1 */
176 u_int8_t lbaflag :1; /* LBA supported - always 1 */
177 u_int8_t iordydis :1; /* IORDY may be disabled */
178 u_int8_t iordyflag :1; /* IORDY supported */
179 u_int8_t softreset :1; /* needs softreset when busy */
180 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
181 u_int8_t queuing :1; /* supports queuing overlap */
182 u_int8_t idmaflag :1; /* interleaved DMA supported */
183 int16_t capvalidate; /* validation for above */
184
185 int8_t vendorunique3;
186 int8_t opiomode; /* PIO modes 0-2 */
187 int8_t vendorunique4;
188 int8_t odmamode; /* old DMA modes, not ATA-3 */
189
190 int16_t atavalid; /* fields valid */
191#define ATA_FLAG_54_58 1 /* words 54-58 valid */
192#define ATA_FLAG_64_70 2 /* words 64-70 valid */
193#define ATA_FLAG_88 4 /* word 88 valid */
194
195 int16_t currcyls;
196 int16_t currheads;
197 int16_t currsectors;
198 int16_t currsize0;
199 int16_t currsize1;
200 int8_t currmultsect;
201 int8_t multsectvalid;
202 int32_t lbasize;
203
204 int16_t sdmamodes; /* singleword DMA modes */
205 int16_t wdmamodes; /* multiword DMA modes */
206 int16_t apiomodes; /* advanced PIO modes */
207
208 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
209 u_int16_t mwdmarec; /* rec. M/W DMA time ns */
210 u_int16_t pioblind; /* min. PIO cycle w/o flow */
211 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
212
213 int16_t reserved69;
214 int16_t reserved70;
215 u_int16_t rlsovlap; /* rel time (us) for overlap */
216 u_int16_t rlsservice; /* rel time (us) for service */
217 int16_t reserved73;
218 int16_t reserved74;
219 int16_t queuelen;
220 int16_t reserved76;
221 int16_t reserved77;
222 int16_t reserved78;
223 int16_t reserved79;
224 int16_t versmajor;
225 int16_t versminor;
226 int16_t featsupp1;
227 int16_t featsupp2;
228 int16_t featsupp3;
229 int16_t featenab1;
230 int16_t featenab2;
231 int16_t featenab3;
232 int16_t udmamodes; /* UltraDMA modes */
233 int16_t erasetime;
234 int16_t enherasetime;
235 int16_t apmlevel;
236 int16_t masterpasswdrev;
237 u_int16_t masterhwres :8;
238 u_int16_t slavehwres :5;
239 u_int16_t cblid :1;
240 u_int16_t reserved93_1415 :2;
241 int16_t reserved94[32];
242 int16_t rmvstat;
243 int16_t securstat;
244 int16_t reserved129[30];
245 int16_t cfapwrmode;
246 int16_t reserved161[84];
247 int16_t integrity;
248};
249
250/* structure describing an ATA device */
251struct ata_softc {
| 129/* structure for holding DMA address data */
130struct ata_dmaentry {
131 u_int32_t base;
132 u_int32_t count;
133};
134
135/* ATA/ATAPI device parameter information */
136struct ata_params {
137 u_int8_t cmdsize :2; /* packet command size */
138#define ATAPI_PSIZE_12 0 /* 12 bytes */
139#define ATAPI_PSIZE_16 1 /* 16 bytes */
140
141 u_int8_t :3;
142 u_int8_t drqtype :2; /* DRQ type */
143#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
144#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
145#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
146
147 u_int8_t removable :1; /* device is removable */
148 u_int8_t device_type :5; /* device type */
149#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
150#define ATAPI_TYPE_TAPE 1 /* streaming tape */
151#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
152#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
153
154 u_int8_t :1;
155 u_int8_t proto :2; /* command protocol */
156#define ATAPI_PROTO_ATAPI 2
157
158 u_int16_t cylinders; /* number of cylinders */
159 int16_t reserved2;
160 u_int16_t heads; /* # heads */
161 int16_t unfbytespertrk; /* # unformatted bytes/track */
162 int16_t unfbytes; /* # unformatted bytes/sector */
163 u_int16_t sectors; /* # sectors/track */
164 int16_t vendorunique0[3];
165 int8_t serial[20]; /* serial number */
166 int16_t buffertype; /* buffer type */
167#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
168#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
169#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
170
171 int16_t buffersize; /* buf size, 512-byte units */
172 int16_t necc; /* ecc bytes appended */
173 int8_t revision[8]; /* firmware revision */
174 int8_t model[40]; /* model name */
175 int8_t nsecperint; /* sectors per interrupt */
176 int8_t vendorunique1;
177 int16_t usedmovsd; /* double word read/write? */
178
179 u_int8_t vendorcap; /* vendor capabilities */
180 u_int8_t dmaflag :1; /* DMA supported - always 1 */
181 u_int8_t lbaflag :1; /* LBA supported - always 1 */
182 u_int8_t iordydis :1; /* IORDY may be disabled */
183 u_int8_t iordyflag :1; /* IORDY supported */
184 u_int8_t softreset :1; /* needs softreset when busy */
185 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
186 u_int8_t queuing :1; /* supports queuing overlap */
187 u_int8_t idmaflag :1; /* interleaved DMA supported */
188 int16_t capvalidate; /* validation for above */
189
190 int8_t vendorunique3;
191 int8_t opiomode; /* PIO modes 0-2 */
192 int8_t vendorunique4;
193 int8_t odmamode; /* old DMA modes, not ATA-3 */
194
195 int16_t atavalid; /* fields valid */
196#define ATA_FLAG_54_58 1 /* words 54-58 valid */
197#define ATA_FLAG_64_70 2 /* words 64-70 valid */
198#define ATA_FLAG_88 4 /* word 88 valid */
199
200 int16_t currcyls;
201 int16_t currheads;
202 int16_t currsectors;
203 int16_t currsize0;
204 int16_t currsize1;
205 int8_t currmultsect;
206 int8_t multsectvalid;
207 int32_t lbasize;
208
209 int16_t sdmamodes; /* singleword DMA modes */
210 int16_t wdmamodes; /* multiword DMA modes */
211 int16_t apiomodes; /* advanced PIO modes */
212
213 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
214 u_int16_t mwdmarec; /* rec. M/W DMA time ns */
215 u_int16_t pioblind; /* min. PIO cycle w/o flow */
216 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
217
218 int16_t reserved69;
219 int16_t reserved70;
220 u_int16_t rlsovlap; /* rel time (us) for overlap */
221 u_int16_t rlsservice; /* rel time (us) for service */
222 int16_t reserved73;
223 int16_t reserved74;
224 int16_t queuelen;
225 int16_t reserved76;
226 int16_t reserved77;
227 int16_t reserved78;
228 int16_t reserved79;
229 int16_t versmajor;
230 int16_t versminor;
231 int16_t featsupp1;
232 int16_t featsupp2;
233 int16_t featsupp3;
234 int16_t featenab1;
235 int16_t featenab2;
236 int16_t featenab3;
237 int16_t udmamodes; /* UltraDMA modes */
238 int16_t erasetime;
239 int16_t enherasetime;
240 int16_t apmlevel;
241 int16_t masterpasswdrev;
242 u_int16_t masterhwres :8;
243 u_int16_t slavehwres :5;
244 u_int16_t cblid :1;
245 u_int16_t reserved93_1415 :2;
246 int16_t reserved94[32];
247 int16_t rmvstat;
248 int16_t securstat;
249 int16_t reserved129[30];
250 int16_t cfapwrmode;
251 int16_t reserved161[84];
252 int16_t integrity;
253};
254
255/* structure describing an ATA device */
256struct ata_softc {
|
252 int32_t unit; /* unit on this controller */
253 int32_t lun; /* logical unit # */
| |
254 struct device *dev; /* device handle */
| 257 struct device *dev; /* device handle */
|
255 int32_t ioaddr; /* port addr */
256 int32_t altioaddr; /* alternate port addr */
257 int32_t bmaddr; /* bus master DMA port */
| 258 int32_t unit; /* unit on this controller */
259 struct resource *r_io; /* io addr resource handle */
260 struct resource *r_altio; /* altio addr resource handle */
261 struct resource *r_bmio; /* bmio addr resource handle */
262 struct resource *r_irq; /* interrupt of this channel */
263 int32_t ioaddr; /* physical port addr */
264 int32_t altioaddr; /* physical alt port addr */
265 int32_t bmaddr; /* physical bus master port */
|
258 int32_t chiptype; /* pciid of controller chip */
259 struct ata_params *dev_param[2]; /* ptr to devices params */
260 void *dev_softc[2]; /* ptr to devices softc's */
261 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
262 int32_t mode[2]; /* transfer mode for devices */
263#define ATA_PIO 0x00
264#define ATA_PIO0 0x08
265#define ATA_PIO1 0x09
266#define ATA_PIO2 0x0a
267#define ATA_PIO3 0x0b
268#define ATA_PIO4 0x0c
269#define ATA_DMA 0x10
270#define ATA_WDMA2 0x22
271#define ATA_UDMA2 0x42
272#define ATA_UDMA4 0x44
273
274 int32_t flags; /* controller flags */
275#define ATA_DMA_ACTIVE 0x01
276#define ATA_ATAPI_DMA_RO 0x02
277#define ATA_USE_16BIT 0x04
| 266 int32_t chiptype; /* pciid of controller chip */
267 struct ata_params *dev_param[2]; /* ptr to devices params */
268 void *dev_softc[2]; /* ptr to devices softc's */
269 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
270 int32_t mode[2]; /* transfer mode for devices */
271#define ATA_PIO 0x00
272#define ATA_PIO0 0x08
273#define ATA_PIO1 0x09
274#define ATA_PIO2 0x0a
275#define ATA_PIO3 0x0b
276#define ATA_PIO4 0x0c
277#define ATA_DMA 0x10
278#define ATA_WDMA2 0x22
279#define ATA_UDMA2 0x42
280#define ATA_UDMA4 0x44
281
282 int32_t flags; /* controller flags */
283#define ATA_DMA_ACTIVE 0x01
284#define ATA_ATAPI_DMA_RO 0x02
285#define ATA_USE_16BIT 0x04
|
| 286#define ATA_ATTACHED 0x08
|
278
279 int32_t devices; /* what is present */
280#define ATA_ATA_MASTER 0x01
281#define ATA_ATA_SLAVE 0x02
282#define ATA_ATAPI_MASTER 0x04
283#define ATA_ATAPI_SLAVE 0x08
284
285 u_int8_t status; /* last controller status */
286 u_int8_t error; /* last controller error */
287 int32_t active; /* active processing request */
288#define ATA_IDLE 0x0
289#define ATA_IMMEDIATE 0x1
290#define ATA_WAIT_INTR 0x2
291#define ATA_WAIT_READY 0x3
292#define ATA_ACTIVE 0x4
293#define ATA_ACTIVE_ATA 0x5
294#define ATA_ACTIVE_ATAPI 0x6
295#define ATA_REINITING 0x7
296
297 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
298 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
299 void *running; /* currently running request */
| 287
288 int32_t devices; /* what is present */
289#define ATA_ATA_MASTER 0x01
290#define ATA_ATA_SLAVE 0x02
291#define ATA_ATAPI_MASTER 0x04
292#define ATA_ATAPI_SLAVE 0x08
293
294 u_int8_t status; /* last controller status */
295 u_int8_t error; /* last controller error */
296 int32_t active; /* active processing request */
297#define ATA_IDLE 0x0
298#define ATA_IMMEDIATE 0x1
299#define ATA_WAIT_INTR 0x2
300#define ATA_WAIT_READY 0x3
301#define ATA_ACTIVE 0x4
302#define ATA_ACTIVE_ATA 0x5
303#define ATA_ACTIVE_ATAPI 0x6
304#define ATA_REINITING 0x7
305
306 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
307 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
308 void *running; /* currently running request */
|
300#if NAPM > 0
301 struct apmhook resume_hook; /* hook for apm */
302#endif
303
| |
304};
305
| 309};
310
|
306/* array to hold all ata softc's */
307extern struct ata_softc *atadevices[];
308#define MAXATA 16
| 311/* To convert unit numbers to devices */
312extern devclass_t ata_devclass;
|
309
310/* public prototypes */
311void ata_start(struct ata_softc *);
312void ata_reset(struct ata_softc *, int32_t *);
313int32_t ata_reinit(struct ata_softc *);
314int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
315int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
| 313
314/* public prototypes */
315void ata_start(struct ata_softc *);
316void ata_reset(struct ata_softc *, int32_t *);
317int32_t ata_reinit(struct ata_softc *);
318int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
319int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
|
| 320int ata_printf(struct ata_softc *, int32_t, const char *, ...) __printflike(3, 4);
321int ata_get_lun(u_int32_t *);
322void ata_free_lun(u_int32_t *, int);
323int8_t *ata_mode2str(int32_t);
324int8_t ata_pio2mode(int32_t);
325int ata_pmode(struct ata_params *);
326int ata_wmode(struct ata_params *);
327int ata_umode(struct ata_params *);
328
|
316void ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
317int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
318void ata_dmastart(struct ata_softc *);
319int32_t ata_dmastatus(struct ata_softc *);
320int32_t ata_dmadone(struct ata_softc *);
| 329void ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
330int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
331void ata_dmastart(struct ata_softc *);
332int32_t ata_dmastatus(struct ata_softc *);
333int32_t ata_dmadone(struct ata_softc *);
|
321int32_t ata_pmode(struct ata_params *);
322int32_t ata_wmode(struct ata_params *);
323int32_t ata_umode(struct ata_params *);
324int8_t *ata_mode2str(int32_t);
325int8_t ata_pio2mode(int32_t);
326int32_t ata_find_dev(device_t, int32_t);
327int32_t ata_printf(struct ata_softc *, int32_t, const char *, ...) __printflike(3, 4);
| |
| |