1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
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20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 67058 2000-10-13 11:21:27Z sos $
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
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106#define ATA_A_4BIT 0x08 /* 4 head bits */
107
108/* misc defines */
109#define ATA_MASTER 0x00
110#define ATA_SLAVE 0x10
111#define ATA_IOSIZE 0x08
112#define ATA_OP_FINISHED 0x00
113#define ATA_OP_CONTINUES 0x01
114#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
115#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
116
117/* busmaster DMA related defines */
118#define ATA_BM_OFFSET1 0x08
119#define ATA_DMA_ENTRIES 256
120#define ATA_DMA_EOT 0x80000000
121
122#define ATA_BMCMD_PORT 0x00
123#define ATA_BMCMD_START_STOP 0x01
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271 u_int16_t cfapwrmode;
272 u_int16_t reserved161[84];
273 u_int16_t integrity;
274};
275
276/* structure describing an ATA device */
277struct ata_softc {
278 struct device *dev; /* device handle */
279 int channel; /* channel on this controller */
280 struct resource *r_io; /* io addr resource handle */
281 struct resource *r_altio; /* altio addr resource handle */
282 struct resource *r_bmio; /* bmio addr resource handle */
283 struct resource *r_irq; /* interrupt of this channel */
284 void *ih; /* interrupt handle */
285 u_int32_t ioaddr; /* physical port addr */
286 u_int32_t altioaddr; /* physical alt port addr */
287 u_int32_t bmaddr; /* physical bus master port */
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303#define ATA_UDMA5 0x45
304
305 int flags; /* controller flags */
306#define ATA_DMA_ACTIVE 0x01
307#define ATA_ATAPI_DMA_RO 0x02
308#define ATA_USE_16BIT 0x04
309#define ATA_ATTACHED 0x08
310#define ATA_QUEUED 0x10
311#define ATA_RAID 0x20
312
313 int devices; /* what is present */
314#define ATA_ATA_MASTER 0x01
315#define ATA_ATA_SLAVE 0x02
316#define ATA_ATAPI_MASTER 0x04
317#define ATA_ATAPI_SLAVE 0x08
318
319 u_int8_t status; /* last controller status */
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328#define ATA_ACTIVE_ATAPI 0x6
329#define ATA_REINITING 0x7
330
331 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
332 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
333 void *running; /* currently running request */
334};
335
336/* externs */
337extern devclass_t ata_devclass;
338
339/* public prototypes */
340void ata_start(struct ata_softc *);
341void ata_reset(struct ata_softc *, int *);
342int ata_reinit(struct ata_softc *);
343int ata_wait(struct ata_softc *, int, u_int8_t);
344int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
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2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
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20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 67058 2000-10-13 11:21:27Z sos $
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
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106#define ATA_A_4BIT 0x08 /* 4 head bits */
107
108/* misc defines */
109#define ATA_MASTER 0x00
110#define ATA_SLAVE 0x10
111#define ATA_IOSIZE 0x08
112#define ATA_OP_FINISHED 0x00
113#define ATA_OP_CONTINUES 0x01
114#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
115#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
116
117/* busmaster DMA related defines */
118#define ATA_BM_OFFSET1 0x08
119#define ATA_DMA_ENTRIES 256
120#define ATA_DMA_EOT 0x80000000
121
122#define ATA_BMCMD_PORT 0x00
123#define ATA_BMCMD_START_STOP 0x01
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271 u_int16_t cfapwrmode;
272 u_int16_t reserved161[84];
273 u_int16_t integrity;
274};
275
276/* structure describing an ATA device */
277struct ata_softc {
278 struct device *dev; /* device handle */
279 int channel; /* channel on this controller */
280 struct resource *r_io; /* io addr resource handle */
281 struct resource *r_altio; /* altio addr resource handle */
282 struct resource *r_bmio; /* bmio addr resource handle */
283 struct resource *r_irq; /* interrupt of this channel */
284 void *ih; /* interrupt handle */
285 u_int32_t ioaddr; /* physical port addr */
286 u_int32_t altioaddr; /* physical alt port addr */
287 u_int32_t bmaddr; /* physical bus master port */
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303#define ATA_UDMA5 0x45
304
305 int flags; /* controller flags */
306#define ATA_DMA_ACTIVE 0x01
307#define ATA_ATAPI_DMA_RO 0x02
308#define ATA_USE_16BIT 0x04
309#define ATA_ATTACHED 0x08
310#define ATA_QUEUED 0x10
311#define ATA_RAID 0x20
312
313 int devices; /* what is present */
314#define ATA_ATA_MASTER 0x01
315#define ATA_ATA_SLAVE 0x02
316#define ATA_ATAPI_MASTER 0x04
317#define ATA_ATAPI_SLAVE 0x08
318
319 u_int8_t status; /* last controller status */
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328#define ATA_ACTIVE_ATAPI 0x6
329#define ATA_REINITING 0x7
330
331 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
332 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
333 void *running; /* currently running request */
334};
335
336/* externs */
337extern devclass_t ata_devclass;
338
339/* public prototypes */
340void ata_start(struct ata_softc *);
341void ata_reset(struct ata_softc *, int *);
342int ata_reinit(struct ata_softc *);
343int ata_wait(struct ata_softc *, int, u_int8_t);
344int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
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