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if_atse.c (271679) if_atse.c (271849)
1/*-
2 * Copyright (c) 2012,2013 Bjoern A. Zeeb
3 * Copyright (c) 2014 Robert N. M. Watson
4 * All rights reserved.
5 *
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
8 * ("MRC2"), as part of the DARPA MRC research programme.

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45 * - test 100Mbit/s and 10Mbit/s
46 * - blacklist the one special factory programmed ethernet address (for now
47 * hardcoded, later from loader?)
48 * - resolve all XXX, left as reminders to shake out details later
49 * - Jumbo frame support
50 */
51
52#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2012,2013 Bjoern A. Zeeb
3 * Copyright (c) 2014 Robert N. M. Watson
4 * All rights reserved.
5 *
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
8 * ("MRC2"), as part of the DARPA MRC research programme.

--- 36 unchanged lines hidden (view full) ---

45 * - test 100Mbit/s and 10Mbit/s
46 * - blacklist the one special factory programmed ethernet address (for now
47 * hardcoded, later from loader?)
48 * - resolve all XXX, left as reminders to shake out details later
49 * - Jumbo frame support
50 */
51
52#include <sys/cdefs.h>
53__FBSDID("$FreeBSD: head/sys/dev/altera/atse/if_atse.c 271679 2014-09-16 15:45:53Z bz $");
53__FBSDID("$FreeBSD: head/sys/dev/altera/atse/if_atse.c 271849 2014-09-19 03:51:26Z glebius $");
54
55#include "opt_device_polling.h"
56
57#include <sys/param.h>
58#include <sys/systm.h>
59#include <sys/kernel.h>
60#include <sys/bus.h>
61#include <sys/endian.h>

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1154{
1155
1156 ATSE_LOCK_ASSERT(sc);
1157
1158 if (sc->atse_watchdog_timer == 0 || --sc->atse_watchdog_timer > 0)
1159 return;
1160
1161 device_printf(sc->atse_dev, "watchdog timeout\n");
54
55#include "opt_device_polling.h"
56
57#include <sys/param.h>
58#include <sys/systm.h>
59#include <sys/kernel.h>
60#include <sys/bus.h>
61#include <sys/endian.h>

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1154{
1155
1156 ATSE_LOCK_ASSERT(sc);
1157
1158 if (sc->atse_watchdog_timer == 0 || --sc->atse_watchdog_timer > 0)
1159 return;
1160
1161 device_printf(sc->atse_dev, "watchdog timeout\n");
1162 sc->atse_ifp->if_oerrors++;
1162 if_inc_counter(sc->atse_ifp, IFCOUNTER_OERRORS, 1);
1163
1164 atse_intr_debug(sc, "poll");
1165
1166 sc->atse_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1167 atse_init_locked(sc);
1168
1169 atse_rx_locked(sc);
1170 if (!IFQ_DRV_IS_EMPTY(&sc->atse_ifp->if_snd))

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1258 */
1259 data = ATSE_RX_DATA_READ(sc);
1260 meta = ATSE_RX_META_READ(sc);
1261 if (meta & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) {
1262 /* XXX-BZ evaluate error. */
1263 atse_update_rx_err(sc, ((meta &
1264 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >>
1265 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
1163
1164 atse_intr_debug(sc, "poll");
1165
1166 sc->atse_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1167 atse_init_locked(sc);
1168
1169 atse_rx_locked(sc);
1170 if (!IFQ_DRV_IS_EMPTY(&sc->atse_ifp->if_snd))

--- 87 unchanged lines hidden (view full) ---

1258 */
1259 data = ATSE_RX_DATA_READ(sc);
1260 meta = ATSE_RX_META_READ(sc);
1261 if (meta & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) {
1262 /* XXX-BZ evaluate error. */
1263 atse_update_rx_err(sc, ((meta &
1264 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >>
1265 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
1266 ifp->if_ierrors++;
1266 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1267 sc->atse_rx_buf_len = 0;
1268 /*
1269 * Should still read till EOP or next SOP.
1270 *
1271 * XXX-BZ might also depend on
1272 * BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC
1273 */
1274 sc->atse_flags |= ATSE_FLAGS_ERROR;

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1287 */
1288 if (sc->atse_rx_buf_len != 0 &&
1289 (sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0)
1290 {
1291 device_printf(sc->atse_dev, "%s: SOP "
1292 "without empty buffer: %u\n",
1293 __func__, sc->atse_rx_buf_len);
1294 /* XXX-BZ any better counter? */
1267 sc->atse_rx_buf_len = 0;
1268 /*
1269 * Should still read till EOP or next SOP.
1270 *
1271 * XXX-BZ might also depend on
1272 * BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC
1273 */
1274 sc->atse_flags |= ATSE_FLAGS_ERROR;

--- 12 unchanged lines hidden (view full) ---

1287 */
1288 if (sc->atse_rx_buf_len != 0 &&
1289 (sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0)
1290 {
1291 device_printf(sc->atse_dev, "%s: SOP "
1292 "without empty buffer: %u\n",
1293 __func__, sc->atse_rx_buf_len);
1294 /* XXX-BZ any better counter? */
1295 ifp->if_ierrors++;
1295 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1296 }
1297
1298 if ((sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0)
1299 {
1300 sc->atse_flags |= ATSE_FLAGS_SOP_SEEN;
1301 sc->atse_rx_buf_len = 0;
1302 }
1303 }
1304#if 0 /* We had to read the data before we could access meta data. See above. */
1305 data = ATSE_RX_DATA_READ(sc);
1306#endif
1307 /* Make sure to not overflow the mbuf data size. */
1308 if (sc->atse_rx_buf_len >= sc->atse_rx_m->m_len -
1309 sizeof(data)) {
1310 /*
1311 * XXX-BZ Error. We need more mbufs and are
1312 * not setup for this yet.
1313 */
1296 }
1297
1298 if ((sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0)
1299 {
1300 sc->atse_flags |= ATSE_FLAGS_SOP_SEEN;
1301 sc->atse_rx_buf_len = 0;
1302 }
1303 }
1304#if 0 /* We had to read the data before we could access meta data. See above. */
1305 data = ATSE_RX_DATA_READ(sc);
1306#endif
1307 /* Make sure to not overflow the mbuf data size. */
1308 if (sc->atse_rx_buf_len >= sc->atse_rx_m->m_len -
1309 sizeof(data)) {
1310 /*
1311 * XXX-BZ Error. We need more mbufs and are
1312 * not setup for this yet.
1313 */
1314 ifp->if_ierrors++;
1314 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1315 sc->atse_flags |= ATSE_FLAGS_ERROR;
1316 }
1317 if ((sc->atse_flags & ATSE_FLAGS_ERROR) == 0)
1318 /*
1319 * MUST keep this bcopy as m_data after m_adj
1320 * for IP header aligment is on half-word
1321 * and not word alignment.
1322 */
1323 bcopy(&data, (uint8_t *)(sc->atse_rx_m->m_data +
1324 sc->atse_rx_buf_len), sizeof(data));
1325 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP) {
1326 uint8_t empty;
1327
1328 empty = (meta &
1329 A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK) >>
1330 A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT;
1331 sc->atse_rx_buf_len += (4 - empty);
1332
1315 sc->atse_flags |= ATSE_FLAGS_ERROR;
1316 }
1317 if ((sc->atse_flags & ATSE_FLAGS_ERROR) == 0)
1318 /*
1319 * MUST keep this bcopy as m_data after m_adj
1320 * for IP header aligment is on half-word
1321 * and not word alignment.
1322 */
1323 bcopy(&data, (uint8_t *)(sc->atse_rx_m->m_data +
1324 sc->atse_rx_buf_len), sizeof(data));
1325 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP) {
1326 uint8_t empty;
1327
1328 empty = (meta &
1329 A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK) >>
1330 A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT;
1331 sc->atse_rx_buf_len += (4 - empty);
1332
1333 ifp->if_ipackets++;
1333 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1334 rx_npkts++;
1335
1336 m = sc->atse_rx_m;
1337 m->m_pkthdr.len = m->m_len =
1338 sc->atse_rx_buf_len;
1339 sc->atse_rx_m = NULL;
1340
1341 sc->atse_rx_buf_len = 0;

--- 67 unchanged lines hidden (view full) ---

1409 atse_intr_debug(sc, "rx");
1410 rxe = ATSE_RX_EVENT_READ(sc);
1411 if (rxe & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1412 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1413 /* XXX-BZ ERROR HANDLING. */
1414 atse_update_rx_err(sc, ((rxe &
1415 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >>
1416 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
1334 rx_npkts++;
1335
1336 m = sc->atse_rx_m;
1337 m->m_pkthdr.len = m->m_len =
1338 sc->atse_rx_buf_len;
1339 sc->atse_rx_m = NULL;
1340
1341 sc->atse_rx_buf_len = 0;

--- 67 unchanged lines hidden (view full) ---

1409 atse_intr_debug(sc, "rx");
1410 rxe = ATSE_RX_EVENT_READ(sc);
1411 if (rxe & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1412 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1413 /* XXX-BZ ERROR HANDLING. */
1414 atse_update_rx_err(sc, ((rxe &
1415 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >>
1416 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
1417 ifp->if_ierrors++;
1417 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1418 }
1419
1420 /*
1421 * There is considerable subtlety in the race-free handling of rx
1422 * interrupts: we must disable interrupts whenever we manipulate the
1423 * FIFO to prevent further interrupts from firing before we are done;
1424 * we must clear the event after processing to prevent the event from
1425 * being immediately reposted due to data remaining; we must clear the

--- 38 unchanged lines hidden (view full) ---

1464#endif
1465
1466 /* XXX-BZ build histogram. */
1467 atse_intr_debug(sc, "tx");
1468 txe = ATSE_TX_EVENT_READ(sc);
1469 if (txe & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1470 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1471 /* XXX-BZ ERROR HANDLING. */
1418 }
1419
1420 /*
1421 * There is considerable subtlety in the race-free handling of rx
1422 * interrupts: we must disable interrupts whenever we manipulate the
1423 * FIFO to prevent further interrupts from firing before we are done;
1424 * we must clear the event after processing to prevent the event from
1425 * being immediately reposted due to data remaining; we must clear the

--- 38 unchanged lines hidden (view full) ---

1464#endif
1465
1466 /* XXX-BZ build histogram. */
1467 atse_intr_debug(sc, "tx");
1468 txe = ATSE_TX_EVENT_READ(sc);
1469 if (txe & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1470 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1471 /* XXX-BZ ERROR HANDLING. */
1472 ifp->if_oerrors++;
1472 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1473 }
1474
1475 /*
1476 * There is also considerable subtlety in the race-free handling of
1477 * tx interrupts: all processing occurs with interrupts disabled to
1478 * prevent spurious refiring while transmit is in progress (which
1479 * could occur if the FIFO drains while sending -- quite likely); we
1480 * must not clear the event mask until after we've sent, also to

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1522 tx = ATSE_TX_EVENT_READ(sc);
1523
1524 if (rx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1525 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1526 /* XXX-BZ ERROR HANDLING. */
1527 atse_update_rx_err(sc, ((rx &
1528 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >>
1529 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
1473 }
1474
1475 /*
1476 * There is also considerable subtlety in the race-free handling of
1477 * tx interrupts: all processing occurs with interrupts disabled to
1478 * prevent spurious refiring while transmit is in progress (which
1479 * could occur if the FIFO drains while sending -- quite likely); we
1480 * must not clear the event mask until after we've sent, also to

--- 41 unchanged lines hidden (view full) ---

1522 tx = ATSE_TX_EVENT_READ(sc);
1523
1524 if (rx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1525 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1526 /* XXX-BZ ERROR HANDLING. */
1527 atse_update_rx_err(sc, ((rx &
1528 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >>
1529 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
1530 ifp->if_ierrors++;
1530 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1531 }
1532 if (tx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1533 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1534 /* XXX-BZ ERROR HANDLING. */
1531 }
1532 if (tx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW|
1533 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
1534 /* XXX-BZ ERROR HANDLING. */
1535 ifp->if_oerrors++;
1535 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1536 }
1537 if (ATSE_TX_READ_FILL_LEVEL(sc) == 0)
1538 sc->atse_watchdog_timer = 0;
1539
1540#if 0
1541 if (/* Severe error; if only we could find out. */) {
1542 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1543 atse_init_locked(sc);

--- 548 unchanged lines hidden --- 		1536 }
1537 if (ATSE_TX_READ_FILL_LEVEL(sc) == 0)
1538 sc->atse_watchdog_timer = 0;
1539
1540#if 0
1541 if (/* Severe error; if only we could find out. */) {
1542 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1543 atse_init_locked(sc);

--- 548 unchanged lines hidden ---