1/*-
2 * Copyright (c) 1999 Luoqi Chen.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/sys/dev/aic/aicvar.h 170872 2007-06-17 05:55:54Z scottl $
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| 26 * $FreeBSD: head/sys/dev/aic/aicvar.h 241591 2012-10-15 16:09:59Z jhb $ |
27 */
28
29struct aic_transinfo {
30 u_int8_t period;
31 u_int8_t offset;
32};
33
34struct aic_tinfo {
35 u_int16_t lubusy;
36 u_int8_t flags;
37 u_int8_t scsirate;
38 struct aic_transinfo current;
39 struct aic_transinfo goal;
40 struct aic_transinfo user;
41};
42
43#define TINFO_DISC_ENB 0x01
44#define TINFO_TAG_ENB 0x02
45#define TINFO_SDTR_NEGO 0x04
46#define TINFO_SDTR_SENT 0x08
47
48struct aic_scb {
49 union ccb *ccb;
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50 SLIST_ENTRY(aic_scb) link;
51 struct callout timer; |
52 u_int8_t flags;
53 u_int8_t tag;
54 u_int8_t target;
55 u_int8_t lun;
56 u_int8_t status;
57 u_int8_t cmd_len;
58 u_int8_t *cmd_ptr;
59 u_int32_t data_len;
60 u_int8_t *data_ptr;
61};
62
63#define ccb_scb_ptr spriv_ptr0
64#define ccb_aic_ptr spriv_ptr1
65
66#define SCB_ACTIVE 0x01
67#define SCB_DISCONNECTED 0x02
68#define SCB_DEVICE_RESET 0x04
69#define SCB_SENSE 0x08
70
71enum { AIC6260, AIC6360, AIC6370, GM82C700 };
72
73struct aic_softc {
74 device_t dev;
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73 int unit;
74 bus_space_tag_t tag;
75 bus_space_handle_t bsh;
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75 struct mtx lock;
76 struct resource *res; |
77 bus_dma_tag_t dmat;
78
79 struct cam_sim *sim;
80 struct cam_path *path;
81 TAILQ_HEAD(,ccb_hdr) pending_ccbs, nexus_ccbs;
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| 82 SLIST_HEAD(,aic_scb) free_scbs; |
83 struct aic_scb *nexus;
84
85 u_int32_t flags;
86 u_int8_t initiator;
87 u_int8_t state;
88 u_int8_t target;
89 u_int8_t lun;
90 u_int8_t prev_phase;
91
92 u_int8_t msg_outq;
93 u_int8_t msg_sent;
94 int msg_len;
95 char msg_buf[8];
96
97 struct aic_tinfo tinfo[8];
98 struct aic_scb scbs[256];
99
100 int min_period;
101 int max_period;
102 int chip_type;
103};
104
105#define AIC_DISC_ENABLE 0x01
106#define AIC_DMA_ENABLE 0x02
107#define AIC_PARITY_ENABLE 0x04
108#define AIC_DWIO_ENABLE 0x08
109#define AIC_RESOURCE_SHORTAGE 0x10
110#define AIC_DROP_MSGIN 0x20
111#define AIC_BUSFREE_OK 0x40
112#define AIC_FAST_ENABLE 0x80
113
114#define AIC_IDLE 0x00
115#define AIC_SELECTING 0x01
116#define AIC_RESELECTED 0x02
117#define AIC_RECONNECTING 0x03
118#define AIC_HASNEXUS 0x04
119
120#define AIC_MSG_IDENTIFY 0x01
121#define AIC_MSG_TAG_Q 0x02
122#define AIC_MSG_SDTR 0x04
123#define AIC_MSG_WDTR 0x08
124#define AIC_MSG_MSGBUF 0x80
125
126#define AIC_SYNC_PERIOD (200 / 4)
127#define AIC_FAST_SYNC_PERIOD (100 / 4)
128#define AIC_MIN_SYNC_PERIOD 112
129#define AIC_SYNC_OFFSET 8
130
131#define aic_inb(aic, port) \
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130 bus_space_read_1((aic)->tag, (aic)->bsh, (port))
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| 132 bus_read_1((aic)->res, (port)) |
133
134#define aic_outb(aic, port, value) \
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133 bus_space_write_1((aic)->tag, (aic)->bsh, (port), (value))
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| 135 bus_write_1((aic)->res, (port), (value)) |
136
137#define aic_insb(aic, port, addr, count) \
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136 bus_space_read_multi_1((aic)->tag, (aic)->bsh, (port), (addr), (count))
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| 138 bus_read_multi_1((aic)->res, (port), (addr), (count)) |
139
140#define aic_outsb(aic, port, addr, count) \
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139 bus_space_write_multi_1((aic)->tag, (aic)->bsh, (port), (addr), (count))
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| 141 bus_write_multi_1((aic)->res, (port), (addr), (count)) |
142
143#define aic_insw(aic, port, addr, count) \
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142 bus_space_read_multi_2((aic)->tag, (aic)->bsh, (port), \
143 (u_int16_t *)(addr), (count))
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| 144 bus_read_multi_2((aic)->res, (port), (u_int16_t *)(addr), (count)) |
145
146#define aic_outsw(aic, port, addr, count) \
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146 bus_space_write_multi_2((aic)->tag, (aic)->bsh, (port), \
147 (u_int16_t *)(addr), (count))
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| 147 bus_write_multi_2((aic)->res, (port), (u_int16_t *)(addr), (count)) |
148
149#define aic_insl(aic, port, addr, count) \
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150 bus_space_read_multi_4((aic)->tag, (aic)->bsh, (port), \
151 (u_int32_t *)(addr), (count))
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| 150 bus_read_multi_4((aic)->res, (port), (u_int32_t *)(addr), (count)) |
151
152#define aic_outsl(aic, port, addr, count) \
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154 bus_space_write_multi_4((aic)->tag, (aic)->bsh, (port), \
155 (u_int32_t *)(addr), (count))
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| 153 bus_write_multi_4((aic)->res, (port), (u_int32_t *)(addr), (count)) |
154
155extern int aic_probe(struct aic_softc *);
156extern int aic_attach(struct aic_softc *);
157extern int aic_detach(struct aic_softc *);
158extern void aic_intr(void *);
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