1/*-
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/agp/agp_nvidia.c 127815 2004-04-03 22:55:12Z njl $
27 */
28
29/*
30 * Written using information gleaned from the
31 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
32 */
33
34#include "opt_bus.h"
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/kernel.h>
40#include <sys/bus.h>
41#include <sys/lock.h>
42
43#if __FreeBSD_version < 500000
44#include "opt_pci.h"
45#endif
46
47#if __FreeBSD_version > 500000
48#include <sys/lockmgr.h>
49#include <sys/mutex.h>
50#include <sys/proc.h>
51#endif
52
53#include <dev/pci/pcivar.h>
54#include <dev/pci/pcireg.h>
55#include <pci/agppriv.h>
56#include <pci/agpreg.h>
57
58#include <vm/vm.h>
59#include <vm/vm_object.h>
60#include <vm/pmap.h>
61
62#include <machine/bus.h>
63#include <machine/resource.h>
64#include <sys/rman.h>
65
66#define NVIDIA_VENDORID 0x10de
67#define NVIDIA_DEVICEID_NFORCE 0x01a4
68#define NVIDIA_DEVICEID_NFORCE2 0x01e0
69
70struct agp_nvidia_softc {
71 struct agp_softc agp;
72 u_int32_t initial_aperture; /* aperture size at startup */
73 struct agp_gatt * gatt;
74
75 device_t dev; /* AGP Controller */
76 device_t mc1_dev; /* Memory Controller */
77 device_t mc2_dev; /* Memory Controller */
78 device_t bdev; /* Bridge */
79
80 u_int32_t wbc_mask;
81 int num_dirs;
82 int num_active_entries;
83 off_t pg_offset;
84};
85
86static const char * agp_nvidia_match (device_t dev);
87static int agp_nvidia_probe (device_t);
88static int agp_nvidia_attach (device_t);
89static int agp_nvidia_detach (device_t);
90static u_int32_t agp_nvidia_get_aperture (device_t);
91static int agp_nvidia_set_aperture (device_t, u_int32_t);
92static int agp_nvidia_bind_page (device_t, int, vm_offset_t);
93static int agp_nvidia_unbind_page (device_t, int);
94
95static int nvidia_init_iorr (u_int32_t, u_int32_t);
96
97static const char *
98agp_nvidia_match (device_t dev)
99{
100 if (pci_get_class(dev) != PCIC_BRIDGE ||
101 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
102 pci_get_vendor(dev) != NVIDIA_VENDORID)
103 return (NULL);
104
105 switch (pci_get_device(dev)) {
106 case NVIDIA_DEVICEID_NFORCE:
107 return ("NVIDIA nForce AGP Controller");
108 case NVIDIA_DEVICEID_NFORCE2:
109 return ("NVIDIA nForce2 AGP Controller");
110 }
111 return ("NVIDIA Generic AGP Controller");
112}
113
114static int
115agp_nvidia_probe (device_t dev)
116{
117 const char *desc;
118
119 if (resource_disabled("agp", device_get_unit(dev)))
120 return (ENXIO);
121 desc = agp_nvidia_match(dev);
122 if (desc) {
123 device_verbose(dev);
124 device_set_desc(dev, desc);
125 return (0);
126 }
127 return (ENXIO);
128}
129
130static int
131agp_nvidia_attach (device_t dev)
132{
133 struct agp_nvidia_softc *sc = device_get_softc(dev);
134 struct agp_gatt *gatt;
135 u_int32_t apbase;
136 u_int32_t aplimit;
137 u_int32_t temp;
138 int size;
139 int i;
140 int error;
141
142 switch (pci_get_device(dev)) {
143 case NVIDIA_DEVICEID_NFORCE:
144 sc->wbc_mask = 0x00010000;
145 break;
146 case NVIDIA_DEVICEID_NFORCE2:
147 sc->wbc_mask = 0x80000000;
148 break;
149 default:
150 sc->wbc_mask = 0;
151 break;
152 }
153
154 /* AGP Controller */
155 sc->dev = dev;
156
157 /* Memory Controller 1 */
158 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
159 if (sc->mc1_dev == NULL) {
160 device_printf(dev,
161 "Unable to find NVIDIA Memory Controller 1.\n");
162 return (ENODEV);
163 }
164
165 /* Memory Controller 2 */
166 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
167 if (sc->mc2_dev == NULL) {
168 device_printf(dev,
169 "Unable to find NVIDIA Memory Controller 2.\n");
170 return (ENODEV);
171 }
172
173 /* AGP Host to PCI Bridge */
174 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
175 if (sc->bdev == NULL) {
176 device_printf(dev,
177 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
178 return (ENODEV);
179 }
180
181 error = agp_generic_attach(dev);
182 if (error)
183 return (error);
184
185 sc->initial_aperture = AGP_GET_APERTURE(dev);
186
187 for (;;) {
188 gatt = agp_alloc_gatt(dev);
189 if (gatt)
190 break;
191 /*
192 * Probably contigmalloc failure. Try reducing the
193 * aperture so that the gatt size reduces.
194 */
195 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
196 goto fail;
197 }
198 sc->gatt = gatt;
199
200 apbase = rman_get_start(sc->agp.as_aperture);
201 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
202 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
204 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
206
207 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
208 if (error) {
209 device_printf(dev, "Failed to setup IORRs\n");
210 goto fail;
211 }
212
213 /* directory size is 64k */
214 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
215 sc->num_dirs = size / 64;
216 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
217 sc->pg_offset = 0;
218 if (sc->num_dirs == 0) {
219 sc->num_dirs = 1;
220 sc->num_active_entries /= (64 / size);
221 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
222 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
223 }
224
225 /* (G)ATT Base Address */
226 for (i = 0; i < 8; i++) {
227 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
228 (sc->gatt->ag_physical +
229 (i % sc->num_dirs) * 64 * 1024),
230 4);
231 }
232
233 /* GTLB Control */
234 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
235 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
236
237 /* GART Control */
238 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
239 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
240
241 return (0);
242fail:
243 agp_generic_detach(dev);
244 return (ENOMEM);
245}
246
247static int
248agp_nvidia_detach (device_t dev)
249{
250 struct agp_nvidia_softc *sc = device_get_softc(dev);
251 int error;
252 u_int32_t temp;
253
254 error = agp_generic_detach(dev);
255 if (error)
256 return (error);
257
258 /* GART Control */
259 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
260 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
261
262 /* GTLB Control */
263 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
264 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
265
266 /* Put the aperture back the way it started. */
267 AGP_SET_APERTURE(dev, sc->initial_aperture);
268
269 /* restore iorr for previous aperture size */
270 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
271 sc->initial_aperture);
272
273 agp_free_gatt(sc->gatt);
274
275 return (0);
276}
277
278static u_int32_t
279agp_nvidia_get_aperture(device_t dev)
280{
281 u_int8_t key;
282
283 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
284 return (1 << (24 + (key ? key : 5)));
285}
286
287static int
288agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
289{
290 u_int8_t val;
291 u_int8_t key;
292
293 switch (aperture) {
294 case (512 * 1024 * 1024): key = 0; break;
295 case (256 * 1024 * 1024): key = 8; break;
296 case (128 * 1024 * 1024): key = 12; break;
297 case (64 * 1024 * 1024): key = 14; break;
298 case (32 * 1024 * 1024): key = 15; break;
299 default:
300 device_printf(dev, "Invalid aperture size (%dMb)\n",
301 aperture / 1024 / 1024);
302 return (EINVAL);
303 }
304 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
305 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
306
307 return (0);
308}
309
310static int
311agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
312{
313 struct agp_nvidia_softc *sc = device_get_softc(dev);
314 u_int32_t index;
315
316 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
317 return (EINVAL);
318
319 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
320 sc->gatt->ag_virtual[index] = physical;
321
322 return (0);
323}
324
325static int
326agp_nvidia_unbind_page(device_t dev, int offset)
327{
328 struct agp_nvidia_softc *sc = device_get_softc(dev);
329 u_int32_t index;
330
331 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
332 return (EINVAL);
333
334 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
335 sc->gatt->ag_virtual[index] = 0;
336
337 return (0);
338}
339
340static int
341agp_nvidia_flush_tlb (device_t dev, int offset)
342{
343 struct agp_nvidia_softc *sc;
344 u_int32_t wbc_reg, temp;
345 int i;
346
347 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
348
349 if (sc->wbc_mask) {
350 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
351 wbc_reg |= sc->wbc_mask;
352 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
353
354 /* Wait no more than 3 seconds. */
355 for (i = 0; i < 3000; i++) {
356 wbc_reg = pci_read_config(sc->mc1_dev,
357 AGP_NVIDIA_1_WBC, 4);
358 if ((sc->wbc_mask & wbc_reg) == 0)
359 break;
360 else
361 DELAY(1000);
362 }
363 if (i == 3000)
364 device_printf(dev,
365 "TLB flush took more than 3 seconds.\n");
366 }
367
368 /* Flush TLB entries. */
369 for(i = 0; i < 32 + 1; i++)
370 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
371 for(i = 0; i < 32 + 1; i++)
372 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
373
374 return (0);
375}
376
377#define SYSCFG 0xC0010010
378#define IORR_BASE0 0xC0010016
379#define IORR_MASK0 0xC0010017
380#define AMD_K7_NUM_IORR 2
381
382static int
383nvidia_init_iorr(u_int32_t addr, u_int32_t size)
384{
385 quad_t base, mask, sys;
386 u_int32_t iorr_addr, free_iorr_addr;
387
388 /* Find the iorr that is already used for the addr */
389 /* If not found, determine the uppermost available iorr */
390 free_iorr_addr = AMD_K7_NUM_IORR;
391 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
392 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
393 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
394
395 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
396 break;
397
398 if ((mask & 0x00000800ULL) == 0)
399 free_iorr_addr = iorr_addr;
400 }
401
402 if (iorr_addr >= AMD_K7_NUM_IORR) {
403 iorr_addr = free_iorr_addr;
404 if (iorr_addr >= AMD_K7_NUM_IORR)
405 return (EINVAL);
406 }
407
408 base = (addr & ~0xfff) | 0x18;
409 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
410 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
411 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
412
413 sys = rdmsr(SYSCFG);
414 sys |= 0x00100000ULL;
415 wrmsr(SYSCFG, sys);
416
417 return (0);
418}
419
420static device_method_t agp_nvidia_methods[] = {
421 /* Device interface */
422 DEVMETHOD(device_probe, agp_nvidia_probe),
423 DEVMETHOD(device_attach, agp_nvidia_attach),
424 DEVMETHOD(device_detach, agp_nvidia_detach),
425 DEVMETHOD(device_shutdown, bus_generic_shutdown),
426 DEVMETHOD(device_suspend, bus_generic_suspend),
427 DEVMETHOD(device_resume, bus_generic_resume),
428
429 /* AGP interface */
430 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
431 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
432 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
433 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
434 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
435
436 DEVMETHOD(agp_enable, agp_generic_enable),
437 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
438 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
439 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
440 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
441
442 { 0, 0 }
443};
444
445static driver_t agp_nvidia_driver = {
446 "agp",
447 agp_nvidia_methods,
448 sizeof(struct agp_nvidia_softc),
449};
450
451static devclass_t agp_devclass;
452
453DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
454MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
455MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/agp/agp_nvidia.c 127815 2004-04-03 22:55:12Z njl $
27 */
28
29/*
30 * Written using information gleaned from the
31 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
32 */
33
34#include "opt_bus.h"
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/kernel.h>
40#include <sys/bus.h>
41#include <sys/lock.h>
42
43#if __FreeBSD_version < 500000
44#include "opt_pci.h"
45#endif
46
47#if __FreeBSD_version > 500000
48#include <sys/lockmgr.h>
49#include <sys/mutex.h>
50#include <sys/proc.h>
51#endif
52
53#include <dev/pci/pcivar.h>
54#include <dev/pci/pcireg.h>
55#include <pci/agppriv.h>
56#include <pci/agpreg.h>
57
58#include <vm/vm.h>
59#include <vm/vm_object.h>
60#include <vm/pmap.h>
61
62#include <machine/bus.h>
63#include <machine/resource.h>
64#include <sys/rman.h>
65
66#define NVIDIA_VENDORID 0x10de
67#define NVIDIA_DEVICEID_NFORCE 0x01a4
68#define NVIDIA_DEVICEID_NFORCE2 0x01e0
69
70struct agp_nvidia_softc {
71 struct agp_softc agp;
72 u_int32_t initial_aperture; /* aperture size at startup */
73 struct agp_gatt * gatt;
74
75 device_t dev; /* AGP Controller */
76 device_t mc1_dev; /* Memory Controller */
77 device_t mc2_dev; /* Memory Controller */
78 device_t bdev; /* Bridge */
79
80 u_int32_t wbc_mask;
81 int num_dirs;
82 int num_active_entries;
83 off_t pg_offset;
84};
85
86static const char * agp_nvidia_match (device_t dev);
87static int agp_nvidia_probe (device_t);
88static int agp_nvidia_attach (device_t);
89static int agp_nvidia_detach (device_t);
90static u_int32_t agp_nvidia_get_aperture (device_t);
91static int agp_nvidia_set_aperture (device_t, u_int32_t);
92static int agp_nvidia_bind_page (device_t, int, vm_offset_t);
93static int agp_nvidia_unbind_page (device_t, int);
94
95static int nvidia_init_iorr (u_int32_t, u_int32_t);
96
97static const char *
98agp_nvidia_match (device_t dev)
99{
100 if (pci_get_class(dev) != PCIC_BRIDGE ||
101 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
102 pci_get_vendor(dev) != NVIDIA_VENDORID)
103 return (NULL);
104
105 switch (pci_get_device(dev)) {
106 case NVIDIA_DEVICEID_NFORCE:
107 return ("NVIDIA nForce AGP Controller");
108 case NVIDIA_DEVICEID_NFORCE2:
109 return ("NVIDIA nForce2 AGP Controller");
110 }
111 return ("NVIDIA Generic AGP Controller");
112}
113
114static int
115agp_nvidia_probe (device_t dev)
116{
117 const char *desc;
118
119 if (resource_disabled("agp", device_get_unit(dev)))
120 return (ENXIO);
121 desc = agp_nvidia_match(dev);
122 if (desc) {
123 device_verbose(dev);
124 device_set_desc(dev, desc);
125 return (0);
126 }
127 return (ENXIO);
128}
129
130static int
131agp_nvidia_attach (device_t dev)
132{
133 struct agp_nvidia_softc *sc = device_get_softc(dev);
134 struct agp_gatt *gatt;
135 u_int32_t apbase;
136 u_int32_t aplimit;
137 u_int32_t temp;
138 int size;
139 int i;
140 int error;
141
142 switch (pci_get_device(dev)) {
143 case NVIDIA_DEVICEID_NFORCE:
144 sc->wbc_mask = 0x00010000;
145 break;
146 case NVIDIA_DEVICEID_NFORCE2:
147 sc->wbc_mask = 0x80000000;
148 break;
149 default:
150 sc->wbc_mask = 0;
151 break;
152 }
153
154 /* AGP Controller */
155 sc->dev = dev;
156
157 /* Memory Controller 1 */
158 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
159 if (sc->mc1_dev == NULL) {
160 device_printf(dev,
161 "Unable to find NVIDIA Memory Controller 1.\n");
162 return (ENODEV);
163 }
164
165 /* Memory Controller 2 */
166 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
167 if (sc->mc2_dev == NULL) {
168 device_printf(dev,
169 "Unable to find NVIDIA Memory Controller 2.\n");
170 return (ENODEV);
171 }
172
173 /* AGP Host to PCI Bridge */
174 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
175 if (sc->bdev == NULL) {
176 device_printf(dev,
177 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
178 return (ENODEV);
179 }
180
181 error = agp_generic_attach(dev);
182 if (error)
183 return (error);
184
185 sc->initial_aperture = AGP_GET_APERTURE(dev);
186
187 for (;;) {
188 gatt = agp_alloc_gatt(dev);
189 if (gatt)
190 break;
191 /*
192 * Probably contigmalloc failure. Try reducing the
193 * aperture so that the gatt size reduces.
194 */
195 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
196 goto fail;
197 }
198 sc->gatt = gatt;
199
200 apbase = rman_get_start(sc->agp.as_aperture);
201 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
202 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
204 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
206
207 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
208 if (error) {
209 device_printf(dev, "Failed to setup IORRs\n");
210 goto fail;
211 }
212
213 /* directory size is 64k */
214 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
215 sc->num_dirs = size / 64;
216 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
217 sc->pg_offset = 0;
218 if (sc->num_dirs == 0) {
219 sc->num_dirs = 1;
220 sc->num_active_entries /= (64 / size);
221 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
222 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
223 }
224
225 /* (G)ATT Base Address */
226 for (i = 0; i < 8; i++) {
227 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
228 (sc->gatt->ag_physical +
229 (i % sc->num_dirs) * 64 * 1024),
230 4);
231 }
232
233 /* GTLB Control */
234 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
235 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
236
237 /* GART Control */
238 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
239 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
240
241 return (0);
242fail:
243 agp_generic_detach(dev);
244 return (ENOMEM);
245}
246
247static int
248agp_nvidia_detach (device_t dev)
249{
250 struct agp_nvidia_softc *sc = device_get_softc(dev);
251 int error;
252 u_int32_t temp;
253
254 error = agp_generic_detach(dev);
255 if (error)
256 return (error);
257
258 /* GART Control */
259 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
260 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
261
262 /* GTLB Control */
263 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
264 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
265
266 /* Put the aperture back the way it started. */
267 AGP_SET_APERTURE(dev, sc->initial_aperture);
268
269 /* restore iorr for previous aperture size */
270 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
271 sc->initial_aperture);
272
273 agp_free_gatt(sc->gatt);
274
275 return (0);
276}
277
278static u_int32_t
279agp_nvidia_get_aperture(device_t dev)
280{
281 u_int8_t key;
282
283 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
284 return (1 << (24 + (key ? key : 5)));
285}
286
287static int
288agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
289{
290 u_int8_t val;
291 u_int8_t key;
292
293 switch (aperture) {
294 case (512 * 1024 * 1024): key = 0; break;
295 case (256 * 1024 * 1024): key = 8; break;
296 case (128 * 1024 * 1024): key = 12; break;
297 case (64 * 1024 * 1024): key = 14; break;
298 case (32 * 1024 * 1024): key = 15; break;
299 default:
300 device_printf(dev, "Invalid aperture size (%dMb)\n",
301 aperture / 1024 / 1024);
302 return (EINVAL);
303 }
304 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
305 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
306
307 return (0);
308}
309
310static int
311agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
312{
313 struct agp_nvidia_softc *sc = device_get_softc(dev);
314 u_int32_t index;
315
316 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
317 return (EINVAL);
318
319 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
320 sc->gatt->ag_virtual[index] = physical;
321
322 return (0);
323}
324
325static int
326agp_nvidia_unbind_page(device_t dev, int offset)
327{
328 struct agp_nvidia_softc *sc = device_get_softc(dev);
329 u_int32_t index;
330
331 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
332 return (EINVAL);
333
334 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
335 sc->gatt->ag_virtual[index] = 0;
336
337 return (0);
338}
339
340static int
341agp_nvidia_flush_tlb (device_t dev, int offset)
342{
343 struct agp_nvidia_softc *sc;
344 u_int32_t wbc_reg, temp;
345 int i;
346
347 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
348
349 if (sc->wbc_mask) {
350 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
351 wbc_reg |= sc->wbc_mask;
352 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
353
354 /* Wait no more than 3 seconds. */
355 for (i = 0; i < 3000; i++) {
356 wbc_reg = pci_read_config(sc->mc1_dev,
357 AGP_NVIDIA_1_WBC, 4);
358 if ((sc->wbc_mask & wbc_reg) == 0)
359 break;
360 else
361 DELAY(1000);
362 }
363 if (i == 3000)
364 device_printf(dev,
365 "TLB flush took more than 3 seconds.\n");
366 }
367
368 /* Flush TLB entries. */
369 for(i = 0; i < 32 + 1; i++)
370 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
371 for(i = 0; i < 32 + 1; i++)
372 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
373
374 return (0);
375}
376
377#define SYSCFG 0xC0010010
378#define IORR_BASE0 0xC0010016
379#define IORR_MASK0 0xC0010017
380#define AMD_K7_NUM_IORR 2
381
382static int
383nvidia_init_iorr(u_int32_t addr, u_int32_t size)
384{
385 quad_t base, mask, sys;
386 u_int32_t iorr_addr, free_iorr_addr;
387
388 /* Find the iorr that is already used for the addr */
389 /* If not found, determine the uppermost available iorr */
390 free_iorr_addr = AMD_K7_NUM_IORR;
391 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
392 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
393 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
394
395 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
396 break;
397
398 if ((mask & 0x00000800ULL) == 0)
399 free_iorr_addr = iorr_addr;
400 }
401
402 if (iorr_addr >= AMD_K7_NUM_IORR) {
403 iorr_addr = free_iorr_addr;
404 if (iorr_addr >= AMD_K7_NUM_IORR)
405 return (EINVAL);
406 }
407
408 base = (addr & ~0xfff) | 0x18;
409 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
410 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
411 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
412
413 sys = rdmsr(SYSCFG);
414 sys |= 0x00100000ULL;
415 wrmsr(SYSCFG, sys);
416
417 return (0);
418}
419
420static device_method_t agp_nvidia_methods[] = {
421 /* Device interface */
422 DEVMETHOD(device_probe, agp_nvidia_probe),
423 DEVMETHOD(device_attach, agp_nvidia_attach),
424 DEVMETHOD(device_detach, agp_nvidia_detach),
425 DEVMETHOD(device_shutdown, bus_generic_shutdown),
426 DEVMETHOD(device_suspend, bus_generic_suspend),
427 DEVMETHOD(device_resume, bus_generic_resume),
428
429 /* AGP interface */
430 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
431 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
432 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
433 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
434 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
435
436 DEVMETHOD(agp_enable, agp_generic_enable),
437 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
438 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
439 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
440 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
441
442 { 0, 0 }
443};
444
445static driver_t agp_nvidia_driver = {
446 "agp",
447 agp_nvidia_methods,
448 sizeof(struct agp_nvidia_softc),
449};
450
451static devclass_t agp_devclass;
452
453DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
454MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
455MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);