1/*
2 * Low level routines for Second Generation
3 * Advanced Systems Inc. SCSI controllers chips
4 *
5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/advansys/adwlib.c 57679 2000-03-02 00:08:35Z gibbs $
33 */
34/*
35 * Ported from:
36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
37 *
38 * Copyright (c) 1995-1998 Advanced System Products, Inc.
39 * All Rights Reserved.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that redistributions of source
43 * code retain the above copyright notice and this comment without
44 * modification.
45 */
46
47#include <sys/param.h>
48#include <sys/systm.h>
49#include <sys/bus.h>
50
51#include <machine/bus_pio.h>
52#include <machine/bus_memio.h>
53#include <machine/bus.h>
54#include <machine/clock.h>
55
56#include <cam/cam.h>
57#include <cam/scsi/scsi_all.h>
58
59#include <dev/advansys/adwlib.h>
60
61const struct adw_eeprom adw_asc3550_default_eeprom =
62{
63 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
64 0x0000, /* cfg_msw */
65 0xFFFF, /* disc_enable */
66 0xFFFF, /* wdtr_able */
67 { 0xFFFF }, /* sdtr_able */
68 0xFFFF, /* start_motor */
69 0xFFFF, /* tagqng_able */
70 0xFFFF, /* bios_scan */
71 0, /* scam_tolerant */
72 7, /* adapter_scsi_id */
73 0, /* bios_boot_delay */
74 3, /* scsi_reset_delay */
75 0, /* bios_id_lun */
76 0, /* termination */
77 0, /* reserved1 */
78 0xFFE7, /* bios_ctrl */
79 { 0xFFFF }, /* ultra_able */
80 { 0 }, /* reserved2 */
81 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
82 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
83 0, /* dvc_cntl */
84 { 0 }, /* bug_fix */
85 { 0, 0, 0 }, /* serial_number */
86 0, /* check_sum */
87 { /* oem_name[16] */
88 0, 0, 0, 0, 0, 0, 0, 0,
89 0, 0, 0, 0, 0, 0, 0, 0
90 },
91 0, /* dvc_err_code */
92 0, /* adv_err_code */
93 0, /* adv_err_addr */
94 0, /* saved_dvc_err_code */
95 0, /* saved_adv_err_code */
96 0 /* saved_adv_err_addr */
97};
98
99const struct adw_eeprom adw_asc38C0800_default_eeprom =
100{
101 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
102 0x0000, /* 01 cfg_msw */
103 0xFFFF, /* 02 disc_enable */
104 0xFFFF, /* 03 wdtr_able */
105 { 0x4444 }, /* 04 sdtr_speed1 */
106 0xFFFF, /* 05 start_motor */
107 0xFFFF, /* 06 tagqng_able */
108 0xFFFF, /* 07 bios_scan */
109 0, /* 08 scam_tolerant */
110 7, /* 09 adapter_scsi_id */
111 0, /* bios_boot_delay */
112 3, /* 10 scsi_reset_delay */
113 0, /* bios_id_lun */
114 0, /* 11 termination_se */
115 0, /* termination_lvd */
116 0xFFE7, /* 12 bios_ctrl */
117 { 0x4444 }, /* 13 sdtr_speed2 */
118 { 0x4444 }, /* 14 sdtr_speed3 */
119 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
120 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
121 0, /* 16 dvc_cntl */
122 { 0x4444 } , /* 17 sdtr_speed4 */
123 { 0, 0, 0 }, /* 18-20 serial_number */
124 0, /* 21 check_sum */
125 { /* 22-29 oem_name[16] */
126 0, 0, 0, 0, 0, 0, 0, 0,
127 0, 0, 0, 0, 0, 0, 0, 0
128 },
129 0, /* 30 dvc_err_code */
130 0, /* 31 adv_err_code */
131 0, /* 32 adv_err_addr */
132 0, /* 33 saved_dvc_err_code */
133 0, /* 34 saved_adv_err_code */
134 0, /* 35 saved_adv_err_addr */
135 { /* 36 - 55 reserved */
136 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
137 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
138 },
139 0, /* 56 cisptr_lsw */
140 0, /* 57 cisprt_msw */
141 /* 58-59 sub-id */
142 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
143};
144
145#define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
146#define ADW_MC_SDTR_OFFSET_ULTRA2 1
147#define ADW_MC_SDTR_OFFSET_ULTRA 2
148const struct adw_syncrate adw_syncrates[] =
149{
150 /* mc_sdtr period rate */
151 { ADW_MC_SDTR_80, 9, "80.0" },
152 { ADW_MC_SDTR_40, 10, "40.0" },
153 { ADW_MC_SDTR_20, 12, "20.0" },
154 { ADW_MC_SDTR_10, 25, "10.0" },
155 { ADW_MC_SDTR_5, 50, "5.0" },
156 { ADW_MC_SDTR_ASYNC, 0, "async" }
157};
158
159const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
160
161static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
162static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
163 u_int data);
164static void adw_eeprom_wait(struct adw_softc *adw);
165
166int
167adw_find_signature(struct adw_softc *adw)
168{
169 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
170 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
171 return (1);
172 return (0);
173}
174
175/*
176 * Reset Chip.
177 */
178void
179adw_reset_chip(struct adw_softc *adw)
180{
181 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
182 DELAY(1000 * 100);
183 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
184
185 /*
186 * Initialize Chip registers.
187 */
188 adw_outw(adw, ADW_SCSI_CFG1,
189 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
190}
191
192/*
193 * Reset the SCSI bus.
194 */
195int
196adw_reset_bus(struct adw_softc *adw)
197{
198 adw_idle_cmd_status_t status;
199
200 status =
201 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
202 if (status != ADW_IDLE_CMD_SUCCESS) {
203 xpt_print_path(adw->path);
204 printf("Bus Reset start attempt failed\n");
205 return (1);
206 }
207 DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
208 status =
209 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
210 if (status != ADW_IDLE_CMD_SUCCESS) {
211 xpt_print_path(adw->path);
212 printf("Bus Reset end attempt failed\n");
213 return (1);
214 }
215 return (0);
216}
217
218/*
219 * Read the specified EEPROM location
220 */
221static u_int16_t
222adw_eeprom_read_16(struct adw_softc *adw, int addr)
223{
224 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
225 adw_eeprom_wait(adw);
226 return (adw_inw(adw, ADW_EEP_DATA));
227}
228
229static void
230adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
231{
232 adw_outw(adw, ADW_EEP_DATA, data);
233 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
234 adw_eeprom_wait(adw);
235}
236
237/*
238 * Wait for and EEPROM command to complete
239 */
240static void
241adw_eeprom_wait(struct adw_softc *adw)
242{
243 int i;
244
245 for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
246 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
247 break;
248 DELAY(1000);
249 }
250 if (i == ADW_EEP_DELAY_MS)
251 panic("%s: Timedout Reading EEPROM", adw_name(adw));
252}
253
254/*
255 * Read EEPROM configuration into the specified buffer.
256 *
257 * Return a checksum based on the EEPROM configuration read.
258 */
259u_int16_t
260adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
261{
262 u_int16_t *wbuf;
263 u_int16_t wval;
264 u_int16_t chksum;
265 int eep_addr;
266
267 wbuf = (u_int16_t *)eep_buf;
268 chksum = 0;
269
270 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
271 eep_addr < ADW_EEP_DVC_CFG_END;
272 eep_addr++, wbuf++) {
273 wval = adw_eeprom_read_16(adw, eep_addr);
274 chksum += wval;
275 *wbuf = wval;
276 }
277
278 /* checksum field is not counted in the checksum */
279 *wbuf = adw_eeprom_read_16(adw, eep_addr);
280 wbuf++;
281
282 /* Driver seeprom variables are not included in the checksum */
283 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
284 eep_addr < ADW_EEP_MAX_WORD_ADDR;
285 eep_addr++, wbuf++)
286 *wbuf = adw_eeprom_read_16(adw, eep_addr);
287
288 return (chksum);
289}
290
291void
292adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
293{
294 u_int16_t *wbuf;
295 u_int16_t addr;
296 u_int16_t chksum;
297
298 wbuf = (u_int16_t *)eep_buf;
299 chksum = 0;
300
301 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
302 adw_eeprom_wait(adw);
303
304 /*
305 * Write EEPROM until checksum.
306 */
307 for (addr = ADW_EEP_DVC_CFG_BEGIN;
308 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
309 chksum += *wbuf;
310 adw_eeprom_write_16(adw, addr, *wbuf);
311 }
312
313 /*
314 * Write calculated EEPROM checksum
315 */
316 adw_eeprom_write_16(adw, addr, chksum);
317
318 /* skip over buffer's checksum */
319 wbuf++;
320
321 /*
322 * Write the rest.
323 */
324 for (addr = ADW_EEP_DVC_CTL_BEGIN;
325 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
326 adw_eeprom_write_16(adw, addr, *wbuf);
327
328 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
329 adw_eeprom_wait(adw);
330}
331
332int
333adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
334{
335 u_int8_t biosmem[ADW_MC_BIOSLEN];
336 const u_int16_t *word_table;
337 const u_int8_t *byte_codes;
338 const u_int8_t *byte_codes_end;
339 u_int bios_sig;
340 u_int bytes_downloaded;
341 u_int addr;
342 u_int end_addr;
343 u_int checksum;
344 u_int scsicfg1;
345 u_int tid;
346
347 /*
348 * Save the RISC memory BIOS region before writing the microcode.
349 * The BIOS may already be loaded and using its RISC LRAM region
350 * so its region must be saved and restored.
351 */
352 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
353 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
354
355 /*
356 * Save current per TID negotiated values if the BIOS has been
357 * loaded (BIOS signature is present). These will be used if
358 * we cannot get information from the EEPROM.
359 */
360 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
361 bios_sig = biosmem[addr]
362 | (biosmem[addr + 1] << 8);
363 if (bios_sig == 0x55AA
364 && (adw->flags & ADW_EEPROM_FAILED) != 0) {
365 u_int major_ver;
366 u_int minor_ver;
367 u_int sdtr_able;
368
369 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
370 minor_ver = biosmem[addr + 1] & 0xF;
371 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
372 if ((adw->chip == ADW_CHIP_ASC3550)
373 && (major_ver <= 3
374 || (major_ver == 3 && minor_ver == 1))) {
375 /*
376 * BIOS 3.1 and earlier location of
377 * 'wdtr_able' variable.
378 */
379 adw->user_wdtr =
380 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
381 } else {
382 adw->user_wdtr =
383 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
384 }
385 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
386 for (tid = 0; tid < ADW_MAX_TID; tid++) {
387 u_int tid_mask;
388 u_int mc_sdtr;
389
390 tid_mask = 0x1 << tid;
391 if ((sdtr_able & tid_mask) == 0)
392 mc_sdtr = ADW_MC_SDTR_ASYNC;
393 else if ((adw->features & ADW_DT) != 0)
394 mc_sdtr = ADW_MC_SDTR_80;
395 else if ((adw->features & ADW_ULTRA2) != 0)
396 mc_sdtr = ADW_MC_SDTR_40;
397 else
398 mc_sdtr = ADW_MC_SDTR_20;
399 adw_set_user_sdtr(adw, tid, mc_sdtr);
400 }
401 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
402 }
403
404 /*
405 * Load the Microcode.
406 *
407 * Assume the following compressed format of the microcode buffer:
408 *
409 * 253 word (506 byte) table indexed by byte code followed
410 * by the following byte codes:
411 *
412 * 1-Byte Code:
413 * 00: Emit word 0 in table.
414 * 01: Emit word 1 in table.
415 * .
416 * FD: Emit word 253 in table.
417 *
418 * Multi-Byte Code:
419 * FD RESEVED
420 *
421 * FE WW WW: (3 byte code)
422 * Word to emit is the next word WW WW.
423 * FF BB WW WW: (4 byte code)
424 * Emit BB count times next word WW WW.
425 *
426 */
427 bytes_downloaded = 0;
428 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
429 byte_codes = (const u_int8_t *)&word_table[253];
430 byte_codes_end = adw->mcode_data->mcode_buf
431 + adw->mcode_data->mcode_size;
432 adw_outw(adw, ADW_RAM_ADDR, 0);
433 while (byte_codes < byte_codes_end) {
434 if (*byte_codes == 0xFF) {
435 u_int16_t value;
436
437 value = byte_codes[2]
438 | byte_codes[3] << 8;
439 adw_set_multi_2(adw, ADW_RAM_DATA,
440 value, byte_codes[1]);
441 bytes_downloaded += byte_codes[1];
442 byte_codes += 4;
443 } else if (*byte_codes == 0xFE) {
444 u_int16_t value;
445
446 value = byte_codes[1]
447 | byte_codes[2] << 8;
448 adw_outw(adw, ADW_RAM_DATA, value);
449 bytes_downloaded++;
450 byte_codes += 3;
451 } else {
452 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
453 bytes_downloaded++;
454 byte_codes++;
455 }
456 }
457 /* Convert from words to bytes */
458 bytes_downloaded *= 2;
459
460 /*
461 * Clear the rest of LRAM.
462 */
463 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
464 adw_outw(adw, ADW_RAM_DATA, 0);
465
466 /*
467 * Verify the microcode checksum.
468 */
469 checksum = 0;
470 adw_outw(adw, ADW_RAM_ADDR, 0);
471 for (addr = 0; addr < bytes_downloaded; addr += 2)
472 checksum += adw_inw(adw, ADW_RAM_DATA);
473
474 if (checksum != adw->mcode_data->mcode_chksum) {
475 printf("%s: Firmware load failed!\n", adw_name(adw));
476 return (EIO);
477 }
478
479 /*
480 * Restore the RISC memory BIOS region.
481 */
482 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
483 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
484
485 /*
486 * Calculate and write the microcode code checksum to
487 * the microcode code checksum location.
488 */
489 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
490 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
491 checksum = 0;
492 adw_outw(adw, ADW_RAM_ADDR, addr);
493 for (; addr < end_addr; addr += 2)
494 checksum += adw_inw(adw, ADW_RAM_DATA);
495 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
496
497 /*
498 * Tell the microcode what kind of chip it's running on.
499 */
500 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
501
502 /*
503 * Leave WDTR and SDTR negotiation disabled until the XPT has
504 * informed us of device capabilities, but do set the desired
505 * user rates in case we receive an SDTR request from the target
506 * before we negotiate. We turn on tagged queuing at the microcode
507 * level for all devices, and modulate this on a per command basis.
508 */
509 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
510 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
511 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
512 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
513 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
514 for (tid = 0; tid < ADW_MAX_TID; tid++) {
515 /* Cam limits the maximum number of commands for us */
516 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
517 adw->max_acbs);
518 }
519 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
520
521 /*
522 * Set SCSI_CFG0 Microcode Default Value.
523 *
524 * The microcode will set the SCSI_CFG0 register using this value
525 * after it is started.
526 */
527 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
528 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
529 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
530
531 /*
532 * Tell the MC about the memory size that
533 * was setup by the probe code.
534 */
535 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
536 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
537
538 /*
539 * Determine SCSI_CFG1 Microcode Default Value.
540 *
541 * The microcode will set the SCSI_CFG1 register using this value
542 * after it is started below.
543 */
544 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
545
546 /*
547 * If the internal narrow cable is reversed all of the SCSI_CTRL
548 * register signals will be set. Check for and return an error if
549 * this condition is found.
550 */
551 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
552 printf("%s: Illegal Cable Config!\n", adw_name(adw));
553 printf("%s: Internal cable is reversed!\n", adw_name(adw));
554 return (EIO);
555 }
556
557 /*
558 * If this is a differential board and a single-ended device
559 * is attached to one of the connectors, return an error.
560 */
561 if ((adw->features & ADW_ULTRA) != 0) {
562 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
563 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
564 printf("%s: A Single Ended Device is attached to our "
565 "differential bus!\n", adw_name(adw));
566 return (EIO);
567 }
568 } else {
569 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
570 printf("%s: A High Voltage Differential Device "
571 "is attached to this controller.\n",
572 adw_name(adw));
573 printf("%s: HVD devices are not supported.\n",
574 adw_name(adw));
575 return (EIO);
576 }
577 }
578
579 /*
580 * Perform automatic termination control if desired.
581 */
582 if ((adw->features & ADW_ULTRA2) != 0) {
583 u_int cable_det;
584
585 /*
586 * Ultra2 Chips require termination disabled to
587 * detect cable presence.
588 */
589 adw_outw(adw, ADW_SCSI_CFG1,
590 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
591 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
592 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
593
594 /* SE Termination first if auto-term has been specified */
595 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
596
597 /*
598 * For all SE cable configurations, high byte
599 * termination is enabled.
600 */
601 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
602 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
603 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
604 /*
605 * If either cable is not present, the
606 * low byte must be terminated as well.
607 */
608 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
609 }
610 }
611
612 /* LVD auto-term */
613 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
614 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
615 /*
616 * If both cables are installed, termination
617 * is disabled. Otherwise it is enabled.
618 */
619 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
620 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
621
622 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
623 }
624 }
625 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
626 } else {
627 /* Ultra Controller Termination */
628 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
629 int cable_count;
630 int wide_cable_count;
631
632 cable_count = 0;
633 wide_cable_count = 0;
634 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
635 cable_count++;
636 wide_cable_count++;
637 }
638 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
639 cable_count++;
640
641 /* There is only one external port */
642 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
643 cable_count++;
644 wide_cable_count++;
645 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
646 cable_count++;
647
648 if (cable_count == 3) {
649 printf("%s: Illegal Cable Config!\n",
650 adw_name(adw));
651 printf("%s: Only Two Ports may be used at "
652 "a time!\n", adw_name(adw));
653 } else if (cable_count <= 1) {
654 /*
655 * At least two out of three cables missing.
656 * Terminate both bytes.
657 */
658 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
659 | ADW_SCSI_CFG1_TERM_CTL_L;
660 } else if (wide_cable_count <= 1) {
661 /* No two 16bit cables present. High on. */
662 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
663 }
664 }
665 }
666
667 /* Tell the user about our decission */
668 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
669 case ADW_SCSI_CFG1_TERM_CTL_MASK:
670 printf("High & Low SE Term Enabled, ");
671 break;
672 case ADW_SCSI_CFG1_TERM_CTL_H:
673 printf("High SE Termination Enabled, ");
674 break;
675 case ADW_SCSI_CFG1_TERM_CTL_L:
676 printf("Low SE Term Enabled, ");
677 break;
678 default:
679 break;
680 }
681
682 if ((adw->features & ADW_ULTRA2) != 0
683 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
684 printf("LVD Term Enabled, ");
685
686 /*
687 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
688 * set 'scsicfg1'. The TERM_POL bit does not need to be
689 * referenced, because the hardware internally inverts
690 * the Termination High and Low bits if TERM_POL is set.
691 */
692 if ((adw->features & ADW_ULTRA2) != 0) {
693 term_scsicfg1 = ~term_scsicfg1;
694 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
695 | ADW2_SCSI_CFG1_TERM_CTL_LVD;
696 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
697 |ADW2_SCSI_CFG1_TERM_CTL_LVD
698 |ADW_SCSI_CFG1_BIG_ENDIAN
699 |ADW_SCSI_CFG1_TERM_POL
700 |ADW2_SCSI_CFG1_DEV_DETECT);
701 scsicfg1 |= term_scsicfg1;
702 } else {
703 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
704 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
705 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
706 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
707 }
708
709 /*
710 * Set SCSI_CFG1 Microcode Default Value
711 *
712 * The microcode will set the SCSI_CFG1 register using this value
713 * after it is started below.
714 */
715 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
716
717 /*
718 * Only accept selections on our initiator target id.
719 * This may change in target mode scenarios...
720 */
721 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
722 (0x01 << adw->initiator_id));
723
724 /*
725 * Tell the microcode where it can find our
726 * Initiator Command Queue (ICQ). It is
727 * currently empty hence the "stopper" address.
728 */
729 adw->commandq = adw->free_carriers;
730 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
731 adw->commandq->next_ba = ADW_CQ_STOPPER;
732 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
733
734 /*
735 * Tell the microcode where it can find our
736 * Initiator Response Queue (IRQ). It too
737 * is currently empty.
738 */
739 adw->responseq = adw->free_carriers;
740 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
741 adw->responseq->next_ba = ADW_CQ_STOPPER;
742 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
743
744 adw_outb(adw, ADW_INTR_ENABLES,
745 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
746
747 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
748
749 return (0);
750}
751
752void
753adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
754{
755 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
756 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
757 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
758}
759
760u_int
761adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
762{
763 u_int mc_sdtr;
764
765 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
766 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
767 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
768 return (mc_sdtr);
769}
770
771void
772adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
773{
774 u_int mc_sdtr_offset;
775 u_int mc_sdtr;
776
777 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
778 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
779 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
780 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
781 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
782 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
783}
784
785u_int
786adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
787{
788 u_int mc_sdtr_offset;
789 u_int mc_sdtr;
790
791 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
792 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
793 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
794 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
795 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
796 return (mc_sdtr);
797}
798
799u_int
800adw_find_sdtr(struct adw_softc *adw, u_int period)
801{
802 int i;
803
804 i = 0;
805 if ((adw->features & ADW_DT) == 0)
806 i = ADW_MC_SDTR_OFFSET_ULTRA2;
807 if ((adw->features & ADW_ULTRA2) == 0)
808 i = ADW_MC_SDTR_OFFSET_ULTRA;
809 if (period == 0)
810 return ADW_MC_SDTR_ASYNC;
811
812 for (; i < adw_num_syncrates; i++) {
813 if (period <= adw_syncrates[i].period)
814 return (adw_syncrates[i].mc_sdtr);
815 }
816 return ADW_MC_SDTR_ASYNC;
817}
818
819u_int
820adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
821{
822 int i;
823
824 for (i = 0; i < adw_num_syncrates; i++) {
825 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
826 break;
827 }
828 return (adw_syncrates[i].period);
829}
830
831u_int
832adw_hshk_cfg_period_factor(u_int tinfo)
833{
834 tinfo &= ADW_HSHK_CFG_RATE_MASK;
835 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
836 if (tinfo == 0x11)
837 /* 80MHz/DT */
838 return (9);
839 else if (tinfo == 0x10)
840 /* 40MHz */
841 return (10);
842 else
843 return (((tinfo * 25) + 50) / 4);
844}
845
846/*
847 * Send an idle command to the chip and wait for completion.
848 */
849adw_idle_cmd_status_t
850adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
851{
852 u_int timeout;
853 adw_idle_cmd_status_t status;
854 int s;
855
856 s = splcam();
857
858 /*
859 * Clear the idle command status which is set by the microcode
860 * to a non-zero value to indicate when the command is completed.
861 */
862 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
863
864 /*
865 * Write the idle command value after the idle command parameter
866 * has been written to avoid a race condition. If the order is not
867 * followed, the microcode may process the idle command before the
868 * parameters have been written to LRAM.
869 */
870 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
871 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
872
873 /*
874 * Tickle the RISC to tell it to process the idle command.
875 */
876 adw_tickle_risc(adw, ADW_TICKLE_B);
877
878 /* Wait for up to 10 seconds for the command to complete */
879 timeout = 5000000;
880 while (--timeout) {
881 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
882 if (status != 0)
883 break;
884 DELAY(20);
885 }
886
887 if (timeout == 0)
888 panic("%s: Idle Command Timed Out!\n", adw_name(adw));
889 splx(s);
890 return (status);
891}
2 * Low level routines for Second Generation
3 * Advanced Systems Inc. SCSI controllers chips
4 *
5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/advansys/adwlib.c 57679 2000-03-02 00:08:35Z gibbs $
33 */
34/*
35 * Ported from:
36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
37 *
38 * Copyright (c) 1995-1998 Advanced System Products, Inc.
39 * All Rights Reserved.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that redistributions of source
43 * code retain the above copyright notice and this comment without
44 * modification.
45 */
46
47#include <sys/param.h>
48#include <sys/systm.h>
49#include <sys/bus.h>
50
51#include <machine/bus_pio.h>
52#include <machine/bus_memio.h>
53#include <machine/bus.h>
54#include <machine/clock.h>
55
56#include <cam/cam.h>
57#include <cam/scsi/scsi_all.h>
58
59#include <dev/advansys/adwlib.h>
60
61const struct adw_eeprom adw_asc3550_default_eeprom =
62{
63 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
64 0x0000, /* cfg_msw */
65 0xFFFF, /* disc_enable */
66 0xFFFF, /* wdtr_able */
67 { 0xFFFF }, /* sdtr_able */
68 0xFFFF, /* start_motor */
69 0xFFFF, /* tagqng_able */
70 0xFFFF, /* bios_scan */
71 0, /* scam_tolerant */
72 7, /* adapter_scsi_id */
73 0, /* bios_boot_delay */
74 3, /* scsi_reset_delay */
75 0, /* bios_id_lun */
76 0, /* termination */
77 0, /* reserved1 */
78 0xFFE7, /* bios_ctrl */
79 { 0xFFFF }, /* ultra_able */
80 { 0 }, /* reserved2 */
81 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
82 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
83 0, /* dvc_cntl */
84 { 0 }, /* bug_fix */
85 { 0, 0, 0 }, /* serial_number */
86 0, /* check_sum */
87 { /* oem_name[16] */
88 0, 0, 0, 0, 0, 0, 0, 0,
89 0, 0, 0, 0, 0, 0, 0, 0
90 },
91 0, /* dvc_err_code */
92 0, /* adv_err_code */
93 0, /* adv_err_addr */
94 0, /* saved_dvc_err_code */
95 0, /* saved_adv_err_code */
96 0 /* saved_adv_err_addr */
97};
98
99const struct adw_eeprom adw_asc38C0800_default_eeprom =
100{
101 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
102 0x0000, /* 01 cfg_msw */
103 0xFFFF, /* 02 disc_enable */
104 0xFFFF, /* 03 wdtr_able */
105 { 0x4444 }, /* 04 sdtr_speed1 */
106 0xFFFF, /* 05 start_motor */
107 0xFFFF, /* 06 tagqng_able */
108 0xFFFF, /* 07 bios_scan */
109 0, /* 08 scam_tolerant */
110 7, /* 09 adapter_scsi_id */
111 0, /* bios_boot_delay */
112 3, /* 10 scsi_reset_delay */
113 0, /* bios_id_lun */
114 0, /* 11 termination_se */
115 0, /* termination_lvd */
116 0xFFE7, /* 12 bios_ctrl */
117 { 0x4444 }, /* 13 sdtr_speed2 */
118 { 0x4444 }, /* 14 sdtr_speed3 */
119 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
120 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
121 0, /* 16 dvc_cntl */
122 { 0x4444 } , /* 17 sdtr_speed4 */
123 { 0, 0, 0 }, /* 18-20 serial_number */
124 0, /* 21 check_sum */
125 { /* 22-29 oem_name[16] */
126 0, 0, 0, 0, 0, 0, 0, 0,
127 0, 0, 0, 0, 0, 0, 0, 0
128 },
129 0, /* 30 dvc_err_code */
130 0, /* 31 adv_err_code */
131 0, /* 32 adv_err_addr */
132 0, /* 33 saved_dvc_err_code */
133 0, /* 34 saved_adv_err_code */
134 0, /* 35 saved_adv_err_addr */
135 { /* 36 - 55 reserved */
136 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
137 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
138 },
139 0, /* 56 cisptr_lsw */
140 0, /* 57 cisprt_msw */
141 /* 58-59 sub-id */
142 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
143};
144
145#define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
146#define ADW_MC_SDTR_OFFSET_ULTRA2 1
147#define ADW_MC_SDTR_OFFSET_ULTRA 2
148const struct adw_syncrate adw_syncrates[] =
149{
150 /* mc_sdtr period rate */
151 { ADW_MC_SDTR_80, 9, "80.0" },
152 { ADW_MC_SDTR_40, 10, "40.0" },
153 { ADW_MC_SDTR_20, 12, "20.0" },
154 { ADW_MC_SDTR_10, 25, "10.0" },
155 { ADW_MC_SDTR_5, 50, "5.0" },
156 { ADW_MC_SDTR_ASYNC, 0, "async" }
157};
158
159const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
160
161static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
162static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
163 u_int data);
164static void adw_eeprom_wait(struct adw_softc *adw);
165
166int
167adw_find_signature(struct adw_softc *adw)
168{
169 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
170 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
171 return (1);
172 return (0);
173}
174
175/*
176 * Reset Chip.
177 */
178void
179adw_reset_chip(struct adw_softc *adw)
180{
181 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
182 DELAY(1000 * 100);
183 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
184
185 /*
186 * Initialize Chip registers.
187 */
188 adw_outw(adw, ADW_SCSI_CFG1,
189 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
190}
191
192/*
193 * Reset the SCSI bus.
194 */
195int
196adw_reset_bus(struct adw_softc *adw)
197{
198 adw_idle_cmd_status_t status;
199
200 status =
201 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
202 if (status != ADW_IDLE_CMD_SUCCESS) {
203 xpt_print_path(adw->path);
204 printf("Bus Reset start attempt failed\n");
205 return (1);
206 }
207 DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
208 status =
209 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
210 if (status != ADW_IDLE_CMD_SUCCESS) {
211 xpt_print_path(adw->path);
212 printf("Bus Reset end attempt failed\n");
213 return (1);
214 }
215 return (0);
216}
217
218/*
219 * Read the specified EEPROM location
220 */
221static u_int16_t
222adw_eeprom_read_16(struct adw_softc *adw, int addr)
223{
224 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
225 adw_eeprom_wait(adw);
226 return (adw_inw(adw, ADW_EEP_DATA));
227}
228
229static void
230adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
231{
232 adw_outw(adw, ADW_EEP_DATA, data);
233 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
234 adw_eeprom_wait(adw);
235}
236
237/*
238 * Wait for and EEPROM command to complete
239 */
240static void
241adw_eeprom_wait(struct adw_softc *adw)
242{
243 int i;
244
245 for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
246 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
247 break;
248 DELAY(1000);
249 }
250 if (i == ADW_EEP_DELAY_MS)
251 panic("%s: Timedout Reading EEPROM", adw_name(adw));
252}
253
254/*
255 * Read EEPROM configuration into the specified buffer.
256 *
257 * Return a checksum based on the EEPROM configuration read.
258 */
259u_int16_t
260adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
261{
262 u_int16_t *wbuf;
263 u_int16_t wval;
264 u_int16_t chksum;
265 int eep_addr;
266
267 wbuf = (u_int16_t *)eep_buf;
268 chksum = 0;
269
270 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
271 eep_addr < ADW_EEP_DVC_CFG_END;
272 eep_addr++, wbuf++) {
273 wval = adw_eeprom_read_16(adw, eep_addr);
274 chksum += wval;
275 *wbuf = wval;
276 }
277
278 /* checksum field is not counted in the checksum */
279 *wbuf = adw_eeprom_read_16(adw, eep_addr);
280 wbuf++;
281
282 /* Driver seeprom variables are not included in the checksum */
283 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
284 eep_addr < ADW_EEP_MAX_WORD_ADDR;
285 eep_addr++, wbuf++)
286 *wbuf = adw_eeprom_read_16(adw, eep_addr);
287
288 return (chksum);
289}
290
291void
292adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
293{
294 u_int16_t *wbuf;
295 u_int16_t addr;
296 u_int16_t chksum;
297
298 wbuf = (u_int16_t *)eep_buf;
299 chksum = 0;
300
301 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
302 adw_eeprom_wait(adw);
303
304 /*
305 * Write EEPROM until checksum.
306 */
307 for (addr = ADW_EEP_DVC_CFG_BEGIN;
308 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
309 chksum += *wbuf;
310 adw_eeprom_write_16(adw, addr, *wbuf);
311 }
312
313 /*
314 * Write calculated EEPROM checksum
315 */
316 adw_eeprom_write_16(adw, addr, chksum);
317
318 /* skip over buffer's checksum */
319 wbuf++;
320
321 /*
322 * Write the rest.
323 */
324 for (addr = ADW_EEP_DVC_CTL_BEGIN;
325 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
326 adw_eeprom_write_16(adw, addr, *wbuf);
327
328 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
329 adw_eeprom_wait(adw);
330}
331
332int
333adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
334{
335 u_int8_t biosmem[ADW_MC_BIOSLEN];
336 const u_int16_t *word_table;
337 const u_int8_t *byte_codes;
338 const u_int8_t *byte_codes_end;
339 u_int bios_sig;
340 u_int bytes_downloaded;
341 u_int addr;
342 u_int end_addr;
343 u_int checksum;
344 u_int scsicfg1;
345 u_int tid;
346
347 /*
348 * Save the RISC memory BIOS region before writing the microcode.
349 * The BIOS may already be loaded and using its RISC LRAM region
350 * so its region must be saved and restored.
351 */
352 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
353 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
354
355 /*
356 * Save current per TID negotiated values if the BIOS has been
357 * loaded (BIOS signature is present). These will be used if
358 * we cannot get information from the EEPROM.
359 */
360 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
361 bios_sig = biosmem[addr]
362 | (biosmem[addr + 1] << 8);
363 if (bios_sig == 0x55AA
364 && (adw->flags & ADW_EEPROM_FAILED) != 0) {
365 u_int major_ver;
366 u_int minor_ver;
367 u_int sdtr_able;
368
369 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
370 minor_ver = biosmem[addr + 1] & 0xF;
371 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
372 if ((adw->chip == ADW_CHIP_ASC3550)
373 && (major_ver <= 3
374 || (major_ver == 3 && minor_ver == 1))) {
375 /*
376 * BIOS 3.1 and earlier location of
377 * 'wdtr_able' variable.
378 */
379 adw->user_wdtr =
380 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
381 } else {
382 adw->user_wdtr =
383 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
384 }
385 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
386 for (tid = 0; tid < ADW_MAX_TID; tid++) {
387 u_int tid_mask;
388 u_int mc_sdtr;
389
390 tid_mask = 0x1 << tid;
391 if ((sdtr_able & tid_mask) == 0)
392 mc_sdtr = ADW_MC_SDTR_ASYNC;
393 else if ((adw->features & ADW_DT) != 0)
394 mc_sdtr = ADW_MC_SDTR_80;
395 else if ((adw->features & ADW_ULTRA2) != 0)
396 mc_sdtr = ADW_MC_SDTR_40;
397 else
398 mc_sdtr = ADW_MC_SDTR_20;
399 adw_set_user_sdtr(adw, tid, mc_sdtr);
400 }
401 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
402 }
403
404 /*
405 * Load the Microcode.
406 *
407 * Assume the following compressed format of the microcode buffer:
408 *
409 * 253 word (506 byte) table indexed by byte code followed
410 * by the following byte codes:
411 *
412 * 1-Byte Code:
413 * 00: Emit word 0 in table.
414 * 01: Emit word 1 in table.
415 * .
416 * FD: Emit word 253 in table.
417 *
418 * Multi-Byte Code:
419 * FD RESEVED
420 *
421 * FE WW WW: (3 byte code)
422 * Word to emit is the next word WW WW.
423 * FF BB WW WW: (4 byte code)
424 * Emit BB count times next word WW WW.
425 *
426 */
427 bytes_downloaded = 0;
428 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
429 byte_codes = (const u_int8_t *)&word_table[253];
430 byte_codes_end = adw->mcode_data->mcode_buf
431 + adw->mcode_data->mcode_size;
432 adw_outw(adw, ADW_RAM_ADDR, 0);
433 while (byte_codes < byte_codes_end) {
434 if (*byte_codes == 0xFF) {
435 u_int16_t value;
436
437 value = byte_codes[2]
438 | byte_codes[3] << 8;
439 adw_set_multi_2(adw, ADW_RAM_DATA,
440 value, byte_codes[1]);
441 bytes_downloaded += byte_codes[1];
442 byte_codes += 4;
443 } else if (*byte_codes == 0xFE) {
444 u_int16_t value;
445
446 value = byte_codes[1]
447 | byte_codes[2] << 8;
448 adw_outw(adw, ADW_RAM_DATA, value);
449 bytes_downloaded++;
450 byte_codes += 3;
451 } else {
452 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
453 bytes_downloaded++;
454 byte_codes++;
455 }
456 }
457 /* Convert from words to bytes */
458 bytes_downloaded *= 2;
459
460 /*
461 * Clear the rest of LRAM.
462 */
463 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
464 adw_outw(adw, ADW_RAM_DATA, 0);
465
466 /*
467 * Verify the microcode checksum.
468 */
469 checksum = 0;
470 adw_outw(adw, ADW_RAM_ADDR, 0);
471 for (addr = 0; addr < bytes_downloaded; addr += 2)
472 checksum += adw_inw(adw, ADW_RAM_DATA);
473
474 if (checksum != adw->mcode_data->mcode_chksum) {
475 printf("%s: Firmware load failed!\n", adw_name(adw));
476 return (EIO);
477 }
478
479 /*
480 * Restore the RISC memory BIOS region.
481 */
482 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
483 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
484
485 /*
486 * Calculate and write the microcode code checksum to
487 * the microcode code checksum location.
488 */
489 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
490 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
491 checksum = 0;
492 adw_outw(adw, ADW_RAM_ADDR, addr);
493 for (; addr < end_addr; addr += 2)
494 checksum += adw_inw(adw, ADW_RAM_DATA);
495 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
496
497 /*
498 * Tell the microcode what kind of chip it's running on.
499 */
500 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
501
502 /*
503 * Leave WDTR and SDTR negotiation disabled until the XPT has
504 * informed us of device capabilities, but do set the desired
505 * user rates in case we receive an SDTR request from the target
506 * before we negotiate. We turn on tagged queuing at the microcode
507 * level for all devices, and modulate this on a per command basis.
508 */
509 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
510 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
511 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
512 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
513 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
514 for (tid = 0; tid < ADW_MAX_TID; tid++) {
515 /* Cam limits the maximum number of commands for us */
516 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
517 adw->max_acbs);
518 }
519 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
520
521 /*
522 * Set SCSI_CFG0 Microcode Default Value.
523 *
524 * The microcode will set the SCSI_CFG0 register using this value
525 * after it is started.
526 */
527 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
528 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
529 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
530
531 /*
532 * Tell the MC about the memory size that
533 * was setup by the probe code.
534 */
535 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
536 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
537
538 /*
539 * Determine SCSI_CFG1 Microcode Default Value.
540 *
541 * The microcode will set the SCSI_CFG1 register using this value
542 * after it is started below.
543 */
544 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
545
546 /*
547 * If the internal narrow cable is reversed all of the SCSI_CTRL
548 * register signals will be set. Check for and return an error if
549 * this condition is found.
550 */
551 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
552 printf("%s: Illegal Cable Config!\n", adw_name(adw));
553 printf("%s: Internal cable is reversed!\n", adw_name(adw));
554 return (EIO);
555 }
556
557 /*
558 * If this is a differential board and a single-ended device
559 * is attached to one of the connectors, return an error.
560 */
561 if ((adw->features & ADW_ULTRA) != 0) {
562 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
563 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
564 printf("%s: A Single Ended Device is attached to our "
565 "differential bus!\n", adw_name(adw));
566 return (EIO);
567 }
568 } else {
569 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
570 printf("%s: A High Voltage Differential Device "
571 "is attached to this controller.\n",
572 adw_name(adw));
573 printf("%s: HVD devices are not supported.\n",
574 adw_name(adw));
575 return (EIO);
576 }
577 }
578
579 /*
580 * Perform automatic termination control if desired.
581 */
582 if ((adw->features & ADW_ULTRA2) != 0) {
583 u_int cable_det;
584
585 /*
586 * Ultra2 Chips require termination disabled to
587 * detect cable presence.
588 */
589 adw_outw(adw, ADW_SCSI_CFG1,
590 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
591 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
592 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
593
594 /* SE Termination first if auto-term has been specified */
595 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
596
597 /*
598 * For all SE cable configurations, high byte
599 * termination is enabled.
600 */
601 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
602 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
603 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
604 /*
605 * If either cable is not present, the
606 * low byte must be terminated as well.
607 */
608 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
609 }
610 }
611
612 /* LVD auto-term */
613 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
614 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
615 /*
616 * If both cables are installed, termination
617 * is disabled. Otherwise it is enabled.
618 */
619 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
620 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
621
622 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
623 }
624 }
625 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
626 } else {
627 /* Ultra Controller Termination */
628 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
629 int cable_count;
630 int wide_cable_count;
631
632 cable_count = 0;
633 wide_cable_count = 0;
634 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
635 cable_count++;
636 wide_cable_count++;
637 }
638 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
639 cable_count++;
640
641 /* There is only one external port */
642 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
643 cable_count++;
644 wide_cable_count++;
645 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
646 cable_count++;
647
648 if (cable_count == 3) {
649 printf("%s: Illegal Cable Config!\n",
650 adw_name(adw));
651 printf("%s: Only Two Ports may be used at "
652 "a time!\n", adw_name(adw));
653 } else if (cable_count <= 1) {
654 /*
655 * At least two out of three cables missing.
656 * Terminate both bytes.
657 */
658 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
659 | ADW_SCSI_CFG1_TERM_CTL_L;
660 } else if (wide_cable_count <= 1) {
661 /* No two 16bit cables present. High on. */
662 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
663 }
664 }
665 }
666
667 /* Tell the user about our decission */
668 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
669 case ADW_SCSI_CFG1_TERM_CTL_MASK:
670 printf("High & Low SE Term Enabled, ");
671 break;
672 case ADW_SCSI_CFG1_TERM_CTL_H:
673 printf("High SE Termination Enabled, ");
674 break;
675 case ADW_SCSI_CFG1_TERM_CTL_L:
676 printf("Low SE Term Enabled, ");
677 break;
678 default:
679 break;
680 }
681
682 if ((adw->features & ADW_ULTRA2) != 0
683 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
684 printf("LVD Term Enabled, ");
685
686 /*
687 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
688 * set 'scsicfg1'. The TERM_POL bit does not need to be
689 * referenced, because the hardware internally inverts
690 * the Termination High and Low bits if TERM_POL is set.
691 */
692 if ((adw->features & ADW_ULTRA2) != 0) {
693 term_scsicfg1 = ~term_scsicfg1;
694 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
695 | ADW2_SCSI_CFG1_TERM_CTL_LVD;
696 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
697 |ADW2_SCSI_CFG1_TERM_CTL_LVD
698 |ADW_SCSI_CFG1_BIG_ENDIAN
699 |ADW_SCSI_CFG1_TERM_POL
700 |ADW2_SCSI_CFG1_DEV_DETECT);
701 scsicfg1 |= term_scsicfg1;
702 } else {
703 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
704 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
705 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
706 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
707 }
708
709 /*
710 * Set SCSI_CFG1 Microcode Default Value
711 *
712 * The microcode will set the SCSI_CFG1 register using this value
713 * after it is started below.
714 */
715 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
716
717 /*
718 * Only accept selections on our initiator target id.
719 * This may change in target mode scenarios...
720 */
721 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
722 (0x01 << adw->initiator_id));
723
724 /*
725 * Tell the microcode where it can find our
726 * Initiator Command Queue (ICQ). It is
727 * currently empty hence the "stopper" address.
728 */
729 adw->commandq = adw->free_carriers;
730 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
731 adw->commandq->next_ba = ADW_CQ_STOPPER;
732 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
733
734 /*
735 * Tell the microcode where it can find our
736 * Initiator Response Queue (IRQ). It too
737 * is currently empty.
738 */
739 adw->responseq = adw->free_carriers;
740 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
741 adw->responseq->next_ba = ADW_CQ_STOPPER;
742 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
743
744 adw_outb(adw, ADW_INTR_ENABLES,
745 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
746
747 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
748
749 return (0);
750}
751
752void
753adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
754{
755 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
756 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
757 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
758}
759
760u_int
761adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
762{
763 u_int mc_sdtr;
764
765 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
766 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
767 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
768 return (mc_sdtr);
769}
770
771void
772adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
773{
774 u_int mc_sdtr_offset;
775 u_int mc_sdtr;
776
777 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
778 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
779 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
780 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
781 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
782 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
783}
784
785u_int
786adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
787{
788 u_int mc_sdtr_offset;
789 u_int mc_sdtr;
790
791 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
792 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
793 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
794 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
795 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
796 return (mc_sdtr);
797}
798
799u_int
800adw_find_sdtr(struct adw_softc *adw, u_int period)
801{
802 int i;
803
804 i = 0;
805 if ((adw->features & ADW_DT) == 0)
806 i = ADW_MC_SDTR_OFFSET_ULTRA2;
807 if ((adw->features & ADW_ULTRA2) == 0)
808 i = ADW_MC_SDTR_OFFSET_ULTRA;
809 if (period == 0)
810 return ADW_MC_SDTR_ASYNC;
811
812 for (; i < adw_num_syncrates; i++) {
813 if (period <= adw_syncrates[i].period)
814 return (adw_syncrates[i].mc_sdtr);
815 }
816 return ADW_MC_SDTR_ASYNC;
817}
818
819u_int
820adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
821{
822 int i;
823
824 for (i = 0; i < adw_num_syncrates; i++) {
825 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
826 break;
827 }
828 return (adw_syncrates[i].period);
829}
830
831u_int
832adw_hshk_cfg_period_factor(u_int tinfo)
833{
834 tinfo &= ADW_HSHK_CFG_RATE_MASK;
835 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
836 if (tinfo == 0x11)
837 /* 80MHz/DT */
838 return (9);
839 else if (tinfo == 0x10)
840 /* 40MHz */
841 return (10);
842 else
843 return (((tinfo * 25) + 50) / 4);
844}
845
846/*
847 * Send an idle command to the chip and wait for completion.
848 */
849adw_idle_cmd_status_t
850adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
851{
852 u_int timeout;
853 adw_idle_cmd_status_t status;
854 int s;
855
856 s = splcam();
857
858 /*
859 * Clear the idle command status which is set by the microcode
860 * to a non-zero value to indicate when the command is completed.
861 */
862 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
863
864 /*
865 * Write the idle command value after the idle command parameter
866 * has been written to avoid a race condition. If the order is not
867 * followed, the microcode may process the idle command before the
868 * parameters have been written to LRAM.
869 */
870 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
871 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
872
873 /*
874 * Tickle the RISC to tell it to process the idle command.
875 */
876 adw_tickle_risc(adw, ADW_TICKLE_B);
877
878 /* Wait for up to 10 seconds for the command to complete */
879 timeout = 5000000;
880 while (--timeout) {
881 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
882 if (status != 0)
883 break;
884 DELAY(20);
885 }
886
887 if (timeout == 0)
888 panic("%s: Idle Command Timed Out!\n", adw_name(adw));
889 splx(s);
890 return (status);
891}