1/*
2 * Generic driver for the Advanced Systems Inc. SCSI controllers
3 * Product specific probe and attach routines can be found in:
4 *
5 * i386/isa/adv_isa.c ABP5140, ABP542, ABP5150, ABP842, ABP852
6 * i386/eisa/adv_eisa.c ABP742, ABP752
7 * pci/adv_pci.c ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U,
8 * ABP940UA, ABP950, ABP960, ABP960U, ABP960UA,
9 * ABP970, ABP970U
10 *
11 * Copyright (c) 1996-2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification, immediately at the beginning of the file.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
|
35 * $FreeBSD: head/sys/dev/advansys/advansys.c 56926 2000-02-01 00:43:58Z gibbs $
|
| 35 * $FreeBSD: head/sys/dev/advansys/advansys.c 59082 2000-04-07 11:32:42Z nyan $ |
36 */
37/*
38 * Ported from:
39 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
40 *
41 * Copyright (c) 1995-1997 Advanced System Products, Inc.
42 * All Rights Reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that redistributions of source
46 * code retain the above copyright notice and this comment without
47 * modification.
48 */
49
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/malloc.h>
53#include <sys/buf.h>
54#include <sys/kernel.h>
55
56#include <machine/bus_pio.h>
57#include <machine/bus.h>
58#include <machine/clock.h>
|
59#include <machine/resource.h>
60#include <sys/bus.h>
61#include <sys/rman.h> |
62
63#include <cam/cam.h>
64#include <cam/cam_ccb.h>
65#include <cam/cam_sim.h>
66#include <cam/cam_xpt_sim.h>
67#include <cam/cam_xpt_periph.h>
68#include <cam/cam_debug.h>
69
70#include <cam/scsi/scsi_all.h>
71#include <cam/scsi/scsi_message.h>
72
73#include <vm/vm.h>
74#include <vm/vm_param.h>
75#include <vm/pmap.h>
76
77#include <dev/advansys/advansys.h>
78
|
76u_long adv_unit;
77
|
79static void adv_action(struct cam_sim *sim, union ccb *ccb);
80static void adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
81 int nsegments, int error);
82static void adv_poll(struct cam_sim *sim);
83static void adv_run_doneq(struct adv_softc *adv);
84static struct adv_ccb_info *
85 adv_alloc_ccb_info(struct adv_softc *adv);
86static void adv_destroy_ccb_info(struct adv_softc *adv,
87 struct adv_ccb_info *cinfo);
88static __inline struct adv_ccb_info *
89 adv_get_ccb_info(struct adv_softc *adv);
90static __inline void adv_free_ccb_info(struct adv_softc *adv,
91 struct adv_ccb_info *cinfo);
92static __inline void adv_set_state(struct adv_softc *adv, adv_state state);
93static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb);
94static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb);
95
|
95struct adv_softc *advsoftcs[NADV]; /* XXX Config should handle this */
96
|
96static __inline struct adv_ccb_info *
97adv_get_ccb_info(struct adv_softc *adv)
98{
99 struct adv_ccb_info *cinfo;
100 int opri;
101
102 opri = splcam();
103 if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
104 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
105 } else {
106 cinfo = adv_alloc_ccb_info(adv);
107 }
108 splx(opri);
109
110 return (cinfo);
111}
112
113static __inline void
114adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
115{
116 int opri;
117
118 opri = splcam();
119 cinfo->state = ACCB_FREE;
120 SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links);
121 splx(opri);
122}
123
124static __inline void
125adv_set_state(struct adv_softc *adv, adv_state state)
126{
127 if (adv->state == 0)
128 xpt_freeze_simq(adv->sim, /*count*/1);
129 adv->state |= state;
130}
131
132static __inline void
133adv_clear_state(struct adv_softc *adv, union ccb* ccb)
134{
135 if (adv->state != 0)
136 adv_clear_state_really(adv, ccb);
137}
138
139static void
140adv_clear_state_really(struct adv_softc *adv, union ccb* ccb)
141{
142 if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0)
143 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK);
144 if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) {
145 int openings;
146
147 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q;
148 if (openings >= adv->openings_needed) {
149 adv->state &= ~ADV_RESOURCE_SHORTAGE;
150 adv->openings_needed = 0;
151 }
152 }
153
154 if ((adv->state & ADV_IN_TIMEOUT) != 0) {
155 struct adv_ccb_info *cinfo;
156
157 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
158 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) {
159 struct ccb_hdr *ccb_h;
160
161 /*
162 * We now traverse our list of pending CCBs
163 * and reinstate their timeouts.
164 */
165 ccb_h = LIST_FIRST(&adv->pending_ccbs);
166 while (ccb_h != NULL) {
167 ccb_h->timeout_ch =
168 timeout(adv_timeout, (caddr_t)ccb_h,
169 (ccb_h->timeout * hz) / 1000);
170 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
171 }
172 adv->state &= ~ADV_IN_TIMEOUT;
173 printf("%s: No longer in timeout\n", adv_name(adv));
174 }
175 }
176 if (adv->state == 0)
177 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
178}
179
180void
181adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
182{
183 bus_addr_t* physaddr;
184
185 physaddr = (bus_addr_t*)arg;
186 *physaddr = segs->ds_addr;
187}
188
189char *
190adv_name(struct adv_softc *adv)
191{
192 static char name[10];
193
194 snprintf(name, sizeof(name), "adv%d", adv->unit);
195 return (name);
196}
197
198static void
199adv_action(struct cam_sim *sim, union ccb *ccb)
200{
201 struct adv_softc *adv;
202
203 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n"));
204
205 adv = (struct adv_softc *)cam_sim_softc(sim);
206
207 switch (ccb->ccb_h.func_code) {
208 /* Common cases first */
209 case XPT_SCSI_IO: /* Execute the requested I/O operation */
210 {
211 struct ccb_hdr *ccb_h;
212 struct ccb_scsiio *csio;
213 struct adv_ccb_info *cinfo;
214
215 ccb_h = &ccb->ccb_h;
216 csio = &ccb->csio;
217 cinfo = adv_get_ccb_info(adv);
218 if (cinfo == NULL)
219 panic("XXX Handle CCB info error!!!");
220
221 ccb_h->ccb_cinfo_ptr = cinfo;
222 cinfo->ccb = ccb;
223
224 /* Only use S/G if there is a transfer */
225 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
226 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
227 /*
228 * We've been given a pointer
229 * to a single buffer
230 */
231 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
232 int s;
233 int error;
234
235 s = splsoftvm();
236 error =
237 bus_dmamap_load(adv->buffer_dmat,
238 cinfo->dmamap,
239 csio->data_ptr,
240 csio->dxfer_len,
241 adv_execute_ccb,
242 csio, /*flags*/0);
243 if (error == EINPROGRESS) {
244 /*
245 * So as to maintain ordering,
246 * freeze the controller queue
247 * until our mapping is
248 * returned.
249 */
250 adv_set_state(adv,
251 ADV_BUSDMA_BLOCK);
252 }
253 splx(s);
254 } else {
255 struct bus_dma_segment seg;
256
257 /* Pointer to physical buffer */
258 seg.ds_addr =
259 (bus_addr_t)csio->data_ptr;
260 seg.ds_len = csio->dxfer_len;
261 adv_execute_ccb(csio, &seg, 1, 0);
262 }
263 } else {
264 struct bus_dma_segment *segs;
265 if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
266 panic("adv_setup_data - Physical "
267 "segment pointers unsupported");
268
269 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
270 panic("adv_setup_data - Virtual "
271 "segment addresses unsupported");
272
273 /* Just use the segments provided */
274 segs = (struct bus_dma_segment *)csio->data_ptr;
275 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0);
276 }
277 } else {
278 adv_execute_ccb(ccb, NULL, 0, 0);
279 }
280 break;
281 }
282 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
283 case XPT_TARGET_IO: /* Execute target I/O request */
284 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
285 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
286 case XPT_EN_LUN: /* Enable LUN as a target */
287 case XPT_ABORT: /* Abort the specified CCB */
288 /* XXX Implement */
289 ccb->ccb_h.status = CAM_REQ_INVALID;
290 xpt_done(ccb);
291 break;
292 case XPT_SET_TRAN_SETTINGS:
293 {
294 struct ccb_trans_settings *cts;
295 target_bit_vector targ_mask;
296 struct adv_transinfo *tconf;
297 u_int update_type;
298 int s;
299
300 cts = &ccb->cts;
301 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
302 update_type = 0;
303
304 /*
305 * The user must specify which type of settings he wishes
306 * to change.
307 */
308 if (((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
309 && ((cts->flags & CCB_TRANS_USER_SETTINGS) == 0)) {
310 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
311 update_type |= ADV_TRANS_GOAL;
312 } else if (((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
313 && ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) == 0)) {
314 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
315 update_type |= ADV_TRANS_USER;
316 } else {
317 ccb->ccb_h.status = CAM_REQ_INVALID;
318 break;
319 }
320
321 s = splcam();
322
323 if ((update_type & ADV_TRANS_GOAL) != 0) {
324 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
325 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
326 adv->disc_enable |= targ_mask;
327 else
328 adv->disc_enable &= ~targ_mask;
329 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B,
330 adv->disc_enable);
331 }
332
333 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
334 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
335 adv->cmd_qng_enabled |= targ_mask;
336 else
337 adv->cmd_qng_enabled &= ~targ_mask;
338 }
339 }
340
341 if ((update_type & ADV_TRANS_USER) != 0) {
342 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
343 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
344 adv->user_disc_enable |= targ_mask;
345 else
346 adv->user_disc_enable &= ~targ_mask;
347 }
348
349 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
350 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
351 adv->user_cmd_qng_enabled |= targ_mask;
352 else
353 adv->user_cmd_qng_enabled &= ~targ_mask;
354 }
355 }
356
357 /*
358 * If the user specifies either the sync rate, or offset,
359 * but not both, the unspecified parameter defaults to its
360 * current value in transfer negotiations.
361 */
362 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
363 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
364 /*
365 * If the user provided a sync rate but no offset,
366 * use the current offset.
367 */
368 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0)
369 cts->sync_offset = tconf->offset;
370
371 /*
372 * If the user provided an offset but no sync rate,
373 * use the current sync rate.
374 */
375 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0)
376 cts->sync_period = tconf->period;
377
378 adv_period_offset_to_sdtr(adv, &cts->sync_period,
379 &cts->sync_offset,
380 cts->ccb_h.target_id);
381
382 adv_set_syncrate(adv, /*struct cam_path */NULL,
383 cts->ccb_h.target_id, cts->sync_period,
384 cts->sync_offset, update_type);
385 }
386
387 splx(s);
388 ccb->ccb_h.status = CAM_REQ_CMP;
389 xpt_done(ccb);
390 break;
391 }
392 case XPT_GET_TRAN_SETTINGS:
393 /* Get default/user set transfer settings for the target */
394 {
395 struct ccb_trans_settings *cts;
396 struct adv_transinfo *tconf;
397 target_bit_vector target_mask;
398 int s;
399
400 cts = &ccb->cts;
401 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
402
403 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
404
405 s = splcam();
406 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
407 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
408 if ((adv->disc_enable & target_mask) != 0)
409 cts->flags |= CCB_TRANS_DISC_ENB;
410 if ((adv->cmd_qng_enabled & target_mask) != 0)
411 cts->flags |= CCB_TRANS_TAG_ENB;
412 } else {
413 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
414 if ((adv->user_disc_enable & target_mask) != 0)
415 cts->flags |= CCB_TRANS_DISC_ENB;
416 if ((adv->user_cmd_qng_enabled & target_mask) != 0)
417 cts->flags |= CCB_TRANS_TAG_ENB;
418 }
419
420 cts->sync_period = tconf->period;
421 cts->sync_offset = tconf->offset;
422 splx(s);
423
424 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
425 cts->valid = CCB_TRANS_SYNC_RATE_VALID
426 | CCB_TRANS_SYNC_OFFSET_VALID
427 | CCB_TRANS_BUS_WIDTH_VALID
428 | CCB_TRANS_DISC_VALID
429 | CCB_TRANS_TQ_VALID;
430 ccb->ccb_h.status = CAM_REQ_CMP;
431 xpt_done(ccb);
432 break;
433 }
434 case XPT_CALC_GEOMETRY:
435 {
436 struct ccb_calc_geometry *ccg;
437 u_int32_t size_mb;
438 u_int32_t secs_per_cylinder;
439 int extended;
440
441 ccg = &ccb->ccg;
442 size_mb = ccg->volume_size
443 / ((1024L * 1024L) / ccg->block_size);
444 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0;
445
446 if (size_mb > 1024 && extended) {
447 ccg->heads = 255;
448 ccg->secs_per_track = 63;
449 } else {
450 ccg->heads = 64;
451 ccg->secs_per_track = 32;
452 }
453 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
454 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
455 ccb->ccb_h.status = CAM_REQ_CMP;
456 xpt_done(ccb);
457 break;
458 }
459 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
460 {
461 int s;
462
463 s = splcam();
464 adv_stop_execution(adv);
465 adv_reset_bus(adv, /*initiate_reset*/TRUE);
466 adv_start_execution(adv);
467 splx(s);
468
469 ccb->ccb_h.status = CAM_REQ_CMP;
470 xpt_done(ccb);
471 break;
472 }
473 case XPT_TERM_IO: /* Terminate the I/O process */
474 /* XXX Implement */
475 ccb->ccb_h.status = CAM_REQ_INVALID;
476 xpt_done(ccb);
477 break;
478 case XPT_PATH_INQ: /* Path routing inquiry */
479 {
480 struct ccb_pathinq *cpi = &ccb->cpi;
481
482 cpi->version_num = 1; /* XXX??? */
483 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
484 cpi->target_sprt = 0;
485 cpi->hba_misc = 0;
486 cpi->hba_eng_cnt = 0;
487 cpi->max_target = 7;
488 cpi->max_lun = 7;
489 cpi->initiator_id = adv->scsi_id;
490 cpi->bus_id = cam_sim_bus(sim);
491 cpi->base_transfer_speed = 3300;
492 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
493 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN);
494 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
495 cpi->unit_number = cam_sim_unit(sim);
496 cpi->ccb_h.status = CAM_REQ_CMP;
497 xpt_done(ccb);
498 break;
499 }
500 default:
501 ccb->ccb_h.status = CAM_REQ_INVALID;
502 xpt_done(ccb);
503 break;
504 }
505}
506
507/*
508 * Currently, the output of bus_dmammap_load suits our needs just
509 * fine, but should it change, we'd need to do something here.
510 */
511#define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs)
512
513static void
514adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
515 int nsegments, int error)
516{
517 struct ccb_scsiio *csio;
518 struct ccb_hdr *ccb_h;
519 struct cam_sim *sim;
520 struct adv_softc *adv;
521 struct adv_ccb_info *cinfo;
522 struct adv_scsi_q scsiq;
523 struct adv_sg_head sghead;
524 int s;
525
526 csio = (struct ccb_scsiio *)arg;
527 ccb_h = &csio->ccb_h;
528 sim = xpt_path_sim(ccb_h->path);
529 adv = (struct adv_softc *)cam_sim_softc(sim);
530 cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr;
531
532 /*
533 * Setup our done routine to release the simq on
534 * the next ccb that completes.
535 */
536 if ((adv->state & ADV_BUSDMA_BLOCK) != 0)
537 adv->state |= ADV_BUSDMA_BLOCK_CLEARED;
538
539 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) {
540 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) {
541 /* XXX Need phystovirt!!!! */
542 /* How about pmap_kenter??? */
543 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
544 } else {
545 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
546 }
547 } else {
548 scsiq.cdbptr = csio->cdb_io.cdb_bytes;
549 }
550 /*
551 * Build up the request
552 */
553 scsiq.q1.status = 0;
554 scsiq.q1.q_no = 0;
555 scsiq.q1.cntl = 0;
556 scsiq.q1.sg_queue_cnt = 0;
557 scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id);
558 scsiq.q1.target_lun = ccb_h->target_lun;
559 scsiq.q1.sense_len = csio->sense_len;
560 scsiq.q1.extra_bytes = 0;
561 scsiq.q2.ccb_index = cinfo - adv->ccb_infos;
562 scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id,
563 ccb_h->target_lun);
564 scsiq.q2.flag = 0;
565 scsiq.q2.cdb_len = csio->cdb_len;
566 if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0)
567 scsiq.q2.tag_code = csio->tag_action;
568 else
569 scsiq.q2.tag_code = 0;
570 scsiq.q2.vm_id = 0;
571
572 if (nsegments != 0) {
573 bus_dmasync_op_t op;
574
575 scsiq.q1.data_addr = dm_segs->ds_addr;
576 scsiq.q1.data_cnt = dm_segs->ds_len;
577 if (nsegments > 1) {
578 scsiq.q1.cntl |= QC_SG_HEAD;
579 sghead.entry_cnt
580 = sghead.entry_to_copy
581 = nsegments;
582 sghead.res = 0;
583 sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs);
584 scsiq.sg_head = &sghead;
585 } else {
586 scsiq.sg_head = NULL;
587 }
588 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN)
589 op = BUS_DMASYNC_PREREAD;
590 else
591 op = BUS_DMASYNC_PREWRITE;
592 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
593 } else {
594 scsiq.q1.data_addr = 0;
595 scsiq.q1.data_cnt = 0;
596 scsiq.sg_head = NULL;
597 }
598
599 s = splcam();
600
601 /*
602 * Last time we need to check if this SCB needs to
603 * be aborted.
604 */
605 if (ccb_h->status != CAM_REQ_INPROG) {
606 if (nsegments != 0)
607 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
608 adv_clear_state(adv, (union ccb *)csio);
609 adv_free_ccb_info(adv, cinfo);
610 xpt_done((union ccb *)csio);
611 splx(s);
612 return;
613 }
614
615 if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) {
616 /* Temporary resource shortage */
617 adv_set_state(adv, ADV_RESOURCE_SHORTAGE);
618 if (nsegments != 0)
619 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
620 csio->ccb_h.status = CAM_REQUEUE_REQ;
621 adv_clear_state(adv, (union ccb *)csio);
622 adv_free_ccb_info(adv, cinfo);
623 xpt_done((union ccb *)csio);
624 splx(s);
625 return;
626 }
627 cinfo->state |= ACCB_ACTIVE;
628 ccb_h->status |= CAM_SIM_QUEUED;
629 LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le);
630 /* Schedule our timeout */
631 ccb_h->timeout_ch =
632 timeout(adv_timeout, csio, (ccb_h->timeout * hz)/1000);
633 splx(s);
634}
635
636static struct adv_ccb_info *
637adv_alloc_ccb_info(struct adv_softc *adv)
638{
639 int error;
640 struct adv_ccb_info *cinfo;
641
642 cinfo = &adv->ccb_infos[adv->ccb_infos_allocated];
643 cinfo->state = ACCB_FREE;
644 error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0,
645 &cinfo->dmamap);
646 if (error != 0) {
647 printf("%s: Unable to allocate CCB info "
648 "dmamap - error %d\n", adv_name(adv), error);
649 return (NULL);
650 }
651 adv->ccb_infos_allocated++;
652 return (cinfo);
653}
654
655static void
656adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
657{
658 bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap);
659}
660
661void
662adv_timeout(void *arg)
663{
664 int s;
665 union ccb *ccb;
666 struct adv_softc *adv;
667 struct adv_ccb_info *cinfo;
668
669 ccb = (union ccb *)arg;
670 adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc;
671 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
672
673 xpt_print_path(ccb->ccb_h.path);
674 printf("Timed out\n");
675
676 s = splcam();
677 /* Have we been taken care of already?? */
678 if (cinfo == NULL || cinfo->state == ACCB_FREE) {
679 splx(s);
680 return;
681 }
682
683 adv_stop_execution(adv);
684
685 if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) {
686 struct ccb_hdr *ccb_h;
687
688 /*
689 * In order to simplify the recovery process, we ask the XPT
690 * layer to halt the queue of new transactions and we traverse
691 * the list of pending CCBs and remove their timeouts. This
692 * means that the driver attempts to clear only one error
693 * condition at a time. In general, timeouts that occur
694 * close together are related anyway, so there is no benefit
695 * in attempting to handle errors in parrallel. Timeouts will
696 * be reinstated when the recovery process ends.
697 */
698 adv_set_state(adv, ADV_IN_TIMEOUT);
699
700 /* This CCB is the CCB representing our recovery actions */
701 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED;
702
703 ccb_h = LIST_FIRST(&adv->pending_ccbs);
704 while (ccb_h != NULL) {
705 untimeout(adv_timeout, ccb_h, ccb_h->timeout_ch);
706 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
707 }
708
709 /* XXX Should send a BDR */
710 /* Attempt an abort as our first tact */
711 xpt_print_path(ccb->ccb_h.path);
712 printf("Attempting abort\n");
713 adv_abort_ccb(adv, ccb->ccb_h.target_id,
714 ccb->ccb_h.target_lun, ccb,
715 CAM_CMD_TIMEOUT, /*queued_only*/FALSE);
716 ccb->ccb_h.timeout_ch =
717 timeout(adv_timeout, ccb, 2 * hz);
718 } else {
719 /* Our attempt to perform an abort failed, go for a reset */
720 xpt_print_path(ccb->ccb_h.path);
721 printf("Resetting bus\n");
722 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
723 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
724 adv_reset_bus(adv, /*initiate_reset*/TRUE);
725 }
726 adv_start_execution(adv);
727 splx(s);
728}
729
730struct adv_softc *
|
732adv_alloc(int unit, bus_space_tag_t tag, bus_space_handle_t bsh)
|
| 731adv_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh) |
732{
|
734 struct adv_softc *adv;
735
736 if (unit >= NADV) {
737 printf("adv: unit number (%d) too high\n", unit);
738 return NULL;
739 }
|
| 733 struct adv_softc *adv = device_get_softc(dev); |
734
735 /*
736 * Allocate a storage area for us
737 */
|
744 if (advsoftcs[unit]) {
745 printf("adv%d: memory already allocated\n", unit);
746 return NULL;
747 }
748
749 adv = malloc(sizeof(struct adv_softc), M_DEVBUF, M_NOWAIT);
750 if (!adv) {
751 printf("adv%d: cannot malloc!\n", unit);
752 return NULL;
753 }
754 bzero(adv, sizeof(struct adv_softc));
|
738 LIST_INIT(&adv->pending_ccbs);
739 SLIST_INIT(&adv->free_ccb_infos);
|
757 advsoftcs[unit] = adv;
758 adv->unit = unit;
|
740 adv->dev = dev;
741 adv->unit = device_get_unit(dev); |
742 adv->tag = tag;
743 adv->bsh = bsh;
744
745 return(adv);
746}
747
748void
749adv_free(struct adv_softc *adv)
750{
751 switch (adv->init_level) {
752 case 6:
753 {
754 struct adv_ccb_info *cinfo;
755
756 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
757 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
758 adv_destroy_ccb_info(adv, cinfo);
759 }
760
761 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap);
762 }
763 case 5:
764 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers,
765 adv->sense_dmamap);
766 case 4:
767 bus_dma_tag_destroy(adv->sense_dmat);
768 case 3:
769 bus_dma_tag_destroy(adv->buffer_dmat);
770 case 2:
771 bus_dma_tag_destroy(adv->parent_dmat);
772 case 1:
773 free(adv->ccb_infos, M_DEVBUF);
774 case 0:
775 break;
776 }
|
794 free(adv, M_DEVBUF);
|
777}
778
779int
780adv_init(struct adv_softc *adv)
781{
782 struct adv_eeprom_config eeprom_config;
783 int checksum, i;
784 int max_sync;
785 u_int16_t config_lsw;
786 u_int16_t config_msw;
787
788 adv_lib_init(adv);
789
790 /*
791 * Stop script execution.
792 */
793 adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE);
794 adv_stop_execution(adv);
795 if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) {
796 printf("adv%d: Unable to halt adapter. Initialization"
797 "failed\n", adv->unit);
798 return (1);
799 }
800 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
801 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) {
802 printf("adv%d: Unable to set program counter. Initialization"
803 "failed\n", adv->unit);
804 return (1);
805 }
806
807 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
808 config_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
809
810 if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) {
811 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
812 /*
813 * XXX The Linux code flags this as an error,
814 * but what should we report to the user???
815 * It seems that clearing the config register
816 * makes this error recoverable.
817 */
818 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
819 }
820
821 /* Suck in the configuration from the EEProm */
822 checksum = adv_get_eeprom_config(adv, &eeprom_config);
823
824 if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) {
825 /*
826 * XXX The Linux code sets a warning level for this
827 * condition, yet nothing of meaning is printed to
828 * the user. What does this mean???
829 */
830 if (adv->chip_version == 3) {
831 if (eeprom_config.cfg_lsw != config_lsw)
832 eeprom_config.cfg_lsw = config_lsw;
833 if (eeprom_config.cfg_msw != config_msw) {
834 eeprom_config.cfg_msw = config_msw;
835 }
836 }
837 }
838 if (checksum == eeprom_config.chksum) {
839
840 /* Range/Sanity checking */
841 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) {
842 eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG;
843 }
844 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) {
845 eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG;
846 }
847 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) {
848 eeprom_config.max_tag_qng = eeprom_config.max_total_qng;
849 }
850 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) {
851 eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC;
852 }
853 adv->max_openings = eeprom_config.max_total_qng;
854 adv->user_disc_enable = eeprom_config.disc_enable;
855 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng;
856 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config);
857 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID;
858 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id);
859 adv->control = eeprom_config.cntl;
860 for (i = 0; i <= ADV_MAX_TID; i++) {
861 u_int8_t sync_data;
862
863 if ((eeprom_config.init_sdtr & (0x1 << i)) == 0)
864 sync_data = 0;
865 else
866 sync_data = eeprom_config.sdtr_data[i];
867 adv_sdtr_to_period_offset(adv,
868 sync_data,
869 &adv->tinfo[i].user.period,
870 &adv->tinfo[i].user.offset,
871 i);
872 }
873 config_lsw = eeprom_config.cfg_lsw;
874 eeprom_config.cfg_msw = config_msw;
875 } else {
876 u_int8_t sync_data;
877
878 printf("adv%d: Warning EEPROM Checksum mismatch. "
879 "Using default device parameters\n", adv->unit);
880
881 /* Set reasonable defaults since we can't read the EEPROM */
882 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1;
883 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG;
884 adv->disc_enable = TARGET_BIT_VECTOR_SET;
885 adv->user_disc_enable = TARGET_BIT_VECTOR_SET;
886 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
887 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
888 adv->scsi_id = 7;
889 adv->control = 0xFFFF;
890
891 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
892 /* Default to no Ultra to support the 3030 */
893 adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA;
894 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4);
895 for (i = 0; i <= ADV_MAX_TID; i++) {
896 adv_sdtr_to_period_offset(adv, sync_data,
897 &adv->tinfo[i].user.period,
898 &adv->tinfo[i].user.offset,
899 i);
900 }
901 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON;
902 }
903 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
904 config_lsw |= ADV_CFG_LSW_HOST_INT_ON;
905 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)
906 && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0)
907 /* 25ns or 10MHz */
908 max_sync = 25;
909 else
910 /* Unlimited */
911 max_sync = 0;
912 for (i = 0; i <= ADV_MAX_TID; i++) {
913 if (adv->tinfo[i].user.period < max_sync)
914 adv->tinfo[i].user.period = max_sync;
915 }
916
917 if (adv_test_external_lram(adv) == 0) {
918 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) {
919 eeprom_config.max_total_qng =
920 ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
921 eeprom_config.max_tag_qng =
922 ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG;
923 } else {
924 eeprom_config.cfg_msw |= 0x0800;
925 config_msw |= 0x0800;
926 eeprom_config.max_total_qng =
927 ADV_MAX_PCI_INRAM_TOTAL_QNG;
928 eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG;
929 }
930 adv->max_openings = eeprom_config.max_total_qng;
931 }
932 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
933 ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw);
934#if 0
935 /*
936 * Don't write the eeprom data back for now.
937 * I'd rather not mess up the user's card. We also don't
938 * fully sanitize the eeprom settings above for the write-back
939 * to be 100% correct.
940 */
941 if (adv_set_eeprom_config(adv, &eeprom_config) != 0)
942 printf("%s: WARNING! Failure writing to EEPROM.\n",
943 adv_name(adv));
944#endif
945
946 adv_set_chip_scsiid(adv, adv->scsi_id);
947 if (adv_init_lram_and_mcode(adv))
948 return (1);
949
950 adv->disc_enable = adv->user_disc_enable;
951
952 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable);
953 for (i = 0; i <= ADV_MAX_TID; i++) {
954 /*
955 * Start off in async mode.
956 */
957 adv_set_syncrate(adv, /*struct cam_path */NULL,
958 i, /*period*/0, /*offset*/0,
959 ADV_TRANS_CUR);
960 /*
961 * Enable the use of tagged commands on all targets.
962 * This allows the kernel driver to make up it's own mind
963 * as it sees fit to tag queue instead of having the
964 * firmware try and second guess the tag_code settins.
965 */
966 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i,
967 adv->max_openings);
968 }
969 adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
970 adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
971 printf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n",
972 adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0)
973 ? "Ultra SCSI" : "SCSI",
974 adv->scsi_id, adv->max_openings);
975 return (0);
976}
977
978void
979adv_intr(void *arg)
980{
981 struct adv_softc *adv;
982 u_int16_t chipstat;
983 u_int16_t saved_ram_addr;
984 u_int8_t ctrl_reg;
985 u_int8_t saved_ctrl_reg;
986 u_int8_t host_flag;
987
988 adv = (struct adv_softc *)arg;
989
990 chipstat = ADV_INW(adv, ADV_CHIP_STATUS);
991
992 /* Is it for us? */
993 if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0)
994 return;
995
996 ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL);
997 saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET |
998 ADV_CC_SINGLE_STEP | ADV_CC_DIAG |
999 ADV_CC_TEST));
1000
1001 if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) {
1002 printf("Detected Bus Reset\n");
1003 adv_reset_bus(adv, /*initiate_reset*/FALSE);
1004 return;
1005 }
1006
1007 if ((chipstat & ADV_CSW_INT_PENDING) != 0) {
1008
1009 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR);
1010 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
1011 adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
1012 host_flag | ADV_HOST_FLAG_IN_ISR);
1013
1014 adv_ack_interrupt(adv);
1015
1016 if ((chipstat & ADV_CSW_HALTED) != 0
1017 && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) {
1018 adv_isr_chip_halted(adv);
1019 saved_ctrl_reg &= ~ADV_CC_HALT;
1020 } else {
1021 adv_run_doneq(adv);
1022 }
1023 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr);
1024#ifdef DIAGNOSTIC
1025 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr)
1026 panic("adv_intr: Unable to set LRAM addr");
1027#endif
1028 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
1029 }
1030
1031 ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg);
1032}
1033
1034void
1035adv_run_doneq(struct adv_softc *adv)
1036{
1037 struct adv_q_done_info scsiq;
1038 u_int doneq_head;
1039 u_int done_qno;
1040
1041 doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF;
1042 done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head)
1043 + ADV_SCSIQ_B_FWD);
1044 while (done_qno != ADV_QLINK_END) {
1045 union ccb* ccb;
1046 struct adv_ccb_info *cinfo;
1047 u_int done_qaddr;
1048 u_int sg_queue_cnt;
1049 int aborted;
1050
1051 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1052
1053 /* Pull status from this request */
1054 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq,
1055 adv->max_dma_count);
1056
1057 /* Mark it as free */
1058 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS,
1059 scsiq.q_status & ~(QS_READY|QS_ABORTED));
1060
1061 /* Process request based on retrieved info */
1062 if ((scsiq.cntl & QC_SG_HEAD) != 0) {
1063 u_int i;
1064
1065 /*
1066 * S/G based request. Free all of the queue
1067 * structures that contained S/G information.
1068 */
1069 for (i = 0; i < sg_queue_cnt; i++) {
1070 done_qno = adv_read_lram_8(adv, done_qaddr
1071 + ADV_SCSIQ_B_FWD);
1072
1073#ifdef DIAGNOSTIC
1074 if (done_qno == ADV_QLINK_END) {
1075 panic("adv_qdone: Corrupted SG "
1076 "list encountered");
1077 }
1078#endif
1079 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1080
1081 /* Mark SG queue as free */
1082 adv_write_lram_8(adv, done_qaddr
1083 + ADV_SCSIQ_B_STATUS, QS_FREE);
1084 }
1085 } else
1086 sg_queue_cnt = 0;
1087#ifdef DIAGNOSTIC
1088 if (adv->cur_active < (sg_queue_cnt + 1))
1089 panic("adv_qdone: Attempting to free more "
1090 "queues than are active");
1091#endif
1092 adv->cur_active -= sg_queue_cnt + 1;
1093
1094 aborted = (scsiq.q_status & QS_ABORTED) != 0;
1095
1096 if ((scsiq.q_status != QS_DONE)
1097 && (scsiq.q_status & QS_ABORTED) == 0)
1098 panic("adv_qdone: completed scsiq with unknown status");
1099
1100 scsiq.remain_bytes += scsiq.extra_bytes;
1101
1102 if ((scsiq.d3.done_stat == QD_WITH_ERROR) &&
1103 (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) {
1104 if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) {
1105 scsiq.d3.done_stat = QD_NO_ERROR;
1106 scsiq.d3.host_stat = QHSTA_NO_ERROR;
1107 }
1108 }
1109
1110 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index];
1111 ccb = cinfo->ccb;
1112 ccb->csio.resid = scsiq.remain_bytes;
1113 adv_done(adv, ccb,
1114 scsiq.d3.done_stat, scsiq.d3.host_stat,
1115 scsiq.d3.scsi_stat, scsiq.q_no);
1116
1117 doneq_head = done_qno;
1118 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD);
1119 }
1120 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head);
1121}
1122
1123
1124void
1125adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat,
1126 u_int host_stat, u_int scsi_status, u_int q_no)
1127{
1128 struct adv_ccb_info *cinfo;
1129
1130 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
1131 LIST_REMOVE(&ccb->ccb_h, sim_links.le);
1132 untimeout(adv_timeout, ccb, ccb->ccb_h.timeout_ch);
1133 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1134 bus_dmasync_op_t op;
1135
1136 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1137 op = BUS_DMASYNC_POSTREAD;
1138 else
1139 op = BUS_DMASYNC_POSTWRITE;
1140 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
1141 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
1142 }
1143
1144 switch (done_stat) {
1145 case QD_NO_ERROR:
1146 if (host_stat == QHSTA_NO_ERROR) {
1147 ccb->ccb_h.status = CAM_REQ_CMP;
1148 break;
1149 }
1150 xpt_print_path(ccb->ccb_h.path);
1151 printf("adv_done - queue done without error, "
1152 "but host status non-zero(%x)\n", host_stat);
1153 /*FALLTHROUGH*/
1154 case QD_WITH_ERROR:
1155 switch (host_stat) {
1156 case QHSTA_M_TARGET_STATUS_BUSY:
1157 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY:
1158 /*
1159 * Assume that if we were a tagged transaction
1160 * the target reported queue full. Otherwise,
1161 * report busy. The firmware really should just
1162 * pass the original status back up to us even
1163 * if it thinks the target was in error for
1164 * returning this status as no other transactions
1165 * from this initiator are in effect, but this
1166 * ignores multi-initiator setups and there is
1167 * evidence that the firmware gets its per-device
1168 * transaction counts screwed up occassionally.
1169 */
1170 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1171 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
1172 && host_stat != QHSTA_M_TARGET_STATUS_BUSY)
1173 scsi_status = SCSI_STATUS_QUEUE_FULL;
1174 else
1175 scsi_status = SCSI_STATUS_BUSY;
1176 adv_abort_ccb(adv, ccb->ccb_h.target_id,
1177 ccb->ccb_h.target_lun,
1178 /*ccb*/NULL, CAM_REQUEUE_REQ,
1179 /*queued_only*/TRUE);
1180 /*FALLTHROUGH*/
1181 case QHSTA_M_NO_AUTO_REQ_SENSE:
1182 case QHSTA_NO_ERROR:
1183 ccb->csio.scsi_status = scsi_status;
1184 switch (scsi_status) {
1185 case SCSI_STATUS_CHECK_COND:
1186 case SCSI_STATUS_CMD_TERMINATED:
1187 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1188 /* Structure copy */
1189 ccb->csio.sense_data =
1190 adv->sense_buffers[q_no - 1];
1191 /* FALLTHROUGH */
1192 case SCSI_STATUS_BUSY:
1193 case SCSI_STATUS_RESERV_CONFLICT:
1194 case SCSI_STATUS_QUEUE_FULL:
1195 case SCSI_STATUS_COND_MET:
1196 case SCSI_STATUS_INTERMED:
1197 case SCSI_STATUS_INTERMED_COND_MET:
1198 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1199 break;
1200 case SCSI_STATUS_OK:
1201 ccb->ccb_h.status |= CAM_REQ_CMP;
1202 break;
1203 }
1204 break;
1205 case QHSTA_M_SEL_TIMEOUT:
1206 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1207 break;
1208 case QHSTA_M_DATA_OVER_RUN:
1209 ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1210 break;
1211 case QHSTA_M_UNEXPECTED_BUS_FREE:
1212 ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1213 break;
1214 case QHSTA_M_BAD_BUS_PHASE_SEQ:
1215 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1216 break;
1217 case QHSTA_M_BAD_CMPL_STATUS_IN:
1218 /* No command complete after a status message */
1219 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1220 break;
1221 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT:
1222 case QHSTA_M_WTM_TIMEOUT:
1223 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET:
1224 /* The SCSI bus hung in a phase */
1225 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1226 adv_reset_bus(adv, /*initiate_reset*/TRUE);
1227 break;
1228 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1229 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1230 break;
1231 case QHSTA_D_QDONE_SG_LIST_CORRUPTED:
1232 case QHSTA_D_ASC_DVC_ERROR_CODE_SET:
1233 case QHSTA_D_HOST_ABORT_FAILED:
1234 case QHSTA_D_EXE_SCSI_Q_FAILED:
1235 case QHSTA_D_ASPI_NO_BUF_POOL:
1236 case QHSTA_M_BAD_TAG_CODE:
1237 case QHSTA_D_LRAM_CMP_ERROR:
1238 case QHSTA_M_MICRO_CODE_ERROR_HALT:
1239 default:
1240 panic("%s: Unhandled Host status error %x",
1241 adv_name(adv), host_stat);
1242 /* NOTREACHED */
1243 }
1244 break;
1245
1246 case QD_ABORTED_BY_HOST:
1247 /* Don't clobber any, more explicit, error codes we've set */
1248 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG)
1249 ccb->ccb_h.status = CAM_REQ_ABORTED;
1250 break;
1251
1252 default:
1253 xpt_print_path(ccb->ccb_h.path);
1254 printf("adv_done - queue done with unknown status %x:%x\n",
1255 done_stat, host_stat);
1256 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
1257 break;
1258 }
1259 adv_clear_state(adv, ccb);
1260 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP
1261 && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
1262 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1263 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1264 }
1265 adv_free_ccb_info(adv, cinfo);
1266 /*
1267 * Null this out so that we catch driver bugs that cause a
1268 * ccb to be completed twice.
1269 */
1270 ccb->ccb_h.ccb_cinfo_ptr = NULL;
1271 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
1272 xpt_done(ccb);
1273}
1274
1275/*
1276 * Function to poll for command completion when
1277 * interrupts are disabled (crash dumps)
1278 */
1279static void
1280adv_poll(struct cam_sim *sim)
1281{
1282 adv_intr(cam_sim_softc(sim));
1283}
1284
1285/*
1286 * Attach all the sub-devices we can find
1287 */
1288int
1289adv_attach(adv)
1290 struct adv_softc *adv;
1291{
1292 struct ccb_setasync csa;
1293 struct cam_devq *devq;
1294 int max_sg;
1295
1296 /*
1297 * Allocate an array of ccb mapping structures. We put the
1298 * index of the ccb_info structure into the queue representing
1299 * a transaction and use it for mapping the queue to the
1300 * upper level SCSI transaction it represents.
1301 */
1302 adv->ccb_infos = malloc(sizeof(*adv->ccb_infos) * adv->max_openings,
1303 M_DEVBUF, M_NOWAIT);
1304
1305 if (adv->ccb_infos == NULL)
1306 goto error_exit;
1307
1308 adv->init_level++;
1309
1310 /*
1311 * Create our DMA tags. These tags define the kinds of device
1312 * accessable memory allocations and memory mappings we will
1313 * need to perform during normal operation.
1314 *
1315 * Unless we need to further restrict the allocation, we rely
1316 * on the restrictions of the parent dmat, hence the common
1317 * use of MAXADDR and MAXSIZE.
1318 *
1319 * The ASC boards use chains of "queues" (the transactional
1320 * resources on the board) to represent long S/G lists.
1321 * The first queue represents the command and holds a
1322 * single address and data pair. The queues that follow
1323 * can each hold ADV_SG_LIST_PER_Q entries. Given the
1324 * total number of queues, we can express the largest
1325 * transaction we can map. We reserve a few queues for
1326 * error recovery. Take those into account as well.
1327 *
1328 * There is a way to take an interrupt to download the
1329 * next batch of S/G entries if there are more than 255
1330 * of them (the counter in the queue structure is a u_int8_t).
1331 * We don't use this feature, so limit the S/G list size
1332 * accordingly.
1333 */
1334 max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q;
1335 if (max_sg > 255)
1336 max_sg = 255;
1337
1338 /* DMA tag for mapping buffers into device visible space. */
1339 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1340 /*lowaddr*/BUS_SPACE_MAXADDR,
1341 /*highaddr*/BUS_SPACE_MAXADDR,
1342 /*filter*/NULL, /*filterarg*/NULL,
1343 /*maxsize*/MAXPHYS,
1344 /*nsegments*/max_sg,
1345 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1346 /*flags*/BUS_DMA_ALLOCNOW,
1347 &adv->buffer_dmat) != 0) {
1348 goto error_exit;
1349 }
1350 adv->init_level++;
1351
1352 /* DMA tag for our sense buffers */
1353 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1354 /*lowaddr*/BUS_SPACE_MAXADDR,
1355 /*highaddr*/BUS_SPACE_MAXADDR,
1356 /*filter*/NULL, /*filterarg*/NULL,
1357 sizeof(struct scsi_sense_data)*adv->max_openings,
1358 /*nsegments*/1,
1359 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1360 /*flags*/0, &adv->sense_dmat) != 0) {
1361 goto error_exit;
1362 }
1363
1364 adv->init_level++;
1365
1366 /* Allocation for our sense buffers */
1367 if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers,
1368 BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) {
1369 goto error_exit;
1370 }
1371
1372 adv->init_level++;
1373
1374 /* And permanently map them */
1375 bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap,
1376 adv->sense_buffers,
1377 sizeof(struct scsi_sense_data)*adv->max_openings,
1378 adv_map, &adv->sense_physbase, /*flags*/0);
1379
1380 adv->init_level++;
1381
1382 /*
1383 * Fire up the chip
1384 */
1385 if (adv_start_chip(adv) != 1) {
1386 printf("adv%d: Unable to start on board processor. Aborting.\n",
1387 adv->unit);
1388 return (0);
1389 }
1390
1391 /*
1392 * Create the device queue for our SIM.
1393 */
1394 devq = cam_simq_alloc(adv->max_openings);
1395 if (devq == NULL)
1396 return (0);
1397
1398 /*
1399 * Construct our SIM entry.
1400 */
1401 adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit,
1402 1, adv->max_openings, devq);
1403 if (adv->sim == NULL)
1404 return (0);
1405
1406 /*
1407 * Register the bus.
1408 *
1409 * XXX Twin Channel EISA Cards???
1410 */
1411 if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) {
1412 cam_sim_free(adv->sim, /*free devq*/TRUE);
1413 return (0);
1414 }
1415
1416 if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim),
1417 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1418 == CAM_REQ_CMP) {
1419 xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5);
1420 csa.ccb_h.func_code = XPT_SASYNC_CB;
1421 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
1422 csa.callback = advasync;
1423 csa.callback_arg = adv;
1424 xpt_action((union ccb *)&csa);
1425 }
1426 return (1);
1427
1428error_exit:
1429 return (0);
1430}
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