1/*
2 * Generic driver for the Advanced Systems Inc. SCSI controllers
3 * Product specific probe and attach routines can be found in:
4 *
5 * i386/isa/adv_isa.c ABP5140, ABP542, ABP5150, ABP842, ABP852
6 * i386/eisa/adv_eisa.c ABP742, ABP752
7 * pci/adv_pci.c ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U,
8 * ABP940UA, ABP950, ABP960, ABP960U, ABP960UA,
9 * ABP970, ABP970U
10 *
11 * Copyright (c) 1996-2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification, immediately at the beginning of the file.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $FreeBSD: head/sys/dev/advansys/advansys.c 56926 2000-02-01 00:43:58Z gibbs $
36 */
37/*
38 * Ported from:
39 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
40 *
41 * Copyright (c) 1995-1997 Advanced System Products, Inc.
42 * All Rights Reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that redistributions of source
46 * code retain the above copyright notice and this comment without
47 * modification.
48 */
49
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/malloc.h>
53#include <sys/buf.h>
54#include <sys/kernel.h>
55
56#include <machine/bus_pio.h>
57#include <machine/bus.h>
58#include <machine/clock.h>
59
60#include <cam/cam.h>
61#include <cam/cam_ccb.h>
62#include <cam/cam_sim.h>
63#include <cam/cam_xpt_sim.h>
64#include <cam/cam_xpt_periph.h>
65#include <cam/cam_debug.h>
66
67#include <cam/scsi/scsi_all.h>
68#include <cam/scsi/scsi_message.h>
69
70#include <vm/vm.h>
71#include <vm/vm_param.h>
72#include <vm/pmap.h>
73
74#include <dev/advansys/advansys.h>
75
76u_long adv_unit;
77
78static void adv_action(struct cam_sim *sim, union ccb *ccb);
79static void adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
80 int nsegments, int error);
81static void adv_poll(struct cam_sim *sim);
82static void adv_run_doneq(struct adv_softc *adv);
83static struct adv_ccb_info *
84 adv_alloc_ccb_info(struct adv_softc *adv);
85static void adv_destroy_ccb_info(struct adv_softc *adv,
86 struct adv_ccb_info *cinfo);
87static __inline struct adv_ccb_info *
88 adv_get_ccb_info(struct adv_softc *adv);
89static __inline void adv_free_ccb_info(struct adv_softc *adv,
90 struct adv_ccb_info *cinfo);
91static __inline void adv_set_state(struct adv_softc *adv, adv_state state);
92static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb);
93static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb);
94
95struct adv_softc *advsoftcs[NADV]; /* XXX Config should handle this */
96
97static __inline struct adv_ccb_info *
98adv_get_ccb_info(struct adv_softc *adv)
99{
100 struct adv_ccb_info *cinfo;
101 int opri;
102
103 opri = splcam();
104 if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
105 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
106 } else {
107 cinfo = adv_alloc_ccb_info(adv);
108 }
109 splx(opri);
110
111 return (cinfo);
112}
113
114static __inline void
115adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
116{
117 int opri;
118
119 opri = splcam();
120 cinfo->state = ACCB_FREE;
121 SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links);
122 splx(opri);
123}
124
125static __inline void
126adv_set_state(struct adv_softc *adv, adv_state state)
127{
128 if (adv->state == 0)
129 xpt_freeze_simq(adv->sim, /*count*/1);
130 adv->state |= state;
131}
132
133static __inline void
134adv_clear_state(struct adv_softc *adv, union ccb* ccb)
135{
136 if (adv->state != 0)
137 adv_clear_state_really(adv, ccb);
138}
139
140static void
141adv_clear_state_really(struct adv_softc *adv, union ccb* ccb)
142{
143 if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0)
144 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK);
145 if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) {
146 int openings;
147
148 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q;
149 if (openings >= adv->openings_needed) {
150 adv->state &= ~ADV_RESOURCE_SHORTAGE;
151 adv->openings_needed = 0;
152 }
153 }
154
155 if ((adv->state & ADV_IN_TIMEOUT) != 0) {
156 struct adv_ccb_info *cinfo;
157
158 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
159 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) {
160 struct ccb_hdr *ccb_h;
161
162 /*
163 * We now traverse our list of pending CCBs
164 * and reinstate their timeouts.
165 */
166 ccb_h = LIST_FIRST(&adv->pending_ccbs);
167 while (ccb_h != NULL) {
168 ccb_h->timeout_ch =
169 timeout(adv_timeout, (caddr_t)ccb_h,
170 (ccb_h->timeout * hz) / 1000);
171 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
172 }
173 adv->state &= ~ADV_IN_TIMEOUT;
174 printf("%s: No longer in timeout\n", adv_name(adv));
175 }
176 }
177 if (adv->state == 0)
178 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
179}
180
181void
182adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
183{
184 bus_addr_t* physaddr;
185
186 physaddr = (bus_addr_t*)arg;
187 *physaddr = segs->ds_addr;
188}
189
190char *
191adv_name(struct adv_softc *adv)
192{
193 static char name[10];
194
195 snprintf(name, sizeof(name), "adv%d", adv->unit);
196 return (name);
197}
198
199static void
200adv_action(struct cam_sim *sim, union ccb *ccb)
201{
202 struct adv_softc *adv;
203
204 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n"));
205
206 adv = (struct adv_softc *)cam_sim_softc(sim);
207
208 switch (ccb->ccb_h.func_code) {
209 /* Common cases first */
210 case XPT_SCSI_IO: /* Execute the requested I/O operation */
211 {
212 struct ccb_hdr *ccb_h;
213 struct ccb_scsiio *csio;
214 struct adv_ccb_info *cinfo;
215
216 ccb_h = &ccb->ccb_h;
217 csio = &ccb->csio;
218 cinfo = adv_get_ccb_info(adv);
219 if (cinfo == NULL)
220 panic("XXX Handle CCB info error!!!");
221
222 ccb_h->ccb_cinfo_ptr = cinfo;
223 cinfo->ccb = ccb;
224
225 /* Only use S/G if there is a transfer */
226 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
227 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
228 /*
229 * We've been given a pointer
230 * to a single buffer
231 */
232 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
233 int s;
234 int error;
235
236 s = splsoftvm();
237 error =
238 bus_dmamap_load(adv->buffer_dmat,
239 cinfo->dmamap,
240 csio->data_ptr,
241 csio->dxfer_len,
242 adv_execute_ccb,
243 csio, /*flags*/0);
244 if (error == EINPROGRESS) {
245 /*
246 * So as to maintain ordering,
247 * freeze the controller queue
248 * until our mapping is
249 * returned.
250 */
251 adv_set_state(adv,
252 ADV_BUSDMA_BLOCK);
253 }
254 splx(s);
255 } else {
256 struct bus_dma_segment seg;
257
258 /* Pointer to physical buffer */
259 seg.ds_addr =
260 (bus_addr_t)csio->data_ptr;
261 seg.ds_len = csio->dxfer_len;
262 adv_execute_ccb(csio, &seg, 1, 0);
263 }
264 } else {
265 struct bus_dma_segment *segs;
266 if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
267 panic("adv_setup_data - Physical "
268 "segment pointers unsupported");
269
270 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
271 panic("adv_setup_data - Virtual "
272 "segment addresses unsupported");
273
274 /* Just use the segments provided */
275 segs = (struct bus_dma_segment *)csio->data_ptr;
276 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0);
277 }
278 } else {
279 adv_execute_ccb(ccb, NULL, 0, 0);
280 }
281 break;
282 }
283 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
284 case XPT_TARGET_IO: /* Execute target I/O request */
285 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
286 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
287 case XPT_EN_LUN: /* Enable LUN as a target */
288 case XPT_ABORT: /* Abort the specified CCB */
289 /* XXX Implement */
290 ccb->ccb_h.status = CAM_REQ_INVALID;
291 xpt_done(ccb);
292 break;
293 case XPT_SET_TRAN_SETTINGS:
294 {
295 struct ccb_trans_settings *cts;
296 target_bit_vector targ_mask;
297 struct adv_transinfo *tconf;
298 u_int update_type;
299 int s;
300
301 cts = &ccb->cts;
302 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
303 update_type = 0;
304
305 /*
306 * The user must specify which type of settings he wishes
307 * to change.
308 */
309 if (((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
310 && ((cts->flags & CCB_TRANS_USER_SETTINGS) == 0)) {
311 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
312 update_type |= ADV_TRANS_GOAL;
313 } else if (((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
314 && ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) == 0)) {
315 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
316 update_type |= ADV_TRANS_USER;
317 } else {
318 ccb->ccb_h.status = CAM_REQ_INVALID;
319 break;
320 }
321
322 s = splcam();
323
324 if ((update_type & ADV_TRANS_GOAL) != 0) {
325 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
326 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
327 adv->disc_enable |= targ_mask;
328 else
329 adv->disc_enable &= ~targ_mask;
330 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B,
331 adv->disc_enable);
332 }
333
334 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
335 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
336 adv->cmd_qng_enabled |= targ_mask;
337 else
338 adv->cmd_qng_enabled &= ~targ_mask;
339 }
340 }
341
342 if ((update_type & ADV_TRANS_USER) != 0) {
343 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
344 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
345 adv->user_disc_enable |= targ_mask;
346 else
347 adv->user_disc_enable &= ~targ_mask;
348 }
349
350 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
351 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
352 adv->user_cmd_qng_enabled |= targ_mask;
353 else
354 adv->user_cmd_qng_enabled &= ~targ_mask;
355 }
356 }
357
358 /*
359 * If the user specifies either the sync rate, or offset,
360 * but not both, the unspecified parameter defaults to its
361 * current value in transfer negotiations.
362 */
363 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
364 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
365 /*
366 * If the user provided a sync rate but no offset,
367 * use the current offset.
368 */
369 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0)
370 cts->sync_offset = tconf->offset;
371
372 /*
373 * If the user provided an offset but no sync rate,
374 * use the current sync rate.
375 */
376 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0)
377 cts->sync_period = tconf->period;
378
379 adv_period_offset_to_sdtr(adv, &cts->sync_period,
380 &cts->sync_offset,
381 cts->ccb_h.target_id);
382
383 adv_set_syncrate(adv, /*struct cam_path */NULL,
384 cts->ccb_h.target_id, cts->sync_period,
385 cts->sync_offset, update_type);
386 }
387
388 splx(s);
389 ccb->ccb_h.status = CAM_REQ_CMP;
390 xpt_done(ccb);
391 break;
392 }
393 case XPT_GET_TRAN_SETTINGS:
394 /* Get default/user set transfer settings for the target */
395 {
396 struct ccb_trans_settings *cts;
397 struct adv_transinfo *tconf;
398 target_bit_vector target_mask;
399 int s;
400
401 cts = &ccb->cts;
402 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
403
404 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
405
406 s = splcam();
407 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
408 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
409 if ((adv->disc_enable & target_mask) != 0)
410 cts->flags |= CCB_TRANS_DISC_ENB;
411 if ((adv->cmd_qng_enabled & target_mask) != 0)
412 cts->flags |= CCB_TRANS_TAG_ENB;
413 } else {
414 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
415 if ((adv->user_disc_enable & target_mask) != 0)
416 cts->flags |= CCB_TRANS_DISC_ENB;
417 if ((adv->user_cmd_qng_enabled & target_mask) != 0)
418 cts->flags |= CCB_TRANS_TAG_ENB;
419 }
420
421 cts->sync_period = tconf->period;
422 cts->sync_offset = tconf->offset;
423 splx(s);
424
425 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
426 cts->valid = CCB_TRANS_SYNC_RATE_VALID
427 | CCB_TRANS_SYNC_OFFSET_VALID
428 | CCB_TRANS_BUS_WIDTH_VALID
429 | CCB_TRANS_DISC_VALID
430 | CCB_TRANS_TQ_VALID;
431 ccb->ccb_h.status = CAM_REQ_CMP;
432 xpt_done(ccb);
433 break;
434 }
435 case XPT_CALC_GEOMETRY:
436 {
437 struct ccb_calc_geometry *ccg;
438 u_int32_t size_mb;
439 u_int32_t secs_per_cylinder;
440 int extended;
441
442 ccg = &ccb->ccg;
443 size_mb = ccg->volume_size
444 / ((1024L * 1024L) / ccg->block_size);
445 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0;
446
447 if (size_mb > 1024 && extended) {
448 ccg->heads = 255;
449 ccg->secs_per_track = 63;
450 } else {
451 ccg->heads = 64;
452 ccg->secs_per_track = 32;
453 }
454 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
455 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
456 ccb->ccb_h.status = CAM_REQ_CMP;
457 xpt_done(ccb);
458 break;
459 }
460 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
461 {
462 int s;
463
464 s = splcam();
465 adv_stop_execution(adv);
466 adv_reset_bus(adv, /*initiate_reset*/TRUE);
467 adv_start_execution(adv);
468 splx(s);
469
470 ccb->ccb_h.status = CAM_REQ_CMP;
471 xpt_done(ccb);
472 break;
473 }
474 case XPT_TERM_IO: /* Terminate the I/O process */
475 /* XXX Implement */
476 ccb->ccb_h.status = CAM_REQ_INVALID;
477 xpt_done(ccb);
478 break;
479 case XPT_PATH_INQ: /* Path routing inquiry */
480 {
481 struct ccb_pathinq *cpi = &ccb->cpi;
482
483 cpi->version_num = 1; /* XXX??? */
484 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
485 cpi->target_sprt = 0;
486 cpi->hba_misc = 0;
487 cpi->hba_eng_cnt = 0;
488 cpi->max_target = 7;
489 cpi->max_lun = 7;
490 cpi->initiator_id = adv->scsi_id;
491 cpi->bus_id = cam_sim_bus(sim);
492 cpi->base_transfer_speed = 3300;
493 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
494 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN);
495 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
496 cpi->unit_number = cam_sim_unit(sim);
497 cpi->ccb_h.status = CAM_REQ_CMP;
498 xpt_done(ccb);
499 break;
500 }
501 default:
502 ccb->ccb_h.status = CAM_REQ_INVALID;
503 xpt_done(ccb);
504 break;
505 }
506}
507
508/*
509 * Currently, the output of bus_dmammap_load suits our needs just
510 * fine, but should it change, we'd need to do something here.
511 */
512#define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs)
513
514static void
515adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
516 int nsegments, int error)
517{
518 struct ccb_scsiio *csio;
519 struct ccb_hdr *ccb_h;
520 struct cam_sim *sim;
521 struct adv_softc *adv;
522 struct adv_ccb_info *cinfo;
523 struct adv_scsi_q scsiq;
524 struct adv_sg_head sghead;
525 int s;
526
527 csio = (struct ccb_scsiio *)arg;
528 ccb_h = &csio->ccb_h;
529 sim = xpt_path_sim(ccb_h->path);
530 adv = (struct adv_softc *)cam_sim_softc(sim);
531 cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr;
532
533 /*
534 * Setup our done routine to release the simq on
535 * the next ccb that completes.
536 */
537 if ((adv->state & ADV_BUSDMA_BLOCK) != 0)
538 adv->state |= ADV_BUSDMA_BLOCK_CLEARED;
539
540 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) {
541 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) {
542 /* XXX Need phystovirt!!!! */
543 /* How about pmap_kenter??? */
544 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
545 } else {
546 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
547 }
548 } else {
549 scsiq.cdbptr = csio->cdb_io.cdb_bytes;
550 }
551 /*
552 * Build up the request
553 */
554 scsiq.q1.status = 0;
555 scsiq.q1.q_no = 0;
556 scsiq.q1.cntl = 0;
557 scsiq.q1.sg_queue_cnt = 0;
558 scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id);
559 scsiq.q1.target_lun = ccb_h->target_lun;
560 scsiq.q1.sense_len = csio->sense_len;
561 scsiq.q1.extra_bytes = 0;
562 scsiq.q2.ccb_index = cinfo - adv->ccb_infos;
563 scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id,
564 ccb_h->target_lun);
565 scsiq.q2.flag = 0;
566 scsiq.q2.cdb_len = csio->cdb_len;
567 if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0)
568 scsiq.q2.tag_code = csio->tag_action;
569 else
570 scsiq.q2.tag_code = 0;
571 scsiq.q2.vm_id = 0;
572
573 if (nsegments != 0) {
574 bus_dmasync_op_t op;
575
576 scsiq.q1.data_addr = dm_segs->ds_addr;
577 scsiq.q1.data_cnt = dm_segs->ds_len;
578 if (nsegments > 1) {
579 scsiq.q1.cntl |= QC_SG_HEAD;
580 sghead.entry_cnt
581 = sghead.entry_to_copy
582 = nsegments;
583 sghead.res = 0;
584 sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs);
585 scsiq.sg_head = &sghead;
586 } else {
587 scsiq.sg_head = NULL;
588 }
589 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN)
590 op = BUS_DMASYNC_PREREAD;
591 else
592 op = BUS_DMASYNC_PREWRITE;
593 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
594 } else {
595 scsiq.q1.data_addr = 0;
596 scsiq.q1.data_cnt = 0;
597 scsiq.sg_head = NULL;
598 }
599
600 s = splcam();
601
602 /*
603 * Last time we need to check if this SCB needs to
604 * be aborted.
605 */
606 if (ccb_h->status != CAM_REQ_INPROG) {
607 if (nsegments != 0)
608 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
609 adv_clear_state(adv, (union ccb *)csio);
610 adv_free_ccb_info(adv, cinfo);
611 xpt_done((union ccb *)csio);
612 splx(s);
613 return;
614 }
615
616 if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) {
617 /* Temporary resource shortage */
618 adv_set_state(adv, ADV_RESOURCE_SHORTAGE);
619 if (nsegments != 0)
620 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
621 csio->ccb_h.status = CAM_REQUEUE_REQ;
622 adv_clear_state(adv, (union ccb *)csio);
623 adv_free_ccb_info(adv, cinfo);
624 xpt_done((union ccb *)csio);
625 splx(s);
626 return;
627 }
628 cinfo->state |= ACCB_ACTIVE;
629 ccb_h->status |= CAM_SIM_QUEUED;
630 LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le);
631 /* Schedule our timeout */
632 ccb_h->timeout_ch =
633 timeout(adv_timeout, csio, (ccb_h->timeout * hz)/1000);
634 splx(s);
635}
636
637static struct adv_ccb_info *
638adv_alloc_ccb_info(struct adv_softc *adv)
639{
640 int error;
641 struct adv_ccb_info *cinfo;
642
643 cinfo = &adv->ccb_infos[adv->ccb_infos_allocated];
644 cinfo->state = ACCB_FREE;
645 error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0,
646 &cinfo->dmamap);
647 if (error != 0) {
648 printf("%s: Unable to allocate CCB info "
649 "dmamap - error %d\n", adv_name(adv), error);
650 return (NULL);
651 }
652 adv->ccb_infos_allocated++;
653 return (cinfo);
654}
655
656static void
657adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
658{
659 bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap);
660}
661
662void
663adv_timeout(void *arg)
664{
665 int s;
666 union ccb *ccb;
667 struct adv_softc *adv;
668 struct adv_ccb_info *cinfo;
669
670 ccb = (union ccb *)arg;
671 adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc;
672 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
673
674 xpt_print_path(ccb->ccb_h.path);
675 printf("Timed out\n");
676
677 s = splcam();
678 /* Have we been taken care of already?? */
679 if (cinfo == NULL || cinfo->state == ACCB_FREE) {
680 splx(s);
681 return;
682 }
683
684 adv_stop_execution(adv);
685
686 if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) {
687 struct ccb_hdr *ccb_h;
688
689 /*
690 * In order to simplify the recovery process, we ask the XPT
691 * layer to halt the queue of new transactions and we traverse
692 * the list of pending CCBs and remove their timeouts. This
693 * means that the driver attempts to clear only one error
694 * condition at a time. In general, timeouts that occur
695 * close together are related anyway, so there is no benefit
696 * in attempting to handle errors in parrallel. Timeouts will
697 * be reinstated when the recovery process ends.
698 */
699 adv_set_state(adv, ADV_IN_TIMEOUT);
700
701 /* This CCB is the CCB representing our recovery actions */
702 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED;
703
704 ccb_h = LIST_FIRST(&adv->pending_ccbs);
705 while (ccb_h != NULL) {
706 untimeout(adv_timeout, ccb_h, ccb_h->timeout_ch);
707 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
708 }
709
710 /* XXX Should send a BDR */
711 /* Attempt an abort as our first tact */
712 xpt_print_path(ccb->ccb_h.path);
713 printf("Attempting abort\n");
714 adv_abort_ccb(adv, ccb->ccb_h.target_id,
715 ccb->ccb_h.target_lun, ccb,
716 CAM_CMD_TIMEOUT, /*queued_only*/FALSE);
717 ccb->ccb_h.timeout_ch =
718 timeout(adv_timeout, ccb, 2 * hz);
719 } else {
720 /* Our attempt to perform an abort failed, go for a reset */
721 xpt_print_path(ccb->ccb_h.path);
722 printf("Resetting bus\n");
723 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
724 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
725 adv_reset_bus(adv, /*initiate_reset*/TRUE);
726 }
727 adv_start_execution(adv);
728 splx(s);
729}
730
731struct adv_softc *
732adv_alloc(int unit, bus_space_tag_t tag, bus_space_handle_t bsh)
733{
734 struct adv_softc *adv;
735
736 if (unit >= NADV) {
737 printf("adv: unit number (%d) too high\n", unit);
738 return NULL;
739 }
740
741 /*
742 * Allocate a storage area for us
743 */
744 if (advsoftcs[unit]) {
745 printf("adv%d: memory already allocated\n", unit);
746 return NULL;
747 }
748
749 adv = malloc(sizeof(struct adv_softc), M_DEVBUF, M_NOWAIT);
750 if (!adv) {
751 printf("adv%d: cannot malloc!\n", unit);
752 return NULL;
753 }
754 bzero(adv, sizeof(struct adv_softc));
755 LIST_INIT(&adv->pending_ccbs);
756 SLIST_INIT(&adv->free_ccb_infos);
757 advsoftcs[unit] = adv;
758 adv->unit = unit;
759 adv->tag = tag;
760 adv->bsh = bsh;
761
762 return(adv);
763}
764
765void
766adv_free(struct adv_softc *adv)
767{
768 switch (adv->init_level) {
769 case 6:
770 {
771 struct adv_ccb_info *cinfo;
772
773 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
774 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
775 adv_destroy_ccb_info(adv, cinfo);
776 }
777
778 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap);
779 }
780 case 5:
781 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers,
782 adv->sense_dmamap);
783 case 4:
784 bus_dma_tag_destroy(adv->sense_dmat);
785 case 3:
786 bus_dma_tag_destroy(adv->buffer_dmat);
787 case 2:
788 bus_dma_tag_destroy(adv->parent_dmat);
789 case 1:
790 free(adv->ccb_infos, M_DEVBUF);
791 case 0:
792 break;
793 }
794 free(adv, M_DEVBUF);
795}
796
797int
798adv_init(struct adv_softc *adv)
799{
800 struct adv_eeprom_config eeprom_config;
801 int checksum, i;
802 int max_sync;
803 u_int16_t config_lsw;
804 u_int16_t config_msw;
805
806 adv_lib_init(adv);
807
808 /*
809 * Stop script execution.
810 */
811 adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE);
812 adv_stop_execution(adv);
813 if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) {
814 printf("adv%d: Unable to halt adapter. Initialization"
815 "failed\n", adv->unit);
816 return (1);
817 }
818 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
819 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) {
820 printf("adv%d: Unable to set program counter. Initialization"
821 "failed\n", adv->unit);
822 return (1);
823 }
824
825 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
826 config_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
827
828 if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) {
829 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
830 /*
831 * XXX The Linux code flags this as an error,
832 * but what should we report to the user???
833 * It seems that clearing the config register
834 * makes this error recoverable.
835 */
836 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
837 }
838
839 /* Suck in the configuration from the EEProm */
840 checksum = adv_get_eeprom_config(adv, &eeprom_config);
841
842 if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) {
843 /*
844 * XXX The Linux code sets a warning level for this
845 * condition, yet nothing of meaning is printed to
846 * the user. What does this mean???
847 */
848 if (adv->chip_version == 3) {
849 if (eeprom_config.cfg_lsw != config_lsw)
850 eeprom_config.cfg_lsw = config_lsw;
851 if (eeprom_config.cfg_msw != config_msw) {
852 eeprom_config.cfg_msw = config_msw;
853 }
854 }
855 }
856 if (checksum == eeprom_config.chksum) {
857
858 /* Range/Sanity checking */
859 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) {
860 eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG;
861 }
862 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) {
863 eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG;
864 }
865 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) {
866 eeprom_config.max_tag_qng = eeprom_config.max_total_qng;
867 }
868 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) {
869 eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC;
870 }
871 adv->max_openings = eeprom_config.max_total_qng;
872 adv->user_disc_enable = eeprom_config.disc_enable;
873 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng;
874 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config);
875 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID;
876 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id);
877 adv->control = eeprom_config.cntl;
878 for (i = 0; i <= ADV_MAX_TID; i++) {
879 u_int8_t sync_data;
880
881 if ((eeprom_config.init_sdtr & (0x1 << i)) == 0)
882 sync_data = 0;
883 else
884 sync_data = eeprom_config.sdtr_data[i];
885 adv_sdtr_to_period_offset(adv,
886 sync_data,
887 &adv->tinfo[i].user.period,
888 &adv->tinfo[i].user.offset,
889 i);
890 }
891 config_lsw = eeprom_config.cfg_lsw;
892 eeprom_config.cfg_msw = config_msw;
893 } else {
894 u_int8_t sync_data;
895
896 printf("adv%d: Warning EEPROM Checksum mismatch. "
897 "Using default device parameters\n", adv->unit);
898
899 /* Set reasonable defaults since we can't read the EEPROM */
900 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1;
901 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG;
902 adv->disc_enable = TARGET_BIT_VECTOR_SET;
903 adv->user_disc_enable = TARGET_BIT_VECTOR_SET;
904 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
905 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
906 adv->scsi_id = 7;
907 adv->control = 0xFFFF;
908
909 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
910 /* Default to no Ultra to support the 3030 */
911 adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA;
912 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4);
913 for (i = 0; i <= ADV_MAX_TID; i++) {
914 adv_sdtr_to_period_offset(adv, sync_data,
915 &adv->tinfo[i].user.period,
916 &adv->tinfo[i].user.offset,
917 i);
918 }
919 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON;
920 }
921 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
922 config_lsw |= ADV_CFG_LSW_HOST_INT_ON;
923 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)
924 && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0)
925 /* 25ns or 10MHz */
926 max_sync = 25;
927 else
928 /* Unlimited */
929 max_sync = 0;
930 for (i = 0; i <= ADV_MAX_TID; i++) {
931 if (adv->tinfo[i].user.period < max_sync)
932 adv->tinfo[i].user.period = max_sync;
933 }
934
935 if (adv_test_external_lram(adv) == 0) {
936 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) {
937 eeprom_config.max_total_qng =
938 ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
939 eeprom_config.max_tag_qng =
940 ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG;
941 } else {
942 eeprom_config.cfg_msw |= 0x0800;
943 config_msw |= 0x0800;
944 eeprom_config.max_total_qng =
945 ADV_MAX_PCI_INRAM_TOTAL_QNG;
946 eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG;
947 }
948 adv->max_openings = eeprom_config.max_total_qng;
949 }
950 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
951 ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw);
952#if 0
953 /*
954 * Don't write the eeprom data back for now.
955 * I'd rather not mess up the user's card. We also don't
956 * fully sanitize the eeprom settings above for the write-back
957 * to be 100% correct.
958 */
959 if (adv_set_eeprom_config(adv, &eeprom_config) != 0)
960 printf("%s: WARNING! Failure writing to EEPROM.\n",
961 adv_name(adv));
962#endif
963
964 adv_set_chip_scsiid(adv, adv->scsi_id);
965 if (adv_init_lram_and_mcode(adv))
966 return (1);
967
968 adv->disc_enable = adv->user_disc_enable;
969
970 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable);
971 for (i = 0; i <= ADV_MAX_TID; i++) {
972 /*
973 * Start off in async mode.
974 */
975 adv_set_syncrate(adv, /*struct cam_path */NULL,
976 i, /*period*/0, /*offset*/0,
977 ADV_TRANS_CUR);
978 /*
979 * Enable the use of tagged commands on all targets.
980 * This allows the kernel driver to make up it's own mind
981 * as it sees fit to tag queue instead of having the
982 * firmware try and second guess the tag_code settins.
983 */
984 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i,
985 adv->max_openings);
986 }
987 adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
988 adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
989 printf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n",
990 adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0)
991 ? "Ultra SCSI" : "SCSI",
992 adv->scsi_id, adv->max_openings);
993 return (0);
994}
995
996void
997adv_intr(void *arg)
998{
999 struct adv_softc *adv;
1000 u_int16_t chipstat;
1001 u_int16_t saved_ram_addr;
1002 u_int8_t ctrl_reg;
1003 u_int8_t saved_ctrl_reg;
1004 u_int8_t host_flag;
1005
1006 adv = (struct adv_softc *)arg;
1007
1008 chipstat = ADV_INW(adv, ADV_CHIP_STATUS);
1009
1010 /* Is it for us? */
1011 if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0)
1012 return;
1013
1014 ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL);
1015 saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET |
1016 ADV_CC_SINGLE_STEP | ADV_CC_DIAG |
1017 ADV_CC_TEST));
1018
1019 if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) {
1020 printf("Detected Bus Reset\n");
1021 adv_reset_bus(adv, /*initiate_reset*/FALSE);
1022 return;
1023 }
1024
1025 if ((chipstat & ADV_CSW_INT_PENDING) != 0) {
1026
1027 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR);
1028 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
1029 adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
1030 host_flag | ADV_HOST_FLAG_IN_ISR);
1031
1032 adv_ack_interrupt(adv);
1033
1034 if ((chipstat & ADV_CSW_HALTED) != 0
1035 && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) {
1036 adv_isr_chip_halted(adv);
1037 saved_ctrl_reg &= ~ADV_CC_HALT;
1038 } else {
1039 adv_run_doneq(adv);
1040 }
1041 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr);
1042#ifdef DIAGNOSTIC
1043 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr)
1044 panic("adv_intr: Unable to set LRAM addr");
1045#endif
1046 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
1047 }
1048
1049 ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg);
1050}
1051
1052void
1053adv_run_doneq(struct adv_softc *adv)
1054{
1055 struct adv_q_done_info scsiq;
1056 u_int doneq_head;
1057 u_int done_qno;
1058
1059 doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF;
1060 done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head)
1061 + ADV_SCSIQ_B_FWD);
1062 while (done_qno != ADV_QLINK_END) {
1063 union ccb* ccb;
1064 struct adv_ccb_info *cinfo;
1065 u_int done_qaddr;
1066 u_int sg_queue_cnt;
1067 int aborted;
1068
1069 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1070
1071 /* Pull status from this request */
1072 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq,
1073 adv->max_dma_count);
1074
1075 /* Mark it as free */
1076 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS,
1077 scsiq.q_status & ~(QS_READY|QS_ABORTED));
1078
1079 /* Process request based on retrieved info */
1080 if ((scsiq.cntl & QC_SG_HEAD) != 0) {
1081 u_int i;
1082
1083 /*
1084 * S/G based request. Free all of the queue
1085 * structures that contained S/G information.
1086 */
1087 for (i = 0; i < sg_queue_cnt; i++) {
1088 done_qno = adv_read_lram_8(adv, done_qaddr
1089 + ADV_SCSIQ_B_FWD);
1090
1091#ifdef DIAGNOSTIC
1092 if (done_qno == ADV_QLINK_END) {
1093 panic("adv_qdone: Corrupted SG "
1094 "list encountered");
1095 }
1096#endif
1097 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1098
1099 /* Mark SG queue as free */
1100 adv_write_lram_8(adv, done_qaddr
1101 + ADV_SCSIQ_B_STATUS, QS_FREE);
1102 }
1103 } else
1104 sg_queue_cnt = 0;
1105#ifdef DIAGNOSTIC
1106 if (adv->cur_active < (sg_queue_cnt + 1))
1107 panic("adv_qdone: Attempting to free more "
1108 "queues than are active");
1109#endif
1110 adv->cur_active -= sg_queue_cnt + 1;
1111
1112 aborted = (scsiq.q_status & QS_ABORTED) != 0;
1113
1114 if ((scsiq.q_status != QS_DONE)
1115 && (scsiq.q_status & QS_ABORTED) == 0)
1116 panic("adv_qdone: completed scsiq with unknown status");
1117
1118 scsiq.remain_bytes += scsiq.extra_bytes;
1119
1120 if ((scsiq.d3.done_stat == QD_WITH_ERROR) &&
1121 (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) {
1122 if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) {
1123 scsiq.d3.done_stat = QD_NO_ERROR;
1124 scsiq.d3.host_stat = QHSTA_NO_ERROR;
1125 }
1126 }
1127
1128 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index];
1129 ccb = cinfo->ccb;
1130 ccb->csio.resid = scsiq.remain_bytes;
1131 adv_done(adv, ccb,
1132 scsiq.d3.done_stat, scsiq.d3.host_stat,
1133 scsiq.d3.scsi_stat, scsiq.q_no);
1134
1135 doneq_head = done_qno;
1136 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD);
1137 }
1138 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head);
1139}
1140
1141
1142void
1143adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat,
1144 u_int host_stat, u_int scsi_status, u_int q_no)
1145{
1146 struct adv_ccb_info *cinfo;
1147
1148 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
1149 LIST_REMOVE(&ccb->ccb_h, sim_links.le);
1150 untimeout(adv_timeout, ccb, ccb->ccb_h.timeout_ch);
1151 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1152 bus_dmasync_op_t op;
1153
1154 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1155 op = BUS_DMASYNC_POSTREAD;
1156 else
1157 op = BUS_DMASYNC_POSTWRITE;
1158 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
1159 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
1160 }
1161
1162 switch (done_stat) {
1163 case QD_NO_ERROR:
1164 if (host_stat == QHSTA_NO_ERROR) {
1165 ccb->ccb_h.status = CAM_REQ_CMP;
1166 break;
1167 }
1168 xpt_print_path(ccb->ccb_h.path);
1169 printf("adv_done - queue done without error, "
1170 "but host status non-zero(%x)\n", host_stat);
1171 /*FALLTHROUGH*/
1172 case QD_WITH_ERROR:
1173 switch (host_stat) {
1174 case QHSTA_M_TARGET_STATUS_BUSY:
1175 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY:
1176 /*
1177 * Assume that if we were a tagged transaction
1178 * the target reported queue full. Otherwise,
1179 * report busy. The firmware really should just
1180 * pass the original status back up to us even
1181 * if it thinks the target was in error for
1182 * returning this status as no other transactions
1183 * from this initiator are in effect, but this
1184 * ignores multi-initiator setups and there is
1185 * evidence that the firmware gets its per-device
1186 * transaction counts screwed up occassionally.
1187 */
1188 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1189 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
1190 && host_stat != QHSTA_M_TARGET_STATUS_BUSY)
1191 scsi_status = SCSI_STATUS_QUEUE_FULL;
1192 else
1193 scsi_status = SCSI_STATUS_BUSY;
1194 adv_abort_ccb(adv, ccb->ccb_h.target_id,
1195 ccb->ccb_h.target_lun,
1196 /*ccb*/NULL, CAM_REQUEUE_REQ,
1197 /*queued_only*/TRUE);
1198 /*FALLTHROUGH*/
1199 case QHSTA_M_NO_AUTO_REQ_SENSE:
1200 case QHSTA_NO_ERROR:
1201 ccb->csio.scsi_status = scsi_status;
1202 switch (scsi_status) {
1203 case SCSI_STATUS_CHECK_COND:
1204 case SCSI_STATUS_CMD_TERMINATED:
1205 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1206 /* Structure copy */
1207 ccb->csio.sense_data =
1208 adv->sense_buffers[q_no - 1];
1209 /* FALLTHROUGH */
1210 case SCSI_STATUS_BUSY:
1211 case SCSI_STATUS_RESERV_CONFLICT:
1212 case SCSI_STATUS_QUEUE_FULL:
1213 case SCSI_STATUS_COND_MET:
1214 case SCSI_STATUS_INTERMED:
1215 case SCSI_STATUS_INTERMED_COND_MET:
1216 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1217 break;
1218 case SCSI_STATUS_OK:
1219 ccb->ccb_h.status |= CAM_REQ_CMP;
1220 break;
1221 }
1222 break;
1223 case QHSTA_M_SEL_TIMEOUT:
1224 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1225 break;
1226 case QHSTA_M_DATA_OVER_RUN:
1227 ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1228 break;
1229 case QHSTA_M_UNEXPECTED_BUS_FREE:
1230 ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1231 break;
1232 case QHSTA_M_BAD_BUS_PHASE_SEQ:
1233 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1234 break;
1235 case QHSTA_M_BAD_CMPL_STATUS_IN:
1236 /* No command complete after a status message */
1237 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1238 break;
1239 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT:
1240 case QHSTA_M_WTM_TIMEOUT:
1241 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET:
1242 /* The SCSI bus hung in a phase */
1243 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1244 adv_reset_bus(adv, /*initiate_reset*/TRUE);
1245 break;
1246 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1247 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1248 break;
1249 case QHSTA_D_QDONE_SG_LIST_CORRUPTED:
1250 case QHSTA_D_ASC_DVC_ERROR_CODE_SET:
1251 case QHSTA_D_HOST_ABORT_FAILED:
1252 case QHSTA_D_EXE_SCSI_Q_FAILED:
1253 case QHSTA_D_ASPI_NO_BUF_POOL:
1254 case QHSTA_M_BAD_TAG_CODE:
1255 case QHSTA_D_LRAM_CMP_ERROR:
1256 case QHSTA_M_MICRO_CODE_ERROR_HALT:
1257 default:
1258 panic("%s: Unhandled Host status error %x",
1259 adv_name(adv), host_stat);
1260 /* NOTREACHED */
1261 }
1262 break;
1263
1264 case QD_ABORTED_BY_HOST:
1265 /* Don't clobber any, more explicit, error codes we've set */
1266 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG)
1267 ccb->ccb_h.status = CAM_REQ_ABORTED;
1268 break;
1269
1270 default:
1271 xpt_print_path(ccb->ccb_h.path);
1272 printf("adv_done - queue done with unknown status %x:%x\n",
1273 done_stat, host_stat);
1274 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
1275 break;
1276 }
1277 adv_clear_state(adv, ccb);
1278 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP
1279 && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
1280 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1281 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1282 }
1283 adv_free_ccb_info(adv, cinfo);
1284 /*
1285 * Null this out so that we catch driver bugs that cause a
1286 * ccb to be completed twice.
1287 */
1288 ccb->ccb_h.ccb_cinfo_ptr = NULL;
1289 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
1290 xpt_done(ccb);
1291}
1292
1293/*
1294 * Function to poll for command completion when
1295 * interrupts are disabled (crash dumps)
1296 */
1297static void
1298adv_poll(struct cam_sim *sim)
1299{
1300 adv_intr(cam_sim_softc(sim));
1301}
1302
1303/*
1304 * Attach all the sub-devices we can find
1305 */
1306int
1307adv_attach(adv)
1308 struct adv_softc *adv;
1309{
1310 struct ccb_setasync csa;
1311 struct cam_devq *devq;
1312 int max_sg;
1313
1314 /*
1315 * Allocate an array of ccb mapping structures. We put the
1316 * index of the ccb_info structure into the queue representing
1317 * a transaction and use it for mapping the queue to the
1318 * upper level SCSI transaction it represents.
1319 */
1320 adv->ccb_infos = malloc(sizeof(*adv->ccb_infos) * adv->max_openings,
1321 M_DEVBUF, M_NOWAIT);
1322
1323 if (adv->ccb_infos == NULL)
1324 goto error_exit;
1325
1326 adv->init_level++;
1327
1328 /*
1329 * Create our DMA tags. These tags define the kinds of device
1330 * accessable memory allocations and memory mappings we will
1331 * need to perform during normal operation.
1332 *
1333 * Unless we need to further restrict the allocation, we rely
1334 * on the restrictions of the parent dmat, hence the common
1335 * use of MAXADDR and MAXSIZE.
1336 *
1337 * The ASC boards use chains of "queues" (the transactional
1338 * resources on the board) to represent long S/G lists.
1339 * The first queue represents the command and holds a
1340 * single address and data pair. The queues that follow
1341 * can each hold ADV_SG_LIST_PER_Q entries. Given the
1342 * total number of queues, we can express the largest
1343 * transaction we can map. We reserve a few queues for
1344 * error recovery. Take those into account as well.
1345 *
1346 * There is a way to take an interrupt to download the
1347 * next batch of S/G entries if there are more than 255
1348 * of them (the counter in the queue structure is a u_int8_t).
1349 * We don't use this feature, so limit the S/G list size
1350 * accordingly.
1351 */
1352 max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q;
1353 if (max_sg > 255)
1354 max_sg = 255;
1355
1356 /* DMA tag for mapping buffers into device visible space. */
1357 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1358 /*lowaddr*/BUS_SPACE_MAXADDR,
1359 /*highaddr*/BUS_SPACE_MAXADDR,
1360 /*filter*/NULL, /*filterarg*/NULL,
1361 /*maxsize*/MAXPHYS,
1362 /*nsegments*/max_sg,
1363 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1364 /*flags*/BUS_DMA_ALLOCNOW,
1365 &adv->buffer_dmat) != 0) {
1366 goto error_exit;
1367 }
1368 adv->init_level++;
1369
1370 /* DMA tag for our sense buffers */
1371 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1372 /*lowaddr*/BUS_SPACE_MAXADDR,
1373 /*highaddr*/BUS_SPACE_MAXADDR,
1374 /*filter*/NULL, /*filterarg*/NULL,
1375 sizeof(struct scsi_sense_data)*adv->max_openings,
1376 /*nsegments*/1,
1377 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1378 /*flags*/0, &adv->sense_dmat) != 0) {
1379 goto error_exit;
1380 }
1381
1382 adv->init_level++;
1383
1384 /* Allocation for our sense buffers */
1385 if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers,
1386 BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) {
1387 goto error_exit;
1388 }
1389
1390 adv->init_level++;
1391
1392 /* And permanently map them */
1393 bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap,
1394 adv->sense_buffers,
1395 sizeof(struct scsi_sense_data)*adv->max_openings,
1396 adv_map, &adv->sense_physbase, /*flags*/0);
1397
1398 adv->init_level++;
1399
1400 /*
1401 * Fire up the chip
1402 */
1403 if (adv_start_chip(adv) != 1) {
1404 printf("adv%d: Unable to start on board processor. Aborting.\n",
1405 adv->unit);
1406 return (0);
1407 }
1408
1409 /*
1410 * Create the device queue for our SIM.
1411 */
1412 devq = cam_simq_alloc(adv->max_openings);
1413 if (devq == NULL)
1414 return (0);
1415
1416 /*
1417 * Construct our SIM entry.
1418 */
1419 adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit,
1420 1, adv->max_openings, devq);
1421 if (adv->sim == NULL)
1422 return (0);
1423
1424 /*
1425 * Register the bus.
1426 *
1427 * XXX Twin Channel EISA Cards???
1428 */
1429 if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) {
1430 cam_sim_free(adv->sim, /*free devq*/TRUE);
1431 return (0);
1432 }
1433
1434 if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim),
1435 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1436 == CAM_REQ_CMP) {
1437 xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5);
1438 csa.ccb_h.func_code = XPT_SASYNC_CB;
1439 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
1440 csa.callback = advasync;
1441 csa.callback_arg = adv;
1442 xpt_action((union ccb *)&csa);
1443 }
1444 return (1);
1445
1446error_exit:
1447 return (0);
1448}
2 * Generic driver for the Advanced Systems Inc. SCSI controllers
3 * Product specific probe and attach routines can be found in:
4 *
5 * i386/isa/adv_isa.c ABP5140, ABP542, ABP5150, ABP842, ABP852
6 * i386/eisa/adv_eisa.c ABP742, ABP752
7 * pci/adv_pci.c ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U,
8 * ABP940UA, ABP950, ABP960, ABP960U, ABP960UA,
9 * ABP970, ABP970U
10 *
11 * Copyright (c) 1996-2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification, immediately at the beginning of the file.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $FreeBSD: head/sys/dev/advansys/advansys.c 56926 2000-02-01 00:43:58Z gibbs $
36 */
37/*
38 * Ported from:
39 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
40 *
41 * Copyright (c) 1995-1997 Advanced System Products, Inc.
42 * All Rights Reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that redistributions of source
46 * code retain the above copyright notice and this comment without
47 * modification.
48 */
49
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/malloc.h>
53#include <sys/buf.h>
54#include <sys/kernel.h>
55
56#include <machine/bus_pio.h>
57#include <machine/bus.h>
58#include <machine/clock.h>
59
60#include <cam/cam.h>
61#include <cam/cam_ccb.h>
62#include <cam/cam_sim.h>
63#include <cam/cam_xpt_sim.h>
64#include <cam/cam_xpt_periph.h>
65#include <cam/cam_debug.h>
66
67#include <cam/scsi/scsi_all.h>
68#include <cam/scsi/scsi_message.h>
69
70#include <vm/vm.h>
71#include <vm/vm_param.h>
72#include <vm/pmap.h>
73
74#include <dev/advansys/advansys.h>
75
76u_long adv_unit;
77
78static void adv_action(struct cam_sim *sim, union ccb *ccb);
79static void adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
80 int nsegments, int error);
81static void adv_poll(struct cam_sim *sim);
82static void adv_run_doneq(struct adv_softc *adv);
83static struct adv_ccb_info *
84 adv_alloc_ccb_info(struct adv_softc *adv);
85static void adv_destroy_ccb_info(struct adv_softc *adv,
86 struct adv_ccb_info *cinfo);
87static __inline struct adv_ccb_info *
88 adv_get_ccb_info(struct adv_softc *adv);
89static __inline void adv_free_ccb_info(struct adv_softc *adv,
90 struct adv_ccb_info *cinfo);
91static __inline void adv_set_state(struct adv_softc *adv, adv_state state);
92static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb);
93static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb);
94
95struct adv_softc *advsoftcs[NADV]; /* XXX Config should handle this */
96
97static __inline struct adv_ccb_info *
98adv_get_ccb_info(struct adv_softc *adv)
99{
100 struct adv_ccb_info *cinfo;
101 int opri;
102
103 opri = splcam();
104 if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
105 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
106 } else {
107 cinfo = adv_alloc_ccb_info(adv);
108 }
109 splx(opri);
110
111 return (cinfo);
112}
113
114static __inline void
115adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
116{
117 int opri;
118
119 opri = splcam();
120 cinfo->state = ACCB_FREE;
121 SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links);
122 splx(opri);
123}
124
125static __inline void
126adv_set_state(struct adv_softc *adv, adv_state state)
127{
128 if (adv->state == 0)
129 xpt_freeze_simq(adv->sim, /*count*/1);
130 adv->state |= state;
131}
132
133static __inline void
134adv_clear_state(struct adv_softc *adv, union ccb* ccb)
135{
136 if (adv->state != 0)
137 adv_clear_state_really(adv, ccb);
138}
139
140static void
141adv_clear_state_really(struct adv_softc *adv, union ccb* ccb)
142{
143 if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0)
144 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK);
145 if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) {
146 int openings;
147
148 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q;
149 if (openings >= adv->openings_needed) {
150 adv->state &= ~ADV_RESOURCE_SHORTAGE;
151 adv->openings_needed = 0;
152 }
153 }
154
155 if ((adv->state & ADV_IN_TIMEOUT) != 0) {
156 struct adv_ccb_info *cinfo;
157
158 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
159 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) {
160 struct ccb_hdr *ccb_h;
161
162 /*
163 * We now traverse our list of pending CCBs
164 * and reinstate their timeouts.
165 */
166 ccb_h = LIST_FIRST(&adv->pending_ccbs);
167 while (ccb_h != NULL) {
168 ccb_h->timeout_ch =
169 timeout(adv_timeout, (caddr_t)ccb_h,
170 (ccb_h->timeout * hz) / 1000);
171 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
172 }
173 adv->state &= ~ADV_IN_TIMEOUT;
174 printf("%s: No longer in timeout\n", adv_name(adv));
175 }
176 }
177 if (adv->state == 0)
178 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
179}
180
181void
182adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
183{
184 bus_addr_t* physaddr;
185
186 physaddr = (bus_addr_t*)arg;
187 *physaddr = segs->ds_addr;
188}
189
190char *
191adv_name(struct adv_softc *adv)
192{
193 static char name[10];
194
195 snprintf(name, sizeof(name), "adv%d", adv->unit);
196 return (name);
197}
198
199static void
200adv_action(struct cam_sim *sim, union ccb *ccb)
201{
202 struct adv_softc *adv;
203
204 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n"));
205
206 adv = (struct adv_softc *)cam_sim_softc(sim);
207
208 switch (ccb->ccb_h.func_code) {
209 /* Common cases first */
210 case XPT_SCSI_IO: /* Execute the requested I/O operation */
211 {
212 struct ccb_hdr *ccb_h;
213 struct ccb_scsiio *csio;
214 struct adv_ccb_info *cinfo;
215
216 ccb_h = &ccb->ccb_h;
217 csio = &ccb->csio;
218 cinfo = adv_get_ccb_info(adv);
219 if (cinfo == NULL)
220 panic("XXX Handle CCB info error!!!");
221
222 ccb_h->ccb_cinfo_ptr = cinfo;
223 cinfo->ccb = ccb;
224
225 /* Only use S/G if there is a transfer */
226 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
227 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
228 /*
229 * We've been given a pointer
230 * to a single buffer
231 */
232 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
233 int s;
234 int error;
235
236 s = splsoftvm();
237 error =
238 bus_dmamap_load(adv->buffer_dmat,
239 cinfo->dmamap,
240 csio->data_ptr,
241 csio->dxfer_len,
242 adv_execute_ccb,
243 csio, /*flags*/0);
244 if (error == EINPROGRESS) {
245 /*
246 * So as to maintain ordering,
247 * freeze the controller queue
248 * until our mapping is
249 * returned.
250 */
251 adv_set_state(adv,
252 ADV_BUSDMA_BLOCK);
253 }
254 splx(s);
255 } else {
256 struct bus_dma_segment seg;
257
258 /* Pointer to physical buffer */
259 seg.ds_addr =
260 (bus_addr_t)csio->data_ptr;
261 seg.ds_len = csio->dxfer_len;
262 adv_execute_ccb(csio, &seg, 1, 0);
263 }
264 } else {
265 struct bus_dma_segment *segs;
266 if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
267 panic("adv_setup_data - Physical "
268 "segment pointers unsupported");
269
270 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
271 panic("adv_setup_data - Virtual "
272 "segment addresses unsupported");
273
274 /* Just use the segments provided */
275 segs = (struct bus_dma_segment *)csio->data_ptr;
276 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0);
277 }
278 } else {
279 adv_execute_ccb(ccb, NULL, 0, 0);
280 }
281 break;
282 }
283 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
284 case XPT_TARGET_IO: /* Execute target I/O request */
285 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
286 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
287 case XPT_EN_LUN: /* Enable LUN as a target */
288 case XPT_ABORT: /* Abort the specified CCB */
289 /* XXX Implement */
290 ccb->ccb_h.status = CAM_REQ_INVALID;
291 xpt_done(ccb);
292 break;
293 case XPT_SET_TRAN_SETTINGS:
294 {
295 struct ccb_trans_settings *cts;
296 target_bit_vector targ_mask;
297 struct adv_transinfo *tconf;
298 u_int update_type;
299 int s;
300
301 cts = &ccb->cts;
302 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
303 update_type = 0;
304
305 /*
306 * The user must specify which type of settings he wishes
307 * to change.
308 */
309 if (((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
310 && ((cts->flags & CCB_TRANS_USER_SETTINGS) == 0)) {
311 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
312 update_type |= ADV_TRANS_GOAL;
313 } else if (((cts->flags & CCB_TRANS_USER_SETTINGS) != 0)
314 && ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) == 0)) {
315 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
316 update_type |= ADV_TRANS_USER;
317 } else {
318 ccb->ccb_h.status = CAM_REQ_INVALID;
319 break;
320 }
321
322 s = splcam();
323
324 if ((update_type & ADV_TRANS_GOAL) != 0) {
325 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
326 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
327 adv->disc_enable |= targ_mask;
328 else
329 adv->disc_enable &= ~targ_mask;
330 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B,
331 adv->disc_enable);
332 }
333
334 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
335 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
336 adv->cmd_qng_enabled |= targ_mask;
337 else
338 adv->cmd_qng_enabled &= ~targ_mask;
339 }
340 }
341
342 if ((update_type & ADV_TRANS_USER) != 0) {
343 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
344 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
345 adv->user_disc_enable |= targ_mask;
346 else
347 adv->user_disc_enable &= ~targ_mask;
348 }
349
350 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
351 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
352 adv->user_cmd_qng_enabled |= targ_mask;
353 else
354 adv->user_cmd_qng_enabled &= ~targ_mask;
355 }
356 }
357
358 /*
359 * If the user specifies either the sync rate, or offset,
360 * but not both, the unspecified parameter defaults to its
361 * current value in transfer negotiations.
362 */
363 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
364 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
365 /*
366 * If the user provided a sync rate but no offset,
367 * use the current offset.
368 */
369 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0)
370 cts->sync_offset = tconf->offset;
371
372 /*
373 * If the user provided an offset but no sync rate,
374 * use the current sync rate.
375 */
376 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0)
377 cts->sync_period = tconf->period;
378
379 adv_period_offset_to_sdtr(adv, &cts->sync_period,
380 &cts->sync_offset,
381 cts->ccb_h.target_id);
382
383 adv_set_syncrate(adv, /*struct cam_path */NULL,
384 cts->ccb_h.target_id, cts->sync_period,
385 cts->sync_offset, update_type);
386 }
387
388 splx(s);
389 ccb->ccb_h.status = CAM_REQ_CMP;
390 xpt_done(ccb);
391 break;
392 }
393 case XPT_GET_TRAN_SETTINGS:
394 /* Get default/user set transfer settings for the target */
395 {
396 struct ccb_trans_settings *cts;
397 struct adv_transinfo *tconf;
398 target_bit_vector target_mask;
399 int s;
400
401 cts = &ccb->cts;
402 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id);
403
404 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
405
406 s = splcam();
407 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
408 tconf = &adv->tinfo[cts->ccb_h.target_id].current;
409 if ((adv->disc_enable & target_mask) != 0)
410 cts->flags |= CCB_TRANS_DISC_ENB;
411 if ((adv->cmd_qng_enabled & target_mask) != 0)
412 cts->flags |= CCB_TRANS_TAG_ENB;
413 } else {
414 tconf = &adv->tinfo[cts->ccb_h.target_id].user;
415 if ((adv->user_disc_enable & target_mask) != 0)
416 cts->flags |= CCB_TRANS_DISC_ENB;
417 if ((adv->user_cmd_qng_enabled & target_mask) != 0)
418 cts->flags |= CCB_TRANS_TAG_ENB;
419 }
420
421 cts->sync_period = tconf->period;
422 cts->sync_offset = tconf->offset;
423 splx(s);
424
425 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
426 cts->valid = CCB_TRANS_SYNC_RATE_VALID
427 | CCB_TRANS_SYNC_OFFSET_VALID
428 | CCB_TRANS_BUS_WIDTH_VALID
429 | CCB_TRANS_DISC_VALID
430 | CCB_TRANS_TQ_VALID;
431 ccb->ccb_h.status = CAM_REQ_CMP;
432 xpt_done(ccb);
433 break;
434 }
435 case XPT_CALC_GEOMETRY:
436 {
437 struct ccb_calc_geometry *ccg;
438 u_int32_t size_mb;
439 u_int32_t secs_per_cylinder;
440 int extended;
441
442 ccg = &ccb->ccg;
443 size_mb = ccg->volume_size
444 / ((1024L * 1024L) / ccg->block_size);
445 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0;
446
447 if (size_mb > 1024 && extended) {
448 ccg->heads = 255;
449 ccg->secs_per_track = 63;
450 } else {
451 ccg->heads = 64;
452 ccg->secs_per_track = 32;
453 }
454 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
455 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
456 ccb->ccb_h.status = CAM_REQ_CMP;
457 xpt_done(ccb);
458 break;
459 }
460 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
461 {
462 int s;
463
464 s = splcam();
465 adv_stop_execution(adv);
466 adv_reset_bus(adv, /*initiate_reset*/TRUE);
467 adv_start_execution(adv);
468 splx(s);
469
470 ccb->ccb_h.status = CAM_REQ_CMP;
471 xpt_done(ccb);
472 break;
473 }
474 case XPT_TERM_IO: /* Terminate the I/O process */
475 /* XXX Implement */
476 ccb->ccb_h.status = CAM_REQ_INVALID;
477 xpt_done(ccb);
478 break;
479 case XPT_PATH_INQ: /* Path routing inquiry */
480 {
481 struct ccb_pathinq *cpi = &ccb->cpi;
482
483 cpi->version_num = 1; /* XXX??? */
484 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
485 cpi->target_sprt = 0;
486 cpi->hba_misc = 0;
487 cpi->hba_eng_cnt = 0;
488 cpi->max_target = 7;
489 cpi->max_lun = 7;
490 cpi->initiator_id = adv->scsi_id;
491 cpi->bus_id = cam_sim_bus(sim);
492 cpi->base_transfer_speed = 3300;
493 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
494 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN);
495 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
496 cpi->unit_number = cam_sim_unit(sim);
497 cpi->ccb_h.status = CAM_REQ_CMP;
498 xpt_done(ccb);
499 break;
500 }
501 default:
502 ccb->ccb_h.status = CAM_REQ_INVALID;
503 xpt_done(ccb);
504 break;
505 }
506}
507
508/*
509 * Currently, the output of bus_dmammap_load suits our needs just
510 * fine, but should it change, we'd need to do something here.
511 */
512#define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs)
513
514static void
515adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs,
516 int nsegments, int error)
517{
518 struct ccb_scsiio *csio;
519 struct ccb_hdr *ccb_h;
520 struct cam_sim *sim;
521 struct adv_softc *adv;
522 struct adv_ccb_info *cinfo;
523 struct adv_scsi_q scsiq;
524 struct adv_sg_head sghead;
525 int s;
526
527 csio = (struct ccb_scsiio *)arg;
528 ccb_h = &csio->ccb_h;
529 sim = xpt_path_sim(ccb_h->path);
530 adv = (struct adv_softc *)cam_sim_softc(sim);
531 cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr;
532
533 /*
534 * Setup our done routine to release the simq on
535 * the next ccb that completes.
536 */
537 if ((adv->state & ADV_BUSDMA_BLOCK) != 0)
538 adv->state |= ADV_BUSDMA_BLOCK_CLEARED;
539
540 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) {
541 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) {
542 /* XXX Need phystovirt!!!! */
543 /* How about pmap_kenter??? */
544 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
545 } else {
546 scsiq.cdbptr = csio->cdb_io.cdb_ptr;
547 }
548 } else {
549 scsiq.cdbptr = csio->cdb_io.cdb_bytes;
550 }
551 /*
552 * Build up the request
553 */
554 scsiq.q1.status = 0;
555 scsiq.q1.q_no = 0;
556 scsiq.q1.cntl = 0;
557 scsiq.q1.sg_queue_cnt = 0;
558 scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id);
559 scsiq.q1.target_lun = ccb_h->target_lun;
560 scsiq.q1.sense_len = csio->sense_len;
561 scsiq.q1.extra_bytes = 0;
562 scsiq.q2.ccb_index = cinfo - adv->ccb_infos;
563 scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id,
564 ccb_h->target_lun);
565 scsiq.q2.flag = 0;
566 scsiq.q2.cdb_len = csio->cdb_len;
567 if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0)
568 scsiq.q2.tag_code = csio->tag_action;
569 else
570 scsiq.q2.tag_code = 0;
571 scsiq.q2.vm_id = 0;
572
573 if (nsegments != 0) {
574 bus_dmasync_op_t op;
575
576 scsiq.q1.data_addr = dm_segs->ds_addr;
577 scsiq.q1.data_cnt = dm_segs->ds_len;
578 if (nsegments > 1) {
579 scsiq.q1.cntl |= QC_SG_HEAD;
580 sghead.entry_cnt
581 = sghead.entry_to_copy
582 = nsegments;
583 sghead.res = 0;
584 sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs);
585 scsiq.sg_head = &sghead;
586 } else {
587 scsiq.sg_head = NULL;
588 }
589 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN)
590 op = BUS_DMASYNC_PREREAD;
591 else
592 op = BUS_DMASYNC_PREWRITE;
593 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
594 } else {
595 scsiq.q1.data_addr = 0;
596 scsiq.q1.data_cnt = 0;
597 scsiq.sg_head = NULL;
598 }
599
600 s = splcam();
601
602 /*
603 * Last time we need to check if this SCB needs to
604 * be aborted.
605 */
606 if (ccb_h->status != CAM_REQ_INPROG) {
607 if (nsegments != 0)
608 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
609 adv_clear_state(adv, (union ccb *)csio);
610 adv_free_ccb_info(adv, cinfo);
611 xpt_done((union ccb *)csio);
612 splx(s);
613 return;
614 }
615
616 if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) {
617 /* Temporary resource shortage */
618 adv_set_state(adv, ADV_RESOURCE_SHORTAGE);
619 if (nsegments != 0)
620 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
621 csio->ccb_h.status = CAM_REQUEUE_REQ;
622 adv_clear_state(adv, (union ccb *)csio);
623 adv_free_ccb_info(adv, cinfo);
624 xpt_done((union ccb *)csio);
625 splx(s);
626 return;
627 }
628 cinfo->state |= ACCB_ACTIVE;
629 ccb_h->status |= CAM_SIM_QUEUED;
630 LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le);
631 /* Schedule our timeout */
632 ccb_h->timeout_ch =
633 timeout(adv_timeout, csio, (ccb_h->timeout * hz)/1000);
634 splx(s);
635}
636
637static struct adv_ccb_info *
638adv_alloc_ccb_info(struct adv_softc *adv)
639{
640 int error;
641 struct adv_ccb_info *cinfo;
642
643 cinfo = &adv->ccb_infos[adv->ccb_infos_allocated];
644 cinfo->state = ACCB_FREE;
645 error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0,
646 &cinfo->dmamap);
647 if (error != 0) {
648 printf("%s: Unable to allocate CCB info "
649 "dmamap - error %d\n", adv_name(adv), error);
650 return (NULL);
651 }
652 adv->ccb_infos_allocated++;
653 return (cinfo);
654}
655
656static void
657adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo)
658{
659 bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap);
660}
661
662void
663adv_timeout(void *arg)
664{
665 int s;
666 union ccb *ccb;
667 struct adv_softc *adv;
668 struct adv_ccb_info *cinfo;
669
670 ccb = (union ccb *)arg;
671 adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc;
672 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
673
674 xpt_print_path(ccb->ccb_h.path);
675 printf("Timed out\n");
676
677 s = splcam();
678 /* Have we been taken care of already?? */
679 if (cinfo == NULL || cinfo->state == ACCB_FREE) {
680 splx(s);
681 return;
682 }
683
684 adv_stop_execution(adv);
685
686 if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) {
687 struct ccb_hdr *ccb_h;
688
689 /*
690 * In order to simplify the recovery process, we ask the XPT
691 * layer to halt the queue of new transactions and we traverse
692 * the list of pending CCBs and remove their timeouts. This
693 * means that the driver attempts to clear only one error
694 * condition at a time. In general, timeouts that occur
695 * close together are related anyway, so there is no benefit
696 * in attempting to handle errors in parrallel. Timeouts will
697 * be reinstated when the recovery process ends.
698 */
699 adv_set_state(adv, ADV_IN_TIMEOUT);
700
701 /* This CCB is the CCB representing our recovery actions */
702 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED;
703
704 ccb_h = LIST_FIRST(&adv->pending_ccbs);
705 while (ccb_h != NULL) {
706 untimeout(adv_timeout, ccb_h, ccb_h->timeout_ch);
707 ccb_h = LIST_NEXT(ccb_h, sim_links.le);
708 }
709
710 /* XXX Should send a BDR */
711 /* Attempt an abort as our first tact */
712 xpt_print_path(ccb->ccb_h.path);
713 printf("Attempting abort\n");
714 adv_abort_ccb(adv, ccb->ccb_h.target_id,
715 ccb->ccb_h.target_lun, ccb,
716 CAM_CMD_TIMEOUT, /*queued_only*/FALSE);
717 ccb->ccb_h.timeout_ch =
718 timeout(adv_timeout, ccb, 2 * hz);
719 } else {
720 /* Our attempt to perform an abort failed, go for a reset */
721 xpt_print_path(ccb->ccb_h.path);
722 printf("Resetting bus\n");
723 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
724 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
725 adv_reset_bus(adv, /*initiate_reset*/TRUE);
726 }
727 adv_start_execution(adv);
728 splx(s);
729}
730
731struct adv_softc *
732adv_alloc(int unit, bus_space_tag_t tag, bus_space_handle_t bsh)
733{
734 struct adv_softc *adv;
735
736 if (unit >= NADV) {
737 printf("adv: unit number (%d) too high\n", unit);
738 return NULL;
739 }
740
741 /*
742 * Allocate a storage area for us
743 */
744 if (advsoftcs[unit]) {
745 printf("adv%d: memory already allocated\n", unit);
746 return NULL;
747 }
748
749 adv = malloc(sizeof(struct adv_softc), M_DEVBUF, M_NOWAIT);
750 if (!adv) {
751 printf("adv%d: cannot malloc!\n", unit);
752 return NULL;
753 }
754 bzero(adv, sizeof(struct adv_softc));
755 LIST_INIT(&adv->pending_ccbs);
756 SLIST_INIT(&adv->free_ccb_infos);
757 advsoftcs[unit] = adv;
758 adv->unit = unit;
759 adv->tag = tag;
760 adv->bsh = bsh;
761
762 return(adv);
763}
764
765void
766adv_free(struct adv_softc *adv)
767{
768 switch (adv->init_level) {
769 case 6:
770 {
771 struct adv_ccb_info *cinfo;
772
773 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) {
774 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links);
775 adv_destroy_ccb_info(adv, cinfo);
776 }
777
778 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap);
779 }
780 case 5:
781 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers,
782 adv->sense_dmamap);
783 case 4:
784 bus_dma_tag_destroy(adv->sense_dmat);
785 case 3:
786 bus_dma_tag_destroy(adv->buffer_dmat);
787 case 2:
788 bus_dma_tag_destroy(adv->parent_dmat);
789 case 1:
790 free(adv->ccb_infos, M_DEVBUF);
791 case 0:
792 break;
793 }
794 free(adv, M_DEVBUF);
795}
796
797int
798adv_init(struct adv_softc *adv)
799{
800 struct adv_eeprom_config eeprom_config;
801 int checksum, i;
802 int max_sync;
803 u_int16_t config_lsw;
804 u_int16_t config_msw;
805
806 adv_lib_init(adv);
807
808 /*
809 * Stop script execution.
810 */
811 adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE);
812 adv_stop_execution(adv);
813 if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) {
814 printf("adv%d: Unable to halt adapter. Initialization"
815 "failed\n", adv->unit);
816 return (1);
817 }
818 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR);
819 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) {
820 printf("adv%d: Unable to set program counter. Initialization"
821 "failed\n", adv->unit);
822 return (1);
823 }
824
825 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
826 config_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
827
828 if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) {
829 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
830 /*
831 * XXX The Linux code flags this as an error,
832 * but what should we report to the user???
833 * It seems that clearing the config register
834 * makes this error recoverable.
835 */
836 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
837 }
838
839 /* Suck in the configuration from the EEProm */
840 checksum = adv_get_eeprom_config(adv, &eeprom_config);
841
842 if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) {
843 /*
844 * XXX The Linux code sets a warning level for this
845 * condition, yet nothing of meaning is printed to
846 * the user. What does this mean???
847 */
848 if (adv->chip_version == 3) {
849 if (eeprom_config.cfg_lsw != config_lsw)
850 eeprom_config.cfg_lsw = config_lsw;
851 if (eeprom_config.cfg_msw != config_msw) {
852 eeprom_config.cfg_msw = config_msw;
853 }
854 }
855 }
856 if (checksum == eeprom_config.chksum) {
857
858 /* Range/Sanity checking */
859 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) {
860 eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG;
861 }
862 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) {
863 eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG;
864 }
865 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) {
866 eeprom_config.max_tag_qng = eeprom_config.max_total_qng;
867 }
868 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) {
869 eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC;
870 }
871 adv->max_openings = eeprom_config.max_total_qng;
872 adv->user_disc_enable = eeprom_config.disc_enable;
873 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng;
874 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config);
875 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID;
876 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id);
877 adv->control = eeprom_config.cntl;
878 for (i = 0; i <= ADV_MAX_TID; i++) {
879 u_int8_t sync_data;
880
881 if ((eeprom_config.init_sdtr & (0x1 << i)) == 0)
882 sync_data = 0;
883 else
884 sync_data = eeprom_config.sdtr_data[i];
885 adv_sdtr_to_period_offset(adv,
886 sync_data,
887 &adv->tinfo[i].user.period,
888 &adv->tinfo[i].user.offset,
889 i);
890 }
891 config_lsw = eeprom_config.cfg_lsw;
892 eeprom_config.cfg_msw = config_msw;
893 } else {
894 u_int8_t sync_data;
895
896 printf("adv%d: Warning EEPROM Checksum mismatch. "
897 "Using default device parameters\n", adv->unit);
898
899 /* Set reasonable defaults since we can't read the EEPROM */
900 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1;
901 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG;
902 adv->disc_enable = TARGET_BIT_VECTOR_SET;
903 adv->user_disc_enable = TARGET_BIT_VECTOR_SET;
904 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
905 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET;
906 adv->scsi_id = 7;
907 adv->control = 0xFFFF;
908
909 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
910 /* Default to no Ultra to support the 3030 */
911 adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA;
912 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4);
913 for (i = 0; i <= ADV_MAX_TID; i++) {
914 adv_sdtr_to_period_offset(adv, sync_data,
915 &adv->tinfo[i].user.period,
916 &adv->tinfo[i].user.offset,
917 i);
918 }
919 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON;
920 }
921 config_msw &= ~ADV_CFG_MSW_CLR_MASK;
922 config_lsw |= ADV_CFG_LSW_HOST_INT_ON;
923 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)
924 && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0)
925 /* 25ns or 10MHz */
926 max_sync = 25;
927 else
928 /* Unlimited */
929 max_sync = 0;
930 for (i = 0; i <= ADV_MAX_TID; i++) {
931 if (adv->tinfo[i].user.period < max_sync)
932 adv->tinfo[i].user.period = max_sync;
933 }
934
935 if (adv_test_external_lram(adv) == 0) {
936 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) {
937 eeprom_config.max_total_qng =
938 ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
939 eeprom_config.max_tag_qng =
940 ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG;
941 } else {
942 eeprom_config.cfg_msw |= 0x0800;
943 config_msw |= 0x0800;
944 eeprom_config.max_total_qng =
945 ADV_MAX_PCI_INRAM_TOTAL_QNG;
946 eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG;
947 }
948 adv->max_openings = eeprom_config.max_total_qng;
949 }
950 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
951 ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw);
952#if 0
953 /*
954 * Don't write the eeprom data back for now.
955 * I'd rather not mess up the user's card. We also don't
956 * fully sanitize the eeprom settings above for the write-back
957 * to be 100% correct.
958 */
959 if (adv_set_eeprom_config(adv, &eeprom_config) != 0)
960 printf("%s: WARNING! Failure writing to EEPROM.\n",
961 adv_name(adv));
962#endif
963
964 adv_set_chip_scsiid(adv, adv->scsi_id);
965 if (adv_init_lram_and_mcode(adv))
966 return (1);
967
968 adv->disc_enable = adv->user_disc_enable;
969
970 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable);
971 for (i = 0; i <= ADV_MAX_TID; i++) {
972 /*
973 * Start off in async mode.
974 */
975 adv_set_syncrate(adv, /*struct cam_path */NULL,
976 i, /*period*/0, /*offset*/0,
977 ADV_TRANS_CUR);
978 /*
979 * Enable the use of tagged commands on all targets.
980 * This allows the kernel driver to make up it's own mind
981 * as it sees fit to tag queue instead of having the
982 * firmware try and second guess the tag_code settins.
983 */
984 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i,
985 adv->max_openings);
986 }
987 adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
988 adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET);
989 printf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n",
990 adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0)
991 ? "Ultra SCSI" : "SCSI",
992 adv->scsi_id, adv->max_openings);
993 return (0);
994}
995
996void
997adv_intr(void *arg)
998{
999 struct adv_softc *adv;
1000 u_int16_t chipstat;
1001 u_int16_t saved_ram_addr;
1002 u_int8_t ctrl_reg;
1003 u_int8_t saved_ctrl_reg;
1004 u_int8_t host_flag;
1005
1006 adv = (struct adv_softc *)arg;
1007
1008 chipstat = ADV_INW(adv, ADV_CHIP_STATUS);
1009
1010 /* Is it for us? */
1011 if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0)
1012 return;
1013
1014 ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL);
1015 saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET |
1016 ADV_CC_SINGLE_STEP | ADV_CC_DIAG |
1017 ADV_CC_TEST));
1018
1019 if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) {
1020 printf("Detected Bus Reset\n");
1021 adv_reset_bus(adv, /*initiate_reset*/FALSE);
1022 return;
1023 }
1024
1025 if ((chipstat & ADV_CSW_INT_PENDING) != 0) {
1026
1027 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR);
1028 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
1029 adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
1030 host_flag | ADV_HOST_FLAG_IN_ISR);
1031
1032 adv_ack_interrupt(adv);
1033
1034 if ((chipstat & ADV_CSW_HALTED) != 0
1035 && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) {
1036 adv_isr_chip_halted(adv);
1037 saved_ctrl_reg &= ~ADV_CC_HALT;
1038 } else {
1039 adv_run_doneq(adv);
1040 }
1041 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr);
1042#ifdef DIAGNOSTIC
1043 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr)
1044 panic("adv_intr: Unable to set LRAM addr");
1045#endif
1046 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
1047 }
1048
1049 ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg);
1050}
1051
1052void
1053adv_run_doneq(struct adv_softc *adv)
1054{
1055 struct adv_q_done_info scsiq;
1056 u_int doneq_head;
1057 u_int done_qno;
1058
1059 doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF;
1060 done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head)
1061 + ADV_SCSIQ_B_FWD);
1062 while (done_qno != ADV_QLINK_END) {
1063 union ccb* ccb;
1064 struct adv_ccb_info *cinfo;
1065 u_int done_qaddr;
1066 u_int sg_queue_cnt;
1067 int aborted;
1068
1069 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1070
1071 /* Pull status from this request */
1072 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq,
1073 adv->max_dma_count);
1074
1075 /* Mark it as free */
1076 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS,
1077 scsiq.q_status & ~(QS_READY|QS_ABORTED));
1078
1079 /* Process request based on retrieved info */
1080 if ((scsiq.cntl & QC_SG_HEAD) != 0) {
1081 u_int i;
1082
1083 /*
1084 * S/G based request. Free all of the queue
1085 * structures that contained S/G information.
1086 */
1087 for (i = 0; i < sg_queue_cnt; i++) {
1088 done_qno = adv_read_lram_8(adv, done_qaddr
1089 + ADV_SCSIQ_B_FWD);
1090
1091#ifdef DIAGNOSTIC
1092 if (done_qno == ADV_QLINK_END) {
1093 panic("adv_qdone: Corrupted SG "
1094 "list encountered");
1095 }
1096#endif
1097 done_qaddr = ADV_QNO_TO_QADDR(done_qno);
1098
1099 /* Mark SG queue as free */
1100 adv_write_lram_8(adv, done_qaddr
1101 + ADV_SCSIQ_B_STATUS, QS_FREE);
1102 }
1103 } else
1104 sg_queue_cnt = 0;
1105#ifdef DIAGNOSTIC
1106 if (adv->cur_active < (sg_queue_cnt + 1))
1107 panic("adv_qdone: Attempting to free more "
1108 "queues than are active");
1109#endif
1110 adv->cur_active -= sg_queue_cnt + 1;
1111
1112 aborted = (scsiq.q_status & QS_ABORTED) != 0;
1113
1114 if ((scsiq.q_status != QS_DONE)
1115 && (scsiq.q_status & QS_ABORTED) == 0)
1116 panic("adv_qdone: completed scsiq with unknown status");
1117
1118 scsiq.remain_bytes += scsiq.extra_bytes;
1119
1120 if ((scsiq.d3.done_stat == QD_WITH_ERROR) &&
1121 (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) {
1122 if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) {
1123 scsiq.d3.done_stat = QD_NO_ERROR;
1124 scsiq.d3.host_stat = QHSTA_NO_ERROR;
1125 }
1126 }
1127
1128 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index];
1129 ccb = cinfo->ccb;
1130 ccb->csio.resid = scsiq.remain_bytes;
1131 adv_done(adv, ccb,
1132 scsiq.d3.done_stat, scsiq.d3.host_stat,
1133 scsiq.d3.scsi_stat, scsiq.q_no);
1134
1135 doneq_head = done_qno;
1136 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD);
1137 }
1138 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head);
1139}
1140
1141
1142void
1143adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat,
1144 u_int host_stat, u_int scsi_status, u_int q_no)
1145{
1146 struct adv_ccb_info *cinfo;
1147
1148 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr;
1149 LIST_REMOVE(&ccb->ccb_h, sim_links.le);
1150 untimeout(adv_timeout, ccb, ccb->ccb_h.timeout_ch);
1151 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1152 bus_dmasync_op_t op;
1153
1154 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1155 op = BUS_DMASYNC_POSTREAD;
1156 else
1157 op = BUS_DMASYNC_POSTWRITE;
1158 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op);
1159 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap);
1160 }
1161
1162 switch (done_stat) {
1163 case QD_NO_ERROR:
1164 if (host_stat == QHSTA_NO_ERROR) {
1165 ccb->ccb_h.status = CAM_REQ_CMP;
1166 break;
1167 }
1168 xpt_print_path(ccb->ccb_h.path);
1169 printf("adv_done - queue done without error, "
1170 "but host status non-zero(%x)\n", host_stat);
1171 /*FALLTHROUGH*/
1172 case QD_WITH_ERROR:
1173 switch (host_stat) {
1174 case QHSTA_M_TARGET_STATUS_BUSY:
1175 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY:
1176 /*
1177 * Assume that if we were a tagged transaction
1178 * the target reported queue full. Otherwise,
1179 * report busy. The firmware really should just
1180 * pass the original status back up to us even
1181 * if it thinks the target was in error for
1182 * returning this status as no other transactions
1183 * from this initiator are in effect, but this
1184 * ignores multi-initiator setups and there is
1185 * evidence that the firmware gets its per-device
1186 * transaction counts screwed up occassionally.
1187 */
1188 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1189 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0
1190 && host_stat != QHSTA_M_TARGET_STATUS_BUSY)
1191 scsi_status = SCSI_STATUS_QUEUE_FULL;
1192 else
1193 scsi_status = SCSI_STATUS_BUSY;
1194 adv_abort_ccb(adv, ccb->ccb_h.target_id,
1195 ccb->ccb_h.target_lun,
1196 /*ccb*/NULL, CAM_REQUEUE_REQ,
1197 /*queued_only*/TRUE);
1198 /*FALLTHROUGH*/
1199 case QHSTA_M_NO_AUTO_REQ_SENSE:
1200 case QHSTA_NO_ERROR:
1201 ccb->csio.scsi_status = scsi_status;
1202 switch (scsi_status) {
1203 case SCSI_STATUS_CHECK_COND:
1204 case SCSI_STATUS_CMD_TERMINATED:
1205 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1206 /* Structure copy */
1207 ccb->csio.sense_data =
1208 adv->sense_buffers[q_no - 1];
1209 /* FALLTHROUGH */
1210 case SCSI_STATUS_BUSY:
1211 case SCSI_STATUS_RESERV_CONFLICT:
1212 case SCSI_STATUS_QUEUE_FULL:
1213 case SCSI_STATUS_COND_MET:
1214 case SCSI_STATUS_INTERMED:
1215 case SCSI_STATUS_INTERMED_COND_MET:
1216 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1217 break;
1218 case SCSI_STATUS_OK:
1219 ccb->ccb_h.status |= CAM_REQ_CMP;
1220 break;
1221 }
1222 break;
1223 case QHSTA_M_SEL_TIMEOUT:
1224 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1225 break;
1226 case QHSTA_M_DATA_OVER_RUN:
1227 ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1228 break;
1229 case QHSTA_M_UNEXPECTED_BUS_FREE:
1230 ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1231 break;
1232 case QHSTA_M_BAD_BUS_PHASE_SEQ:
1233 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1234 break;
1235 case QHSTA_M_BAD_CMPL_STATUS_IN:
1236 /* No command complete after a status message */
1237 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1238 break;
1239 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT:
1240 case QHSTA_M_WTM_TIMEOUT:
1241 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET:
1242 /* The SCSI bus hung in a phase */
1243 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1244 adv_reset_bus(adv, /*initiate_reset*/TRUE);
1245 break;
1246 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1247 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1248 break;
1249 case QHSTA_D_QDONE_SG_LIST_CORRUPTED:
1250 case QHSTA_D_ASC_DVC_ERROR_CODE_SET:
1251 case QHSTA_D_HOST_ABORT_FAILED:
1252 case QHSTA_D_EXE_SCSI_Q_FAILED:
1253 case QHSTA_D_ASPI_NO_BUF_POOL:
1254 case QHSTA_M_BAD_TAG_CODE:
1255 case QHSTA_D_LRAM_CMP_ERROR:
1256 case QHSTA_M_MICRO_CODE_ERROR_HALT:
1257 default:
1258 panic("%s: Unhandled Host status error %x",
1259 adv_name(adv), host_stat);
1260 /* NOTREACHED */
1261 }
1262 break;
1263
1264 case QD_ABORTED_BY_HOST:
1265 /* Don't clobber any, more explicit, error codes we've set */
1266 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG)
1267 ccb->ccb_h.status = CAM_REQ_ABORTED;
1268 break;
1269
1270 default:
1271 xpt_print_path(ccb->ccb_h.path);
1272 printf("adv_done - queue done with unknown status %x:%x\n",
1273 done_stat, host_stat);
1274 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
1275 break;
1276 }
1277 adv_clear_state(adv, ccb);
1278 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP
1279 && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
1280 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1281 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1282 }
1283 adv_free_ccb_info(adv, cinfo);
1284 /*
1285 * Null this out so that we catch driver bugs that cause a
1286 * ccb to be completed twice.
1287 */
1288 ccb->ccb_h.ccb_cinfo_ptr = NULL;
1289 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
1290 xpt_done(ccb);
1291}
1292
1293/*
1294 * Function to poll for command completion when
1295 * interrupts are disabled (crash dumps)
1296 */
1297static void
1298adv_poll(struct cam_sim *sim)
1299{
1300 adv_intr(cam_sim_softc(sim));
1301}
1302
1303/*
1304 * Attach all the sub-devices we can find
1305 */
1306int
1307adv_attach(adv)
1308 struct adv_softc *adv;
1309{
1310 struct ccb_setasync csa;
1311 struct cam_devq *devq;
1312 int max_sg;
1313
1314 /*
1315 * Allocate an array of ccb mapping structures. We put the
1316 * index of the ccb_info structure into the queue representing
1317 * a transaction and use it for mapping the queue to the
1318 * upper level SCSI transaction it represents.
1319 */
1320 adv->ccb_infos = malloc(sizeof(*adv->ccb_infos) * adv->max_openings,
1321 M_DEVBUF, M_NOWAIT);
1322
1323 if (adv->ccb_infos == NULL)
1324 goto error_exit;
1325
1326 adv->init_level++;
1327
1328 /*
1329 * Create our DMA tags. These tags define the kinds of device
1330 * accessable memory allocations and memory mappings we will
1331 * need to perform during normal operation.
1332 *
1333 * Unless we need to further restrict the allocation, we rely
1334 * on the restrictions of the parent dmat, hence the common
1335 * use of MAXADDR and MAXSIZE.
1336 *
1337 * The ASC boards use chains of "queues" (the transactional
1338 * resources on the board) to represent long S/G lists.
1339 * The first queue represents the command and holds a
1340 * single address and data pair. The queues that follow
1341 * can each hold ADV_SG_LIST_PER_Q entries. Given the
1342 * total number of queues, we can express the largest
1343 * transaction we can map. We reserve a few queues for
1344 * error recovery. Take those into account as well.
1345 *
1346 * There is a way to take an interrupt to download the
1347 * next batch of S/G entries if there are more than 255
1348 * of them (the counter in the queue structure is a u_int8_t).
1349 * We don't use this feature, so limit the S/G list size
1350 * accordingly.
1351 */
1352 max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q;
1353 if (max_sg > 255)
1354 max_sg = 255;
1355
1356 /* DMA tag for mapping buffers into device visible space. */
1357 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1358 /*lowaddr*/BUS_SPACE_MAXADDR,
1359 /*highaddr*/BUS_SPACE_MAXADDR,
1360 /*filter*/NULL, /*filterarg*/NULL,
1361 /*maxsize*/MAXPHYS,
1362 /*nsegments*/max_sg,
1363 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1364 /*flags*/BUS_DMA_ALLOCNOW,
1365 &adv->buffer_dmat) != 0) {
1366 goto error_exit;
1367 }
1368 adv->init_level++;
1369
1370 /* DMA tag for our sense buffers */
1371 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0,
1372 /*lowaddr*/BUS_SPACE_MAXADDR,
1373 /*highaddr*/BUS_SPACE_MAXADDR,
1374 /*filter*/NULL, /*filterarg*/NULL,
1375 sizeof(struct scsi_sense_data)*adv->max_openings,
1376 /*nsegments*/1,
1377 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1378 /*flags*/0, &adv->sense_dmat) != 0) {
1379 goto error_exit;
1380 }
1381
1382 adv->init_level++;
1383
1384 /* Allocation for our sense buffers */
1385 if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers,
1386 BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) {
1387 goto error_exit;
1388 }
1389
1390 adv->init_level++;
1391
1392 /* And permanently map them */
1393 bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap,
1394 adv->sense_buffers,
1395 sizeof(struct scsi_sense_data)*adv->max_openings,
1396 adv_map, &adv->sense_physbase, /*flags*/0);
1397
1398 adv->init_level++;
1399
1400 /*
1401 * Fire up the chip
1402 */
1403 if (adv_start_chip(adv) != 1) {
1404 printf("adv%d: Unable to start on board processor. Aborting.\n",
1405 adv->unit);
1406 return (0);
1407 }
1408
1409 /*
1410 * Create the device queue for our SIM.
1411 */
1412 devq = cam_simq_alloc(adv->max_openings);
1413 if (devq == NULL)
1414 return (0);
1415
1416 /*
1417 * Construct our SIM entry.
1418 */
1419 adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit,
1420 1, adv->max_openings, devq);
1421 if (adv->sim == NULL)
1422 return (0);
1423
1424 /*
1425 * Register the bus.
1426 *
1427 * XXX Twin Channel EISA Cards???
1428 */
1429 if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) {
1430 cam_sim_free(adv->sim, /*free devq*/TRUE);
1431 return (0);
1432 }
1433
1434 if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim),
1435 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1436 == CAM_REQ_CMP) {
1437 xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5);
1438 csa.ccb_h.func_code = XPT_SASYNC_CB;
1439 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
1440 csa.callback = advasync;
1441 csa.callback_arg = adv;
1442 xpt_action((union ccb *)&csa);
1443 }
1444 return (1);
1445
1446error_exit:
1447 return (0);
1448}